ANALOG DEVICES AD9742

12-Bit, 210 MSPS ® TxDAC D/A Converter AD9742 FEATURES APPLICATIONS High performance member of pin-compatible Wideband communication transmit channel: TxDAC product family Direct IF Excellent spurious-free dynamic range performance Base stations SNR @ 5 MHz output, 125 MSPS: 70 dB Wireless local loops Twos complement or straight binary data format Digital radio links Differential current outputs: 2 mA to 20 mA Direct digital synthesis (DDS) Power dissipation: 135 mW @ 3.3 V Instrumentation Power-down mode: 15 mW @ 3.3 V FUNCTIONAL BLOCK DIAGRAM On-chip 1.2 V Reference 3.3V CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP REFLO AVDD ACOM 150pF packages 1.2V REF 0.1µF AD9742 Edge-triggered latches REFIO CURRENT SOURCE FS ADJ ARRAY R SET 3.3V DVDD IOUTA SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES CLOCK MODE CLOCK LATCHES DIGITAL DATA INPUTS (DB11–DB0) SLEEP Figure 1. Edge-triggered input latches and a 1.2 V temperature compen- GENERAL DESCRIPTION sated band gap reference have been integrated to provide a 1 The AD9742 is a 12-bit resolution, wideband, third generation complete monolithic DAC solution. The digital inputs support member of the TxDAC series of high performance, low power 3 V CMOS logic families. CMOS digital-to-analog converters (DACs). The TxDAC family, PRODUCT HIGHLIGHTS consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is 1. The AD9742 is the 12-bit member of the pin-compatible specifically optimized for the transmit signal path of communi- TxDAC family, which offers excellent INL and DNL cation systems. All of the devices share the same interface performance. options, small outline package, and pinout, providing an upward 2. Data input supports twos complement or straight binary or downward component selection path based on performance, data coding. resolution, and cost. The AD9742 offers exceptional ac and dc 3. High speed, single-ended CMOS clock input supports performance while supporting update rates up to 210 MSPS. 210 MSPS conversion rate. The AD9742’s low power dissipation makes it well suited for 4. Low power: Complete CMOS DAC function operates on portable and low power applications. Its power dissipation can 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- be further reduced to a mere 60 mW with a slight degradation scale current can be reduced for lower power operation, in performance by lowering the full-scale current output. Also, a and a sleep mode is provided for low power idle periods. power-down mode reduces the standby power dissipation to 5. On-chip voltage reference: The AD9742 includes a 1.2 V approximately 15 mW. A segmented current source architecture temperature compensated band gap voltage reference. is combined with a proprietary switching technique to reduce 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and spurious components and enhance dynamic performance. 32-lead LFCSP packages. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 02913-B-001 AD9742 TABLE OF CONTENTS Specifications..................................................................................... 3 REVISION HISTORY DC Specifications ......................................................................... 3 6/04—Data Sheet Changed from Rev. A to Rev. B Changes to the Title.................................................................................1 Dynamic Specifications ............................................................... 4 Changes to General Description............................................................1 Changes to Product Highlights..............................................................1 Digital Specifications ................................................................... 5 Changes to Dynamic Specifications......................................................4 Changes to Figures 6 and 10...................................................................9 Absolute Maximum Ratings............................................................ 6 Changes to Figures 12 to 15 .................................................................10 Thermal Characteristics .............................................................. 6 Changes to the Functional Description Section................................12 Changes to the Digital Inputs Section ................................................14 ESD Caution.................................................................................. 6 Changes to Figure 29.............................................................................15 Changes to Figure 30.............................................................................16 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 5/03—Data Sheet Changed from Rev. 0 to Rev. A Added 32-Lead LFCSP Package ........................................... Universal Typical Performance Characteristics ............................................. 9 Edits to Features..................................................................................... 1 Edits to Product Highlights.................................................................. 1 Functional Description .................................................................. 12 Edits to DC Specifications.................................................................... 2 Edits to Dynamic Specifications.......................................................... 3 Reference Operation .................................................................. 12 Edits to Digital Specifications .............................................................. 4 Reference Control Amplifier..................................................... 13 Edits to Absolute Maximum Ratings.................................................. 5 Edits to Thermal Characteristics......................................................... 5 DAC Transfer Function ............................................................. 13 Edits to Ordering Guide ....................................................................... 5 Edits to Pin Configuration ................................................................... 6 Analog Outputs........................................................................... 13 Edits to Pin Function Descriptions..................................................... 6 Digital Inputs .............................................................................. 14 Edits to Figure 2..................................................................................... 7 Replaced TPCs 1, 4, 7, and 8 ................................................................ 8 Clock Input.................................................................................. 14 Edits to Figure 3................................................................................... 10 Edits to Functional Description Section .......................................... 10 DAC Timing................................................................................ 15 Added Clock Input Section................................................................ 12 Added Figure 7..................................................................................... 12 Power Dissipation....................................................................... 15 Edits to DAC Timing Section ............................................................ 12 Edits to Sleep Mode Operation Section............................................ 13 Applying the AD9742 ................................................................ 16 Edits to Power Dissipation Section................................................... 13 Differential Coupling Using a Transformer................................ 16 Renumbered Figures 8 to 26 .............................................................. 13 Added Figure 11................................................................................... 13 Differential Coupling Using an Op Amp ................................ 16 Added Figures 27 to 35 ....................................................................... 21 Updated Outline Dimensions............................................................ 26 Single-Ended, Unbuffered Voltage Output ............................. 17 5/02—Revision 0: Initial Version Single-Ended, Buffered Voltage Output Configuration ........ 17 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 17 Evaluation Board ............................................................................ 19 General Description................................................................... 19 Outline Dimensions ....................................................................... 29 Ordering Guide........................................................................... 30 Rev. B | Page 2 of 32 AD9742 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 12 Bits 1 DC ACCURACY Integral Linearity Error (INL) −2.5 ±0.5 +2.5 LSB Differential Nonlinearity (DNL) −1.3 ±0.4 +1.3 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (Ext. Reference) 1 MΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 2.7 3.3 3.6 V DVDD 2.7 3.3 3.6 V CLKVDD 2.7 3.3 3.6 V Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 8 9 mA DVDD Clock Supply Current (I ) 5 6 mA CLKVDD Supply Current Sleep Mode (IAVDD) 5 6 mA 4 Power Dissipation 135 145 mW 5 Power Dissipation 145 mW 6 Power Supply Rejection Ratio—AVDD −1 +1 % of FSR/V 6 Power Supply Rejection Ratio—DVDD −0.04 +0.04 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. 6 ±5% power supply variation. Rev. B | Page 3 of 32 AD9742 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly ter- minated, unless otherwise noted. Table 2 Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) 210 MSPS 1 Output Settling Time (tST) (to 0.1%) 11 ns Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns 2 Output Noise (IOUTFS = 20 mA) 50 pA/√Hz 2 Output Noise (I = 2 mA) 30 pA/√Hz OUTFS 3 Noise Spectral Density −152 dBm/Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output 74 84 dBc −6 dBFS Output 85 dBc −12 dBFS Output 82 dBc −18 dBFS Output 76 dBc f = 65 MSPS; f = 1.00 MHz 85 dBc CLOCK OUT f = 65 MSPS; f = 2.51 MHz 83 dBc CLOCK OUT f = 65 MSPS; f = 10 MHz 80 dBc CLOCK OUT fCLOCK = 65 MSPS; fOUT = 15 MHz 75 dBc fCLOCK = 65 MSPS; fOUT = 25 MHz 74 dBc f = 165 MSPS; f = 21 MHz 72 dBc CLOCK OUT f = 165 MSPS; f = 41 MHz 60 dBc CLOCK OUT f = 210 MSPS; f = 40 MHz 67 dBc CLOCK OUT fCLOCK = 210 MSPS; fOUT = 69 MHz 60 dBc Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span 80 dBc f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 90 dBc CLOCK OUT f = 65 MSPS; f = 5.03 MHz; 2.5 MHz Span 90 dBc CLOCK OUT f = 125 MSPS; f = 5.04 MHz; 4 MHz Span 90 dBc CLOCK OUT Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz −82 −74 dBc fCLOCK = 50 MSPS; fOUT = 2.00 MHz −77 dBc f = 65 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT f = 125 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 78 dB fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 86 dB f = 125 MSPS; f = 5 MHz; I = 20 mA 73 dB CLOCK OUT OUTFS f = 125 MSPS; f = 5 MHz; I = 5 mA 78 dB CLOCK OUT OUTFS f = 165 MSPS; f = 5 MHz; I = 20 mA 69 dB CLOCK OUT OUTFS fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 71 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 69 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 66 dB Rev. B | Page 4 of 32 AD9742 Parameter Min Typ Max Unit Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output 65 dBc −6 dBFS Output 67 dBc −12 dBFS Output 65 dBc −18 dBFS Output 63 dBc 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. DIGITAL SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 3. Parameter Min Typ Max Unit 1 DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulse Width (t ) 1.5 ns LPW 2 CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. 2 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% 0.1% IOUTB Figure 2. Timing Diagram Rev. B | Page 5 of 32 02912-B-002 AD9742 ABSOLUTE MAXIMUM RATINGS Table 4. 1 THERMAL CHARACTERISTICS With Thermal Resistance Parameter Respect to Min Max Unit 28-Lead 300-Mil SOIC AVDD ACOM −0.3 +3.9 V θJA = 55.9°C/W DVDD DCOM −0.3 +3.9 V 28-Lead TSSOP CLKVDD CLKCOM −0.3 +3.9 V θJA = 67.7°C/W ACOM DCOM −0.3 +0.3 V 32-Lead LFCSP ACOM CLKCOM −0.3 +0.3 V θ = 32.5°C/W JA DCOM CLKCOM −0.3 +0.3 V AVDD DVDD −3.9 +3.9 V AVDD CLKVDD −3.9 +3.9 V 1 Thermal impedance measurements were taken on a 4-layer board in still air, DVDD CLKVDD −3.9 +3.9 V in accordance with EIA/JESD51-7. CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V Junction 150 °C Temperature Storage −65 +150 °C Temperature Lead Temperature 300 °C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features pro- prietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electro- static discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 32 AD9742 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS (MSB) DB11 1 28 CLOCK DB10 2 27 DVDD DB9 3 26 DCOM DB8 4 25 MODE DB7 5 24 AVDD 24 FS ADJ DB5 1 PIN 1 AD9742 INDICATOR DB6 6 23 RESERVED DB4 2 23 REFIO TOP VIEW DVDD 3 22 ACOM DB5 7 22 IOUTA (Not to Scale) AD9742 DB3 4 21 IOUTA DB2 5 20 IOUTB DB4 8 21 IOUTB TOP VIEW DB1 6 (Not to Scale) 19 ACOM DB3 9 20 ACOM (LSB) DB0 7 18 AVDD NC 8 17 AVDD DB2 10 19 NC DB1 11 18 FS ADJ (LSB) DB0 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP NC = NO CONNECT NC = NO CONNECT Figure 4. 32-Lead LFCSP Pin Configuration Figure 3. 28-Lead SOIC and TSSOP Pin Configuration Table 5. Pin Function Descriptions SOIC/TSSOP LFCSP Pin No. Pin No. Mnemonic Description 1 27 DB11 Most Significant Data Bit (MSB). 2 to 11 28 to 32, DB10 to Data Bits 10 to 1. 1, 2, 4 to 6 DB1 12 7 DB0 Least Significant Data Bit (LSB). 13, 14 8, 9 N/C No Internal Connection. 15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. 16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 23 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. 18 24 FS ADJ Full-Scale Current Output Adjust. 19 N/A NC No Internal Connection. 20 19, 22 ACOM Analog Common. 21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 N/A RESERVED Reserved. Do not connect to common or supply. 24 17, 18 AVDD Analog Supply Voltage (3.3 V). 25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). 26 10, 26 DCOM Digital Common. 27 3 DVDD Digital Supply Voltage (3.3 V). 28 N/A CLOCK Clock Input. Data latched on positive edge of clock. N/A 12 CLK+ Differential Clock Input. N/A 13 CLK− Differential Clock Input. N/A 11 CLKVDD Clock Supply Voltage (3.3 V). N/A 14 CLKCOM Clock Common. Rev. B | Page 7 of 32 NC 9 32 DB6 DCOM 10 31 DB7 CLKVDD 11 30 DB8 CLK+ 12 29 DB9 CLK– 13 28 DB10 CLKCOM 14 27 DB11 (MSB) CMODE 15 26 DCOM MODE 16 25 SLEEP 02912-B-003 02912-B-004 AD9742 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the ac- The maximum change in the full-scale output as the supplies tual analog output from the ideal output, determined by a are varied from nominal to minimum and maximum specified straight line drawn from zero to full scale. voltages. Differential Nonlinearity (or DNL) Settling Time DNL is the measure of the variation in analog value, normalized The time required for the output to reach and remain within a to full scale, associated with a 1 LSB change in digital input specified error band about its final value, measured from the code. start of the output transition. Monotonicity Glitch Impulse A DAC is monotonic if the output either increases or remains Asymmetrical switching times in a DAC give rise to undesired constant as the digital input increases. output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is Spurious-Free Dynamic Range called the offset error. For IOUTA, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when the inputs are all 0s. For IOUTB, 0 mA output is expected signal and the peak spurious signal over the specified band- when all inputs are set to 1s. width. Gain Error Total Harmonic Distortion (THD) The difference between the actual and ideal output span. The THD is the ratio of the rms sum of the first six harmonic com- actual span is determined by the output when all inputs are set ponents to the rms value of the measured input signal. It is ex- to 1s minus the output when all inputs are set to 0s. pressed as a percentage or in decibels (dB). Output Compliance Range Multitone Power Ratio The range of allowable voltage at the output of a current output The spurious-free dynamic range containing multiple carrier DAC. Operation beyond the maximum compliance limits may tones of equal amplitude. It is measured as the difference be- cause either output stage saturation or breakdown, resulting in tween the rms amplitude of a carrier tone to the peak spurious nonlinear performance. signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9742 0.1µF REFIO PMOS CURRENT SOURCE FS ADJ ARRAY MINI-CIRCUITS R SET T1-1T 2kΩ 3.3V DVDD ROHDE & SCHWARZ IOUTA FSEA30 SEGMENTED SWITCHES LSB DCOM SPECTRUM IOUTB FOR DB11–DB3 SWITCHES ANALYZER CLOCK MODE LATCHES DVDD 50Ω SLEEP 50Ω DCOM RETIMED 50Ω CLOCK DIGITAL OUTPUT* DATA *AWG2021 CLOCK RETIMED CLOCK OUTPUT SO THAT THE DIGITAL DATA LECROY 9210 TEKTRONIX AWG-2021 TRANSITIONS ON FALLING EDGE PULSE GENERATOR WITH OPTION 4 OF 50% DUTY CYCLE CLOCK. Figure 5. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages) Rev. B | Page 8 of 32 02912-B-005 AD9742 TYPICAL PERFORMANCE CHARACTERISTICS 95 95 125MSPS 0dBFS 90 210MSPS (LFCSP) 90 –6dBFS (LFCSP) 85 85 165MSPS (LFCSP) 80 80 65MSPS 75 75 –12dBFS 210MSPS 70 70 165MSPS 65 65 125MSPS (LFCSP) –12dBFS (LFCSP) 60 60 0dBFS (LFCSP) –6dBFS 55 55 50 50 45 45 1 10 100 0 10 20 30 405060 f (MHz) f (MHz) OUT OUT Figure 6. SFDR vs. f @ 0 dBFS Figure 9. SFDR vs. f @ 165 MSPS OUT OUT 95 95 90 90 0dBFS (LFCSP) 85 85 80 80 0dBFS –12dBFS 75 75 –6dBFS (LFCSP) –6dBFS 70 70 –6dBFS 65 65 –12dBFS 60 60 55 55 –12dBFS (LFCSP) 50 0dBFS 50 45 45 0 5 10 15 20 25 010 20 30 40 50 60 70 f (MHz) f (MHz) OUT OUT Figure 7. SFDR vs. fOUT @ 65 MSPS Figure 10. SFDR vs. fOUT @ 210 MSPS 95 95 90 90 85 85 80 80 20mA 75 75 10mA –6dBFS 70 70 65 –12dBFS 5mA 65 0dBFS 60 60 55 55 50 50 45 45 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. f @ 125 MSPS OUT Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS Rev. B | Page 9 of 32 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02912-B-006 02912-B-012 02912-B-009 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02912-B-054 02912-B-010 02912-B-007 AD9742 95 95 78MSPS (10.1,12.1) 90 90 85 85 65MSPS (8.3,10.3) 65MSPS 80 80 125MSPS 75 75 125MSPS (16.9, 18.9) 165MSPS 70 70 210MSPS (29, 31) 65 210MSPS 65 165MSPS (22.6, 24.6) 210MSPS (29, 31) 60 210MSPS (LFCSP) 60 55 55 50 50 45 45 –25 –20 –15 –10 –5 0 –25 –20 –15 –10 –5 0 A (dBFS) A (dBFS) OUT OUT Figure 12. Single-Tone SFDR vs. A @ f = f /11 Figure 15. Dual-Tone IMD vs. A @ f = f /7 OUT OUT CLOCK OUT OUT CLOCK 95 1.0 90 85 125MSPS (LFCSP) 0.5 65MSPS 80 75 165MSPS (LFCSP) 70 0 65 165MSPS 60 125MSPS –0.5 55 210MSPS (LFCSP) 210MSPS 50 45 –1.0 –25 –20 –15 –10 –5 0 0 1024 2048 3072 4096 A (dBFS) CODE OUT Figure 13. Single-Tone SFDR vs. A @ f = f /5 Figure 16. Typical INL OUT OUT CLOCK 80 1.0 0.8 75 20mA 0.6 0.4 70 0.2 65 0 5mA 10mA –0.2 60 –0.4 –0.6 55 –0.8 50 –1.0 25 45 65 85 105 125 145 165 185 205 0 1024 2048 3072 4096 f (MHz) CODE CLOCK Figure 17. Typical DNL Figure 14. SNR vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS Rev. B | Page 10 of 32 SNR SFDR (dBc) SFDR (dBc) 02912-B-011 02912-B-008 02912-B-013 ERROR (LSB) SFDR (dBc) ERROR (LSB) 02912-B-014 02912-B-017 02912-B-015 AD9742 90 0 f = 78MSPS CLOCK –10 85 f = 15.0MHz OUT1 4MHz f = 15.4MHz OUT2 –20 SFDR = 77dBc 80 AMPLITUDE = 0dBFS –30 75 –40 19MHz 70 –50 –60 65 49MHz –70 60 –80 34MHz 55 –90 50 –100 1 6 11 16 21 26 31 36 –40 –20 020 40 60 80 TEMPERATURE (°C) FREQUENCY (MHz) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS Figure 20. Dual-Tone SFDR 0 0 f = 78MSPS f = 78MSPS CLOCK CLOCK –10 –10 f = 15.0MHz OUT f = 15.0MHz OUT1 SFDR = 79dBc –20 –20 f = 15.4MHz OUT2 AMPLITUDE = 0dBFS f = 15.8MHz OUT3 –30 –30 f = 16.2MHz OUT4 –40 –40 SFDR = 75dBc AMPLITUDE = 0dBFS –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 1 6 11 16 21 26 31 36 1 6 11 16 21 26 31 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Single-Tone SFDR Figure 21. Four-Tone SFDR 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9742 V REFIO REFIO PMOS I REF CURRENT SOURCE FS ADJ 0.1µF ARRAY V = V – V R SET DIFF OUTA OUTB 2kΩ 3.3V DVDD IOUTA IOUTA V OUTA SEGMENTED SWITCHES LSB DCOM IOUTB IOUTB FOR DB11–DB3 SWITCHES V OUTB R LOAD 50Ω CLOCK R MODE LOAD LATCHES CLOCK 50Ω SLEEP DIGITAL DATA INPUTS (DB11–DB0) Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. B | Page 11 of 32 SFDR (dBc) MAGNITUDE (dBm) 02912-B-016 02912-B-019 MAGNITUDE (dBm) MAGNITUDE (dBm) 02912-B-021 02912-B-020 02912-B-018 AD9742 FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9742. The REFERENCE OPERATION AD9742 consists of a DAC, digital control logic, and full-scale The AD9742 contains an internal 1.2 V band gap reference. The output current control. The DAC contains a PMOS current internal reference can be disabled by raising REFLO to AVDD. source array capable of providing up to 20 mA of full-scale It can also be easily overridden by an external reference with no current (I ). The array is divided into 31 equal currents that OUTFS effect on performance. REFIO serves as either an input or an make up the five most significant bits (MSBs). The next four output depending on whether the internal or an external refer- bits, or middle bits, consist of 15 equal current sources whose ence is used. To use the internal reference, simply decouple the value is 1/16th of an MSB current source. The remaining LSBs REFIO pin to ACOM with a 0.1 µF capacitor and connect are binary weighted fractions of the middle bits current sources. REFLO to ACOM via a resistance less than 5 Ω. The internal Implementing the middle and lower bits with current sources, reference voltage will be present at REFIO. If the voltage at instead of an R-2R ladder, enhances its dynamic performance REFIO is to be used anywhere else in the circuit, an external for multitone or low amplitude signals and helps maintain the buffer amplifier with an input bias current of less than 100 nA DAC’s high output impedance (i.e., >100 kΩ). should be used. An example of the use of the internal reference is shown in Figure 23. All of these current sources are switched to one or the other of 3.3V the two output nodes (i.e., IOUTA or IOUTB) via PMOS differ- OPTIONAL ential current switches. The switches are based on the architec- EXTERNAL REF BUFFER REFLO AVDD 150pF ture that was pioneered in the AD9764 family, with further 1.2V REF refinements to reduce distortion contributed by the switching REFIO transient. This switch architecture also reduces various timing CURRENT ADDITIONAL FS ADJ SOURCE 0.1µF LOAD errors and provides matching complementary drive signals to ARRAY 2kΩ the inputs of the differential current switches. AD9742 The analog and digital sections of the AD9742 have separate Figure 23. Internal Reference Configuration power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 V to 3.6 V range. The digital section, An external reference can be applied to REFIO, as shown in which is capable of operating at a rate of up to 210 MSPS, con- Figure 24. The external reference may provide either a fixed sists of edge-triggered latches and segment decoding logic reference voltage to enhance accuracy and drift performance or circuitry. The analog section includes the PMOS current a varying reference voltage for gain control. Note that the 0.1 µF sources, the associated differential switches, a 1.2 V band gap compensation capacitor is not required since the internal refer- voltage reference, and a reference control amplifier. ence is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. The DAC full-scale output current is regulated by the reference 3.3V control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FS ADJ) pin. The external resistor, in combination with both the refer- REFLO 150pF AVDD ence control amplifier and voltage reference ,VREFIO, sets the AVDD 1.2V REF reference current, IREF, which is replicated to the segmented V REFIO REFIO EXTERNAL current sources with the proper scaling factor. The full-scale CURRENT REF FS ADJ SOURCE current, I , is 32 times I . OUTFS REF ARRAY R I = SET REF V /R REFERENCE REFIO SET AD9742 CONTROL AMPLIFIER Figure 24. External Reference Configuration Rev. B | Page 12 of 32 02912-B-023 02912-B-022 AD9742 REFERENCE CONTROL AMPLIFIER V = IOUTA× R (5) OUTA LOAD The AD9742 contains a control amplifier that is used to regulate V = IOUTB× R (6) OUTB LOAD the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 24, so that its Note that the full-scale value of VOUTA and VOUTB should not current output, I , is determined by the ratio of the V and REF REFIO exceed the specified output compliance range to maintain an external resistor, R , as stated in Equation 4. I is copied to SET REF specified distortion and linearity performance. the segmented current sources with the proper scale factor to , as stated in Equation 3. V =(IOUTA− IOUTB)× R set IOUTFS (7) DIFF LOAD The control amplifier allows a wide (10:1) adjustment span of Substituting the values of IOUTA, IOUTB, I , and V can be REF DIFF IOUTFS over a 2 mA to 20 mA range by setting IREF between expressed as: 62.5 µA and 625 µA. The wide adjustment span of IOUTFS V ={(2× DAC CODE− 4095)/4096} provides several benefits. The first relates directly to the power DIFF (8) dissipation of the AD9742, which is proportional to IOUTFS () 32× R /R ×V LOAD REFIO SET (see the Power Dissipation section). The second relates to the Equations 7 and 8 highlight some of the advantages of operat- 20 dB adjustment, which is useful for system gain control ing the AD9742 differentially. First, the differential operation purposes. helps cancel common-mode error sources associated with The small signal bandwidth of the reference control amplifier is IOUTA and IOUTB, such as noise, distortion, and dc offsets. approximately 500 kHz and can be used for low frequency small Second, the differential code-dependent current and subsequent signal multiplying applications. voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal DAC TRANSFER FUNCTION power to the load. Both DACs in the AD9742 provide complementary current Note that the gain drift temperature performance for a single- outputs, IOUTA and IOUTB. IOUTA provides a near full-scale ended (V and V ) or differential output (V ) of the current output, IOUTFS, when all bits are high (i.e., DAC CODE = OUTA OUTB DIFF AD9742 can be enhanced by selecting temperature tracking 4095), while IOUTB, the complementary output, provides no resistors for R and R due to their ratiometric relationship, current. The current output appearing at IOUTA and IOUTB is LOAD SET as shown in Equation 8. and can be a function of both the input code and IOUTFS expressed as: ANALOG OUTPUTS IOUTA=(DAC CODE/4096)× I (1) OUTFS The complementary current outputs in each DAC, IOUTA, and IOUTB may be configured for single-ended or differential IOUTB=(4095− DAC CODE)/4096× I (2) OUTFS operation. IOUTA and IOUTB can be converted into comple- mentary single-ended voltage outputs, VOUTA and VOUTB, via a where DAC CODE = 0 to 4095 (i.e., decimal representation). load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, As mentioned previously, IOUTFS is a function of the reference existing between VOUTA and VOUTB, can also be converted to a current I , which is nominally set by a reference voltage, V , REF REFIO single-ended voltage via a transformer or differential amplifier and external resistor, R . It can be expressed as: SET configuration. The ac performance of the AD9742 is optimum I = 32× I (3) and specified using a differential transformer-coupled output in OUTFS REF which the voltage swing at IOUTA and IOUTB is limited to where ±0.5 V. I = V /R (4) REF REFIO SET The distortion and noise performance of the AD9742 can be enhanced when it is configured for differential operation. The The two current outputs will typically drive a resistive load common-mode error sources of both IOUTA and IOUTB can directly or via a transformer. If dc coupling is required, IOUTA be significantly reduced by the common-mode rejection of a and IOUTB should be directly connected to matching resistive transformer or differential amplifier. These common-mode loads, R , that are tied to analog common, ACOM. Note that LOAD error sources include even-order distortion products and noise. RLOAD may represent the equivalent load resistance seen by The enhancement in distortion performance becomes more IOUTA or IOUTB as would be the case in a doubly terminated significant as the frequency content of the reconstructed wave- 50 Ω or 75 Ω cable. The single-ended voltage output appearing form increases and/or its amplitude decreases. This is due to the at the IOUTA and IOUTB nodes is simply first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. B | Page 13 of 32 AD9742 Performing a differential-to-single-ended conversion via a The digital interface is implemented using an edge-triggered transformer also provides the ability to deliver twice the master/slave latch. The DAC output updates on the rising edge reconstructed signal power to the load (assuming no source of the clock and is designed to support a clock rate as high as termination). Since the output currents of IOUTA and IOUTB 210 MSPS. The clock can be operated at any duty cycle that are complementary, they become additive when processed dif- meets the specified latch pulse width. The setup and hold times ferentially. A properly selected transformer will allow the can also be varied within the clock cycle as long as the specified AD9742 to provide the required power and voltage levels to minimum times are met, although the location of these transition different loads. edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transi- The output impedance of IOUTA and IOUTB is determined tions on the falling edge of a 50% duty cycle clock. by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in CLOCK INPUT SOIC/TSSOP Packages parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS The 28-lead package options have a single-ended clock input device. As a result, maintaining IOUTA and/or IOUTB at a (CLOCK) that must be driven to rail-to-rail CMOS levels. The virtual ground via an I-V op amp configuration will result in quality of the DAC output is directly related to the clock quality, the optimum dc linearity. Note that the INL/DNL specifications and jitter is a key concern. Any noise or jitter in the clock will for the AD9742 are measured with IOUTA maintained at a vir- translate directly into the DAC output. Optimal performance tual ground via an op amp. will be achieved if the CLOCK input has a sharp rising edge, since the DAC latches are positive edge triggered. IOUTA and IOUTB also have a negative and positive voltage LFCSP Package compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range A configurable clock input is available in the LFCSP package, of −1 V is set by the breakdown limits of the CMOS process. which allows for one single-ended and two differential modes. Operation beyond this maximum limit may result in a break- The mode selection is controlled by the CMODE input, as down of the output stage and affect the reliability of the summarized in Table 6. Connecting CMODE to CLKCOM AD9742. selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK− input is The positive output compliance range is slightly dependent on left floating. If CMODE is connected to CLKVDD, the differen- the full-scale output current, IOUTFS. It degrades slightly from its tial receiver mode is selected. In this mode, both inputs are high nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. impedance. The final mode is selected by floating CMODE. The optimum distortion performance for a single-ended or This mode is also differential, but internal terminations for differential output is achieved when the maximum full-scale positive emitter-coupled logic (PECL) are activated. There is no signal at IOUTA and IOUTB does not exceed 0.5 V. significant performance difference between any of the three clock input modes. DIGITAL INPUTS Table 6. Clock Mode Selection The AD9742 digital section consists of 12 input bit channels CMODE Pin Clock Input Mode and a clock input. The 12-bit parallel data inputs follow stan- dard positive binary coding, where DB11 is the most significant CLKCOM Single-Ended bit (MSB) and DB0 is the least significant bit (LSB). IOUTA CLKVDD Differential produces a full-scale output current when all data bits are at Float PECL Logic 1. IOUTB produces a complementary output with the The single-ended input mode operates in the same way as the full-scale current split between the two outputs as a function of CLOCK input in the 28-lead packages, as described previously. the input code. In the differential input mode, the clock input functions as a DVDD high impedance differential pair. The common-mode level of the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and DIGITAL the differential voltage can be as low as 0.5 V p-p. This mode INPUT can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. Figure 25. Equivalent Digital Input Rev. B | Page 14 of 32 02912-B-024 AD9742 The final clock mode allows for a reduced external component active pull-down circuit that ensures that the AD9742 remains count when the DAC clock is distributed on the board using enabled if this input is left disconnected. The AD9742 takes less PECL logic. The internal termination configuration is shown in than 50 ns to power down and approximately 5 µs to power Figure 26. These termination resistors are untrimmed and can back up. vary up to ±20%. However, matching between the resistors should generally be better than ±1%. POWER DISSIPATION The power dissipation, P , of the AD9742 is dependent on D AD9742 several factors that include: CLK+ CLOCK • The power supply voltages (AVDD, CLKVDD, and DVDD) TO DAC CORE CLK– RECEIVER • The full-scale current output I OUTFS 50Ω 50Ω • The update rate f CLOCK • The reconstructed digital input waveform V = 1.3V NOM TT The power dissipation is directly proportional to the analog Figure 26. Clock Termination in PECL Mode supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 28, and is DAC TIMING insensitive to fCLOCK. Conversely, IDVDD is dependent on both the Input Clock and Data Timing Relationship digital input waveform, fCLOCK, and digital supply DVDD. Figure Dynamic performance in a DAC is dependent on the relation- 29 shows I as a function of full-scale sine wave output ratios DVDD ship between the position of the clock edges and the time at (f /f ) for various update rates with DVDD = 3.3 V. OUT CLOCK which the input data changes. The AD9742 is rising edge 35 triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal 30 when applying the AD9742 is to make the data transition close to the falling clock edge. This becomes more important as the 25 sample rate increases. Figure 27 shows the relationship of SFDR to clock placement with different sample rates. Note that at the 20 lower sample rates, more tolerance is allowed in clock place- ment, while at higher rates, more care must be taken. 15 75 10 70 65 0 2 4 6 8 101214 161820 I (mA) 60 20MHz SFDR OUTFS Figure 28. I vs. I AVDD OUTFS 55 50MHz SFDR 20 50 18 45 16 210MSPS 40 14 50MHz SFDR 12 35 165MSPS –3 –2 –1 0 1 2 3 10 ns 125MSPS 8 Figure 27. SFDR vs. Clock Placement @ f = 20 MHz and 50 MHz OUT 6 Sleep Mode Operation 4 65MSPS The AD9742 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA 2 over the specified supply range of 2.7 V to 3.6 V and tempera- 0 0.01 0.1 1 ture range. This mode can be activated by applying a Logic RATIO (f /f ) OUT CLOCK Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V Rev. B | Page 15 of 32 dB 02912-B-025 02912-B-026 I (mA) I (mA) DVDD AVDD 02912-B-028 02912-B-027 AD9742 12 for impedance matching purposes. Note that the transformer provides ac coupling only. 10 MINI-CIRCUITS DIFF T1-1T IOUTA 22 8 PECL R AD9742 LOAD 6 IOUTB 21 OPTIONAL R DIFF 4 SE Figure 31. Differential Output Using a Transformer 2 The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path 0 0 50 100 150 200 250 for both IOUTA and IOUTB. The complementary voltages f (MSPS) CLOCK appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with Figure 30. ICLKVDD vs. fCLOCK and Clock Mode the specified output compliance range of the AD9742. A differ- APPLYING THE AD9742 ential resistor, R , may be inserted in applications where the DIFF Output Configurations output of the transformer is connected to the load, R , via a LOAD The following sections illustrate some typical output passive reconstruction filter or cable. R is determined by the DIFF configurations for the AD9742. Unless otherwise noted, it is transformer’s impedance ratio and provides the proper source assumed that IOUTFS is set to a nominal 20 mA. For applications termination that results in a low VSWR. Note that approxi- requiring the optimum dynamic performance, a differential mately half the signal power will be dissipated across RDIFF. output configuration is suggested. A differential output configu- DIFFERENTIAL COUPLING USING AN OP AMP ration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides An op amp can also be used to perform a differential-to-single- the optimum high frequency performance and is recommended ended conversion, as shown in Figure 32. The AD9742 is for any application that allows ac coupling. The differential op configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is amp configuration is suitable for applications requiring dc converted to a single-ended signal via the differential op amp coupling, a bipolar output, signal gain, and/or level shifting configuration. An optional capacitor can be installed across within the bandwidth of the chosen op amp. IOUTA and IOUTB, forming a real pole in a low-pass filter. The A single-ended output is suitable for applications requiring a addition of this capacitor also enhances the op amp’s distortion unipolar voltage output. A positive unipolar output voltage will performance by preventing the DAC’s high slewing output from result if IOUTA and/or IOUTB are connected to an appropri- overloading the op amp’s input. ately sized load resistor, R , referred to ACOM. This LOAD 500Ω configuration may be more suitable for a single-supply system AD9742 requiring a dc-coupled, ground-referred output voltage. Alter- 225Ω IOUTA 22 natively, an amplifier could be configured as an I-V converter, AD8047 225Ω thus converting IOUTA or IOUTB into a negative unipolar 21 IOUTB C voltage. This configuration provides the best dc linearity since OPT 500Ω IOUTA or IOUTB is maintained at a virtual ground. 25Ω 25Ω DIFFERENTIAL COUPLING USING A TRANSFORMER Figure 32. DC Differential Coupling Using an Op Amp An RF transformer can be used to perform a differential-to- single-ended signal conversion, as shown in Figure 31. A The common-mode rejection of this configuration is typically differentially coupled transformer output provides the optimum determined by the resistor matching. In this circuit, the differ- distortion performance for output signals whose spectral con- ential op amp circuit using the AD8047 is configured to provide tent lies within the transformer’s pass band. An RF transformer, some additional signal gain. The op amp must operate off a dual such as the Mini-Circuits T1–1T, provides excellent rejection of supply since its output is approximately ±1 V. A high speed common-mode distortion (i.e., even-order harmonics) and amplifier capable of preserving the differential performance of noise over a wide frequency range. It also provides electrical the AD9742 while meeting other system level objectives (e.g., isolation and the ability to deliver twice the power to the load. cost or power) should be selected. The op amp’s differential gain, Transformers with different impedance ratios may also be used gain setting resistor values, and full-scale output swing capabili- ties should all be considered when optimizing this circuit. Rev. B | Page 16 of 32 I (mA) CLKVDD 02912-B-029 02912-B-030 02912-B-031 AD9742 The differential circuit shown in Figure 33 provides the SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT necessary level shifting required in a single-supply system. In CONFIGURATION this case, AVDD, which is the positive analog supply for both Figure 35 shows a buffered single-ended output configuration the AD9742 and the op amp, is also used to level shift the in which the op amp U1 performs an I-V conversion on the differential output of the AD9742 to midsupply (i.e., AVDD/2). AD9742 output current. U1 maintains IOUTA (or IOUTB) at a The AD8041 is a suitable op amp for this application. virtual ground, minimizing the nonlinear output impedance 500Ω effect on the DAC’s INL performance as described in the AD9742 Analog Outputs section. Although this single-ended configura- 225Ω 22 IOUTA tion typically provides the best dc linearity performance, its ac AD8041 225Ω distortion performance at higher DAC update rates may be 21 IOUTB C limited by U1’s slew rate capabilities. U1 provides a negative OPT 1kΩ AVDD unipolar output voltage, and its full-scale output voltage is sim- 25Ω 25Ω 1kΩ ply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS Figure 33. Single-Supply DC Differential Coupled Circuit and/or RFB. An improvement in ac distortion performance may result with a reduced I since U1 will be required to sink less OUTFS SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT signal current. Figure 34 shows the AD9742 configured to provide a unipolar C output range of approximately 0 V to 0.5 V for a doubly termi- OPT nated 50 Ω cable since the nominal full-scale current, IOUTFS, of R FB 20 mA flows through the equivalent RLOAD of 25 Ω. In this case, 200Ω I = 10mA R represents the equivalent load resistance seen by IOUTA OUTFS LOAD AD9742 or IOUTB. The unused output (IOUTA or IOUTB) can be IOUTA 22 U1 V = I × R connected to ACOM directly or via a matching R . Different OUT OUTFS FB LOAD 21 IOUTB values of I and R can be selected as long as the positive OUTFS LOAD 200Ω compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Figure 35. Unipolar Buffered Voltage Output Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is POWER AND GROUNDING CONSIDERATIONS, suggested. POWER SUPPLY REJECTION Many applications seek high speed and high performance I = 20mA AD9742 OUTFS V = 0V TO 0.5V OUTA under less than ideal operating conditions. In these application 22 IOUTA circuits, the implementation and construction of the printed 50Ω 50Ω IOUTB 21 circuit board is as important as the circuit design. Proper RF 25Ω techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to Figure 34. 0 V to 0.5 V Unbuffered Voltage Output ensure optimum performance. Figure 40 to Figure 43 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9742 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, I . AC noise on the dc supplies OUTFS is common in applications where the power distribution is gen- erated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR versus frequency of the AD9742 AVDD supply over this frequency range is shown in Figure 36. Rev. B | Page 17 of 32 02912-B-033 02912-B-032 02912-B-034 AD9742 85 appear as current noise superimposed on the DAC’s full-scale current, I , one must determine the PSRR in dB using Figure 36 80 OUTFS at 250 kHz. To calculate the PSRR for a given R , such that the LOAD 75 units of PSRR are converted from A/V to V/V, adjust the curve in 70 Figure 36 by the scaling factor 20 Ω log (RLOAD). For instance, if 65 RLOAD is 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB VOUT/VIN). 60 55 Proper grounding and decoupling should be a primary objec- tive in any high speed, high resolution system. The AD9742 50 features separate analog and digital supplies and ground pins to 45 optimize the management of analog and digital ground currents 40 in a system. In general, AVDD, the analog supply, should be 0 24 68 10 12 decoupled to ACOM, the analog common, as close to the chip FREQUENCY (MHz) as physically possible. Similarly, DVDD, the digital supply, Figure 36. Power Supply Rejection Ratio (PSRR) should be decoupled to DCOM as close to the chip as physically Note that the ratio in Figure 36 is calculated as amps out/volts possible. in. Noise on the analog power supply has the effect of modulat- For those applications that require a single 3.3 V supply for both ing the internal switches, and therefore the output current. The the analog and digital supplies, a clean analog supply may be voltage noise on AVDD, therefore, will be added in a nonlinear generated using the circuit shown in Figure 37. The circuit con- manner to the desired IOUT. Due to the relative different size sists of a differential LC filter with separate power supply and of these switches, the PSRR is very code dependent. This can return lines. Lower noise can be attained by using low ESR type produce a mixing effect that can modulate low frequency power electrolytic and tantalum capacitors. supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs will occur when the full- FERRITE BEADS scale current is directed toward that output. As a result, the AVDD TTL/CMOS LOGIC PSRR measurement in Figure 36 represents a worst-case condi- 100µF 10µF–22µF 0.1µF CIRCUITS ELECT. TANT. CER. tion in which the digital inputs remain static and the full-scale ACOM output current of 20 mA is directed to the DAC output being measured. 3.3V An example serves to illustrate the effect of supply noise on the POWER SUPPLY analog supply. Suppose a switching regulator with a switching Figure 37. Differential LC Filter for Single 3.3 V Applications frequency of 250 kHz produces 10 mV of noise and, for simplic- ity’s sake (ignoring harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will Rev. B | Page 18 of 32 PSRR (dB) 02912-B-035 02912-B-036 AD9742 EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP pack- ages. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9742 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9742 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9742 with either the internal or external reference or to exercise the power-down feature. J1 21 DB13X 4 3 DB12X 65 DB11X 87 DB10X RP5 RP1 10 9 OPT OPT DB9X 12 11 DB8X 14 13 DB7X RP3 22Ω 1 16 DB13X DB13 16 15 DB6X RP3 22Ω 2 15 DB12X DB12 18 17 DB5X RP3 22Ω 3 14 DB11X DB11 20 19 DB4X RP3 22Ω 4 13 DB10X DB10 22 21 DB3X RP3 22Ω 5 12 DB9X DB9 24 23 DB2X RP3 22Ω 6 11 DB8X DB8 26 25 DB1X RP3 22Ω 7 10 DB7X DB7 28 27 DB0X RP3 22Ω 8 9 DB6X DB6 30 29 RP4 22Ω 1 16 DB5X DB5 32 31 JP3 RP4 22Ω 2 15 DB4X DB4 34 33 CKEXTX RP4 22Ω 3 14 DB3X DB3 36 35 RP4 22Ω 4 13 DB2X DB2 38 37 RP4 22Ω 5 12 DB1X DB1 40 39 RP4 22Ω 6 11 DB0X DB0 RP4 22Ω 7 10 RP4 22Ω 8 9 CKEXTX CKEXT RIBBON RP6 RP2 RED OPT OPT L2 BEAD TP2 TB1 1 DVDD + C4 C7 C6 10µF BLK BLK BLK 0.1µF 0.1µF 25V TP4 TP7 TP8 TB1 2 RED L3 BEAD TP5 TB1 3 AVDD + C5 C9 C8 10µF BLK BLK BLK 0.1µF 0.1µF 25V TP6 TP10 TP9 TB1 4 Figure 38. SOIC Evaluation Board—Power Supply and Digital Inputs Rev. B | Page 19 of 32 1 DCOM 1 DCOM R1 R1 2 2 R2 R2 3 3 R3 4 4 R3 R4 R4 5 5 R5 R5 6 6 R6 7 7 R6 R7 R7 8 8 R8 R8 9 9 R9 10 10 R9 DCOM DCOM 1 1 R1 R1 2 2 R2 3 3 R3 R3 4 4 R4 R4 5 5 R5 R5 6 6 R6 R6 7 7 R7 R7 8 8 R8 R8 9 9 R9 R9 10 10 02912-B-037 R2 AD9742 AVDD CUT C14 + UNDER DUT C16 C17 10µF 0.1µF 0.1µF 16V JP6 DVDD + DVDD C15 JP10 C18 C19 10µF 1 3 0.1µF 0.1µF IX A B 16V 2 R5 OPT S2 CLOCK R11 IOUTA 50Ω CKEXT S5 CLOCK DVDD JP4 R4 TP1 50Ω WHT 1 28 R2 C13 DB13 CLOCK DB13 10kΩ OPT 2 27 JP8 DB12 DVDD DB12 DVDD 3 26 DB11 DCOM JP2 IOUT DB11 4 25 DB10 MODE DB10 5 24 MODE 3 4 DB9 DB9 AVDD AVDD T1 6 23 DB8 DB8 RESERVED S3 7 22 2 5 DB7 DB7 IOUTA U1 R6 8 21 DB6 DB6 IOUTB OPT AD9742 9 20 DB5 ACOM 1 6 DB5 10 19 T1-1T DB4 NC DB4 11 18 REF DB3 FS ADJ DB3 TP3 12 17 C1 C2 WHT DB2 REFIO DB2 0.1µF 0.1µF 13 16 DB1 REFLO C12 DB1 JP9 14 15 C11 OPT DB0 SLEEP DB0 R1 0.1µF AVDD 2kΩ 2 R10 AVDD AB SLEEP S1 1 3 50Ω TP11 JP5 INT IOUTB EXT WHT REF R3 2 IY 10kΩ AB 3 1 JP11 Figure 39. SOIC Evaluation Board—Output Signal Conditioning Rev. B | Page 20 of 32 02912-B-038 AD9742 Figure 40. SOIC Evaluation Board—Primary Side Figure 41. SOIC Evaluation Board—Secondary Side Rev. B | Page 21 of 32 02912-B-040 02912-B-039 AD9742 Figure 42. SOIC Evaluation Board—Ground Plane Figure 43. SOIC Evaluation Board—Power Plane Rev. B | Page 22 of 32 02912-B-042 02912-B-041 AD9742 Figure 44. SOIC Evaluation Board Assembly—Primary Side Figure 45. SOIC Evaluation Board Assembly—Secondary Side Rev. B | Page 23 of 32 02912-B-044 02912-B-043 AD9742 RED L1 TP12 BEAD CVDD TB1 1 2 1 DB13X 4 3 BLK DB12X C2 C10 C3 6 5 DB11X 10µF 0.1µF 0.1µF TP2 8 7 6.3V DB10X TB1 2 10 9 DB9X 12 11 DB8X 14 13 RED DB7X L2 16 15 TP13 BEAD DB6X DVDD 18 17 TB3 1 DB5X 20 19 DB4X BLK C7 C4 C6 22 21 DB3X 0.1µF 10µF 0.1µF TP4 24 23 DB2X 6.3V TB3 2 26 25 DB1X 28 27 DB0X RED 30 29 L3 TP5 BEAD 32 31 AVDD JP3 TB4 1 33 34 CKEXTX 36 35 BLK C9 C5 C8 38 37 0.1µF 10µF 0.1µF TP6 6.3V 40 39 TB4 2 J1 R3 R4 R15 R16 R17 R18 R19 R20 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 1 RP3 22Ω 16 DB13X DB13 2 RP3 22Ω 15 DB12X DB12 22Ω 14 3 RP3 DB11X DB11 4 RP3 22Ω 13 DB10 DB10X 5 RP3 22Ω 12 DB9X DB9 6 RP3 22Ω 11 DB8X DB8 22Ω 10 7 RP3 DB7 DB7X 8 RP3 22Ω 9 DB6X DB6 1 RP4 22Ω 16 DB5X DB5 2 RP4 22Ω 15 DB4 DB4X 22Ω 14 3 RP4 DB3 DB3X 4 RP4 22Ω 13 DB2X DB2 5 RP4 22Ω 12 DB1 DB1X 6 RP4 22Ω 11 DB0X DB0 7 RP4 22Ω 10 8 RP4 22Ω 9 CKEXT CKEXTX R21 R24 R25 R26 R27 R28 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω Figure 46. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs Rev. B | Page 24 of 32 HEADER STRAIGHT UP MALE NO SHROUD 02912-B-045 AD9742 AVDD DVDD CVDD C17 C19 C19 C32 0.1 0.1µF 0.1µF 0.1µF SLEEP TP11 WHT R29 10kΩ 32 1 DB7 DB8 DB7 DB8 R11 2 31 DB6 DB9 DB6 DB9 50Ω 30 3 DVDD DB10 DVDD DB10 DNP 4 29 DB5 DB11 DB5 DB11 C13 5 28 DB4 DB12 DB4 DB12 27 6 DB3 DB3 DB13 DB13 7 26 TP3 TP1 JP8 DB2 DB2 DCOM1 25 8 DB1 SLEEP DB1 IOUT WHT WHT 9 24 DB0 FS ADJ DB0 10 23 DCOM REFIO 3 4 T1 U1 11 22 CVDD ACOM CVDD S3 12 21 CLK IA CLK 2 5 AGND: 3, 4, 5 13 20 CLKB IB CLKB 6 14 19 CCOM ACOM1 1 15 18 CMODE C11 T1 – 1T AVDD AVDD CMODE 16 17 0.1µF MODE AVDD1 JP9 AD9744LFCSP DNP C12 TP7 R30 10kΩ WHT R10 CVDD 50Ω R1 2kΩ JP1 0.1% MODE Figure 47. LFCSP Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 C20 C35 2 10µF 0.1µF 16V AGND: 5 CVDD: 8 CVDD R5 120Ω 3 CLKB 6 U4 JP2 4 S5 CKEXT AGND: 3, 4, 5 C34 AGND: 5 0.1µF CVDD: 8 CLK R2 R6 120Ω 50Ω Figure 48. LFCSP Evaluation Board Schematic—Clock Input Rev. B | Page 25 of 32 02912-B-047 02912-B-046 AD9742 Figure 49. LFCSP Evaluation Board Layout—Primary Side Figure 50. LFCSP Evaluation Board Layout—Secondary Side Rev. B | Page 26 of 32 02912-B-049 02912-B-048 AD9742 Figure 51. LFCSP Evaluation Board Layout—Ground Plane Figure 52. LFCSP Evaluation Board Layout—Power Plane Rev. B | Page 27 of 32 02912-B-051 02912-B-050 AD9742 Figure 53. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev. B | Page 28 of 32 02912-B-053 02912-B-052 AD9742 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 COPLANARITY 0.19 SEATING 0.09 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 55. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) × 45° 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8° 1.27 (0.0500) SEATING 0.51 (0.0201) 0° 1.27 (0.0500) COPLANARITY 0.32 (0.0126) BSC PLANE 0.33 (0.0130) 0.40 (0.0157) 0.10 0.23 (0.0091) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56. 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) Rev. B | Page 29 of 32 AD9742 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC 3.25 4.75 TOP BOTTOM VIEW BSC SQ 3.10 SQ VIEW 2.95 0.50 17 0.40 8 16 9 0.30 0.25 MIN 3.50 REF 0.80 MAX 12° MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.30 COPLANARITY 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE 1 Models Temperature Range Package Description Package Options AD9742AR −40°C to +85°C 28-Lead 300-Mil SOIC R-28 AD9742ARRL −40°C to +85°C 28-Lead 300-Mil SOIC R-28 2 AD9742ARZ −40°C to +85°C 28-Lead 300-Mil SOIC R-28 2 AD9742ARZRL −40°C to +85°C 28-Lead 300-Mil SOIC R-28 AD9742ARU −40°C to +85°C 28-Lead TSSOP RU-28 AD9742ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28 2 AD9742ARUZ −40°C to +85°C 28-Lead TSSOP RU-28 2 AD9742ARUZRL7 −40°C to +85°C 28-Lead TSSOP RU-28 AD9742ACP −40°C to +85°C 32-Lead LFCSP CP-32-2 AD9742ACPRL7 −40°C to +85°C 32-Lead LFCSP CP-32-2 2 AD9742ACPZ −40°C to +85°C 32-Lead LFCSP CP-32-2 2 AD9742ACPZRL7 −40°C to +85°C 32-Lead LFCSP CP-32-2 AD9742-EB Evaluation Board (SOIC) AD9742ACP-PCB Evaluation Board (LFCSP) 1 R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package. 2 Z = Pb-free part. Rev. B | Page 30 of 32 AD9742 NOTES Rev. B | Page 31 of 32 AD9742 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. C02912–0–6/04(B) Rev. B | Page 32 of 32