ANALOG DEVICES AD9740

® 10-Bit, 210 MSPS TxDAC D/A Converter AD9740 FEATURES APPLICATIONS High performance member of pin-compatible Wideband communication transmit channel TxDAC product family Direct IF Excellent spurious-free dynamic range performance Base stations SNR @ 5 MHz output, 125 MSPS: 65 dB Wireless local loops Twos complement or straight binary data format Digital radio links Differential current outputs: 2 mA to 20 mA Direct digital synthesis (DDS) Power dissipation: 135 mW @ 3.3 V Instrumentation Power-down mode: 15 mW @ 3.3 V FUNCTIONAL BLOCK DIAGRAM On-chip 1.2 V Reference 3.3V CMOS-compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP REFLO AVDD ACOM 150pF 1.2V REF packages 0.1μF AD9740 REFIO CURRENT Edge-triggered latches SOURCE FS ADJ ARRAY R SET 3.3V DVDD IOUTA SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES CLOCK MODE CLOCK LATCHES DIGITAL DATA INPUTS (DB9–DB0) SLEEP Figure 1. GENERAL DESCRIPTION 1 The AD9740 is a 10-bit resolution, wideband, third generation Edge-triggered input latches and a 1.2 V temperature-compensated member of the TxDAC series of high performance, low power band gap reference have been integrated to provide a complete CMOS digital-to-analog converters (DACs). The TxDAC monolithic DAC solution. The digital inputs support 3 V CMOS family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit logic families. DACs, is specifically optimized for the transmit signal path PRODUCT HIGHLIGHTS of communication systems. All of the devices share the same 1. The AD9740 is the 10-bit member of the pin-compatible interface options, small outline package, and pinout, providing TxDAC family, which offers excellent INL and DNL an upward or downward component selection path based performance. on performance, resolution, and cost. The AD9740 offers 2. Data input supports twos complement or straight binary exceptional ac and dc performance while supporting update data coding. rates up to 210 MSPS. 3. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. The AD9740’s low power dissipation makes it well suited for 4. Low power: Complete CMOS DAC function operates on portable and low power applications. Its power dissipation 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- can be further reduced to 60 mW with a slight degradation in scale current can be reduced for lower power operation, performance by lowering the full-scale current output. In and a sleep mode is provided for low power idle periods. addition, a power-down mode reduces the standby power 5. On-chip voltage reference: The AD9740 includes a 1.2 V dissipation to approximately 15 mW. A segmented current temperature-compensated band gap voltage reference. source architecture is combined with a proprietary switching 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32- technique to reduce spurious components and enhance lead LFCSP packages. dynamic performance. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02911-001 AD9740 TABLE OF CONTENTS Features .............................................................................................. 1 DAC Transfer Function ............................................................. 14 Applications....................................................................................... 1 Analog Outputs .......................................................................... 14 Functional Block Diagram .............................................................. 1 Digital Inputs .............................................................................. 15 General Description ......................................................................... 1 Clock Input.................................................................................. 15 Product Highlights ........................................................................... 1 DAC Timing................................................................................ 16 Revision History ............................................................................... 3 Power Dissipation....................................................................... 16 Specifications..................................................................................... 4 Applying the AD9740 ................................................................ 17 DC Specifications ......................................................................... 4 Differential Coupling Using a Transformer............................... 17 Dynamic Specifications ............................................................... 5 Differential Coupling Using an Op Amp................................ 18 Digital Specifications ................................................................... 6 Single-Ended, Unbuffered Voltage Output............................. 18 Absolute Maximum Ratings............................................................ 7 Single-Ended, Buffered Voltage Output Configuration........ 18 Thermal Characteristics .............................................................. 7 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 19 ESD Caution.................................................................................. 7 Evaluation Board ............................................................................ 20 Pin Configurations and Function Descriptions ........................... 8 General Description................................................................... 20 Terminology ...................................................................................... 9 Outline Dimensions ....................................................................... 30 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 31 Functional Description .................................................................. 13 Reference Operation .................................................................. 13 Reference Control Amplifier .................................................... 14 Rev. B | Page 2 of 32 AD9740 REVISION HISTORY 12/05—Rev. A to Rev. B 5/03—Rev. 0 to Rev. A Updated Format.................................................................. Universal Added 32-Lead LFCSP Package ....................................... Universal Changes to General Description and Product Highlights...........1 Edits to Features ................................................................................1 Changes to Table 1 ............................................................................4 Edits to Product Highlights .............................................................1 Changes to Table 2 ............................................................................5 Edits to DC Specifications ...............................................................2 Changes to Table 5 ............................................................................8 Edits to Dynamic Specifications .....................................................3 Changes to Figure 6.........................................................................10 Edits to Digital Specifications..........................................................4 Inserted Figure 11; Renumbered Sequentially ............................10 Edits to Absolute Maximum Ratings..............................................5 Changes to Figure 12, Figure 13, Figure 14, and Figure 15 .......11 Edits to Thermal Characteristics ....................................................5 Changes to Functional Description and Reference Edits to Ordering Guide...................................................................5 Operation Sections..........................................................................13 Edits to Pin Configuration...............................................................6 Inserted Figure 23; Renumbered Sequentially ............................13 Edits to Pin Function Descriptions ................................................6 Changes to DAC Transfer Function Section and Figure 25 ......14 Edits to Figure 2 ................................................................................7 Changes to Digital Inputs Section.................................................15 Replaced TPCs 1, 4, 7, and 8............................................................8 Changes to Figure 30 and Figure 31 .............................................17 Edits to Figure 3 ..............................................................................10 Updated Outline Dimensions........................................................30 Edits to Functional Description Section......................................10 Changes to Ordering Guide...........................................................31 Edits to Digital Inputs Section.......................................................12 Added Clock Input Section............................................................12 Added Figure 7 ................................................................................12 Edits to DAC Timing Section........................................................12 Edits to Sleep Mode Operation Section .......................................13 Edits to Power Dissipation Section...............................................13 Renumbered Figures 8 to 26..........................................................13 Added Figure 11 ..............................................................................13 Added Figures 27 to 35...................................................................21 Updated Outline Dimensions........................................................26 5/02—Revision 0: Initial Version Rev. B | Page 3 of 32 AD9740 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) −0.7 ±0.15 +0.7 LSB Differential Nonlinearity (DNL) −0.5 ±0.12 +0.5 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error (Without Internal Reference) −2 ±0.1 +2 % of FSR Gain Error (With Internal Reference) −2 ±0.1 +2 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (External Reference) 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 2.7 3.3 3.6 V DVDD 2.7 3.3 3.6 V CLKVDD 2.7 3.3 3.6 V Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 8 9 mA DVDD Clock Supply Current (I ) 5 6 mA CLKVDD Supply Current Sleep Mode (IAVDD) 5 6 mA 4 Power Dissipation 135 145 mW 5 Power Dissipation 145 mW 6 Power Supply Rejection Ratio—AVDD −1 +1 % of FSR/V 6 Power Supply Rejection Ratio—DVDD −0.04 +0.04 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f = 25 MSPS and f = 1 MHz. CLOCK OUT 5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz. 6 ±5% power supply variation. Rev. B | Page 4 of 32 AD9740 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) 210 MSPS 1 Output Settling Time (tST) (to 0.1%) 11 ns Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns 2 Output Noise (IOUTFS = 20 mA) 50 pA/√Hz 2 Output Noise (I = 2 mA) 30 pA/√Hz OUTFS 3 Noise Spectral Density −143 dBm/Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output 71 79 dBc −6 dBFS Output 75 dBc −12 dBFS Output 67 dBc −18 dBFS Output 61 dBc f = 65 MSPS; f = 1.00 MHz 84 dBc CLOCK OUT f = 65 MSPS; f = 2.51 MHz 80 dBc CLOCK OUT f = 65 MSPS; f = 10 MHz 78 dBc CLOCK OUT fCLOCK = 65 MSPS; fOUT = 15 MHz 76 dBc fCLOCK = 65 MSPS; fOUT = 25 MHz 75 dBc f = 165 MSPS; f = 21 MHz 70 dBc CLOCK OUT f = 165 MSPS; f = 41 MHz 60 dBc CLOCK OUT f = 210 MSPS; f = 40 MHz 67 dBc CLOCK OUT fCLOCK = 210 MSPS; fOUT = 69 MHz 63 dBc Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span 80 dBc f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 90 dBc CLOCK OUT f = 65 MSPS; f = 5.03 MHz; 2.5 MHz Span 90 dBc CLOCK OUT f = 125 MSPS; f = 5.04 MHz; 4 MHz Span 90 dBc CLOCK OUT Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz −79 −71 dBc fCLOCK = 50 MSPS; fOUT = 2.00 MHz −77 dBc f = 65 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT f = 125 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 68 dB fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 64 dB f = 125 MSPS; f = 5 MHz; I = 20 mA 64 dB CLOCK OUT OUTFS f = 125 MSPS; f = 5 MHz; I = 5 mA 62 dB CLOCK OUT OUTFS f = 165 MSPS; f = 5 MHz; I = 20 mA 64 dB CLOCK OUT OUTFS fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 62 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 63 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 60 dB Rev. B | Page 5 of 32 AD9740 Parameter Min Typ Max Unit Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output 65 dBc −6 dBFS Output 66 dBc −12 dBFS Output 60 dBc −18 dBFS Output 55 dBc 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit 1 DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (tH) 1.5 ns Latch Pulse Width (tLPW) 1.5 ns 2 CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. 2 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode. DB0–DB9 t t S H CLOCK t LPW t PD t ST IOUTA 0.1% OR 0.1% IOUTB Figure 2. Timing Diagram Rev. B | Page 6 of 32 02911-002 AD9740 ABSOLUTE MAXIMUM RATINGS Table 4. 1 THERMAL CHARACTERISTICS With Thermal Resistance Parameter Respect to Min Max Unit 28-Lead 300-Mil SOIC AVDD ACOM −0.3 +3.9 V θJA = 55.9°C/W DVDD DCOM −0.3 +3.9 V 28-Lead TSSOP CLKVDD CLKCOM −0.3 +3.9 V θJA = 67.7°C/W ACOM DCOM −0.3 +0.3 V 32-Lead LFCSP ACOM CLKCOM −0.3 +0.3 V θ = 32.5°C/W JA DCOM CLKCOM −0.3 +0.3 V 1 Thermal impedance measurements were taken on a 4-layer board in still air, AVDD DVDD −3.9 +3.9 V in accordance with EIA/JESD51-7. AVDD CLKVDD −3.9 +3.9 V DVDD CLKVDD −3.9 +3.9 V CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V Junction 150 °C Temperature Storage −65 +150 °C Temperature Range Lead Temperature 300 °C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 32 AD9740 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS (MSB) DB9 1 28 CLOCK 2 27 DB8 DVDD 3 26 DB7 DCOM DB6 4 25 MODE 5 24 DB5 AVDD DB3 1 24 FS ADJ 6 23 DB4 RESERVED PIN 1 AD9740 DB2 2 23 REFIO INDICATOR 7 22 DVDD 3 22 ACOM DB3 TOP VIEW IOUTA DB1 4 21 IOUTA AD9740 (Not to Scale) 8 21 DB2 IOUTB DB0 5 20 IOUTB TOP VIEW NC 6 19 ACOM DB1 9 20 ACOM (Not to Scale) NC 7 18 AVDD 10 19 DB0 NC NC 8 17 AVDD 11 18 NC FS ADJ 12 17 NC REFIO 13 16 NC REFLO 14 15 NC SLEEP NC = NO CONNECT NC = NO CONNECT Figure 3. 28-Lead SOIC and TSSOP Pin Configuration Figure 4. 32-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SOIC/TSSOP LFCSP Pin No. Pin No. Mnemonic Description 1 27 DB9 (MSB) Most Significant Data Bit (MSB). 2 to 9 28 to 32, 1, 2, 4 DB8 to DB1 Data Bits 8 to 1. 10 5 DB0 (LSB) Least Significant Data Bit (LSB). 11 to 14, 19 6 to 9 NC No Internal Connection. 15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated if not used. 16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal and external reference operation modes. 17 23 REFIO Reference Input/Output. Serves as reference input when using external reference. Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor to ACOM when using internal reference. 18 24 FS ADJ Full-Scale Current Output Adjust. 20 19, 22 ACOM Analog Common. 21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 N/A RESERVED Reserved. Do Not Connect to Common or Supply. 24 17, 18 AVDD Analog Supply Voltage (3.3 V). 25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). 26 10, 26 DCOM Digital Common. 27 3 DVDD Digital Supply Voltage (3.3 V). 28 N/A CLOCK Clock Input. Data latched on positive edge of clock. N/A 12 CLK+ Differential Clock Input. N/A 13 CLK− Differential Clock Input. N/A 11 CLKVDD Clock Supply Voltage (3.3 V). N/A 14 CLKCOM Clock Common. Rev. B | Page 8 of 32 02911-003 02911-004 32 DB4 NC 9 DCOM 10 31 DB5 CLKVDD 11 30 DB6 CLK+ 12 29 DB7 CLK– 13 28 DB8 CLKCOM 14 27 DB9 (MSB) CMODE 15 26 DCOM MODE 16 25 SLEEP AD9740 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the The maximum change in the full-scale output as the supplies actual analog output from the ideal output, determined by a are varied from nominal to minimum and maximum specified straight line drawn from zero to full scale. voltages. Differential Nonlinearity (or DNL) Settling Time The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input code. start of the output transition. Monotonicity Glitch Impulse A DAC is monotonic if the output either increases or remains Asymmetrical switching times in a DAC give rise to undesired constant as the digital input increases. output transients that are quantified by a glitch impulse. It is Offset Error specified as the net area of the glitch in pV-s. The deviation of the output current from the ideal of zero is Spurious-Free Dynamic Range called the offset error. For IOUTA, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when the inputs are all 0s. For IOUTB, 0 mA output is expected signal and the peak spurious signal over the specified bandwidth. when all inputs are set to 1s. TTotal Harmonic Distortion (THD) Gain Error THD is the ratio of the rms sum of the first six harmonic The difference between the actual and ideal output span. The components to the rms value of the measured input signal. It is actual span is determined by the output when all inputs are set expressed as a percentage or in decibels (dB). to 1s minus the output when all inputs are set to 0s. Multitone Power Ratio Output Compliance Range The spurious-free dynamic range containing multiple carrier The range of allowable voltage at the output of a current output tones of equal amplitude. It is measured as the difference DAC. Operation beyond the maximum compliance limits can between the rms amplitude of a carrier tone to the peak cause either output stage saturation or breakdown, resulting in spurious signal in the region of a removed tone. nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9740 0.1μF REFIO PMOS FS ADJ CURRENT SOURCE ARRAY MINI-CIRCUITS R SET T1-1T ROHDE & SCHWARZ 2kΩ 3.3V DVDD IOUTA FSEA30 SEGMENTED SWITCHES LSB SPECTRUM DCOM IOUTB FOR DB9–DB1 SWITCHES ANALYZER CLOCK MODE LATCHES DVDD 50Ω SLEEP 50Ω DCOM RETIMED 50Ω CLOCK DIGITAL OUTPUT* DATA CLOCK *AWG2021 CLOCK RETIMED OUTPUT SO THAT THE DIGITAL DATA LECROY 9210 TEKTRONIX AWG-2021 TRANSITIONS ON FALLING EDGE PULSE GENERATOR WITH OPTION 4 OF 50% DUTY CYCLE CLOCK. Figure 5. Basic AC Characterization Test Setup (SOIC/TSSOP Packages) Rev. B | Page 9 of 32 02911-005 AD9740 TYPICAL PERFORMANCE CHARACTERISTICS 95 95 210MSPS (LFCSP) 90 90 125MSPS 0dBFS 85 85 165MSPS (LFCSP) 80 80 75 75 –6dBFS 65MSPS 70 70 125MSPS (LFCSP) 65 65 –12dBFS 60 60 210MSPS 55 55 165MSPS 50 50 45 45 0 10 100 02 100 30 40 50 60 f (MHz) OUT f (MHz) OUT Figure 6. SFDR vs. f @ 0 dBFS Figure 9. SFDR vs. fOUT @ 165 MSPS OUT 95 95 90 90 85 85 80 80 0dBFS 20mA 75 75 10mA –6dBFS 70 70 –12dBFS 5mA 65 65 60 60 55 55 50 50 45 45 0 5 10 15 20 25 0151052025 f (MHz) f (MHz) OUT OUT Figure 7. SFDR vs. fOUT @ 65 MSPS Figure 10. SFDR vs. f and I @ 65 MSPS and 0 dBFS OUT OUTFS 95 95 90 90 0dBFS 0dBFS (LFCSP) 85 85 –12dBFS (LFCSP) 80 80 75 75 –6dBFS (LFCSP) –6dBFS 70 70 –12dBFS 0dBFS 65 65 60 60 –12dBFS 55 55 –6dBFS 50 50 45 45 0152 0 150 25 30 35 40 45 02 100 30 40 50 60 70 80 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. f @ 125 MSPS Figure 11. SFDR vs. fOUT @ 210 MSPS OUT Rev. B | Page 10 of 32 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02911-006 02911-008 02911-007 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02911-009 02911-054 02911-010 AD9740 95 95 165MSPS 90 125MSPS 125MSPS 85 85 65MSPS 165MSPS 80 65MSPS 75 75 210MSPS (LFCSP) 70 210MSPS (29, 31) 210MSPS (29, 31) LFCSP 210MSPS 65 65 78MSPS 60 55 55 50 45 45 –25 –20 –15 –10 –5 0 –25 –20 –15 –10 –5 0 A (dBFS) A (dBFS) OUT OUT Figure 12. Single-Tone SFDR vs. A @ f = f /11 Figure 15. Dual-Tone IMD vs. A @ f = f /7 OUT OUT CLOCK OUT OUT CLOCK 95 0.25 90 0.15 85 65MSPS 125MSPS 80 210MSPS (LFCSP) 0.05 75 70 –0.05 65 165MSPS 60 –0.15 210MSPS 55 50 –0.25 45 0 256 512 768 1024 –25 –20 –15 –10 –5 0 CODE A (dBFS) OUT Figure 13. Single-Tone SFDR vs. A @ f = f /5 OUT OUT CLOCK Figure 16. Typical INL 90 0.25 85 0.15 80 20mA 75 0.05 20mA (LFCSP) 70 –0.05 65 5mA 60 –0.15 10mA (LFCSP) 10mA 5mA (LFCSP) 55 –0.25 50 0 256 512 768 1024 06 30090 120 180 210 150 CODE f (MSPS) CLOCK Figure 14. SNR vs. f and I @ f = 5 MHz and 0 dBFS Figure 17. Typical DNL CLOCK OUTFS OUT Rev. B | Page 11 of 32 SNR (dB) SFDR (dBc) SFDR (dBc) 02911-013 02911-012 02911-011 SFDR (dBc) ERROR (LSB) ERROR (LSB) 02911-016 02911-015 02911-014 AD9740 90 0 f = 78MSPS CLOCK –10 85 f = 15.0MHz OUT1 f = 15.4MHz OUT2 –20 SFDR = 77dBc 80 AMPLITUDE = 0dBFS –30 4MHz 75 –40 70 –50 19MHz –60 65 34MHz –70 60 –80 49MHz 55 –90 50 –100 –40 –20 0 20 40 60 80 1162 1161 2631 36 TEMPERATURE (°C) FREQUENCY (MHz) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS Figure 20. Dual-Tone SFDR 0 0 f = 78MSPS f = 78MSPS CLOCK CLOCK –10 –10 f = 15.0MHz f = 15.0MHz OUT OUT1 SFDR = 77dBc f = 15.4MHz OUT2 –20 –20 AMPLITUDE = 0dBFS f = 15.8MHz OUT3 –30 –30 f = 16.2MHz OUT4 SFDR = 72dBc AMPLITUDE = 0dBFS –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 1162 1161 2631 36 1162 1161 2631 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Single-Tone SFDR Figure 21. Four-Tone SFDR 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9740 V REFIO REFIO PMOS I REF CURRENT SOURCE FS ADJ 0.1μF ARRAY V = V – V R DIFF OUTA OUTB SET 2kΩ 3.3V DVDD IOUTA IOUTA V OUTA SEGMENTED SWITCHES LSB DCOM IOUTB IOUTB FOR DB9–DB1 SWITCHES V OUTB R LOAD CLOCK 50Ω R LOAD LATCHES MODE CLOCK 50Ω SLEEP DIGITAL DATA INPUTS (DB9–DB0) Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. B | Page 12 of 32 MAGNITUDE (dBm) SFDR (dBc) 02911-018 02911-017 MAGNITUDE (dBm) MAGNITUDE (dBm) 02911-021 02911-020 02911-019 AD9740 FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9740. The REFERENCE OPERATION AD9740 consists of a DAC, digital control logic, and full-scale The AD9740 contains an internal 1.2 V band gap reference. The output current control. The DAC contains a PMOS current internal reference cannot be disabled, but can be easily overridden source array capable of providing up to 20 mA of full-scale by an external reference with no effect on performance. Figure 23 current (I ). The array is divided into 31 equal currents that OUTFS shows an equivalent circuit of the band gap reference. REFIO make up the five most significant bits (MSBs). The next four serves as either an output or an input depending on whether bits, or middle bits, consist of 15 equal current sources whose the internal or an external reference is used. To use the internal value is 1/16 of an MSB current source. The remaining LSBs are reference, simply decouple the REFIO pin to ACOM with a binary weighted fractions of the middle bits current sources. 0.1 μF capacitor and connect REFLO to ACOM via a resistance Implementing the middle and lower bits with current sources, less than 5 Ω. The internal reference voltage is present at instead of an R-2R ladder, enhances its dynamic performance REFIO. If the voltage at REFIO is to be used anywhere else in for multitone or low amplitude signals and helps maintain the the circuit, then an external buffer amplifier with an input bias DAC’s high output impedance (that is, >100 kΩ). current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 24. All of these current sources are switched to one or the other of AVDD the two output nodes (that is, IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the 84µA architecture that was pioneered in the AD9764 family, with REFIO further refinements to reduce distortion contributed by the 7kΩ switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. REFLO Figure 23. Equivalent Circuit of Internal Reference The analog and digital sections of the AD9740 have separate power supply inputs (that is, AVDD and DVDD) that can 3.3V OPTIONAL operate independently over a 2.7 V to 3.6 V range. The digital EXTERNAL REF BUFFER REFLO AVDD section, which is capable of operating at a clock rate of up to 150pF 1.2V REF 210 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS REFIO CURRENT ADDITIONAL FS ADJ SOURCE current sources, the associated differential switches, a 1.2 V 0.1μF LOAD ARRAY band gap voltage reference, and a reference control amplifier. 2kΩ AD9740 The DAC full-scale output current is regulated by the reference Figure 24. Internal Reference Configuration control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust An external reference can be applied to REFIO, as shown in (FS ADJ) pin. The external resistor, in combination with both Figure 25. The external reference can provide either a fixed the reference control amplifier and voltage reference, VREFIO, sets reference voltage to enhance accuracy and drift performance the reference current, IREF, which is replicated to the segmented or a varying reference voltage for gain control. Note that the current sources with the proper scaling factor. The full-scale 0.1 μF compensation capacitor is not required because the current, I , is 32 times I . OUTFS REF internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. Rev. B | Page 13 of 32 02911-057 02911-022 AD9740 3.3V The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, then IOUTA and IOUTB should be directly connected to matching resistive REFLO 150pF AVDD loads, RLOAD, that are tied to analog common, ACOM. Note that 1.2V REF RLOAD can represent the equivalent load resistance seen by REFIO IOUTA or IOUTB, as would be the case in a doubly terminated CURRENT SOURCE FS ADJ 50 Ω or 75 Ω cable. The single-ended voltage output appearing ARRAY at the IOUTA and IOUTB nodes is simply REFERENCE V = IOUTA × R (5) AD9740 CONTROL OUTA LOAD AMPLIFIER V = IOUTB × R (6) OUTB LOAD Figure 25. External Reference Configuration Note that the full-scale value of V and V should not OUTA OUTB REFERENCE CONTROL AMPLIFIER exceed the specified output compliance range to maintain specified distortion and linearity performance. The AD9740 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is VDIFF = (IOUTA − IOUTB) × RLOAD (7) configured as a V-I converter, as shown in Figure 24, so that its Substituting the values of IOUTA, IOUTB, I , and V can be REF DIFF current output, I , is determined by the ratio of the V and REF REFIO expressed as: an external resistor, R , as stated in Equation 4. I is copied SET REF to the segmented current sources with the proper scale factor to V = {(2 × DAC CODE − 1023)/1024} DIFF set I , as stated in Equation 3. /R ) × V (8) OUTFS (32 × RLOAD SET REFIO The control amplifier allows a wide (10:1) adjustment span of Equation 7 and Equation 8 highlight some of the advantages of IOUTFS over a 2 mA to 20 mA range by setting IREF between operating the AD9740 differentially. First, the differential 62.5 μA and 625 μA. The wide adjustment span of IOUTFS operation helps cancel common-mode error sources associated provides several benefits. The first relates directly to the power with IOUTA and IOUTB, such as noise, distortion, and dc dissipation of the AD9740, which is proportional to I (see offsets. Second, the differential code-dependent current and OUTFS the Power Dissipation section). The second relates to a 20 dB subsequent voltage, V , is twice the value of the single-ended DIFF adjustment, which is useful for system gain control purposes. voltage output (that is, V or V ), thus providing twice the OUTA OUTB signal power to the load. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small Note that the gain drift temperature performance for a single- signal multiplying applications. ended (VOUTA and VOUTBB) or differential output (VDIFF) of the AD9740 can be enhanced by selecting temperature tracking DAC TRANSFER FUNCTION resistors for R and R due to their ratiometric relationship, LOAD SET The AD9740 provides complementary current outputs, IOUTA as shown in Equation 8. and IOUTB. IOUTA provides a near full-scale current output, ANALOG OUTPUTS IOUTFS, when all bits are high (that is, DAC CODE = 1023), while IOUTB, the complementary output, provides no current. The The complementary current outputs in each DAC, IOUTA, current output appearing at IOUTA and IOUTB is a function of and IOUTB can be configured for single-ended or differential both the input code and I and can be expressed as: operation. IOUTA and IOUTB can be converted into OUTFS complementary single-ended voltage outputs, V and V , OUTA OUTB IOUTA = (DAC CODE/1023) × I (1) OUTFS , as described in the DAC Transfer via a load resistor, RLOAD IOUTB = (1023 − DAC CODE)/1024 × IOUTFS (2) Function section by Equation 5 through Equation 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can where DAC CODE = 0 to 1023 (that is, decimal representation). also be converted to a single-ended voltage via a transformer or As mentioned previously, IOUTFS is a function of the reference differential amplifier configuration. The ac performance of the current IREF, which is nominally set by a reference voltage, AD9740 is optimum and specified using a differential V , and external resistor, R . It can be expressed as: transformer-coupled output in which the voltage swing at REFIO SET IOUTA and IOUTB is limited to ±0.5 V. I = 32 × I (3) OUTFS REF where The distortion and noise performance of the AD9740 can be I = V /R (4) REF REFIO SET enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a Rev. B | Page 14 of 32 02911-023 AD9740 DVDD transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more DIGITAL significant as the frequency content of the reconstructed INPUT waveform increases and/or its amplitude decreases. This is due to the first-order cancellation of various dynamic common- mode distortion mechanisms, digital feedthrough, and noise. Figure 26. Equivalent Digital Input Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the The digital interface is implemented using an edge-triggered reconstructed signal power to the load (assuming no source master/slave latch. The DAC output updates on the rising edge termination). Because the output currents of IOUTA and of the clock and is designed to support a clock rate as high as IOUTB are complementary, they become additive when 210 MSPS. The clock can be operated at any duty cycle that processed differentially. A properly selected transformer allows meets the specified latch pulse width. The setup and hold times the AD9740 to provide the required power and voltage levels to can also be varied within the clock cycle as long as the specified different loads. minimum times are met, although the location of these transition edges can affect digital feedthrough and distortion performance. The output impedance of IOUTA and IOUTB is determined by Best performance is typically achieved when the input data the equivalent parallel combination of the PMOS switches transitions on the falling edge of a 50% duty cycle clock. associated with the current sources and is typically 100 kΩ in parallel with 5 pF. It is also slightly dependent on the output CLOCK INPUT voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS SOIC/TSSOP Packages device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the The 28-lead package options have a single-ended clock input optimum dc linearity. Note that the INL/DNL specifications for (CLOCK) that must be driven to rail-to-rail CMOS levels. The the AD9740 are measured with IOUTA maintained at a virtual quality of the DAC output is directly related to the clock quality, ground via an op amp. and jitter is a key concern. Any noise or jitter in the clock translates directly into the DAC output. Optimal performance is IOUTA and IOUTB also have a negative and positive voltage achieved if the CLOCK input has a sharp rising edge, because compliance range that must be adhered to in order to achieve the DAC latches are positive edge triggered. optimum performance. The negative output compliance range LFCSP Package of −1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit can result in a A configurable clock input is available in the LFCSP package, breakdown of the output stage and affect the reliability of the which allows for one single-ended and two differential modes. AD9740. The mode selection is controlled by the CMODE input, as summarized in Table 6. Connecting CMODE to CLKCOM The positive output compliance range is slightly dependent on selects the single-ended clock input. In this mode, the CLK+ the full-scale output current, I . It degrades slightly from its OUTFS input is driven with rail-to-rail swings and the CLK− input is nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. left floating. If CMODE is connected to CLKVDD, then the The optimum distortion performance for a single-ended or differential receiver mode is selected. In this mode, both inputs differential output is achieved when the maximum full-scale are high impedance. The final mode is selected by floating signal at IOUTA and IOUTB does not exceed 0.5 V. CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are DIGITAL INPUTS activated. There is no significant performance difference The AD9740 digital section consists of 10 input bit channels between any of the three clock input modes. and a clock input. The 10-bit parallel data inputs follow Table 6. Clock Mode Selection standard positive binary coding, where DB9 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). CMODE Pin Clock Input Mode IOUTA produces a full-scale output current when all data bits CLKCOM Single-ended are at Logic 1. IOUTB produces a complementary output with CLKVDD Differential the full-scale current split between the two outputs as a Float PECL function of the input code. The single-ended input mode operates in the same way as the clock input in the 28-lead packages, as described previously. Rev. B | Page 15 of 32 02911-024 AD9740 75 In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of 70 the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode 65 can be used to drive the clock with a differential sine wave 60 20MHz SFDR because the high gain bandwidth of the differential inputs converts the sine wave into a single-ended square wave internally. 55 50MHz SFDR The final clock mode allows for a reduced external component 50 count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in 45 Figure 27. These termination resistors are untrimmed and can vary up to ±20%. However, matching between the resistors 40 50MHz SFDR should generally be better than ±1%. 35 –3 –2 –1 0 1 2 3 AD9740 ns CLK+ Figure 28. SFDR vs. Clock Placement @ CLOCK f = 20 MHz and 50 MHz (f = 165 MSPS) OUT CLOCK TO DAC CORE RECEIVER CLK– Sleep Mode Operation 50Ω 50Ω The AD9740 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the V = 1.3V NOM TT specified supply range of 2.7 V to 3.6 V and the temperature range. This mode can be activated by applying a Logic Level 1 to the Figure 27. Clock Termination in PECL Mode SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω DAC TIMING AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9740 remains enabled if this Input Clock and Data Timing Relationship input is left disconnected. The AD9740 takes less than 50 ns Dynamic performance in a DAC is dependent on the to power down and approximately 5 μs to power back up. relationship between the position of the clock edges and the time at which the input data changes. The AD9740 is rising POWER DISSIPATION edge triggered, and so exhibits dynamic performance sensitivity The power dissipation, PD, of the AD9740 is dependent on when the data transition is close to this edge. In general, the several factors that include: goal when applying the AD9740 is to make the data transition close to the falling clock edge. This becomes more important as • The power supply voltages (AVDD, CLKVDD, and the sample rate increases. Figure 28 shows the relationship of DVDD) SFDR to clock placement with different sample rates. Note that • The full-scale current output (I ) OUTFS at the lower sample rates, more tolerance is allowed in clock • The update rate (f ) CLOCK placement, while at higher rates, more care must be taken. • The reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current, I , and the digital supply current, I . I AVDD DVDD AVDD is directly proportional to IOUTFS, as shown in Figure 29, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 30 shows IDVDD as a function of full-scale sine wave output ratios (f /f ) for various update rates with DVDD = 3.3 V. OUT CLOCK Rev. B | Page 16 of 32 02911-025 dB 02911-026 AD9740 35 APPLYING THE AD9740 Output Configurations 30 The following sections illustrate some typical output configurations for the AD9740. Unless otherwise noted, it is 25 assumed that I is set to a nominal 20 mA. For applications OUTFS requiring the optimum dynamic performance, a differential 20 output configuration is suggested. A differential output configuration can consist of either an RF transformer or a 15 differential op amp configuration. The transformer configuration provides the optimum high frequency 10 performance and is recommended for any application that allows ac coupling. The differential op amp configuration is 0 2 4 6 8 10 121416 1820 suitable for applications requiring dc coupling, bipolar output, I (mA) OUTFS signal gain, and/or level shifting within the bandwidth of the Figure 29. IAVDD vs. IOUTFS chosen op amp. 20 A single-ended output is suitable for applications requiring a 18 210MSPS unipolar voltage output. A positive unipolar output voltage 16 results if IOUTA and/or IOUTB is connected to an 14 appropriately sized load resistor, R , referred to ACOM. 165MSPS LOAD 12 This configuration can be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. 10 125MSPS Alternatively, an amplifier could be configured as an I-V 8 converter, thus converting IOUTA or IOUTB into a negative 6 65MSPS unipolar voltage. This configuration provides the best dc linearity 4 because IOUTA or IOUTB is maintained at a virtual ground. 2 DIFFERENTIAL COUPLING USING A TRANSFORMER 0 0.01 0.1 1 An RF transformer can be used to perform a differential-to- RATIO (f /f ) OUT CLOCK single-ended signal conversion, as shown in Figure 32. A Figure 30. IDVDD vs. Ratio @ DVDD = 3.3 V differentially coupled transformer output provides the 11 optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An 10 RF transformer, such as the Mini-Circuits® T1–1T, provides 9 DIFF excellent rejection of common-mode distortion (that is, even- 8 order harmonics) and noise over a wide frequency range. It also 7 provides electrical isolation and the ability to deliver twice the 6 PECL power to the load. Transformers with different impedance ratios 5 SE can also be used for impedance matching purposes. Note that 4 the transformer provides ac coupling only. 3 MINI-CIRCUITS 2 T1-1T IOUTA 22 1 0 R 0 50 100 150 200 250 AD9740 LOAD f (MSPS) CLOCK IOUTB 21 Figure 31. ICLKVDD vs. fCLOCK and Clock Mode OPTIONAL R DIFF Figure 32. Differential Output Using a Transformer Rev. B | Page 17 of 32 I (mA) CLKVDD I (mA) AVDD I (mA) DVDD 02911-055 02911-027 02911-056 02911-030 AD9740 500Ω The center tap on the primary side of the transformer must be AD9740 connected to ACOM to provide the necessary dc current path 225Ω 22 IOUTA for both IOUTA and IOUTB. The complementary voltages AD8041 225Ω appearing at IOUTA and IOUTB (that is, VOUTA and VOUTBB) 21 IOUTB C OPT swing symmetrically around ACOM and should be maintained 1kΩ AVDD with the specified output compliance range of the AD9740. A 25Ω 25Ω 1kΩ differential resistor, RDIFF, can be inserted in applications where the output of the transformer is connected to the load, R , LOAD Figure 34. Single-Supply DC Differential Coupled Circuit via a passive reconstruction filter or cable. R is determined DIFF by the transformer’s impedance ratio and provides the proper SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT source termination that results in a low VSWR. Note that Figure 35 shows the AD9740 configured to provide a unipolar approximately half the signal power is dissipated across RDIFF. output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable because the nominal full-scale current, DIFFERENTIAL COUPLING USING AN OP AMP I , of 20 mA flows through the equivalent R of 25 Ω. OUTFS LOAD An op amp can also be used to perform a differential-to-single- In this case, RLOAD represents the equivalent load resistance seen Figure 33. The AD9740 is ended conversion, as shown in by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) configured with two equal load resistors, RLOAD, of 25 Ω. The can be connected to ACOM directly or via a matching RLOAD. differential voltage developed across IOUTA and IOUTB is Different values of IOUTFS and RLOAD can be selected as long as converted to a single-ended signal via the differential op amp the positive compliance range is adhered to. One additional configuration. An optional capacitor can be installed across consideration in this mode is the integral nonlinearity (INL), IOUTA and IOUTB, forming a real pole in a low-pass filter. The discussed in the Analog Outputs section. For optimum INL addition of this capacitor also enhances the op amp’s distortion performance, the single-ended, buffered voltage output performance by preventing the DAC’s high slewing output from configuration is suggested. overloading the op amp’s input. 500Ω I = 20mA OUTFS AD9740 V = 0V TO 0.5V OUTA AD9740 22 IOUTA 225Ω IOUTA 22 50Ω 50Ω 21 IOUTB AD8047 225Ω 21 25Ω IOUTB C OPT 500Ω Figure 35. 0 V to 0.5 V Unbuffered Voltage Output 25Ω 25Ω SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT Figure 33. DC Differential Coupling Using an Op Amp CONFIGURATION Figure 36 shows a buffered single-ended output configuration The common-mode rejection of this configuration is typically in which the op amp U1 performs an I-V conversion on the determined by the resistor matching. In this circuit, the AD9740 output current. U1 maintains IOUTA (or IOUTB) at a differential op amp circuit using the AD8047 is configured to virtual ground, minimizing the nonlinear output impedance provide some additional signal gain. The op amp must operate effect on the DAC’s INL performance as described in the Analog off a dual supply because its output is approximately ±1 V. A Outputs section. Although this single-ended configuration high speed amplifier capable of preserving the differential typically provides the best dc linearity performance, its ac performance of the AD9740 while meeting other system level distortion performance at higher DAC update rates can be objectives (that is, cost or power) should be selected. The op limited by U1’s slew rate capabilities. U1 provides a negative amp’s differential gain, gain setting resistor values, and full-scale unipolar output voltage, and its full-scale output voltage is output swing capabilities should all be considered when simply the product of R and I . The full-scale output FB OUTFS optimizing this circuit. should be set within U1’s voltage output swing capabilities by scaling I and/or R . An improvement in ac distortion The differential circuit shown in Figure 34 provides the OUTFS FB necessary level shifting required in a single-supply system. In performance can result with a reduced IOUTFS because U1 is required to sink less signal current. this case, AVDD, which is the positive analog supply for both the AD9740 and the op amp, is also used to level shift the differential output of the AD9740 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. Rev. B | Page 18 of 32 02911-031 02911-033 02911-032 AD9740 C OPT Note that the ratio in Figure 37 is calculated as amps out/volts R in. Noise on the analog power supply has the effect of modulating FB 200Ω the internal switches, and therefore the output current. The I = 10mA OUTFS AD9740 voltage noise on AVDD, therefore, is added in a nonlinear 22 IOUTA manner to the desired IOUT. Due to the relative different size of U1 V = I × R OUT OUTFS FB these switches, the PSRR is very code dependent. This can produce 21 IOUTB 200Ω a mixing effect that can modulate low frequency power supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs occur when the full-scale current Figure 36. Unipolar Buffered Voltage Output is directed toward that output. POWER AND GROUNDING CONSIDERATIONS, As a result, the PSRR measurement in Figure 37 represents a POWER SUPPLY REJECTION worst-case condition in which the digital inputs remain static Many applications seek high speed and high performance and the full-scale output current of 20 mA is directed to the under less than ideal operating conditions. In these application DAC output being measured. circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF The following illustrates the effect of supply noise on the analog techniques must be used for device selection, placement, and supply. Suppose a switching regulator with a switching frequency routing as well as power supply bypassing and grounding to of 250 kHz produces 10 mV of noise and, for simplicity’s sake ensure optimum performance. Figure 41 to Figure 44 illustrate (ignoring harmonics), all of this noise is concentrated at 250 kHz. the recommended printed circuit board ground, power, and To calculate how much of this undesired noise appears as current signal plane layouts implemented on the AD9740 evaluation noise superimposed on the DAC’s full-scale current, IOUTFS, users board. must determine the PSRR in dB using Figure 37 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR One factor that can measurably affect system performance is are converted from A/V to V/V, adjust the curve in Figure 37 by the ability of the DAC output to reject dc variations or ac noise the scaling factor 20 Ω log (R ). For instance, if R is 50 Ω, LOAD LOAD superimposed on the analog or digital dc power distribution. then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at This is referred to as the power supply rejection ratio (PSRR). 250 kHz, which is 85 dB in Figure 37, becomes 51 dB V /V ). OUT IN For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with Proper grounding and decoupling should be a primary the DAC’s full-scale current, I . AC noise on the dc supplies OUTFS objective in any high speed, high resolution system. The is common in applications where the power distribution is AD9740 features separate analog and digital supplies and generated by a switching power supply. Typically, switching ground pins to optimize the management of analog and digital power supply noise occurs over the spectrum from tens of ground currents in a system. In general, AVDD, the analog kilohertz to several megahertz. The PSRR vs. frequency of the supply, should be decoupled to ACOM, the analog common, as AD9740 AVDD supply over this frequency range is shown in close to the chip as physically possible. Similarly, DVDD, the Figure 37. digital supply, should be decoupled to DCOM as close to the chip as physically possible. 85 80 For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply can be 75 generated using the circuit shown in Figure 38. The circuit 70 consists of a differential LC filter with separate power supply 65 and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. 60 FERRITE 55 BEADS AVDD TTL/CMOS 50 LOGIC 100μF 10μF–22μF 0.1μF CIRCUITS ELECT. TANT. CER. 45 ACOM 40 0 24 68 10 12 FREQUENCY (MHz) 3.3V Figure 37. Power Supply Rejection Ratio (PSRR) POWER SUPPLY Figure 38. Differential LC Filter for Single 3.3 V Applications Rev. B | Page 19 of 32 PSRR (dB) 02911-035 02911-034 02911-036 AD9740 EVALUATION BOARD GENERAL DESCRIPTION This board allows the user the flexibility to operate the AD9740 in various configurations. Possible output configurations The TxDAC family evaluation boards allow for easy setup and include transformer coupled, resistor terminated, and single testing of any TxDAC product in the SOIC and LFCSP packages. and differential outputs. The digital inputs are designed to be Careful attention to layout and circuit design, combined with a driven from various word generators, with the on-board option prototyping area, allows the user to evaluate the AD9740 easily to add a resistor network for proper load termination. Provisions and effectively in any application where high resolution, high are also made to operate the AD9740 with either the internal or speed conversion is required. external reference or to exercise the power-down feature. J1 21 DB13X 4 3 DB12X 65 DB11X 87 DB10X RP5 RP1 10 9 OPT OPT DB9X 12 11 DB8X 14 13 DB7X RP3 22Ω 1 16 DB13X DB13 16 15 DB6X RP3 22Ω 2 15 DB12X DB12 18 17 DB5X RP3 22Ω 3 14 DB11X DB11 20 19 DB4X RP3 22Ω 4 13 DB10X DB10 22 21 DB3X RP3 22Ω 5 12 DB9X DB9 24 23 DB2X RP3 22Ω 6 11 DB8X DB8 26 25 DB1X RP3 22Ω 7 10 DB7X DB7 28 27 DB0X RP3 22Ω 8 9 DB6X DB6 30 29 RP4 22Ω 1 16 DB5X DB5 32 31 JP3 RP4 22Ω 2 15 DB4X DB4 34 33 CKEXTX RP4 22Ω 3 14 DB3X DB3 36 35 RP4 22Ω 4 13 DB2X DB2 38 37 RP4 22Ω 5 12 DB1X DB1 40 39 RP4 22Ω 6 11 DB0X DB0 RP4 22Ω 7 10 RP4 22Ω 8 9 CKEXTX CKEXT RIBBON RP6 RP2 RED OPT OPT L2 BEAD TP2 DVDD TB1 1 C4 + C7 C6 10μF BLK BLK BLK 0.1μF 0.1μF 25V TP4 TP7 TP8 TB1 2 RED L3 BEAD TP5 TB1 3 AVDD + C5 C9 C8 10μF BLK BLK BLK 0.1μF 0.1μF 25V TP6 TP10 TP9 TB1 4 Figure 39. SOIC Evaluation Board—Power Supply and Digital Inputs Rev. B | Page 20 of 32 1 DCOM 1 DCOM R1 R1 2 2 R2 R2 3 3 R3 4 4 R3 R4 R4 5 5 R5 R5 6 6 R6 7 7 R6 R7 R7 8 8 R8 R8 9 9 R9 10 10 R9 DCOM DCOM 1 1 R1 R1 2 2 R2 3 3 R3 R3 4 4 R4 R4 5 5 R5 R5 6 6 R6 R6 7 7 R7 R7 8 8 R8 R8 9 9 R9 R9 10 10 02911-037 R2 AD9740 AVDD CUT +C14 UNDER DUT C16 C17 10μF 0.1μF 0.1μF 16V JP6 DVDD DVDD +C15 JP10 C18 C19 10μF 1 3 0.1μF 0.1μF A IX B 16V 2 R5 OPT S2 CLOCK R11 IOUTA 10kΩ CKEXT S5 CLOCK JP4 DVDD R4 TP1 50Ω WHT R2 1 28 C13 DB13 CLOCK DB13 10kΩ OPT 2 27 JP8 DB12 DVDD DB12 DVDD 3 26 DB11 DCOM JP2 IOUT DB11 4 25 DB10 MODE DB10 5 24 DB9 AVDD MODE 3 4 DB9 AVDD T1 6 23 DB8 DB8 RESERVED S3 7 22 2 5 DB7 DB7 IOUTA R6 U1 21 8 DB6 DB6 IOUTB OPT AD9740 9 20 DB5 DB5 ACOM 1 6 10 19 T1-1T DB4 DB4 NC 11 18 REF DB3 DB3 FS ADJ TP3 12 17 C1 C2 WHT DB2 DB2 REFIO 0.1μF 0.1μF 13 16 DB1 DB1 REFLO C12 JP9 C11 14 15 OPT DB0 SLEEP DB0 R1 0.1μF AVDD 2kΩ 2 R10 AVDD AB SLEEP S1 1 3 10kΩ JP5 TP11 EXT INT IOUTB WHT REF R3 2 IY 10kΩ AB 1 3 JP11 Figure 40. SOIC Evaluation Board—Output Signal Conditioning Rev. B | Page 21 of 32 02911-038 AD9740 Figure 41. SOIC Evaluation Board—Primary Side Figure 42. SOIC Evaluation Board—Secondary Side Rev. B | Page 22 of 32 02911-040 02911-039 AD9740 Figure 43. SOIC Evaluation Board—Ground Plane Figure 44. SOIC Evaluation Board—Power Plane Rev. B | Page 23 of 32 02911-042 02911-041 AD9740 Figure 45. SOIC Evaluation Board Assembly—Primary Side Figure 46. SOIC Evaluation Board Assembly—Secondary Side Rev. B | Page 24 of 32 02911-043 02911-044 AD9740 RED L1 TP12 BEAD CVDD TB1 1 2 1 DB13X 4 3 BLK DB12X C2 C10 C3 6 5 DB11X 10μF 0.1μF 0.1μF TP2 8 7 6.3V DB10X TB1 2 10 9 DB9X 12 11 DB8X 14 13 RED DB7X L2 16 15 TP13 DB6X BEAD DVDD TB3 1 18 17 DB5X 20 19 DB4X BLK C7 C4 C6 22 21 DB3X 0.1μF 10μF 0.1μF TP4 24 23 DB2X 6.3V 26 25 TB3 2 DB1X 28 27 DB0X RED 30 29 L3 TP5 BEAD 32 31 AVDD TB4 1 JP3 33 34 CKEXTX 36 35 BLK C9 C5 C8 38 37 0.1μF 10μF 0.1μF TP6 6.3V 40 39 TB4 2 J1 R3 R4 R15 R16 R17 R18 R19 R20 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 1 RP3 22Ω 16 DB13X DB13 2 RP3 22Ω 15 DB12X DB12 22Ω 14 3 RP3 DB11X DB11 4 RP3 22Ω 13 DB10X DB10 5 RP3 22Ω 12 DB9X DB9 6 RP3 22Ω 11 DB8 DB8X 22Ω 10 7 RP3 DB7X DB7 8 RP3 22Ω 9 DB6 DB6X 1 RP4 22Ω 16 DB5X DB5 2 RP4 22Ω 15 DB4 DB4X 22Ω 14 3 RP4 DB3 DB3X 4 RP4 22Ω 13 DB2 DB2X 22Ω 12 5 RP4 DB1 DB1X 6 RP4 22Ω 11 DB0X DB0 7 RP4 22Ω 10 8 RP4 22Ω 9 CKEXT CKEXTX R21 R24 R25 R26 R27 R28 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω Figure 47. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs Rev. B | Page 25 of 32 HEADER STRAIGHT UP MALE NO SHROUD 02911-045 AD9740 AVDD DVDD CVDD C17 C19 C19 C32 0.1μF 0.1μF 0.1μF SLEEP TP11 WHT R29 10kΩ 32 1 DB7 DB8 DB7 DB8 R11 2 31 DB6 DB9 DB6 DB9 50kΩ 30 3 DVDD DB10 DVDD DB10 DNP 4 29 DB5 DB11 DB5 DB11 C13 5 28 DB4 DB4 DB12 DB12 27 6 DB3 DB3 DB13 DB13 7 26 DB2 DCOM1 TP3 TP1 JP8 DB2 25 8 DB1 SLEEP DB1 WHT WHT IOUT 9 24 DB0 FS ADJ DB0 10 23 DCOM REFIO 3 4 T1 11 U1 22 CVDD ACOM CVDD S3 12 21 CLK IA CLK 2 5 AGND: 3, 4, 5 13 20 CLKB CLKB IB 6 14 19 CCOM ACOM1 1 15 18 CMODE AVDD AVDD C11 T1 – 1T CMODE 16 17 0.1μF MODE AVDD1 JP9 AD9740LFCSP DNP C12 TP7 R30 10kΩ WHT R10 CVDD 50Ω R1 2kΩ JP1 0.1% MODE Figure 48. LFCSP Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 C20 C35 2 10μF 0.1μF 16V AGND: 5 CVDD: 8 CVDD R5 120Ω 3 CLKB 6 U4 JP2 4 S5 CKEXT AGND: 3, 4, 5 C34 AGND: 5 0.1μF CVDD: 8 CLK R2 R6 120Ω 50Ω Figure 49. LFCSP Evaluation Board Schematic—Clock Input Rev. B | Page 26 of 32 02911-047 02911-046 AD9740 Figure 50. LFCSP Evaluation Board Layout—Primary Side Figure 51. LFCSP Evaluation Board Layout—Secondary Side Rev. B | Page 27 of 32 02911-049 02911-048 AD9740 Figure 52. LFCSP Evaluation Board Layout—Ground Plane Figure 53. LFCSP Evaluation Board Layout—Power Plane Rev. B | Page 28 of 32 02911-051 02911-050 AD9740 Figure 54. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 55. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev. B | Page 29 of 32 02911-053 02911-052 AD9740 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 SEATING COPLANARITY 0.19 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 56. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) × 45° 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8° 1.27 (0.0500) SEATING 0.51 (0.0201) 0° 1.27 (0.0500) 0.33 (0.0130) COPLANARITY BSC PLANE 0.31 (0.0122) 0.40 (0.0157) 0.10 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. B | Page 30 of 32 AD9740 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9740AR −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARRL −40°C to +85°C 28-Lead Wide Body SOIC RW-28 1 AD9740ARZ −40°C to +85°C 28-Lead Wide Body SOIC RW-28 1 AD9740ARZRL −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARU −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28 1 AD9740ARUZ −40°C to +85°C 28-Lead TSSOP RU-28 1 AD9740ARUZRL7 −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ACP −40°C to +85°C 32-Lead LFCSP CP-32-2 AD9740ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 1 AD9740ACPZ −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 1 AD9740ACPZRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9740-EB Evaluation Board (SOIC) AD9740ACP-PCB Evaluation Board (LFCSP) 1 Z = Pb-free part. Rev. B | Page 31 of 32 AD9740 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02911–0–12/05(B) Rev. B | Page 32 of 32