ANALOG DEVICES AD9739

14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter Data Sheet AD9739 FEATURES FUNCTIONAL BLOCK DIAGRAM Direct RF synthesis at 2.5 GSPS update rate RESET IRQ DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix mode AD9739 1.2V SDIO Industry leading single/multicarrier IF or RF synthesis SDO SPI f = 350 MHz, ACLR =80 dBc DAC BIAS OUT CS VREF SCLK f = 950 MHz, ACLR = 78 dBc OUT I120 f = 2100 MHz, ACLR = 69 dBc OUT Dual-port LVDS data interface Up to 1.25 GSPS operation Source synchronous DDR clocking IOUTP TxDAC DCI Pin-compatible with the AD9739A CORE IOUTN Multichip synchronization capability Programmable output current: 8.7 mA to 31.7 mA Low power: 1.16 W at 2.5 GSPS APPLICATIONS CLK DISTRIBUTION Broadband communications systems DCO (DIV-BY-4) Military jammers SYNC_OUT SYNC- Instrumentation, automatic test equipment SYNC_IN CONTROLLER Radar, avionics DACCLK Figure 1. GENERAL DESCRIPTION The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) capable of synthesizing wideband 1. Ability to synthesize high quality wideband signals with signals from dc up to 3.0 GHz. Its DAC core features a quad- bandwidths of up to 1.25 GHz in the first or second switch architecture that provides exceptionally low distortion Nyquist zone. performance with an industry-leading direct RF synthesis 2. A proprietary quad-switch DAC architecture provides capability. This feature enables multicarrier generation up to exceptional ac linearity performance while enabling mix the Nyquist frequency in baseband mode as well as second and mode operation. third Nyquist zones in mix mode. The output current can be 3. A dual-port, double data rate, LVDS interface supports the programmed over the 8.66 mA to 31.66 mA range. maximum conversion rate of 2500 MSPS. The inclusion of on-chip controllers simplifies system integration. 4. On-chip controllers manage external and internal clock A dual-port, source synchronous, LVDS interface simplifies the domain skews. digital interface with existing FGPA/ASIC technology. On-chip 5. A multichip synchronization capability. controllers are used to manage external and internal clock domain 6. Programmable differential current output with a 8.66 mA variations over temperature to ensure reliable data transfer from to 31.66 mA range. the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. The AD9739 is manufactured on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DB1[13:0] DB0[13:0] DATA CONTROLLER LVDS DDR LVDS DDR RECEIVER RECEIVER 4-TO-1 DATA ASSEMBLER DATA LATCH DLL (MU CONTROLLER) 07851-001 AD9739 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DCI Phase Alignment Status .................................................... 23  Applications....................................................................................... 1  SYNC_IN Phase Alignment Status.......................................... 23  General Description ......................................................................... 1  Data Receiver Controller Configuration................................. 23  Functional Block Diagram .............................................................. 1  Data Receiver Controller_Data Sample Delay Value ............ 24  Product Highlights ........................................................................... 1  Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation......................................... 24  Revision History ............................................................................... 2  Data Receiver Controller_Delay Line Status and Sync Specifications..................................................................................... 4  Controller SYNC_OUT Status ................................................. 24  DC Specifications ......................................................................... 4  Sync and Data Receiver Controller Lock/Tracking Status.... 25  LVDS Digital Specifications........................................................ 5  CLK Input Common Mode ...................................................... 25  Serial Port Specifications............................................................. 6  Mu Controller Configuration and Status................................ 25  AC Specifications.......................................................................... 7  Part ID ......................................................................................... 26  Absolute Maximum Ratings............................................................ 8  Theory of Operation ...................................................................... 27  Thermal Resistance ...................................................................... 8  LVDS Data Port Interface.......................................................... 28  ESD Caution.................................................................................. 8  Mu Controller ............................................................................. 32  Pin Configurations and Function Descriptions ........................... 9  Interrupt Requests...................................................................... 34  Typical Performance Characteristics ........................................... 12  Multiple Device Synchronization............................................. 35  AC (Normal Mode).................................................................... 12  Analog Interface Considerations.................................................. 38  AC (Mix Mode) .......................................................................... 15  Analog Modes of Operation ..................................................... 38  Terminology .................................................................................... 17  Clock Input Considerations...................................................... 39  Serial Port Interface (SPI) Register............................................... 18  Voltage Reference ....................................................................... 40  SPI Register Map Description................................................... 18  Analog Outputs .......................................................................... 40  SPI Operation.............................................................................. 18  Nonideal Spectral Artifacts....................................................... 43  SPI Register Map............................................................................. 20  Lab Evaluation of the AD9739 ................................................. 44  SPI Port Configuration and Software Reset............................ 22  Power Dissipation and Supply Domains................................. 44  Power-Down LVDS Interface and TxDAC®............................ 22  Recommended Start-Up Sequence .......................................... 45  Controller Clock Disable........................................................... 22  Outline Dimensions....................................................................... 48  Interrupt Request (IRQ) Enable/Status ................................... 22  Ordering Guide .......................................................................... 48  TxDAC Full-Scale Current Setting (I ) and Sleep ........... 23  OUTFS TxDAC Quad-Switch Mode of Operation.............................. 23  REVISION HISTORY 1/12—Rev. A to Rev. B Deleted Static Linearity Section and Figure 7 to Figure 17; Changes to Features Section, Applications Section, General Renumbered Sequentially ............................................................. 11 Description Section, Figure 1, Product Highlights Section........ 1 Changed Dynamic Performance Normal Mode, 20 mA Full Changes to DC Specifications Section........................................... 4 Scale (Unless Otherwise Noted) Section to AC (Normal Mode) Changed Digital Specifications Section to LVDS Digital Section.............................................................................................. 12 Specifications Section....................................................................... 5 Changes to AC (Normal Mode) Section ..................................... 12 Changes to LVDS Digital Specifications Section ......................... 5 Changed Dynamic Performance Mix Mode, 20 mA Full Scale Added Serial Port Specifications Section and Table 3; Section to AC (Mix Mode) Section.............................................. 15 Renumbered Sequentially................................................................ 6 Changes to AC (Mix Mode) Section............................................ 15 Changes to AC Specifications Section ........................................... 7 Added Serial Port Interface (SPI) Register Section, SPI Register Changes to Table 5............................................................................ 8 Map Description Section, Reset Section, Table 8, and SPI Operation Section and Figure 34 ................................................. 18 Changes to Table 7.......................................................................... 10 Rev. B | Page 2 of 48 Data Sheet AD9739 Deleted DOCSIS Performance Section and Changes to Analog Modes of Operation Section .......................38 Figure 46 to Figure 72.....................................................................19 Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39 Added Figure 35 through Figure 38; Renumbered Sequentially....19 Added Clock Input Considerations Section, Figure 58 to Figure 60...........................................................................................39 Changes to SPI Register Map Section and Table 9......................20 Added SPI Port Configuration and Software Reset Section, Deleted Clock Phase Noise Affects on AC Performance Section, Power-Down LVDS Interface and TxDAC® Section, Controller Table 32 to Table 34, Applying Data to the AD9739 Section, and Clock Disable Section, Interrupt Request (IRQ) Enable/Status Figure 87...........................................................................................40 Section, and Table 10 to Table 13 ..................................................22 Moved Figure 61..............................................................................40 Added TxDAC Full-Scale Current Setting (I ) and Sleep Changes to Voltage References Section and Analog Outputs OUTFS Section, TxDAC Quad-Switch Mode of Operation Section, DCI Section ..............................................................................................40 Phase Alignment Status Section, SYNC_IN Phase Alignment Added Equivalent DAC Output and Transfer Function and Figure 63...........................................................................................40 Status Section, Data Receiver Controller Configuration Section, and Table 14 to Table 18 .................................................................23 Deleted Mu Control Operation Section, Search Mode Section, Added Data Receiver Controller_Data Sample Delay Value and Figure 89 ...................................................................................41 Section, Data and Sync Receiver Controller_DCI Delay Moved Figure 64..............................................................................41 Value/Window and Phase Rotation Section, Data Receiver Added Peak DAC Output Power Capability Section and Figure 65. 41 Controller_Delay Line Status and Sync Controller SYNC_OUT Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay Status Section, and Table 19 to Table 21.......................................24 and Phase Readback Section, Operating the Mu Controller Deleted Serial Peripheral Interface Section, General Operation Manually Section, and Calculating Mu Delay Line Step Size Section ..............................................................................................42 of the Serial Interface Section, Instruction Mode (8-Bit Instruction) Section, and Serial Interface Port Pin Description Section.......25 Added Output Stage Configuration Section and Figure 66 to Added Sync and Data Receiver Controller Lock/Tracking Status Figure 70...........................................................................................42 Section, CLK Input Common Mode Section, Mu Controller Added Nonideal Spectral Artifacts Section, Figure 71, and Configuration and Status Section, and Table 22 to Table 24.....25 Table 30.............................................................................................43 Deleted MSB/LSB Transfers Section, Serial Port Configuration Deleted Operation in Master Mode, Figure 93, and Section, and Figure 74 to Figure 79 ..............................................26 Figure 94...........................................................................................44 Added Lab Evaluation of the AD9739 Section, Power Dissipation Added Part ID Section and Table 25 ............................................26 and Supply Domains Section, and Figure 72 to Figure 74.........44 Changes to Theory of Operation Section ....................................27 Added Figure 39 ..............................................................................27 Deleted Figure 95, Operation in Slave Mode Section, and Data Deleted SPI Registers Section and Table 8 to Table 31...............28 Receiver Operation in Auto Mode Section..................................45 Moved and Changes to LVDS Data Port Interface Section .......28 Changes to Recommended Start-Up Sequence Section ............45 Added Figure 40 and Figure 41 .....................................................28 Added Figure 75 ..............................................................................45 Changes to Figure 42 ......................................................................29 Deleted Figure 97, Data Receiver Operation in Manual Mode Moved and Changes to Figure 43..................................................29 Section, Calculating the DCI Delay Line Step Size Section, and Maximum Allowable Data Timing Skew/Jitter Section.............46 Added Data Receiver Controller Initialization Description Added Table 31................................................................................46 Section, Table 26, and Data Receiver Operation at Lower Clock Rates Section ....................................................................................30 Deleted Optimizing the Clock Common-Mode Voltage Section, Added LVDS Driver and Receiver Input Section, Figure 44 to Figure 99, Analog Control Registers Section, Mirror Roll-Off Figure 47, and Table 27...................................................................31 Frequency Control Section, and Figure 101................................47 Changed and Moved Mu Delay Controller Section to Mu Added Table 32................................................................................47 Controller Section ...........................................................................32 Deleted Figure 103, Figure 104, and Figure 106 .........................48 Changes to Mu Controller Section, Figure 48, and Figure 49...32 Updated Outline Dimensions........................................................48 Deleted Figure 107 to Figure 109..................................................49 Added Figure 50 and Table 28 .......................................................32 Added Mu Controller Initialization Description Section..........33 Deleted Table 35 to Table 44..........................................................50 Changes to Interrupt Requests Section ........................................34 Added Table 29 ................................................................................34 7/11—Rev 0 to Rev A Changed Synchronization Controller Section to Multiple Changes to Table 2, DAC CLOCK INPUT (DACCLK_P, Device Synchronization Section....................................................35 DACCLK_N), Added DAC Clock Rate .........................................4 Added Figure 52 ..............................................................................35 Changes to Table 3, Added Dynamic Performance Parameters.......5 Changes to Figure 53 ......................................................................36 Change to Ordering Guide ............................................................53 Added Sync Controller Initialization Description Section........36 Added Synchronization Limitations Section...............................37 2/09—Revision 0: Initial Release Changed Applications Information to Analog Interface Considerations Section...................................................................38 Rev. B | Page 3 of 48 AD9739 Data Sheet SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I = 20 mA. OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 14 Bits ACCURACY Integral Nonlinearity (INL) ±1.3 LSB Differential Nonlinearity (DNL) ±0.8 LSB ANALOG OUTPUTS Gain Error (with Internal Reference) 5.5 % Full-Scale Output Current 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Common-Mode Output Resistance 10 MΩ Differential Output Resistance 70 Ω Output Capacitance 1 pF DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage 1.2 1.6 2.0 V Common-Mode Voltage 900 mV DAC Clock Rate 0.8 2.5 GHz TEMPERATURE DRIFT Gain 60 ppm/°C Reference Voltage 20 ppm/°C REFERENCE Internal Reference Voltage 1.15 1.2 1.25 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES VDDA 3.1 3.3 3.5 V VDDC 1.70 1.8 1.90 V DIGITAL SUPPLY VOLTAGES VDD33 3.10 3.3 3.5 V VDD 1.70 1.8 1.90 V SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS IVDDA 37 38 mA I 159 166 mA VDDC I 34 37 mA VDD33 I 233 238 mA VDD Power Dissipation 0.940 0.975 W Sleep Mode, IVDDA 2.5 2.75 mA Power-Down Mode (Register 0x01 = 0x33 and Register 0x02 = 0x80) I 0.02 mA VDDA I 3.8 mA VDDC IVDD33 0.5 mA IVDD 0.1 mA SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS IVDDA 37 mA IVDDC 223 mA IVDD33 34 mA I 290 mA VDD Power Dissipation 1.16 W Rev. B | Page 4 of 48 Data Sheet AD9739 LVDS DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3- 1996 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit 1 LVDS DATA INPUTS (DB0[13:0], DB1[13:0]) Input Common-Mode Voltage Range, VCOM 825 1575 mV Logic High Differential Input Threshold, VIH_DTH 175 400 mV Logic Low Differential Input Threshold, V −175 −400 mV IL_DTH Receiver Differential Input Impedance, R 80 120 Ω IN Input Capacitance 1.2 pF LVDS Input Rate 1250 MSPS LVDS Minimum Data Valid Period, tVALID (See Figure 41) 344 ps 2 LVDS CLOCK INPUT (DCI and SYNC_IN) Input Common-Mode Voltage Range, VCOM 825 1575 mV Logic High Differential Input Threshold, VIH_DTH 175 400 mV Logic Low Differential Input Threshold, V −175 −400 mV IL_DTH Receiver Differential Input Impedance, R 80 120 Ω IN Input Capacitance 1.2 pF Maximum Clock Rate 625 MHz 3 LVDS CLOCK OUTPUT (DCO and SYNC_OUT) Output Voltage High (x_P or x_N) 1375 mV Output Voltage Low (x_P or x_N) 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, R 80 100 120 Ω O R Single-Ended Mismatch 10 % O Maximum Clock Rate 625 MHz 1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins. 2 DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins. 3 DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination. Rev. B | Page 5 of 48 AD9739 Data Sheet SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3. Parameter Min Typ Max Unit WRITE OPERATION (See Figure 36) SCLK Clock Rate, fSCLK (or /tSCLK) 20 MHz SCLK Clock High, tHI 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, t 2 ns DS SCLK to SDIO Hold Time, t 1 ns DH CS to SCLK Setup Time, tS 3 ns SCLK to CS Hold Time, tH 2 ns READ OPERATION (See Figure 37 and Figure 38) SCLK Clock Rate, fSCLK (or /tSCLK) 20 MHz SCLK Clock High, tHI 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, t 2 ns DS SCLK to SDIO Hold Time, t 1 ns DH 3 ns CS to SCLK Setup Time, tS SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns CS to SDIO (or SDO) Output Valid to High-Z, tEZ 2 ns INPUTS (SDIO, SCLK, CS) Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, I −10 +10 μA IH Current in Low, I −10 +10 μA IL OUTPUT (SDIO) Voltage Out High, V 2.4 3.5 V OH Voltage Out Low, V 0 0.4 V OL Current Out High, I 4 mA OH Current Out Low, IOL 4 mA Rev. B | Page 6 of 48 Data Sheet AD9739 AC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS. Table 4. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE DAC Clock Rate 800 2500 MSPS 1 Adjusted DAC Update Rate 800 2500 MSPS Output Settling Time (tst) to 0.1% 13 ns SPURIOUS-FREE DYNAMIC RANGE (SFDR) fOUT = 100 MHz 69.5 dBc f = 350 MHz 58.5 dBc OUT f = 550 MHz 54 dBc OUT f = 950 MHz 60 dBc OUT TWO-TONE INTERMODULATION DISTORTION (IMD), f = f + 1.25 MHz OUT2 OUT1 f = 100 MHz 94 dBc OUT f = 350 MHz 78 dBc OUT fOUT = 550 MHz 72 dBc fOUT = 950 MHz 68 dBc NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE fOUT = 100 MHz −166 dBm/Hz fOUT = 350 MHz −161 dBm/Hz fOUT = 550 MHz −160 dBm/Hz f = 850 MHz −160 dBm/Hz OUT WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL fDAC = 2457.6 MSPS fOUT = 350 MHz 80/80 dBc f = 2457.6 MSPS, f = 950 MHz 78/79 dBc DAC OUT f = 2457.6 MSPS, f = 1700 MHz (Mix Mode) 74/74 dBc DAC OUT fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix Mode) 69/72 dBc 1 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus, with f = 2500 MSPS, f adjusted = 2500 MSPS. DAC DAC Rev. B | Page 7 of 48 AD9739 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. With θ is specified for the worst-case conditions, that is, a device JA Parameter Respect To Rating soldered in a circuit board for surface-mount packages. VDDA VSSA −0.3 V to +3.6 V Table 6. Thermal Resistance VDD33 VSS −0.3 V to +3.6 V Package Type θ θ Unit JA JC VDD VSS −0.3 V to +1.98 V 1 160-Ball CSP_BGA 31.2 7.0 °C/W VDDC VSSC −0.3 V to +1.98 V 1 With no airflow movement. VSSA VSS −0.3 V to +0.3 V VSSA VSSC −0.3 V to +0.3 V ESD CAUTION VSS VSSC −0.3 V to +0.3 V DACCLK_P, DACCLK_N VSSC −0.3 V to VDDC + 0.18 V DCI, DCO, SYNC_IN, VSS −0.3 V to VDD33 + 0.3 V SYNC_OUT LVDS Data Inputs VSS −0.3 V to VDD33 + 0.3 V IOUTP, IOUTN VSSA −1.0 V to VDDA + 0.3 V I120, VREF VSSA −0.3 V to VDDA + 0.3 V IRQ, CS, SCLK, SDO, VSS −0.3 V to VDD33 + 0.3 V SDIO, RESET Junction Temperature 150°C Storage Temperature −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 48 Data Sheet AD9739 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 19 2 3 4 5 6 7 8 10 11 12 13 14 19 2 3 4 5 6 7 8 10 11 12 13 14 A A B B C C D D E E F F G G H H J J K K L L M M N N P P VDDA, 3.3V, ANALOG SUPPLY VDDC, 1.8V, CLOCK SUPPLY VSSA, ANALOG SUPPLY GROUND VSSC, CLOCK SUPPLY GROUND VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD Figure 4. Digital LVDS Clock Supply Pins (Top View) Figure 2. Analog Supply Pins (Top View) 19 2 3 4 5 6 7 8 10 11 12 13 14 19 2 3 4 5 6 7 8 10 11 12 13 14 A A B B DACCLK_N C C DACCLK_P D D E E F F G G H H SYNC_OUT_P/_N J DCO_P/_N J DCI_P/_N SYNC_IN_P/_N K K L DB1[0:13]P L DB1[0:13]N M M DB0[0:13]P N DB0[0:13]N P N P DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA) VDD, 1.8V, DIGITAL SUPPLY VSS DIGITAL SUPPLY GROUND VDD33, 3.3V DIGITAL SUPPLY Figure 5. Digital LVDS Input, Clock I/O (Top View) Figure 3. Digital Supply Pins (Top View) Rev. B | Page 9 of 48 07851-003 07851-002 07851-004 07851-005 AD9739 Data Sheet 19 2 3 4 5 6 7 8 10 11 12 13 14 A B I120 C VREF IPTAT D E IRQ RESET F CS SDIO G SCLK SDO H J K L M N P Figure 6. Analog I/O and SPI Control Pins (Top View) Table 7. AD9739 Pin Function Descriptions Pin No. Mnemonic Description C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, VSSC Clock Supply Return. C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 VDDA 3.3 V Analog Supply Input. A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Return. A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3, VSSA Shield Analog Supply Return Shield. Tie to VSSA at the DAC. F4, E11, E12, E13, E14, F11, F12 A14 NC No Connect. Do not connect to this pin. A7, B7, C7, D7 IOUTN DAC Negative Current Output Source. A8, B8, C8, D8 IOUTP DAC Positive Current Output Source. B14 I120 Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 μA reference current. C14 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. D14 NC Factory Test Pin. Do not connect to this pin. C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK). F13 IRQ Interrupt Request Open Drain Output. Active high. Pull up to VDD33 with a 10 kΩ resistor. F14 RESET Reset Input. Active high. Tie to VSS if unused. G13 CS Serial Port Enable Input. G14 SDIO Serial Port Data Input/Output. H13 SCLK Serial Port Clock Input. H14 SDO Serial Port Data Output. J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input. G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply. Input. H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Return. J1, J2 SYNC_OUT_P/SYNC_OUT_N Positive/Negative SYNC Output (SYNC_OUT) K1, K2 SYNC_IN_P/SYNC_IN_N Positive/Negative SYNC Input (SYNC_IN) J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO). K13, K14 DCI_P/DCI_N Positive/Negative Data Clock Input (DCI). L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3. L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. Rev. B | Page 10 of 48 IOUTN IOUTP 07851-006 Data Sheet AD9739 Pin No. Mnemonic Description L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11. L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12. L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13. N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13. Rev. B | Page 11 of 48 AD9739 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AC (NORMAL MODE) I = 20 mA, nominal supplies, 25°C, unless otherwise noted. OUTFS START 20MHz STOP 2.4GHz START 20MHz STOP 2.4GHz VBW 10kHz VBW 10kHz Figure 7. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS Figure 10. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS 80 100 1.2GSPS 95 1.6GSPS 75 1.2GSPS 90 70 2.0GSPS 85 80 65 75 60 1.6GSPS 70 2.4GSPS 55 65 2.0GSPS 2.4GSPS 60 50 55 45 50 45 40 40 35 35 30 30 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. f over f Figure 11. IMD vs. f over f OUT DAC OUT DAC –150 –160 –152 –161 –154 –162 –156 –163 –158 –164 2.4GSPS –160 –165 2.4GSPS –166 –162 –164 –167 1.2GSPS –166 –168 1.2GSPS –168 –169 –170 –170 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 f (MHz) f (MHz) OUT OUT Figure 9. Single-Tone NSD over f Figure 12. Eight-Tone NSD over f OUT OUT Rev. B | Page 12 of 48 NSD (dBm/Hz) SFDR (dBc) 10dB/DIV 07851-007 07851-009 07851-008 NSD (dBm/Hz) IMD (dBc) 10dB/DIV 07851-010 07851-012 07851-011 Data Sheet AD9739 f = 2 GSPS, I = 20 mA, nominal supplies, 25°C, unless otherwise noted. DAC OUTFS 110 90 100 80 –6dBFS 90 –6dBFS –3dBFS 70 80 70 60 0dBFS –3dBFS 60 0dBFS 50 50 40 40 30 30 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 16. IMD vs. f over Digital Full Scale OUT Figure 13. SFDR vs. f over Digital Full Scale OUT 90 90 –6dBFS –6dBFS 80 80 –3dBFS 70 70 60 60 0dBFS –3dBFS 0dBFS 50 50 40 40 30 30 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 17. SFDR for Third Harmonic over fOUT vs. Digital Full Scale Figure 14. SFDR for Second Harmonic over fOUT vs. Digital Full Scale 110 90 100 80 20mA FS 90 30mA FS 10mA FS 70 80 70 60 10mA FS 60 20mA FS 30mA FS 50 50 40 40 30 30 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) OUT f (MHz) OUT Figure 18. IMD vs. fOUT over DAC IOUTFS Figure 15. SFDR vs. f over DAC I OUT OUTFS Rev. B | Page 13 of 48 SFDR (dBc) SFDR (dBc) SFDR (dB) 07851-014 07851-015 07851-013 IMD (dBc) SFDR (dB) IMD (dBc) 07851-017 07851-016 07851-018 AD9739 Data Sheet 90 110 100 80 90 +85°C 70 +85°C –40°C 80 60 70 +25°C 60 –40°C +25°C 50 50 40 40 30 30 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 19. SFDR vs. f over Temperature Figure 22. IMD vs. f over Temperature OUT OUT –150 –150 –152 –152 –154 –154 –156 –156 –40°C –158 –158 –160 –160 –162 –162 –40°C +85°C –164 –164 –166 –166 +25°C +85°C –168 –168 +25°C –170 –170 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 20. Single-Tone NSD vs. fOUT over Temperature Figure 23. Eight-Tone NSD vs. f over Temperature OUT –50 –55 –60 –65 –70 FIRST ADJ CH –75 –80 SECOND ADJ CH FIFTH ADJ CH –85 –90 CENTER 350.27MHz SPAN 53.84MHz 0 245.76 491.52 737.28 983.04 1228.80 #RES BW 30kHz SWEEP 174.6ms (601pts) 122.88 368.64 614.40 860.16 1105.90 VBW 300kHz f (MHz) FREQ REF OUT RMS RESULTS OFFSET BW LOWER UPPER CARRIER POWER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) 5 3.84 –79.90 –94.44 –79.03 –93.57 –14.54dBm/ 10 3.84 –80.60 –95.14 –79.36 –94.40 3.84MHz 15 3.84 –80.90 –95.45 –80.73 –95.27 20 3.84 –80.62 –95.16 –80.97 –95.51 25 3.84 –80.76 –95.30 –80.95 –95.49 Figure 24. Four-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Figure 21. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Rev. B | Page 14 of 48 NSD (dBm/Hz) SFDR (dBc) 10dB/DIV 07851-021 07851-019 07851-020 ACLR (dBc) NSD (dBm/Hz) IMD (dBc) 07851-022 07851-024 07851-023 Data Sheet AD9739 AC (MIX MODE) fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted. S ST TART ART 20M 20MH Hz z S ST TOP OP 2. 2.4 4G GHz Hz START 20MHz STOP 2.4GHz #RES BW 10kHz SWEEP 28.7s (601pts) #RES BW 10kHz SWEEP 28.7s (601pts) VBW 10kHz VBW 10kHz Figure 28. Single-Tone Spectrum in Mix Mode at f = 1.31 GHz, Figure 25. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS OUT f = 2.4 GSPS DAC 80 90 75 85 70 80 65 75 60 70 55 65 50 45 60 40 55 35 50 30 45 25 40 20 35 15 10 30 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f (MHz) f (MHz) OUT OUT Figure 26. SFDR in Mix Mode vs. fOUT at 2.4 GSPS Figure 29. IMD in Mix Mode vs. f at 2.4 GSPS OUT –40 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –45 –50 –55 –60 FIRST ADJ CH –65 –70 SECOND ADJ CH –75 FIFTH ADJ CH –80 –85 –90 CENTER 2.10706MHz SPAN 53.84MHz 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 #RES VW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz f (MHz) OUT FREQ REF RMS RESULTS OFFSET BW LOWER UPPER CARRIER POWER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) 5 3.84 –68.99 –90.43 –63.94 –90.37 –21.43dBm/ 10 3.84 –72.09 –93.52 –71.07 –92.50 3.84MHz 15 3.84 –72.86 –94.30 –71.34 –92.77 20 3.84 –74.34 –95.77 –72.60 –94.03 25 3.84 –74.77 –96.20 –73.26 –94.70 Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz, Figure 30. Single-Carrier WCDMA ACLR vs. f at 2457.6 MSPS OUT fDAC = 2457.6 MSPS (Second Nyquist Zone) Rev. B | Page 15 of 48 SFDR (dBc) 10dB/DIV 10dB/DIV 07851-027 07851-025 07851-026 ACLR (dBc) IMD (dBc) 10dB/DIV 07851-028 07851-030 07851-029 AD9739 Data Sheet CENTER 2.807GHz SPAN 53.84MHz CENTER 2.81271GHz SPAN 63.84MHz #RES BW 30kHz SWEEP 174.6ms (601pts) #RES BW 30kHz SWEEP 207ms (601pts) VBW 300kHz VBW 300kHz FREQ REF FREQ REF RMS RESULTS RMS RESULTS OFFSET BW LOWER UPPER OFFSET BW LOWER UPPER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) CARRIER POWER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) CARRIER POWER 5 3.84 –64.90 –89.30 –63.82 –88.22 5 3.84 –0.42 –28.40 –0.10 –28.07 –27.98dBm/ –24.4dBm/ 10 3.84 –66.27 –90.67 –65.70 –90.10 10 3.84 –64.32 –92.30 –0.08 –28.06 3.84MHz 3.84MHz 15 3.84 –68.44 –92.84 –66.55 –90.95 15 3.84 –66.03 –94.01 –65.37 –93.34 20 3.84 –70.20 –94.60 –68.95 –93.35 20 3.84 –66.27 –94.24 –66.06 –94.03 25 3.84 –70.85 –95.25 –70.45 –94.85 25 3.84 –66.82 –94.79 –63.36 –93.34 30 3.84 –67.16 –95.13 –66.54 –94.51 Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, Figure 33. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) fDAC = 2457.6 MSPS (Third Nyquist Zone) CENTER 2.09758GHz SPAN 63.84MHz #RES BW 30kHz SWEEP 207ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER UPPER CARRIER POWER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) 5 3.84 0.22 –25.31 0.24 –25.29 –25.53dBm/ 10 3.84 –66.68 –92.21 0.14 –25.38 3.84MHz 15 3.84 –68.01 –93.53 –66.82 –92.35 20 3.84 –68.61 –94.14 –67.83 –93.36 25 3.84 –68.87 –94.40 –67.64 –93.17 30 3.84 –69.21 –94.74 –68.50 –94.03 Figure 32. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz, f = 2457.6 MSPS (Second Nyquist Zone) DAC Rev. B | Page 16 of 48 10dB/DIV 10dB/DIV 07851-031 07851-032 10dB/DIV 07851-033 Data Sheet AD9739 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Power Supply Rejection (PSR) The maximum deviation of the actual analog output from the The maximum change in the full-scale output as the supplies ideal output, determined by a straight line drawn from 0 to are varied from nominal to minimum and maximum specified full scale. voltages. Differential Nonlinearity (DNL) Spurious-Free Dynamic Range (SFDR) The measure of the variation in analog value, normalized to full The difference, in decibels (dB), between the rms amplitude of scale, associated with a 1 LSB change in digital input code. the output signal and the peak spurious signal over the specified bandwidth. Monotonicity A DAC is monotonic if the output either increases or remains Total Harmonic Distortion (THD) constant as the digital input increases. The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as Offset Error a percentage or in decibels (dB). The deviation of the output current from the ideal of 0 is called the offset error. For IOUTP, 0 mA output is expected when the Noise Spectral Density (NSD) inputs are all 0s. For IOUTN, 0 mA output is expected when all NSD is the converter noise power per unit of bandwidth. This inputs are set to 1. is usually specified in dBm/Hz in the presence of a 0 dBm full-scale signal. Gain Error The difference between the actual and ideal output span. The Adjacent Channel Leakage Ratio (ACLR) actual span is determined by the output when all inputs are set The adjacent channel leakage (power) ratio is a ratio, in dBc, of the to 1 minus the output when all inputs are set to 0. measured power within a channel relative to its adjacent channels. Output Compliance Range Modulation Error Ratio (MER) The range of allowable voltage at the output of a current output Modulated signals create a discrete set of output values referred DAC. Operation beyond the maximum compliance limits may to as a constellation. Each symbol creates an output signal cause either output stage saturation or breakdown, resulting in corresponding to one point on the constellation. MER is a nonlinear performance. measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. Temperature Drift Specified as the maximum change from the ambient (25°C) Intermodulation Distortion (IMD) value to the value at either TMIN or TMAX. For offset and gain IMD is the result of two or more signals at different frequencies drift, the drift is reported in ppm of full-scale range (FSR) mixing together. Many products are created according to the per °C. For reference drift, the drift is reported in ppm per °C. formula, aF1 ± bF2, where a and b are integer values. Rev. B | Page 17 of 48 AD9739 Data Sheet SERIAL PORT INTERFACE (SPI) REGISTER SPI OPERATION SPI REGISTER MAP DESCRIPTION The serial port of the AD9739 shown in Figure 34 has a 3- or The AD9739 contains a set of programmable registers described 4-wire SPI capability, allowing read/write access to all registers in Table 10 that are used to configure and monitor various internal that configure the device’s internal parameters. It provides a parameters. Note the following points when programming the flexible, synchronous serial communications port, allowing easy AD9739 SPI registers: interface to many industry-standard microcontrollers and • Registers pertaining to similar functions are grouped microprocessors. The 3.3 V serial I/O is compatible with most together and assigned adjacent addresses. synchronous transfer formats, including the Motorola® SPI and • Bits that are undefined within a register should be assigned the Intel® SSR protocols. a 0 when writing to that register. • Registers that are undefined should not be written to. SDO (PIN H14) • A hardware or software reset is recommended upon SDIO (PIN G14) AD9739 SPI PORT power-up to place SPI registers in a known state. SCLK (PIN H13) • A SPI initialization routine is required as part of the boot CS (PIN G13) process. See Table 31 and Table 32 for example procedures. Figure 34. AD9739 SPI Port Reset The default 4-wire SPI interface consists of a clock (SCLK), serial Issuing a hardware or software reset places the AD9739 SPI port enable (CS), serial data input (SDIO), and serial data output registers in a known state. All SPI registers (excluding 0x00) are (SDO). The inputs to SCLK, CS, and SDIO contain a Schmitt set to their default states as described in Table 10 upon issuing a trigger with a nominal hysteresis of 0.4 V centered about VDD33/2. reset. After issuing a reset, the SPI initialization process need only The maximum frequency for SCLK is 20 MHz. The SDO pin is write to registers that are required for the boot process as well as active only during the transmission of data and remains three- any other register settings that must be modified, depending on stated at any other time. the target application. A 3-wire SPI interface can be enabled by setting the SDIO_DIR Although the AD9739 does feature an internal power-on-reset bit (Register 0x00, Bit 7). This causes the SDIO pin to become (POR), it is still recommended that a software or hardware reset bidirectional such that output data only appears on the SDIO be implemented shortly after power-up. The internal reset signal is pin during a read operation. The SDO pin remains three-stated derived from a logical OR operation from the internal POR in a 3-wire SPI interface. signal, the RESET pin, and the software reset state. A software reset can be issued via the reset bit (Register 0x00, Bit 5) by Instruction Header Information toggling the bit high then low. Note that, because the MSB/LSB MSB LSB format may still be unknown upon initial power-up (that is, 17 16 15 14 13 12 11 10 internal POR is unsuccessful), it is also recommended that the R/W A6 A5 A4 A3 A2 A1 A0 bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the An 8-bit instruction header must accompany each read and write instruction cycle that issues a software reset. A hardware reset operation. The MSB is a R/W indicator bit with logic high can be issued from a host or external supervisory IC by applying a indicating a read operation. The remaining seven bits specify high pulse with a minimum width of 40 ns to the RESET pin the address bits to be accessed during the data transfer portion. (that is, Pin F14). RESET should be tied to VSS if unused. The eight data bits immediately follow the instruction header Table 8. SPI Registers Pertaining to SPI Options for both read and write operations. For write operations, registers change immediately upon writing to the last bit of each transfer Address (Hex) Bit Description CS byte. can be raised after each sequence of eight bits (except 0x00 7 Enable 3-wire SPI the last byte) to stall the bus. The serial transfer resumes when 6 Enable SPI LSB first CS is lowered. Stalling on nonbyte boundaries resets the SPI. 5 Software reset Rev. B | Page 18 of 48 07851-034 Data Sheet AD9739 The AD9739 serial port can support both most significant bit Figure 36 illustrates the timing requirements for a write operation (MSB) first and least significant bit (LSB) first data formats. CS to the SPI port. After the serial port enable ( ) signal goes low, Figure 35 illustrates how the serial port words are formed for data (SDIO) pertaining to the instruction header is read on the the MSB first and LSB first modes. The bit order is controlled rising edges of the clock (SCLK). To initiate a write operation, by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0, the read/not-write bit is set low. After the instruction header is MSB first. When the LSB first bit is set high, the serial port read, the eight data bits pertaining to the specified register are interprets both instruction and data bytes LSB first. shifted into the SDIO pin on the rising edge of the next eight clock cycles. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS Figure 37 illustrates the timing for a 3-wire read operation to SCLK CS the SPI port. After goes low, data (SDIO) pertaining to the SDATA R/W N1 N2 A4 A3 A2 A1 A0 D7 D6 D1 D0 1 1 N N instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO INSTRUCTION CYCLE DATA TRANSFER CYCLE CS pin on the falling edges of the next eight clock cycles. SCLK Figure 38 illustrates the timing for a 4-wire read operation to SDATA A0 A1 A2 A3 A4 N2 N1 R/W D0 D1 D6 D7 1 1 N N the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, while the SDIO pin remains at high impedance throughout the operation. Figure 35. SPI Timing, MSB First (Upper) and LSB First (Lower) The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times. t 1/f S SCLK t H CS t t HI LOW SCLK t DS t DH D1 SDIO R/W N1 N0 A0 D7 D6 D0 Figure 36. SPI Write Operation Timing t 1/f S SCLK CS t t LOW HI SCLK t DV t DS t t DH EZ N1 A2 A1 A0 D7 D6 D1 D0 SDIO R/W Figure 37. SPI 3-Wire Read Operation Timing t 1/f S SCLK CS t t LOW HI SCLK t DS t t DH EZ N1 A1 A0 SDIO R/W A2 t EZ t DV D7 D6 D1 D0 SDO Figure 38. SPI 4-Wire Read Operation Timing Rev. B | Page 19 of 48 07851-035 07851-037 07851-036 07851-038 AD9739 Data Sheet SPI REGISTER MAP Table 9. Full Register Map (N/A = Not Applicable) Hex Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Mode 00 SDIO_DIR LSB/MSB Reset N/A N/A N/A N/A N/A 0x00 Power- 01 N/A N/A LVDS_ LVDS_ N/A N/A CLK_ DAC_ 0x00 Down DRVR_PD RCVR_PD RCVR_PD BIAS_PD CNT_ 02 N/A N/A N/A N/A CLKGEN_PD N/A REC_CNT_ MU_CNT_ 0x03 CLK_DIS CLK CLK IRQ_EN 03 N/A N/A SYNC_ SYNC_ MU_LST_EN MU_LCK_EN RCV_ RCV_ 0x00 LST_EN LCK_EN LST_EN LCK_EN IRQ_REQ 04 N/A N/A SYNC_ SYNC_ MU_LST_ MU_LCK_ RCVLST_ RCVLCK_ 0x00 LST_IRQ LCK_IRQ IRQ IRQ IRQ IRQ RSVD 05 N/A N/A N/A N/A N/A N/A N/A N/A N/A FSC_1 06 FSC[7] FSC[6] FSC[5] FSC[4] FSC[3] FSC[2] FSC[1] FSC[0] 0x00 FSC_2 07 Sleep N/A N/A N/A N/A N/A FSC[9] FSC[8] 0x02 DEC_ 08 N/A N/A N/A N/A N/A N/A DAC_DEC[1] DAC_DEC[0] 0x00 CNT RSVD 09 N/A N/A N/A N/A N/A N/A N/A N/A N/A LVDS_ 0A N/A N/A N/A N/A HNDOFF_ N/A LVDS_ LVDS_ 0x00 CNT CHK_RST Bias[1] Bias[0] DIG_ 0B HNDOFF_ HNDOFF_ HNDOFF_ HNDOFF_ HNDOFF_ HNDOFF_ HNDOFF_ HNDOFF_ RNDM STAT Fall[3] Fall[2] Fall[1] Fall[0] Rise[3] Rise[2] Rise[1] Rise[0] LVDS_ 0C SUP/HLD_ N/A DCI_ DCI_ DCI_PRE_ DCI_PRE_ DCI_PST_ DCI_PST_ RNDM STAT1 Edge1 PHS3 PHS1 PH2 PH0 PH2 PH0 LVDS_ 0D SUP/HLD_ SUP/HLD_ SYNC_ SYNC_ LVDS1_HI LVDS1_LO LVDS0_HI LVDS0_LO RNDM/0 STAT2 SYNC Edge0 SAMP1 SAMP0 RSVD 0E N/A N/A N/A N/A N/A N/A N/A N/A N/A RSVD 0F N/A N/A N/A N/A N/A N/A N/A N/A N/A LVDS_ 10 SYNC_ SYNC_ SYNC_ SYNC_ N/A RCVR_ RCVR_ RCVR_ 0x42 REC_ FLG_RST LOOP_ON MST/SLV CNT_ENA FLG_RST LOOP_ON CNT_ENA CNT1 LVDS_ 11 SMP_DEL[1] SMP_ FINE_ FINE_ FINE_DEL_ FINE_DEL_ RCVR_ RCVR_ 0xDD REC_ DEL[0] DEL_ DEL_ MID[1] MID[0] GAIN[1] GAIN[0] CNT2 MID[3] MID[2] LVDS_ 12 SMP_DEL[9] SMP_ SMP_ SMP_ SMP_ SMP_ SMP_ SMP_ 0x29 REC_ DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] CNT3 LVDS_ 13 DCI_DEL[3] DCI_ DCI_ DCI_ FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ 0x71 REC_ DEL[2] DEL[1] DEL[0] SKW[3] SKW[2] SKW[1] SKW[0] CNT4 LVDS_ 14 CLKDIVPH[1] CLKDIVPH[0] DCI_ DCI_ DCI_ DCI_ DCI_ DCI_ 0x0A REC_ DEL[9] DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] CNT5 LVDS_ 15 SYNC_ SYNC_ SYNCOUT_ SYNCOUT_ LCKTHR[3] LCKTHR[2] LCKTHR[1] LCKTHR[0] 0x42 REC_ GAIN[1] GAIN[0] PH[1] PH[0] CNT6 LVDS_ 16 N/A SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ 0x00 REC_ DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] DEL[1] DEL[0] CNT7 LVDS_ 17 SYNCSH_ N/A N/A N/A N/A N/A N/A N/A 0x00 REC_ DEL[0] CNT8 LVDS_ 18 SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ 0x00 REC_ DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] DEL[1] CNT9 LVDS_ 19 SMP_DEL[1] SMP_DEL[0] N/A N/A SMP_ SMP_ SMP_ SMP_ 0xC7 REC_ FINE_ FINE_ FINE_ FINE_ STAT1 DEL[3] DEL[2] DEL[1] DEL[0] LVDS_ 1A SMP_DEL[9] SMP_ SMP_ SMP_ SMP_ SMP_ SMP_ SMP_ 0x29 REC_ DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] STAT2 Rev. B | Page 20 of 48 Data Sheet AD9739 Hex Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default LVDS_ 1B DCI_DEL[1] DCI_DEL[0] N/A N/A SYNCOUT SYNCOUT CLKDIV CLKDIV 0xC0 REC_ PH[1] PH[0] PH[1] PH[0] STAT3 LVDS_ 1C DCI_DEL[9] DCI_ DCI_ DCI_ DCI_ DCI_ DCI_ DCI_ 0x29 REC_ DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] STAT4 LVDS_ 1D FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ 0x86 REC_ PST[3] PST[2] PST[1] PST[0] PRE[3] PRE[2] PRE[1] PRE[0] STAT5 LVDS_ 1E N/A SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ SYNCO_ 0x00 REC_ DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] DEL[1] DEL[0] STAT6 LVDS_ 1F SYNCSH_ N/A N/A N/A N/A N/A N/A N/A 0x00 REC_ DEL[0] STAT7 LVDS_ 20 SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ 0x00 REC_ DEL[8] DEL[7] DEL[6] DEL[5] DEL[4] DEL[3] DEL[2] DEL[1] STAT8 LVDS_ 21 SYNC_ SYNC_ SYNC_ SYNC_LCK RCVR_ RCVR_ RCVR_LST RCVR_LCK 0x00 REC_ TRK_ON INIT_ON LST_LCK TRK_ON FE_ON STAT9 CROSS_ 22 N/A N/A N/A DIR_P CLKP_ CLKP_ CLKP_ CLKP_ 0x00 CNT1 OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] CROSS_ 23 N/A N/A N/A DIR_N CLKN_ CLKN_ CLKN_ CLKN_ 0x00 CNT2 OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] PHS_ 24 N/A N/A CMP_BST PHS_DET Bias[3] Bias[2] Bias[1] Bias[0] 0x00 DET AUTO_EN MU_ 25 MU_ POS/NEG ADJ[5] ADJ[4] ADJ[3] ADJ[2] ADJ[1] ADJ[0] 0x00 DUTY DUTYAUTO_EN MU_ 26 N/A Slope Mode[1] Mode[0] Read Gain[1] Gain[0] Enable 0x42 CNT1 MU_ 27 MUDEL[0] SRCH_MODE SRCH_MODE SET_PHS[4] SET_PHS[3] SET_PHS[2] SET_PHS[1] SETPHS[0] 0x40 CNT2 [1] [0] MU_ 28 MUDEL[8] MUDEL[7] MUDEL[6] MUDEL[5] MUDEL[4] MUDEL[3] MUDEL[2] MUDEL[1] 0x00 CNT3 MU_ 29 SEARCH_TOL Retry CONTRST Guard[4] Guard[3] Guard[2] Guard[1] Guard[0] 0x0B CNT4 MU_ 2A N/A N/A N/A N/A N/A N/A MU_LOST MU_LKD 0x00 STAT1 RSVD 2B N/A N/A N/A N/A N/A N/A N/A N/A N/A RSVD 2C N/A N/A N/A N/A N/A N/A N/A N/A N/A ANA_ 32 HDRM[7] HDRM[6] HDRM[5] HDRM[4] HDRM[3] HDRM[2] HDRM[1] HDRM[0] 0xCA CNT1 ANA_ 33 N/A N/A N/A N/A N/A N/A MSEL[1] MSEL[0] 0x03 CNT2 RSVD 34 N/A N/A N/A N/A N/A N/A N/A N/A N/A PART ID 35 ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 0x20 Rev. B | Page 21 of 48 AD9739 Data Sheet SPI PORT CONFIGURATION AND SOFTWARE RESET Table 10. SPI Port Configuration and Software Reset Register Address Default (Hex) Name Bit R/W Setting Comments 0x00 SDIO_DIR 7 R/W 0 0 = 4-wire SPI, 1 = 3-wire SPI. LSB/MSB 6 R/W 0 0 = MSB first, 1 = LSB first. Reset 5 R/W 0 Software reset is recommended before modification of other SPI registers from the default setting. Setting the bit to 1 causes all registers (except 0x00) to be set to the default setting. Setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers from the default setting. POWER-DOWN LVDS INTERFACE AND TXDAC® Table 11. Power-Down LVDS Interface and TxDAC Register Address Default (Hex) Name Bit R/W Setting Comments 0x01 LVDS_DRVR_PD 5 R/W 0 Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable. LVDS_RCVR_PD 4 R/W 0 CLK_RCVR_PD 1 R/W 0 DAC_BIAS_PD 0 R/W 0 CONTROLLER CLOCK DISABLE Table 12. Controller Clock Disable Register Address Default (Hex) Name Bit R/W Setting Comments 0x02 CLKGEN_PD 3 R/W 0 Internal CLK distribution enable: 0 = enable, 1 = disable. REC_CNT_CLK 1 R/W 1 LVDS receiver and Mu controller clock disable. 0 = disable, 1 = enable. MU_CNT_CLK 0 R/W 1 INTERRUPT REQUEST (IRQ) ENABLE/STATUS Table 13. Interrupt Request (IRQ) Enable/Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x03 SYNC_LST_EN 5 W 0 This register enables the sync, mu, and LVDS Rx controllers to update their corresponding IRQ status bits in Register 0x04, which defines whether the controller is SYNC_LCK_EN 4 W 0 locked (LCK) or unlocked (LST). MU_LST_EN 3 W 0 0 = disable (resets the status bit). MU_LCK_EN 2 W 0 1 = enable. RCV_LST_EN 1 W 0 RCV_LCK_EN 0 W 0 0x04 SYNC_LST_IRQ 5 R 0 This register indicates the status of the controllers. For LCK_IQR bits: 0 = lost locked, 1 = locked. For LST_IQR bits: 0 = not lost locked, 1 = unlocked. Note that, if the SYNC_LCK_IRQ 4 R 0 controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing MU_LST_IRQ 3 R 0 0, followed by another write of 1 to enable. MU_LCK_IRQ 2 R 0 RCV_LST_IRQ 1 R 0 RCV_LCK_IRQ 0 R 0 Rev. B | Page 22 of 48 Data Sheet AD9739 TxDAC FULL-SCALE CURRENT SETTING (I ) AND SLEEP OUTFS Table 14. TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Register Address Default (Hex) Name Bit R/W Setting Comments 0x06 FSC_1 [7:0] R/W 0x00 Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA). IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023. 0x07 FSC_2 [1:0] R/W 0x02 Sleep 7 R/W 0 = enable DAC output, 1 = disable DAC output (sleep). TxDAC QUAD-SWITCH MODE OF OPERATION Table 15. TxDAC Quad-Switch Mode of Operation Register Address Default (Hex) Name Bit R/W Setting Comments 0x08 DAC-DEC [1:0] R/W 0x00 0x00 = normal baseband mode. 0x01 = return-to-zero mode. 0x02 = mix mode. DCI PHASE ALIGNMENT STATUS Table 16. DCI Phase Alignment Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x0C DCI_PRE_PH0 2 R 0 0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling edge. DCI_PST_PH0 0 R 0 0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling edge. SYNC_IN PHASE ALIGNMENT STATUS Table 17. SYNC_IN Phase Alignment Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x0D SYNC_IN_PH90 5 R 0 0 = SYNCIN rising edge is after Phase 90 sampling edge. 1 = SYNCIN rising edge is before Phase 90 sampling edge. SYNC_IN_PH0 4 R 0 0 = SYNCIN rising edge is after Phase 0 sampling edge. 1 = SYNCIN rising edge is before Phase 0 sampling edge. DATA RECEIVER CONTROLLER CONFIGURATION Table 18. Data Receiver Controller Configuration Register Address Default (Hex) Name Bit R/W Setting Comments 0x10 SYNC_FLG_RST 7 W 0 Sync controller flag reset. Write 1 followed by 0 to reset flags. SYNC_LOOP_ON 6 R/W 1 0 = disable, 1 = enable. Enable for master only. When enabled, sync controller generates an IRQ when master falls out of lock and automatically begins search/track routine. SYNC_MST/SLV 5 R/W 0 Sync controller configuration. 0 = slave, 1 = master. SYNC_CNT_ENA 4 R/W 0 Sync controller enable. 0 = disable, 1 = enable RCVR_FLG_RST 2 W 0 Data receiver controller flag reset. Write 1 followed by 0 to reset flags. RCVR_LOOP_ON 1 R/W 1 0 = disable, 1 = enable. When enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine. RCVR_CNT_ENA 0 R/W 0 Data receiver controller enabled. 0 = disable, 1 = enable. Rev. B | Page 23 of 48 AD9739 Data Sheet DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE Table 19. Data Receiver Controller_Data Sample Delay Value Register Address Default (Hex) Name Bit R/W Setting Comments 0x11 SMP_DEL[1:0] [7:6] R/W 11 Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample data. Leave at the default 0x12 SMP_DEL[9:2] [7:0] R/W 0x25 setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION Table 20. Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Register Address Default (Hex) Name Bit R/W Setting Comments 0x13 DCI_DEL[3:0] [7:4] R/W 0111 Refer to the DCI_DEL description in Register 0x14. FINE_DEL_SKEW [3:0] R/W 0001 A 4-bit value sets the difference (that is, window) for the DCI PRE and POST sampling clocks. Leave at the default value of 1 for a narrow window. 0x14 CLKDIVPH[1:0] [7:6] R/W 00 Relative phase of internal div-by-4 circuit. This feature allows phase rotation in 90° increments (that is, 1 count) to extend Rx controllers locking range for clock rates between 0.8 GSPS to 1.6 GSPS (only valid with sync controller disabled). DCI_DEL[9:4] [5:0] R/W 001010 Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample the DCI input. Leave at the default setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. 0x15 SYNC GAIN[1:0] [7:6] R/W 00 Sets the sync tracking gain (optimal value is 1). SYNCOUT_PH[1:0] [5:4] R/W 00 Readback of the present SYNC_OUT phase selection. LCKTHR[3:0] [3:0] R/W 0000 Sets the difference between the sample and DCI delays to lock (optimal value is 2). 0x16 SYNCO_DEL[6:0] [6:0] R/W 0x00 Sets the sync output delay value when the synch controller is disabled; otherwise, is the read status of the sync output delay value when sync is enabled. 0x17 SYNCSH_DEL[0] [7] R/W 0x00 Sets the sync setup and hold delay value when the synch controller is disabled; otherwise, is the read status of sync setup and hold value when sync is enabled. 0x18 SYNCSH_DEL[8:1] [7:0] R/W 0x00 Sets the sync setup and hold delay value when the synch controller is disabled; otherwise, is the read status of sync setup and hold value when sync is enabled. DATA RECEIVER CONTROLLER_DELAY LINE STATUS AND SYNC CONTROLLER SYNC_OUT STATUS Table 21. Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x19 SMP_DEL[1:0] [7:6] R 00 The actual value of the DCI and data delay lines determined by the data receiver controller (when enabled) after the state machine completes its search and enters 0x1A SMP_DEL[9:2] [7:0] R 0x00 track mode. Note that these values should be equal. 0x1B SYNCOUT_PH[1:0] 3:2 R 00 SYNCOUT_PH provides phase status (0/90/180/270) of phase select mux, while CLKDIV PH[1:0] 1:0 R 00 CLKDIVPH provides phase status of data receiver controller (Register 0x14). DCI_DEL[1:0] [7:6] R 00 0x1C DCI_DEL[9:2] [7:0] R 0x00 Rev. B | Page 24 of 48 Data Sheet AD9739 SYNC AND DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS Table 22. Sync and Data Receiver Controller Lock/Tracking Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x21 SYNC_TRK_ON 7 R 0 SYNC_TRK_ON and RCVR_TRK_ON: 0 = tracking not established. SYNC_LST 5 R 0 1 = tracking established. SYNC_LCK 4 R 0 SYNC_LCK and RCVR_LCK: RCVR_TRK_ON 3 R 0 0 = controller is not locked. RCVR_LST 1 R 0 1 = controller is locked. SYNC_LST and RCVR_LST: RCVR_LCK 0 R 0 0 = lock has not been lost. 1 = lock has been lost at some point. CLK INPUT COMMON MODE Table 23. CLK Input Common Mode Register Address Default (Hex) Name Bit R/W Setting Comments 0x22 DIR_P 4 R/W 0 DIR_P and DIR_N: 0 = VCM at the DACCLK_P input decreases with the offset value. CLKP_OFFSET[3:0] [3:0] R/W 0000 1 = VCM at the DACCLK_P input increases with the offset value. 0x23 DIR_N 4 R/W 0 CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N CLKN_OFFSET[3:0] [3:0] R/W 0000 inputs. For optimum performance, set to 1111. MU CONTROLLER CONFIGURATION AND STATUS Table 24. Mu Controller Configuration and Status Register Address Default (Hex) Name Bit R/W Setting Comments 0x24 CMP_BST 5 R/W 0 Phase detector enable and boost bias bits. Note that both bits should always be set to 1 to enable these functions. PHS_DET 4 R/W 0 AUTO_EN 0x25 MU_DUTY 7 R/W 0 Mu controller duty cycle enable. Note that this bit should always be set to 1 to enable. AUTO_EN 0x26 Slope 6 R/W 1 Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Refer to Table 28 for optimum setting. Mode[1:0] [5:4] R/W 00 Sets the mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track. Read 3 R/W 0 Set to 1 to read the current value of the Mu delay line in. Gain[1:0] [2:1] R/W 01 Sets the mu controller tracking gain. Recommended to leave at the default 01 setting. Enable 0 R/W 0 1 = enable the mu controller. 0 = disable the mu controller. 0x27 MUDEL[0] 7 R/W 0 The LSB of the 9-bit MUDEL setting. SRCH_MODE[1:0] [6:5] R/W 0 Sets the direction in which the mu controller searches (from its initial MUDEL setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, SET_PHS and slope ). 00 = down. 01 = up. 10 = down/up (recommended). SET_PHS[4:0] [4:0] R/W 0 Sets the target phase that the mu controller locks to with a maximum setting of 16. Refer to Table 28 for optimum setting. Rev. B | Page 25 of 48 AD9739 Data Sheet Address Default (Hex) Name Bit R/W Setting Comments 0x28 MUDEL[8:1] [7:0] W 0x00 With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value that the mu delay is set to. Note that the maximum value is 432. With enable set to 1, this value represents the mu delay value at which the controller begins its search. Setting this value to the delay line midpoint of 216 is recommended. R 0x00 When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the mu controller locks to when enable = 1. 0x29 SEARCH_TOL 7 R/W 0 0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting). Retry 6 R/W 0 0 = stop the search if the correct value is not found. 1 = retry the search if the correct value is not found. CONTRST 5 R/W 0 Controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting). 1 = reset. Guard[4:0] 4 R/W 01011 Sets a guard band from the beginning and end of the mu delay line which the mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is Decimal 11 or 0x0B). 0x2A MU_LST 1 R 0 0 = mu controller has not lost lock. 1 = mu controller has lost lock. MU_LKD 0 R 0 0 = mu controller is not locked. 1= mu controller is locked. PART ID Table 25. Part ID Register Default Address (Hex) Name Bit R/W Setting Comments 0x35 PART_ID [7:0] R 0x20 Part ID number. Rev. B | Page 26 of 48 Data Sheet AD9739 THEORY OF OPERATION Figure 39 shows a top-level functional diagram of the AD9739. The AD9739 data receiver controller generates an internal A high performance TxDAC core delivers a signal dependent, sampling clock offset by 90° from the DCI to sample the input differential current (nominal ±10 mA) to a balanced load data on the DB0 and DB1 ports. When enabled and configured referenced to ground. The frequency of the clock signal properly for track mode, it ensures proper data recovery between appearing at the AD9739 differential clock receiver, DACCLK, the host and the AD9739 clock domains. The data receiver sets the TxDAC’s update rate. This clock signal, which serves as controller has the ability to track several hundreds of ps of drift the master clock, is routed directly to the TxDAC as well as to a between these clock domains, typically caused by supply and clock distribution block that generates all critical internal and temperature variation. external clocks. As mentioned, the host processor provides the AD9739 with a RESET IRQ deinterleaved data stream such that the DB0 and DB1 data ports receive alternating samples (that is, odd/even data streams). The AD9739 AD9739 data assembler is used to reassemble (that is, multiplex) 1.2V SDIO SDO the odd/even data streams into their original order before SPI DAC BIAS CS VREF delivery into the TxDAC for signal reconstruction. The pipeline SCLK I120 delay from a sample being latched into the data port to when it appears at the DAC output is on the order of 78 (±) DACCLK cycles. Applications that require matching pipeline delays (that is, synchronization) between multiple AD9739s can use the IOUTP TxDAC SYNC controller. The SYNC controller phase aligns the outputs DCI CORE IOUTN of one or more AD9739 devices (that is,. slaves) to a master AD9739 device. The AD9739 includes a delay lock loop (DLL) circuit controlled via a mu controller to optimize the timing hand-off between the AD9739 digital clock domain and TxDAC core. Besides ensuring CLK DISTRIBUTION DCO (DIV-BY-4) proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains SYNC_OUT SYNC- SYNC_IN CONTROLLER with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing DACCLK alignment over temperature, time, and power supply variation. Figure 39. Functional Block Diagram of the AD9739 A SPI interface is used to configure the various functional blocks as The AD9739 includes two 14-bit LVDS data ports (DB0 and well as monitor their status for debug purposes. Proper operation DB1) to reduce the data interface rate to ½ the TxDAC update rate. of the AD9739 requires that controller blocks be initialized upon The host processor drives deinterleaved data with offset binary power-up. A simple SPI initialization routine is used to configure format onto the DB0 and DB1 ports, along with an embedded DCI the controller blocks (see Figure 51 and Figure 52). An IRQ clock that is synchronous with the data. Because the interface is output signal is available to alert the host should any of the double data rate (DDR), the DCI clock is essentially an alternating controllers fall out of lock during normal operation. 010101……….01010 bit pattern with a frequency equal to ¼ the The following sections discuss the various functional blocks in TxDAC update rate (f ). To simplify synchronization with the DAC more detail as well as their implications when interfacing to host processor, the AD9739 passes an LVDS clock output (DCO) external ICs and circuitry. While a detailed description of the that is also equal to the DCI frequency. various controllers (and associated SPI registers used to configure and monitor) is also included for completeness, the recommended SPI boot procedure can be used to ensure reliable operation. Rev. B | Page 27 of 48 DB1[13:0] DB0[13:0] DATA CONTROLLER LVDS DDR LVDS DDR RECEIVER RECEIVER 4-TO-1 DATA ASSEMBLER DATA LATCH DLL (MU CONTROLLER) 07851-039 AD9739 Data Sheet The maximum allowable skew and jitter out of the host LVDS DATA PORT INTERFACE processor with respect to the DCI clock edge on each LVDS The AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS port is calculated as using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard data clock input (DCI) at f /4 with its rising and falling edges DAC = 800 ps − 344 ps − 100 ps aligned with the data transitions. The data format is offset binary; = 356 ps however, twos complement format can be realized by reversing where ValidWindow(ps) is represented by tVALID and Guard is the polarity of the MSB differential trace. As shown in Figure 40, represented by tGUARD in Figure 41. the host feeds the AD9739 with deinterleaved input data into two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock The minimum specified LVDS valid window is 344 ps, and a rate (that is, fDAC/2). The AD9739 internal data receiver controller guard band of 100 ps is recommended. Therefore, at the maximum then generates a phase shifted version of DCI to register the operating frequency of 2.5 GSPS, the maximum allowable FPGA input data on both the rising and falling edges. and PCB bit skew plus jitter is equal to 356 ps. HOST AD9739 PROCESSOR For synchronous operation, the AD9739 provides a data clock output, DCO, to the host at the same rate as DCI (that is, fDAC/4) EVEN DATA SAMPLES to maintain the lowest skew variation between these clock 14 × 2 domains. Since the DCO signal is generated from a separate clock divider, its phase relationship relative to the f /4 clocks DAC used by the data receiver controller will vary upon each power-up. f = f /2 DATA DAC Applications sensitive to this phase ambiguity (resulting in a ±2 ODD DATA DACCLK pipeline variation) should consider using the sync SAMPLES 14 × 2 controller. The host processor has a worst-case skew between DCO and 1 × 2 DCI DCI that is both implementation and process dependent. This f = f /4 DCI DAC worst-case skew can also vary an additional 30% over temperature 1 × 2 DCO DIV-BY-4 f and supply corners. The delay line within the data receiver DAC f = f /4 DCO DAC controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that Figure 40. Recommended Digital Interface Between the AD9739 and Host Processor generates a synchronous fDAC/4 from which the DCI signal is derived, digital implementations that result in the shortest As shown in Figure 41, the DCI clocks edges must be coincident propagation delays result in the lowest skew variation. with the data bit transitions with minimum skew, jitter, and intersymbol interference. To ensure coincident transitions with the The data receiver controller is used to ensure proper data hand-off data bits, the DCI signal should be implemented as an additional between the host and AD9739 internal digital clock domains. data line with an alternating (010101…) bit sequence from the The circuit shown in Figure 42 functions as a delay lock loop in o same output drivers used for the data. Maximizing the opening which a 90 phase shifted version of the DCI clock input is used of the eye in both the DCI and data signals improves the reliability to sample the input data into the DDR receiver registers. This of the data port interface. Differential controlled impedance traces ensures that the sampling instance occurs in the middle of the of equal length (that is, delay) should also be used between the data pattern eyes (assuming matched DCI and DBx[13:0] delays). host processor and AD9739 input to limit bit-to-bit skew. Note that, because the DCI delay and sample delay clocks are derived from the div-by-4 circuitry, this 90° phase relationship holds as long as the delay settings (that is, DCI_DEL, SMP_DEL) are also matched. 2 × 1/f DAC DCI t + t VALID GUARD MAX SKEW t + JITTER VALID DB0[13:0] AND DB1[13:0] Figure 41. LVDS Data Port Timing Requirements Rev. B | Page 28 of 48 DATA DEINTERLEAVER LVDS DDR DRIVER DB1[13:0] DB0[13:0] LVDS DDR LVDS DDR RECEIVER RECEIVER DATA CONTROLLER 07851-040 07851-041 Data Sheet AD9739 DATA RECEIVER CONTROLLER DCI WINDOW PRE DDR DCI FF FINE DELAY DELAY DELAY DCI FROM SYNC CONTROLLER PRE DELAY OR PATH SPI REG 0x14, BIT[7:6] PHASE DCI DELAY DDR DCI WINDOW POST ROTATION FF 0 STATE MACHINE/ 90 FINE TRACKING LOOP DIV-BY-4 F DAC 180 DELAY 270 POST SAMPLE DELAY DCI WINDOW SAMPLE DDR FF TO SYNC SAMPLE CONTROLLER DELAY PATH FINE DELAY DELAY DELAY SAMPLE DATA TO CORE DDR DDR DDR DDR DBx[13:1] FF FF FF FF ELASTIC FIFO DCO DIV-BY-4 Figure 42. Top Level Diagram of the Data Receiver Controller The div-by-4 circuit generates four clock phases that serve as inputs Proper sampling of the DCI signal can also be confirmed by to the data receiver controller. All of the DDR registers in the data monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI paths operate on both clock edges; however, for clarity and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings o o purposes, only the phases (that is, 0 and 90 ) corresponding to are correct, the state of DCI_ PRE_PH0 should be 0, and the the positive edge of each path are shown. One of the div-by-4 state of DCI_PST_PH0 should be 1. Note that the states of these phases is used to generate the DCO signal; therefore, the phase status bits may toggle occasionally due to cycle-to cycle jitter relationship between DCO and clocks fed into the controller exceeding the window width. However, the controller averages remains fixed. Note that it is this attribute that allows possible these status bits over multiple clock cycles to ensure that the factory calibration of images and clock spurs attributed to fDAC/4 DCI signal falls within a programmable window. modulation of the critical DAC clock. DCI FINE DELAY Once this data has been successively sampled into the first set PST of registers, an elastic FIFO is used to transfer the data into FINE DELAY PRE the AD9739 clock domain. To continuously track any phase FINE_DEL_SKEW variation between the two clock domains, the data receiver Figure 43. Pre- and Post-Delay Sampling Diagram controller should always be enabled and placed into track The skew or window width (FINE_DEL_SKEW) is set via mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates Register 0x13, Bits[3:0], with a maximum skew of approximately continuously in the background to track delay variations between 180 ps and resolution of 12 ps. It is recommended that the skew the host and AD9739 clock domains. It does so by ensuring that be set to 36 ps (that is, Register 0x13 = 0x72) during initialization. the DCI signal is sampled within a very narrow window defined The skew setting also affects the speed of the controller loop, by two internally generated clocks (that is, PRE and PST), as with tighter skew settings corresponding to longer response time. shown in Figure 43. Rev. B | Page 29 of 48 07851-043 07851-042 AD9739 Data Sheet Data Receiver Controller Initialization Description synchronization controller (optional), the data receiver controller should be enabled only after these other controllers have been The data controller should be initialized and placed into track enabled and established locked. All of the internal controllers mode as the second step in the SPI boot sequence. The following operate at submultiples of the DAC update rate. The number of steps are recommended for the initialization of the data receiver fDAC clock cycles required to lock onto the DCI clock is dependent controller: on whether the synchronization controller is enabled as shown 1. Set FINE_DEL_SKEW to 2 for a larger DCI sampling in Table 26. window (Register 0x13 = 0x72). Note that the default DCI_DEL and SMP_DEL settings of 167 are optimum. Table 26. Typical/Worst-Case Lock Times for LVDS Controller 2. Disable the controller before enabling (that is, Register (Relative to 1/f ) DAC 0x10 = 0x00). Synchronization Controller Typical Worst Case Off 70K 135K 3. Enable the Rx controller in two steps: Register 0x10 = 0x02 Slave 70K 135K followed by Register 0x10 = 0x03. Master 300K 560K 4. Wait 135K clock cycles. 5. Read back Register 0x21 and confirm that it is equal to During the SPI initialization process, the user has the option of 0x05 to ensure that the DLL loop is locked and tracking. polling Register 0x21 (Bit 0, Bit 1, and Bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into 6. Include this step for operation <1.6 GSPS. Read back the track mode before completing the boot sequence. Alternatively, the DCI_DEL value to determine whether the value falls appropriate IRQ bit (Register 0x03 and Register 0x04) can be within a user-defined tracking guard band. If it does not, enabled such that an IRQ output signal is generated upon the rotate CLKDIVPH by 1 (Register 0x14, Bits[7:6] and go controller establishing lock (see the Interrupt Requests section). back to Step 2. The data receiver controller can also be configured to generate Once the controller is enabled during the initial SPI boot an interrupt request (IRQ) upon losing lock. Losing lock can be process (see Table 31 and Table 32), the controller enters a caused by excessive jitter on the DCI input signal, disruption of search mode where it seeks to find the closest rising edge of the the main DAC clock input, or loss of a power supply rail. To service DCI clock (relative to a delayed version of an internal f /4 clock) DAC the interrupt, the host can poll the RCVR_LCK bit (Register 0x21, by simultaneously adjusting the delays in the clocks used to Bit 0) to determine the current state of the controller. If this bit register the DCI and data inputs. A state machine searches is cleared, the search/track procedure can be restarted by setting above and below the initial DCI_DEL value. The state machine the RCVR_LOOP_ON bit in Register 0x10, Bit 1. After waiting first searches for the first rising edge above the DCI_DEL and the required lock time, the host can poll the RCVR_LCK bit to then searches for the first rising edge below the DCI_DEL value. see if it has been set. Before leaving the interrupt routine, the The state machine selects the closest rising edge and then enters RCVR_FLG_RST bit (Register 0x10, Bit 2) should be reset by track mode. It is recommended that the default midscale delay writing a high followed by a low. setting (that is, Decimal 167) for the DCI_DEL and SMP_DEL Data Receiver Operation at Lower Clock Rates bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for At clock rates below 1.6 GSPS, it is recommended to include tracking timing variations and preventing the controller from provisions to rotate the CLKDIVPH setting in the SPI boot falling out of lock. process. As previously mentioned, the delay line can be varied over a nominal 4 ns window. If the minimum specified clock The adjustable delay span for these internal clocks (that is, DCI rate of 800 MSPS is considered, a DCI clock rate of 200 MSPS and sample delay) is nominally 4 ns. The 10-bit delay value is corresponds to a 5 ns period, thus exceeding the delay line length. user programmable from the decimal equivalent code (0 to 384) Therefore, it becomes possible that the initial startup phase from with approximately 12 ps/LSB resolution via the DCI_DEL and the div-by-4 circuit (and DCO output) is such that the data receiver SMP_DEL registers (via Register 0x11 thru Register 0x14). When controller can never establish initial lock upon power up. the controller is enabled, it overwrites these registers with the delay value it converges upon. The minimum difference If the clock rate is increased to 1600 MSPS (that is, DCI clock between this delay value and the minimum/maximum values period of 2.5 ns), the controller will always be able to find at (that is, 0 and 334) represents the guard band for tracking. least two DCI clock edges, therefore, establish lock. However, Therefore, if the controller initially converges upon a DCI_DEL should the DCI edges fall symmetrically (equal distance) from and SMP_DEL value between 80 and 304, the controller has a the initial DCI_DEL midscale setting, a guard band of ±0.75 ns guard band of at least 80 code (approximately 1 ns) to track (that is, (4.0 − 2.5)/2) results. Rotating the CLKDIVPH can result phase variations between the clock domains. in an improvement in this case by skewing one of the DCI edges toward the DCI_DEL midscale value. Upon initialization of the AD9739, a certain period of time is required for the data receiver controller to lock onto the DCI clock signal. Note that, due to its dependency on the mu controller and Rev. B | Page 30 of 48 Data Sheet AD9739 Rotating the CLKDIVPH phase provides a means of adjusting LVDS INPUTS (NO FAIL-SAFE) the delay in course steps of f /4. For example, in the 800 MSPS DAC and 1600 MSPS cases described above, rotating the CLKDIVPH V LVDS COM V 100Ω P,N RECEIVER setting by 1 corresponds to a delay shift of 5 ns and 2.5 ns, = (V + V )/2 P N respectively. By adding an additional step in the SPI initialization V V P N routine for the data receiver controller, it becomes possible to GND increase the effective range of the delay line to ensure a DCI_DEL value that falls within a reasonable guard band. EXAMPLE LVDS Driver and Receiver Input V 1.4V P The AD9739 features a LVDS-compatible driver and receivers. The LVDS driver output used for the DCO and SYNC_OUT V 1.0V N signal includes an equivalent 200 Ω source resistor that limits its V 0.4V P nominal output voltage swing to ±200 mV when driving a 100 Ω load. The DCO output driver can be powered down via 0V Register 0x01, Bit 5. An equivalent circuit is shown in Figure 44 –0.4V V N VDD33 LOGIC 1 LOGIC BIT EQUIVALENT LOGIC 0 Figure 46. LVDS Data Input Levels V+ V– VDD33 = 3.3V 100Ω 100Ω DCO_N ESD ESD DCO_P R1 VCM V– V+ V = 1.4V P LVDS_1 100Ω LVDS_2 100Ω VSS Figure 44. Equivalent LVDS Output VDD33 LVDS_N 100Ω 100Ω V = 1.4V P R2 DCI_P DCI_N ESD ESD DBx[13:0]P DBx[13:0]N R1 = 4.75 × 100/N R2 = 2.50 × 100/N Figure 47. Resistor Network to Bias Unused LVDS Data Inputs The AD9739 LVDS inputs do not include fail-safe capability. VSS Any unused data input pins should be biased with an external Figure 45. Equivalent LVDS Input network or static driver. Figure 47 shows an external biasing The LVDS receivers include 100 Ω termination resistors, as network that can be used to place unused data bits into a known shown in Figure 45. These receivers meet the IEEE-1596.3-1996 state. The resistor values for R1 and R2 are selected to establish reduced swing specification (with the exception of input hysteresis, a V and V of 1.4 V and 1.0 V, respectively, depending on the P N which cannot be guaranteed over all process corners). Figure 46 number of unused digital inputs, N. and Figure 47 show an example of nominal LVDS voltage levels seen at the input of the differential receiver with resulting common- mode voltage and equivalent logic level. The LVDS receivers can be powered down via Register 0x01, Bit 4. Table 27. Example of LVDS Input Levels Applied Voltages Resulting Differential Voltage Resulting Common-Model Voltage V (V) V (V) V V Logic Bit Binary Equivalent P N P, N COM 1.4 1.0 +0.4 V 1.2 V 1 1.0 1.4 −0.4 V 1.2 V 0 1.0 0.8 +200 mV 900 mV 1 0.8 1.0 −200 mV 900 mV 0 Rev. B | Page 31 of 48 07851-044 07851-045 07851-047 07851-046 AD9739 Data Sheet Figure 49 maps the typical mu phase characteristic at 2.4 GSPS vs. MU CONTROLLER the 9-bit digital delay setting (MUDEL). The mu phase scaling A delay lock loop (DLL) is used to optimize the timing between is such that a value of 16 corresponds to 180 degrees. The critical the internal digital and analog domains of the AD9739 such that keep-out window between the digital and analog domains occurs data is successfully transferred into the TxDAC core at rates of at a value of 0 (but can extend out to 2 depending on the clock up to 2.5 GSPS. As shown in Figure 48, the DAC clock is split rate). The target mu phase (and slope) is selected to provide into an analog and a digital path with the critical analog path optimum ac performance while ensuring that the mu controller leading to the DAC core (for minimum jitter degradation) and for any device can establish and maintain lock. For example, the digital path leading to a programmable delay line. Note that while a slope and phase setting of −6 is considered optimum the output of this delay line serves as the master internal digital for operation between 1.6 GSPS and 2.5 GSPS, other values are clock from which all other internal and external digital clocks required below 1.6 GSPS. are derived. The amount of delay added to this path is under the 18 control of the mu controller, which optimizes the timing between NOM_P1 SLOW_P1 these two clock domains and continuously tracks any variation 16 FAST_P1 (once in track mode) to ensure proper data hand-off. 14 14-BIT 14-BIT DATA DATA IOUTP 12 DIGITAL ANALOG CIRCUITRY CIRCUITRY IOUTN 10 MU PHASE 8 DELAY DETECTOR 6 MU DAC DELAY CLOCK 4 CONTROLLER 2 Figure 48. Mu Delay Controller Block Diagram 0 0 40 80 120 160 200 240 280 320 360 400 440 DELAY LINE TAP The mu controller adjusts the timing relationship between the Figure 50. Mu Phase Characteristics of Three Devices from Different Process digital and analog domains via a tapped digital delay line having Lots at 1.2 GSPS a nominal total delay of 864 ps. The delay value is programmable to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL The mu phase characteristics can vary significantly among devices register, resulting in a nominal resolution of 2 ps/LSB. Because a due to gm variations in the digital delay line that are sensitive to time delay maps to a phase offset for a fixed clock frequency, process skews (along with temperature and supply). As a result, the control loop essentially compares the phase relationship careful selection of the target phase location is required such between the two clock domains and adjusts the phase (that is, via a that the mu controller can converge upon this phase location tapped delay line) of the digital clock such that it is at the desired for all devices. Figure 50 shows that mu phase characteristics of fixed phase offset (SET_PHS) from the critical analog clock. three devices at 25°C from slow, nominal, and fast skew lots at 18 1.2 GSPS. Note that a −6 mu phase setting does not map to any delay line tap setting for the fast process skew case; therefore, 16 another target mu phase is recommended at this clock rate. GUARD GUARD BAND 14 BAND Table 28 provides a list of recommended mu phase/slope settings 12 over the specified clock range of the AD9739 based on the 10 considerations previously described. These values should be DESIRED PHASE used to ensure robust operation of the mu controller. 8 6 Table 28. Recommended Target Mu Phase Settings vs. Clock Rate Clock Rate (GSPS) Slope MU Phase 4 0.8 − 6 SEARCH STARTING 2 LOCATION 0.9 − 4 0 1.0 + 5 0 40 80 120 160 200 240 280 320 360 400 440 1.1 + 8 MU DELAY 1.2 + 12 Figure 49. Typical Mu Phase Characteristic Plot at 2.4 GSPS 1.3 − 12 1.4 − 10 1.5 − 8 1.6 to 2.5 − 6 Rev. B | Page 32 of 48 MU PHASE 07851-049 07851-048 MU PHASE 07851-050 Data Sheet AD9739 After the mu controller completes its search and establishes lock If everything matches, the search algorithm is finished. If not, on the target mu phase, it attempts to maintain a constant timing the search continues in both directions until an exact match can relationship between the two clock domains over the specified be found or a programmable guard band is reached in one of the directions. When the guard band is reached, the search still temperature and supply range. If the mu controller requests a mu delay setting that exceeds the tapped delay line range (that continues but only in the opposite direction. If the desired phase is is, <0 or >432), the mu controller can lose lock, causing possible not found before the guard band is reached in the second direction, system disruption (that is, can generate IRQ or restart the search). the search changes back to the alternating mode and continues To avoid this scenario, symmetrical guard bands are recommended looking within the guard band. The typical locking time for the mu at each end of the mu delay range. The guard band scaling is controller is approximately 180K DAC cycles (at 2 GSPS ~ 75 μs). such that one LSB of Guard[4:0] (Register 0x29) corresponds to The search fails if the mu delay controller reaches the endpoints. eight LSBs of MUDEL (Register 0x28). The recommended guard The mu controller can be configured to retry (Register 0x29, Bit 6) band setting of 11 (that is, Register 0x29 = 0xCB) corresponds the search or stop. For applications that have a microcontroller, to 88 LSBs, thus providing sufficient margin. the preferred approach is to poll the MU_LKD status bit Mu Controller Initialization Description (Register 0x2A, Bit 0) after the typical locking time has expired. This method allows the system controller to check the status of The mu controller must be initialized and placed into track other system parameters (that is, power supplies and clock source) mode as a first step in the SPI boot sequence. The following before reattempting the search (by writing 0x03 to Register 0x26). steps are required for initialization of the mu controller. Note For applications that do not have polling capabilities, the mu that the AD9739 data sheet specifications and characterization controller state machine should be reconfigured to restart the data are based on the following mu controller settings: search in hopes that the system’s condition that did not cause 1. Turn on the phase detector with boost (Register 0x24 = 0x30). locking on the first attempt has disappeared. 2. Enable the mu delay controller duty-cycle correction Once the mu delay value is found that exactly matches the desired circuitry and specify the recommended slope for phase. mu phase setting and slope (for example, 6 with a negative. (that is, Register 0x25 = 0x80 corresponds to a negative slope). slope), the mu controller goes into track mode. In this mode, 3. Specify search/track mode with a recommended target the mu controller makes slight adjustments to the delay value phase, SET_PHS, of 6 (for example) and an initial to track any variations between the two clock paths due to MUDEL[8:0] setting of 216 (Register 0x27 = 0x46 and temperature, time, and supply variations. Two status bits, Register 0x28 = 0x6C). MU_LKD (Register 0x2A, Bit 0) and MU_LST (Register 0x2A, 4. Set search tolerance to exact and retry if the search fails Bit 1) are available to the user to signal the existing status control its initial attempt. Also, set the guard band to the loop. If the current phase is more than four steps away from the recommended setting of 11 (Register 0x29 = 0xCB). desired phase, the MU_LKD bit is cleared, and if the lock 5. Set the mu controller tracking gain to the recommended acquired was previously set, the MU_LST bit is set. Should the setting and enable the mu controller state machine phase deviation return to within three steps, the MU_LKD bit is (Register 0x26 = 0x03). set again while the MU_LST is cleared. Note that this sort of event Upon completion of the last step, the mu controller begins a may occur if the main clock input (that is, DACCLK) is disrupted search algorithm that starts with an initial delay setting specified or the mu controller exceeds the tapped delay line range (that is, by the MUDEL register (that is, 216, which corresponds to the <0 or >432). midpoint of the delay line). The initial search algorithm works If lock is lost, the mu controller has the option of remaining in by sweeping through different mu delay values in an alternating the tracking loop or resetting and starting the search again via manner until the desired phase (that is, a SET_PHS of 4) is the CONTRST bit (Register 0x29, Bit 5). Continued tracking is exactly measured. When the desired phase is measured, the the preferred state because it is the least disruptive to a system slope of the phase measurement is then calculated and in which the AD9739 temporarily loses lock. The user can poll compared against the specified slope (slope = negative). the mu delay and phase value by first setting the read bit high (Register 0x26, Bit 3). Once the read bit is set, the MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27 and Register 0x28) that the controller is currently using can be read. Rev. B | Page 33 of 48 AD9739 Data Sheet It is also possible to use the IRQ during the AD9739 initialization INTERRUPT REQUESTS phase after power-up to determine when the mu and data receiver The AD9739 can provide the host processor with an interrupt controllers have achieved lock. For example, before enabling the request output signal (IRQ) that indicates that one or more of the mu controller, the MU_LCK_EN bit (Register 0x03, Bit 2) can be AD9739 internal controllers have achieved lock or lost lock. These set and the IRQ output signal monitored to determine when lock controllers include the mu, data receiver, and synchronization has been established before continuing in a similar manner with controllers. The host can then poll the IRQ status register the data receiver controllers. Note that the relevant LCK bit should (Register 0x04) to determine which controller has lost lock. be cleared before continuing to the next controller. After all The IRQ output signal is an active high output signal available controllers are locked, the lost lock enable bits (that is, x_LST_EN) on Pin F13. If used, its output should be connected via a 10 kΩ should be set. pull-up resistor to VDD33. Table 29. Interrupt Request Registers Each IRQ is enabled by setting the enable bits in Register 0x03, Address (Hex) which purposely has the same bit mapping as the IRQ status Bit Description bits in Register 0x04. Note that these IRQ status bits are set only 0x03 5 SYNC_LST_EN when the controller transitions from a false to true state. Therefore, 4 SYNC_LCK_EN it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to 3 MU_LST_EN be set when a controller temporarily loses lock but is able to 2 MU_LCK_EN reestablish lock before the IRQ is serviced by the host. In this 1 RCV_LST_EN case, the host should validate the present status of the suspect 0 RCV_LCK_EN controller by reading back its current status bits, which are 0x04 5 SYNC_LST_IRQ available in Register 0x21 and/or Register 0x2A. Based on the 4 SYNC_LCK_IRQ status of these bits, the host can take appropriate action, if required, 3 MU_LST_IRQ to reestablish lock. To clear an IRQ after servicing, it is necessary to 2 MU_LCK_IRQ reset relevant bits in Register 0x03 by writing 0 followed by 1 RCV_LST_IRQ another write of 1 to reenable. A detailed diagram of the 0 RCV_LCK_IRQ interrupt circuitry is shown in Figure 51. 0x21 7 SYNC_TRK_ON 5 SYNC_LST 4 SYNC_LCK (PIN F13) INT D INT(n) SOURCE SPI 3 RCVR_TRK_ON Q DATA SPI ISR 1 RCVR_LST READ DATA 0 RCVR_LCK INT 0x2A 1 MU_LST SPI WRITE SOURCE SCLK SPI ADDRESS 0 MU_LKD IMR DATA = 1 Figure 51. Interrupt Request Circuitry Rev. B | Page 34 of 48 07851-051 Data Sheet AD9739 One AD9739 is designated as the master providing a SYNC_OUT MULTIPLE DEVICE SYNCHRONIZATION reference clock (equal to f /4) to itself as well as the other DAC Synchronization of multiple AD9739s requires all of the devices AD9739 slave device’s SYNC_IN input. LVDS fanout buffers with to have matching pipeline delays. This implies the DAC outputs matched output delays are again used to distribute the SYNC_OUT are time aligned to the same phase when all devices are fed with and DCO signals of the master to the slave devices and FPGAs, the same data pattern at the same instance of time. The main respectively, thus ensuring tight time alignment. Note, in the contributor to phase ambiguity between devices is from the case of a single FPGA implementation (that is, I/Q application), div-by-4 circuitry that drives the Rx data path and data controller the DCO of the master can drive the FPGA directly. (see Figure 53). This phase ambiguity can result in a ±2 sample After synchronization, the internal div-by-4 circuitry will have offset between any two devices. Because the state of this internal equal phases that drive their respective LVDS controllers. Note, divider is unknown at power-up, a synchronization method that the mu and data receiver controller of both devices must be phase aligns the digital paths of multiple AD9739s is required to ensure matching pipeline delays. configured for the same SPI register settings (that is, SET_PHS and DCI_DEL) upon SPI initialization such that controllers Figure 52 shows a top-level diagram of multiple AD9739s converge to similar delays. To validate that delays are roughly synchronized to each other with sample alignment of the matched, the user can read back the delays of both devices (that is, different data streams within the FPGA (or among multiple MUDEL and DCI_DEL) to determine if they are in an acceptable FPGAs) being assumed. A common RF clock source is window that accounts for slight mismatches between different distributed to each of the AD9739 devices via a dual clock devices’ delay lines. buffer (such as the ADCLK946) with matched PCB trace lengths to each device to ensure matched propagation delays. MATCHED DELAYS 1:N LVDS TO FPGA_2 REPEATER TO OTHER FPGAs MATCHED DELAYS COMMON CLOCK SOURCE 0.8GHz TO 2.0GHz TO SLAVE_1 ADCLK346 DCO DACCLK TO SLAVE_N AD9739 MASTER DCI SYNC_IN SYNC_OUT MATCHED DELAYS FPGA_1 1:N LVDS DCO DACCLK REPEATER AD9739 SLAVE_1 DCI SYNC_OUT SYNC_IN DCO MASTER DCO DCO DACCLK AD9739 SLAVE_N DCI FPGA_2 SYNC_OUT SYNC_IN Figure 52. Functional Block Diagram of Two AD9739s Synchronized Rev. B | Page 35 of 48 07851-052 AD9739 Data Sheet DB0[13:0] DB0 EVEN DB0 ODD TO DAC DB1[13:0] DB1 EVEN DCI DB1 ODD f DISTRIBUTION DAC 90/270 DELAY DELAY f /4 DIV-BY-4 Mu Delay DAC MU DELAY f DAC 0/180 STATE MACHINE TRACKING LOOP RX DATA CONTROLLER PHASE ROTATOR SYNCHRONIZATION CONTROLLER SLAVE ONLY PHASE SYNC_IN COMPARISON 0 0 90 90 SYNC_OUT DELAY 180 270 STATE MACHINE TRACKING LOOP DIV-BY-4 DCO Figure 53. Top Level Block Diagram of Synchronization Circuitry and Controller Figure 53 shows a top-level diagram of the synchronization • It is not possible to manually rotate the div-by-4 phases of controller (bottom) and how it interfaces to other digital the data path with the sync controller enabled. This can be functional blocks within the AD9739. Note the following a problem at lower clock rates were one may desire to rotate observations of this top level diagram: the div-by-4 phase to ensure locking of the data receiver controller and/or achieve a more optimum DCI_DEL value. • Synchronization between multiple devices is achieved by • The DCO output signal is generated from a separate div- rotating the div-by-4 phases of the slave devices such that by-4 circuit, and therefore, has a random phase upon each they align with the master. startup. For this reason, the DCO of the master should be • For the slave devices, the sync controller compares the phase distributed to all the FPGAs. alignment of the master’s SYNC_IN reference signal with o o the initial 0 /90 outputs of the div-by-4 and then rotates SYNC Controller Initialization Description the div-by-4 phase until the SYNC_IN signal falls between The sync controller of the master is enabled by writing 0x70 to these phases. Register 0x10. Once enabled, a state machine automatically adjusts • A reference signal common to all devices is required for the output delay of its SYNC_OUT signal such that the fed back synchronization. The master device generates this signal by reference SYNC_IN signal is centered between the 0° and 90° providing a SYNC_OUT signal which is then distributed to output phases associated with its div-by-4 circuit. Note that the all the devices (including itself with tight time alignment) coarse delay is performed by shifting phases via PHZ MUX while as a SYNC_IN signal. the fine delay that centers (and tracks) variation is done by a • Because the SYNC_IN signal has a defined relationship variable delay line. The variable delay line tap size is 12 ps. Once between the div-by-4 phase of the master, the slave devices can SYNC_IN is centered, the controller enters tracking mode such now align their respective div-by-4 phases to the SYNC_IN that SYNC_IN remains centered despite possible system variations phase thus ensuring phase alignment among all devices. in temperature and/or supply. Centering the SYNC_IN signal on the master device ensures that the SYNC_IN signals of the slave Rev. B | Page 36 of 48 PHZ MUX 4:1 MUX DATA ASSMBLER 07851-053 Data Sheet AD9739 devices also remain centered between their respective div-by-4 These sources of timing skews become more significant as the phases; therefore, providing the greatest margin to absorb nonideal DACCLK period is decreased (that is, clock rate is increased), timing skews. The following status bits are available in Register leaving less margin for timing skews external to the master-to- slave device(s). Special consideration to PCB layout and selection 0x21 indicating lock, lost-lock, and tracking: SYNC_LCK, SYNC_LST and SYNC_TRK_ON. of clock distribution ICs are required to ensure minimum skew between the distributed DACCLK and SYNC_IN signals. Note The sync controller of the slave is enabled by writing 0x50 to that timing skews can quickly accumulate considering that the Register 0x10. Once enabled, the state machine compares the propagation delay on an FR4 PCB is on the order of 170 ps/inch, reference SYNC_IN signal to the 0°/90° phase outputs of the and that output-to-output skews on each clock distribution IC div-by-4 phase settings. If the SYNC_IN signal does not fall can be as high as 25 ps. between these phases, the state machine of the slave rotates the div- by-4 phase setting until it does. To validate that phase alignment The problem becomes more pronounced in multiboard has been achieved, the SYNC_IN_PH90 and SYNC_IN_PH0 synchronization where clock signals (that is, DACCLK, status bits should read 1 and 0, respectively (that is, Register 0x0D, SYNC_OUT, and DCO) are distributed over a back plane to Bits[5:4]). Note that the DCO and SYNC_OUT outputs of the multiple PCBs. Data alignment among the various data sources slave can be disabled via Register 0x01, Bit 5. is required when driven by phase aligned DCO signals that are a buffered version of the master’s DCO. However, these data Synchronization Limitations sources (FPGAs) also have process, supply voltage, and Ensuring consistent synchronization over production lots in temperature sensitivities (PVTs) that can cause misalignment systems containing two or more AD9739s becomes increasingly among their respective DCI outputs. more challenging at the higher update rates because the timing Adding to this dilemma is that it also possible for the data offset between adjacent phases of the div-by-4 output clock is receiver controller of different AD9739s to converge on different equal to 1/fDAC . For example, a DAC update of 2 GSPS corresponds delay settings due to PVT variations of the delay line (even if to a 500 ps period. If the SYNC_IN signal of an ideal master o o DCI inputs are exactly aligned). This can result in a four sample device is positioned in the center of its div-by-4 0 and 90 phase pipeline mismatch between devices if the difference in absolute outputs, only ±250 ps of timing margin exists for the slave delays exceeds a period of 4/f . Recall that the controller searches DAC devices. This ideal margin is actually reduced by quadrature up/down for its first valid edge from its initial start value (that is, phase errors in the div-by-4 circuit of the master as well as its DCI_DEL and SMP_DEL). While the initial start values between ability to position the SYNC_IN exactly in the center of the 0° devices should be made the same, different absolute time delays and 90° output phases. due to PVT can cause devices to converge on different edges of The timing margin is further eroded by the following sources: DCI above or below this initial start value. As a result, confirm • Master-to-slave device(s) mismatch in the propagation delays that DCI_DEL values between multiple devices are matched in the mu delay clock path and SYNC_IN. Note that these sufficiently such that the absolute differences between the mismatches can be up to 100 ps between devices that are at readback DCI_DEL values do not exceed a data period (that is, opposite extremes of the process corners. 4/f ). If the difference exceeds a data period, modify the DAC • Quadrature phase errors in the div-by-4 outputs of the slave. DCI_DEL (and SMP_DEL) setting of the slave device so that its start point is roughly ½ the difference between the master and slave readback values. Rev. B | Page 37 of 48 AD9739 Data Sheet ANALOG INTERFACE CONSIDERATIONS INPUT D D D D D D D D D D 1 2 3 4 5 6 7 8 9 10 DATA ANALOG MODES OF OPERATION DACCLK_x The AD9739 uses the quad-switch architecture shown in Figure 54. D –D 3 8 The quad-switch architecture masks the code-dependent glitches D D –D –D 2 4 7 9 D D –D –D 1 5 6 10 that occur in a conventional two-switch DAC. Figure 55 compares FOUR-SWITCH t DAC OUTPUT the waveforms for a conventional DAC and the quad-switch (f MIX MODE) S –D –D D D 5 6 10 1 DAC. In the two-switch architecture, a code-dependent glitch –D D –D D 2 4 7 9 occurs each time the DAC switches to a different state (that is, –D D 3 8 D1 to D2). This code-dependent glitching causes an increased amount of distortion in the DAC. In a quad-switch architecture FOUR-SWITCH D D D D D DAC OUTPUT 6 7 8 9 10 t (no matter what the codes are), there are always two switches (RETURN TO D D D D D 1 2 3 4 5 ZERO MODE) transitioning at each half clock cycle, thus eliminating the code- dependent glitches. However, a constant glitch occurs at 2 × Figure 56. Mix-Mode and RZ DAC Waveforms DACCLK because half of the internal switches change state on the rising DACCLK edge, while the other half change state on Figure 56 shows the DAC waveforms for both the mix mode the falling DACCLK edge. and the RZ mode. Note that the disadvantage of the RZ mode V is the 6 dB loss of power to the load because the DAC is only DD functioning for ½ the DAC update period. This ability to change DACCLK_x modes provides the user the flexibility to place a carrier anywhere CLK V 1 G in the first three Nyquist zones, depending on the operating V 2 G mode selected. Switching between the analog modes reshapes V1 V 2 V 3V 4 LATCHES G G G G V 3 G the sinc roll-off inherent at the DAC output. The maximum DBx[13:0] V 4 G amplitude in all three Nyquist zones is impacted by this sinc roll-off, depending on where the carrier is placed (see Figure 57). IOUTP IOUTN As a practical matter, the usable bandwidth in the third Nyquist Figure 54. AD9739 Quad-Switch Architecture zone becomes limited at higher DAC clock rates (that is, >2 GSPS) INPUT D D D D D D D D D D 1 2 3 4 5 6 7 8 9 10 DATA when the output bandwidth of DAC core and the interface DACCLK_x network (that is, balun) contributes to additional roll-off. FIRST SECOND THIRD NYQUIST ZONE NYQUIST ZONE NYQUIST ZONE D D D D D 0 t TWO-SWITCH 1 2 3 4 5 MIX MODE DAC OUTPUT D D D D D 6 7 8 9 10 –5 RZ MODE –10 FOUR-SWITCH D D D D D 6 7 8 9 10 t DAC OUTPUT D D D D D –15 (NORMAL MODE) 1 2 3 4 5 NORMAL MODE –20 Figure 55. Two-Switch and Quad-Switch DAC Waveforms –25 Another attribute of the quad-switch architecture is that it also enables the DAC core to operate in one of the following three –30 modes: normal mode, mix mode, and return-to-zero (RZ) mode. –35 The mode is selected via SPI Register 0x08, Bits[1:0] with 0FS 0.25FS 0.50FS 0.75FS 1.00FS 1.25FS 1.50FS normal mode being the default value. In the mix mode, the FREQUENCY (Hz) output is effectively chopped at the DAC sample rate. This has Figure 57. Sinc Roll-Off for Each Analog Operating Mode the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the DAC sample rate, thus improving the output power of these images. The RZ mode is similar to the analog mix mode, except that the intermediate data samples are replaced with midscale values. Rev. B | Page 38 of 48 07851-054 07851-055 dBFS 07851-057 07851-056 Data Sheet AD9739 Each single-ended output can provide a squared-up output level CLOCK INPUT CONSIDERATIONS that can be varied from −4 dBm to +5 dBm allowing for >2 V p-p The quality of the clock source and its drive strength are output differential swings. The ADF4350 also includes an important considerations in maintaining the specified ac additional CML buffer that can be used to drive another performance. The phase noise and spur characteristics of the AD9739 device. clock source should be selected to meet the target application VDDC requirements. Phase noise and spurs at a given frequency offset 4-BIT PMOS IOUT ARRAY on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10 CLKx_OFFSET DIR_x = 0 (fOUT/fCLK) when the DAC clock path contribution, along with DACCLK_P ESD DACCLK_N CLKx_OFFSET thermal and quantization effects, are negligible. DIR_x = 0 The AD9739 clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or 4-BIT NMOS CML output drivers. For a low jitter sinusoidal clock source, the IOUT ARRAY ADCLK914 can be used to square-up the signal and provide a VSSC CML input signal for the AD9739 clock receiver. Note that all Figure 58. Clock Input and Common-Mode Control specifications and characterization presented in the data sheet The AD9739 clock receiver features the ability to independently are with the ADCLK914 driven by a high quality RF signal adjust the common-mode level of its inputs over a span of generator with the clock receiver biased at a 800 mV level. A ±100 mV centered about its midsupply point (that is, VDDC/2) dc blocking capacitor is used between the clock driver output as well as an offset for hysteresis purposes. Figure 58 shows the and clock receiver input to allow for different dc bias levels. equivalent input circuit of one of the inputs. ESD diodes are not To minimize signal loss for high clock rates, a high quality, dc shown for clarity purposes. It has been found through blocking RF capacitor is recommended. characterization that the optimum setting is for both inputs to Figure 60 shows a clock source based on the ADF4350 low phase be biased at approximately 0.8 V. This can be achieved by writing a noise/jitter PLL. The ADF4350 can provide output frequencies 0x0F (corresponding to a −15) setting to both cross controller from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. registers (that is, Register 0x22 and Register 0x23). V V CC REF ADCLK914 AD9739 V T 50Ω 50Ω 50Ω 50Ω 10nF 1nF 50Ω D Q DACCLK_P 100Ω D Q DACCLK_N 10nF 1nF 50Ω V EE Figure 59. ADCLK914 Interface to the AD9739 CLK Input AD9739 3.9nH V VCO ADF4350 1nF RF A+ OUT DACCLK_P N DIV-BY-2 PLL 100Ω VCO 1nF N = 0 – 4 DACCLK_N FREF RF A– OUT 1.8V p-p RF A+ OUT RF A– OUT Figure 60. ADF4350 Interface to the AD9739 CLK Input Rev. B | Page 39 of 48 07851-058 07851-059 07851-060 AD9739 Data Sheet 1.10 The following equation relates I to the FSC[9:0] register, OUTFS CLKP CLKN which can be set from 0 to 1023: 1.05 I = 22.6 × FSC[9:0]/1000 + 8.7 (1) OUTFS 1.00 Note that a default value of 0x200 generates 20 mA full scale, 0.95 which is used for most of the characterization presented in this 0.90 data sheet (unless noted otherwise). ANALOG OUTPUTS 0.85 Equivalent DAC Output and Transfer Function 0.80 The AD9739 provides complementary current outputs, IOUTP 0.75 and IOUTN, that source current into an external ground reference load. Figure 63 shows an equivalent output circuit for the DAC. 0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 Note that, compared to most current output DACs of this type, OFFSET CODE the AD9739 outputs exhibit a slight offset current (that is, Figure 61. Common-Mode Voltage with Respect to IOUTFS/16), and the peak differential ac current is slightly below CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N IOUTFS/2 (that is, 15/32 × IOUTFS). VOLTAGE REFERENCE I = 8.6 – 31.2mA OUTFS The AD9739 output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 62. 17/32 × I OUTFS AD9739 I = PEAK FSC[9:0] AC 15/32 × I 2.2pF V 70Ω OUTFS BG DAC 1.2V VREF 17/32 × I – OUTFS I120 CURRENT + 1nF SCALING IFULL-SCALE 10kΩ Figure 63. Equivalent DAC Output Circuit I120 AGND As shown in Figure 63, the DAC output can be modeled as a pair of Figure 62. Voltage Reference Circuit dc current sources that source a current of 17/32 × IOUTFS to each output. A differential ac current source, I is used to model PEAK, The reference current is obtained by forcing the band gap voltage the signal-dependent nature of the DAC output. The polarity across an external 10 kΩ resistor from I120 (Pin B14) to ground. and signal dependency of this ac current source are related to The 1.2 V nominal band gap voltage (VREF) generates a 120 μA the digital code by the following equations: reference current in the 10 kΩ resistor. Note the following constraints when configuring the voltage reference circuit: F(Code) = (DACCODE − 8192)/8192 (2) • Both the 10 kΩ resistor and 1 nF bypass capacitor are required −1 ≤ F(Code) < 1 (3) for proper operation. where DACCODE = 0 to 16,383 (decimal). • Adjusting the output full-scale current, I , of the DAC OUTFS Because I can swing ±(15/32) × I , the output currents PEAK OUTFS from its default setting of 20 mA should be performed measured at IOUTP and IOUTN can span from I /16 to OUTFS digitally. I . However, because the ac signal-dependent current OUTFS • The AD9739 is not a multiplying DAC. Modulating the component is complementary, the sum of the two outputs is reference current, I120, with an ac signal is not supported. always constant (that is, IOUTP + IOUTN = (34/32) × IOUTFS). • The band gap voltage appearing at VREF (Pin C14) must The code-dependent current measured at the IOUTP (and be buffered for use with external circuitry because its IOUTN) output is as follows: output impedance is approximately 5 kΩ. • An external reference can be used to overdrive the internal IOUTP = 17/32 × I + 15/32 × I × F(Code) (4) OUTFS OUTFS reference by connecting it to VREF (Pin C14). IOUTN = 17/32 × I − 15/32 × I × F(Code) (5) OUTFS OUTFS I can be adjusted digitally over 8.7 mA to 31.7 mA by using OUTFS FSC[9:0] (Register 0x06 and Register 0x07). Rev. B | Page 40 of 48 COMMON-MODE (V) 07851-062 07851-061 07851-063 Data Sheet AD9739 Figure 64 shows the IOUTP vs. DACCODE transfer function If the AD9739 is programmed for I = 20 mA, its peak ac OUTFS when I is set to 19.65 mA. current is 9.375 mA and its peak power delivered to the equivalent OUTFS 2 load is 2.2 mW (that is, P = I R). Because the source and load 20 resistance seen by the 1:1 balun are equal, this power is shared 18 equally; therefore, the output load receives 1.1 mW or 0.4 dBm. 16 To calculate the rms power delivered to the load, the following 14 must be considered: 12 • Peak-to-rms of the digital waveform 10 • Any digital backoff from digital full scale 8 • The DAC’s sinc response and nonideal losses in external 6 network 4 For example, a reconstructed sine wave with no digital backoff 2 ideally measures −2.6 dBm because it has a peak-to-rms ratio of 0 3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of 0 4096 8192 12,288 16,384 DAC CODE actual power can be expected in the region where the sinc response Figure 64. Gain Curve for FSC[9:0] = 512, DAC Offset = 1.228 mA of the DAC has negligible influence. Increasing the output power is best accomplished by increasing IOUTFS, although any degradation in Peak DAC Output Power Capability linearity performance must be considered acceptable for the The maximum peak power capability of a differential current target application. output DAC is dependent on its peak differential ac current, IPEAK, and the equivalent load resistance it sees. Because the AD9739 includes a differential 70 Ω resistance, it is best to use a doubly terminated external output network similar to what is shown in Figure 65. In this case, the equivalent load seen by the ac current source of the DAC is 25 Ω. R SOURCE = 50Ω I = 8.6 – 31.2mA OUTFS LOSSLESS I = R PEAK BALUN LOAD AC 70Ω 180Ω 15/32 × I = 50Ω OUTFS 1:1 Figure 65. Equivalent Circuit for Determining Maximum Peak Power to a 50 Ω Load Rev. B | Page 41 of 48 OUTPUT CURRENT (mA) 07851-064 07851-065 AD9739 Data Sheet Figure 68 shows an interface that can be considered when Output Stage Configuration interfacing the DAC output to a self-biased differential gain The AD9739 is intended to serve high dynamic range applications block. The inductors shown serve as RF chokes (L) that provide that require wide signal reconstruction bandwidth (that is, the dc bias path to analog ground. The value of the inductor, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac along with the dc blocking capacitors (C), determines the lower performance can only be realized if the DAC output is configured cutoff frequency of the composite pass-band response. An RF for differential (that is, balanced) operation with its output balun should also be considered before the RF differential gain common-mode voltage biased to analog ground. The output stage and any filtering to ensure symmetrical common-mode network used to interface to the DAC should provide a near 0 Ω impedance seen by the DAC output while suppressing any dc bias path to analog ground. Any imbalance in the output common-mode noise, harmonics, and clock spurs prior to impedance between the IOUTP and IOUTN pins results in amplification. asymmetrical signal swings that degrade the distortion OPTIONAL BALUN AND FILTER performance (mostly even order) and noise performance. IOUTP C Component selection and layout are critical in realizing the 90Ω L RF DIFF performance potential of the AD9739. C 70Ω AMP LPF 90Ω ® L MINI-CIRCUITS TC1-33-75G+ IOUTN IOUTP 90Ω Figure 68. Interfacing the DAC Output to the Self-Biased Differential Gain Stage 70Ω For applications operating the AD9739 in mix mode with output frequencies extending beyond 2.2 GHz, the circuits shown in IOUTN 90Ω Figure 69 should be considered. The circuit in Figure 69 uses a wideband balun with a configuration similar to the one shown Figure 66. Recommended Balun for Wideband Applications with Upper in Figure 68 to provide a dc bias path for the DAC outputs. The Bandwidths of up to 2.2 GHz circuit in Figure 70 takes advantage of ceramic chip baluns to Most applications requiring balanced-to-unbalanced conversion can provide a dc bias path for the DAC outputs while providing take advantage of the Ruthroff 1:1 balun configuration shown in excellent amplitude/phase balance over a narrower RF band. Figure 66. This configuration provides excellent amplitude/phase These low cost, low insertion loss baluns are available for balance over a wide frequency range while providing a 0 Ω dc bias different popular RF bands and provide excellent amplitude/ path to each DAC output. Also, its design provides exceptional phase balance over their specified frequency range. bandwidth and can be considered for applications requiring MINI-CIRCUITS C TC1-1-462M signal reconstruction of up to 2.2 GHz. The characterization plots IOUTP shown in this data sheet are based on the AD9739 evaluation 90Ω L board, which uses this configuration. Figure 67 compares the 70Ω L measured frequency response for normal and mix mode using 90Ω IOUTN the AD9739 evaluation board vs. the ideal frequency response. C 0 IDEAL BASEBAND MODE Figure 69. Recommended Mix Mode Configuration Offering Extended RF –3 Bandwidth Using a TC1-1-43A+ Balun BASEBAND –6 TC1-33-75G MURATA MIX MODE JOHANSON TECHNOLOGY –9 TC1-33-75G CHIP BALUNS IOUTP –12 IDEAL MIX MODE –15 70Ω 180Ω –18 –21 IOUTN –24 –27 Figure 70. Lowest Cost and Size Configuration for Narrow RF Band Operation –30 –33 –36 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz) Figure 67. Measured vs. Ideal Frequency Response for Normal (Baseband) and Mix Mode Operation Using a TC1-33-75G Transformer on the AD9739 Evaluation Board Rev. B | Page 42 of 48 POWER (dBc) 07851-067 07851-066 07851-070 07851-069 07851-068 Data Sheet AD9739 3. Images appear as replicas of the original signal, therefore, NONIDEAL SPECTRAL ARTIFACTS can be easier to identify. In the case of the AD9739, internal The AD9739 output spectrum contains spectral artifacts that modulation of the sampling clock at intervals related to are not part of the original digital input waveform. These non- f DAC/4 generate image pairs at ¼ × fDAC, ½ × fDAC, and ¾ × fDAC. ideal artifacts included harmonics (including alias harmonics), Both upper and lower sideband images associated with ¼ × images, and clock spurs. Figure 71 shows a spectral plot of the fDAC fall within the first Nyquist zone, while only the lower AD9739 within the first Nyquist zone (that is, dc to f /2) DAC image of ½ × fDAC and ¾ × fDAC fall back. Note that the lower reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides images appear frequency inverted. The difference in dBc the desired fundamental tone at the −7.8 dBm level, the spectrum between the fundamental and various images remains also reveals these nonideal artifacts that also appear as spurs mostly signal independent because the mechanism causing above the measurement noise floor. Because these nonideal these images is related to corruption of the sampling clock. artifacts are also evident in the second and third Nyquist zones 4. The magnitude of these images for a given device is dependent during mix mode operation, the effects of these artifacts should on several factors including DAC clock rate, output frequency, also be considered when selecting the DAC clock rate for a mu controller phase setting, and div-by-4 clock divider target RF band. phase (Register 0x14, bit [7:6]. Table 30 shows how the 0 magnitude of these images vary as the phase is varied for FUND AT –10 –7.6dBm the case represented in Figure 71. Because the phase varies –20 at power up, the image magnitude varies making it difficult to compensate digitally through a one-time factory –30 calibration procedure. Also, the image magnitude can vary –40 f /2 – DAC f /4 3/4 × f /4 – f DAC DAC OUT a few decibels over temperature and between devices due f –50 OUT HD3 to process dependencies. (Note that the AD9739A is a f /4 – DAC –60 HD2 f OUT viable option if factory calibration is considered acceptable HD5 –70 for nonmultichip synchronization applications operating HD6 HD9 HD4 –80 with clock rates in the 1.6 GSPS to 2.5 GSPS range). –90 Table 30. Image Magnitude vs. Phase (PHZ) Setting –100 0 200 400 600 800 1000 1200 Image location PHZ0 PHZ1 PHZ2 PHZ3 FREQUENCY (MHz) fDAC/4 − fOUT −70.2 −71.4 −72.2 −77.1 Figure 71. Spectral Plot fDAC/2 − fOUT −80.2 −71.3 −69.9 −74.9 ¾ × fDAC − fOUT −69.9 −72.5 −73.4 −73.7 Note the following important observations pertaining to these nonideal spectral artifacts: 5. A clock spur appears at f /4 and integer multiples of this DAC 1. A full-scale sine wave (that is, single-tone) typically represents frequency. Similar to images, the spur magnitude is also the worst-case condition because it has a peak-to-rms ratio of dependent on the same factors that cause variations in 3 dB and is unmodulated. Harmonics and aliased harmonics image levels. However, unlike images and harmonics, clock of a sine wave are easy to identify because they also appear spurs always appear as discrete spurs, albeit their magnitude as discrete spurs. Significant characterization of a high shows a slight dependency on the digital waveform and speed DAC is performed using single (or multitone) output frequency. Note that the clock spur appearing at fDAC/4 signals for this reason. can also be factory calibrated. 2. Modulated signals (that is, AM, PM, or FM) do not appear as 6. A large clock spur also appears at 2 × f in either normal DAC spurs but rather as signals whose power spectral density is or mix mode operation. This clock spur is due to the quad spread over a defined bandwidth determined by the switch DAC architecture causing switching events to occur modulation parameters of the signals. Any harmonics from on both edges of f . DAC the DAC spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. For this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern. Rev. B | Page 43 of 48 POWER (dBc) 07851-071 AD9739 Data Sheet LAB EVALUATION OF THE AD9739 POWER DISSIPATION AND SUPPLY DOMAINS Figure 72 shows a recommended lab setup that was used to The power dissipation of the AD9739 is dependent on the DAC characterize the performance of the AD9739. The DPG2 is a clock rate as shown in Figure 73 and Figure 74. The current dual port LVDS/CMOS data pattern generator available from consumption from the 3.3 V supply remains relatively constant Analog Devices, Inc., with an up to 1.25 GSPS data rate. The because it is used for biasing the DAC core (that is, VDDA) and DPG2 directly interfaces to the AD9739 evaluation board via differential input receivers (that is, VDD33). However, the current Tyco Z-PACK HM-Zd connectors. A low phase noise/jitter RF consumption from the 1.8 V supply is clock rate dependent and source, such as an R&S SMA100A signal generator, is used for increases linearly with frequency because this supply is used by the DAC clock. A 5 V power supply is used to power up the the digital path (that is, VDD) as well as the clock distribution AD9739 evaluation board, and SMA cabling is used to interface circuitry (that is, VDDC). to the supply, clock source, and spectrum analyzer. A USB 2.0 Treat the VDDC supply as an analog supply because the clock interface to a host PC is used to communicate to both the AD9739 distribution circuitry has poor power supply rejection; therefore, evaluation board and the DPG2. noise on this supply can induce clock jitter. To ensure low noise A high dynamic range spectrum analyzer is required to evaluate on this sensitive supply, use a separate 1.8 V regulator powered the AD9739 reconstructed waveform’s ac performance. This is from the 3.3 V analog supply rail that is also used to power especially the case when measuring ACLR performance for high VDDA. This supply rail can also be used to power-up VDD33 dynamic range applications, such as multicarrier DOCSIS CMTS via an LC filter network. The digital 1.8 V supply, VDD, can be applications. Harmonic, SFDR, and IMD measurements pertaining supplied via a well-filtered switching regulator. to unmodulated carriers can benefit by using a sufficiently high 1.2 RF attenuation setting because these artifacts are easy to identify 1.1 above the spectrum analyzer noise floor. However, reconstructed 1.0 TOTAL waveforms having modulated carrier(s) often benefit from the 0.9 use of a high dynamic range RF amplifier and/or passive filters 0.8 to measure close-in and wideband ACLR performance when 0.7 using spectrum analyzers of limited dynamic range. 0.6 0.5 VDD USB 2.0 ADI PATTERN GENERATOR LAB 0.4 PC DPG2 VDDC 0.3 0.2 LVDS VDDA DATA 0.1 DCO AND DCI VDD33 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 GPIB f (MHz) DAC 1.6GHz TO Figure 73. Power Consumption vs. f @ 25°C POWER DAC 2.5GHz AD9739 SUPPLY 3dBm RHODE AND EVAL. BOARD +5V 360 SCHWARTZ SMA 100A 330 10 MHz 300 REFIN AGILENT PSA 10 MHz E4440A 270 REOUT 240 Figure 72. Lab Test Setup Used to Characterize the AD9739 210 I_VDD 180 150 I_VDDC 120 90 60 I_VDDA 30 I_VDD33 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 f (MHz) DAC Figure 74. Current Consumption vs. fDAC @ 25°C Rev. B | Page 44 of 48 07851-072 CURRENT (mA) POWER (W) 07851-074 07851-073 Data Sheet AD9739 RECOMMENDED START-UP SEQUENCE • The mu controller must be first enabled (and in track mode) before the data receiver controller is enabled because the Upon power-up of the AD9739, a host processor is required DCO output signal is derived from this circuitry. to initialize and configure the AD9739 via its SPI port. Figure 75 • A wait period is related to f periods. DATA shows a flowchart of the sequential steps required, while Table 31 • Limit the number of attempts to lock the controllers to and Table 32 provides more detail on the SPI register write/read three; locks typically occur on the first attempt. operations required to implement the flowchart steps. Note the • Hardware or software interrupts can be used to monitor following: the status of the controllers. • A software reset is optional because the AD9739 has both an internal POR circuit and a RESET pin. • The SYNC controller is optional because it is only required to synchronize two or more devices. If synchronization is required, validate that DCI_DEL values between devices are sufficiently matched. CONFIGURE NO CONFIGURE NO CONFIGURE NO COMPARE CONFIGURE SYNC. SPI PORT SYNC Rx DATA DCI_DEL MU CONT. ONLY CONT. VALUES CONT. SOFTWARE WAIT A RESET WAIT A WAIT A RECONFIGURE FEW 100µs FEW 100µs FEW 100µs TxDAC FROM DEFAULT SETTING SET CLK INPUT CMV Rx OPTIONAL MU CONT. SYNC CONT. DATA CONT. LOCKED? VALID? LOCKED? YES YES YES Figure 75. Flowchart for Initialization and Configuration of the AD9739 Rev. B | Page 45 of 48 07851-075 AD9739 Data Sheet Table 31. Recommended SPI Initialization with SYNC Controller Disabled Step Address (Hex) Write Value Comments 1 0x00 0x00 Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up. 2 0x00 0x20 Software reset to default SPI values. 3 0x00 0x00 Clear the reset bit. 4 0x22 0x0F Set the common-mode voltage of DACCLK_P and DACCLK_N inputs. 5 0x23 0x0F 6 0x24 0x30 Configure the mu controller. Refer to Table 28 for recommended target mu slope and phase settings vs. clock rate. 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6C 10 0x29 0xCB 11 0x26 0x02 12 0x26 0x03 Enable the mu controller search and track mode. 13 Not applicable Not applicable Wait for 160 K × 1/f cycles. DATA 14 0x2A Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure. 15 Not applicable Not applicable Ensure that the AD9739 is fed with DCI clock input from the data source. 16 0x13 0x72 Set FINE_DEL_SKEW to 2. 17 0x10 0x00 Disable the data Rx controller before enabling it. 18 0x10 0x02 Enable the data Rx controller for loop and IRQ. 19 0x10 0x03 Enable the data Rx controller for search and track mode. 20 Not applicable Not applicable Wait for 135 K × 1/f cycles. DATA 21 0x21 Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, advance the CLKDIVPH[1:0] phase in Register 0x14, Bit[7:6] before proceeding to Step 17 to repeat attempt. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure. 22 0x06, 0x07 0x00, 0x02 Optional: modify the TxDAC I setting (the default is 20 mA). OUTFS 23 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode). Rev. B | Page 46 of 48 Data Sheet AD9739 Table 32. Recommended SPI Initialization with SYNC Controller Enabled Step Address (Hex) Write Value Comments 1 0x00 0x00 Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up. 2 0x00 0x20 Software reset to default SPI values. 3 0x00 0x00 Clear the reset bit. 4 0x22 0x0F Set the common-mode voltage of DACCLK_P and DACCLK_N inputs. 5 0x23 0x0F 6 0x24 0x30 Configure the mu controller. Refer to Table 28 for recommended target Mu slope and phase settings vs. clock rate. 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6C 10 0x29 0xCB 11 0x26 0x02 12 0x26 0x03 Enable the mu controller search and track mode. 13 Not applicable Not applicable Wait for 160 K × 1/f cycles. DATA 14 0x2A Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure. 15 0x15 0x42 Configure sync controller. 16 0x10 0x00 Disable sync controller before enabling it. 17 0x10 0x60 or 0x40 Enable sync controller for loop and IRQ. 0x60 = master mode. 0x40 = slave mode. 18 0x10 0x70 or 0x50 Enable sync controller: 0x70 = master mode. 0x50 = slave mode. 19 Not applicable Not applicable Wait for 160 K × 1/f for DLL to lock. DATA 20 0x21 Read back Register 0x21 to confirm proper operation: 0x90 = master mode. 0x00 = slave mode. If not, proceed to Step 15 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure. 21 0x0D Read back Register 0x0D and confirm Bits[5:4] = 10. If not, proceed to Step 2 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure. 22 Not applicable Not applicable Ensure that the AD9739 is fed with DCI clock input from the data source. 23 0x13 0x72 Set FINE_DEL_SKEW to 2. 24 0x10 0x00 Disable the data Rx controller before enabling it. 25 0x10 0x02 Enable the data Rx controller for loop and IRQ. 26 0x10 0x03 Enable the data Rx controller for search and track mode. 27 Wait for 135 K × 1/fDATA cycles. 28 0x21 Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure. 29 Not applicable Not applicable Readback DCI_DEL value in Register 0x13 and Register 0x14 for master and. If slave devices are not within 40 codes of each other, re-specify target DCI_DEL value to be average between master and readback DCI_DEL value. 30 0x06, 0x07 0x00, 0x02 Optional: modify the TxDAC I setting (the default is 20 mA). OUTFS 31 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode). Rev. B | Page 47 of 48 AD9739 Data Sheet OUTLINE DIMENSIONS 12.10 12.00 SQ A1 BALL 11.90 CORNER A1 BALL 13 11 9 7 5 3 1 10 8 6 4 2 14 12 CORNER A B C D 10.40 E BSC SQ F G H 0.80 J BSC K L M N P BOTTOM VIEW TOP VIEW 1.00 MAX DETAIL A DETAIL A 0.85 MIN 0.43 MAX 1.40 MAX 0.25 MIN 0.55 COPLANARITY SEATING 0.50 0.12 PLANE 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. Figure 76. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9739BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBC −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBCRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739-R2-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07851-0-1/12(B) Rev. B | Page 48 of 48 11-18-2011-A