ANALOG DEVICES AD9726

16-Bit, 400 MSPS Digital-to-Analog Converter AD9726 FEATURES FUNCTIONAL BLOCK DIAGRAM Dynamic performance CLK+ SFDR ≥ 78 dBc at f = 20 MHz CLOCK DISTRIBUTION CSB OUT AND CONTROL CLK– IMD ≥ 82 dBc at f = 70 MHz OUT SCLK ACLR ≥ 76 dBc at f = 70 MHz OUT SPI SDIO NSD ≤ −160 dB/Hz at f = 70 MHz OUT SDO DCLK_OUT+ Precision calibrated linearity LVDS OUTPUT DRIVER RESET DCLK_OUT– DNL ≤ ±0.5 LSB at +25°C INL ≤ ±1.0 LSB at +25°C THD ≤ −95 dB at f = 1 MHz OUT CALIBRATION LVDS inputs with internal 100 Ω terminations MEMORY DB[15]+ Automatic data/clock timing synchronization Single data rate or double data rate capable DB[15]– Differential current outputs IOUTA Internal precision reference 16-BIT DAC Operates on 2.5 V and 3.3 V supplies DB[0]+ IOUTB Extended industrial temperature range DB[0]– Thermally enhanced, 80-lead, RoHS-compliant TQFP_EP package REFIO DCLK_IN+ INTERNAL REFERENCE DCLK_IN– FSADJ APPLICATIONS Instrumentation Figure 1. Test equipment . Waveform synthesis Communications systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9726 is a 16-bit digital-to-analog converter (DAC) 1. A unique combination of precision and performance that offers leading edge performance at conversion rates of up makes the AD9726 equally suited to applications with to 400 MSPS. The device uses low voltage differential signaling demanding frequency domain or demanding time domain (LVDS) inputs and includes internal 100 Ω terminations. The requirements. analog output can be single-ended or differential current. An 2. Nonvolatile factory calibration assures a highly linear internal precision reference is included. transfer function. Internal logic offers on demand self- calibration for linearity even at extended operating The AD9726 also features synchronization logic to monitor and temperatures. optimize the timing between incoming data and the sample clock. 3. Proprietary architecture minimizes data dependent, This reduces system complexity and simplifies timing require- discrete mixing spurs and offers enhanced dynamic ments. An LVDS clock output is also available to drive an external performance over a wide range of output frequencies. data pump in either single data rate (SDR) or double data rate High input data rates create a very high frequency (DDR) mode. synthesis bandwidth. All device operation is fully programmable using the flexible 4. The fully automatic, transparent synchronizer maintains serial port interface (SPI). The AD9726 is also fully functional optimized timing between clock and data in real time and in its default state for applications without a controller. offers programmable control options for added flexibility. 5. Full-scale output current is external resistor programmable. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. LVDS INPUT DATA CAPTURE DATA SYNCHRONIZATION 04540-001 AD9726 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ........................................... 12  Applications ....................................................................................... 1  Serial Port Interface ........................................................................ 15  Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 17  General Description ......................................................................... 1  DAC Clock and Data Clock Output ........................................ 17  Product Highlights ........................................................................... 1  Data Clock Input ........................................................................ 17  Revision History ............................................................................... 2  Data Synchronization Circuitry ............................................... 18  Specif ica t ions ..................................................................................... 3  Analog Output ............................................................................ 18  DC Specifications ......................................................................... 3  Internal Reference and Full-Scale Output .............................. 19  AC Specifications .......................................................................... 4  Reset ............................................................................................. 19  Digital Signal Specifications ........................................................ 5  Serial Port Interface ................................................................... 19  Timing Specifications .................................................................. 5  SPI Pin Description .................................................................... 20  Timing Diagrams .......................................................................... 6 Calibration ................................................................................... 20  Absolute Maximum Ratings ............................................................ 8  Sync Logic Operation and Programming ............................... 22  Thermal Resistance ...................................................................... 8  Outline Dimensions ....................................................................... 24  ESD Caution .................................................................................. 8  Ordering Guide .......................................................................... 24  Pin Configuration and Function Descriptions ............................. 9  Terminology .................................................................................... 11  REVISION HISTORY 2/10—Rev. A to Rev. B 11/05—Rev. 0 to Rev. A Changes to Table 4 ............................................................................ 5 Changes to Features .......................................................................... 1 Added Figure 4 and Figure 5, Renumbered Sequentially ........... 6 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Figure 5 and Table 7 ..................................................... 9 Changes to the Terminology Section ........................................... 10 Changes to Table 9 .......................................................................... 16 Changes to the Driving the DAC Clock Inputs Section ............ 15 Added Data Synchronization Circuitry Bypass Section ............ 18 Changes to the Reset and Serial Port Interface Sections ........... 17 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 22 Changes to the Ordering Guide ................................................... 22 7/05—Revision 0: Initial Version Rev. B | Page 2 of 24 AD9726 SPECIFICATIONS DC SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, I = 20 mA, internal reference, OUT-FS T to T , unless otherwise specified. MIN MAX Table 1. Parameter Min Typ Max Unit 1 ACCURACY DNL ±0.5 ±1.0 LSB INL ±1.0 ±2.5 LSB Offset Error 0.003 % FS Gain Error 0.003 % FS ANALOG OUTPUT Full-Scale Current 20 mA Compliance Voltage ±1 V Output Impedance 10 MΩ INTERNAL REFERENCE Output Voltage 1.18 1.22 1.27 V 2 Output Current 1 μA EXTERNAL REFERENCE Input Voltage 1.2 V Input Resistance 10 MΩ Small Signal Bandwidth 200 kHz TEMPERATURE COEFFICIENTS Gain Drift ±10 ppm of FS/ºC Offset Drift ±10 ppm of FS/ºC Reference Drift ±30 ppm/ºC 3 POWER SUPPLIES AVDD1, AVDD2 Voltage Range 3.13 3.47 V Supply Current (IAVDD1 + IAVDD2) 52 60 mA ADVDD, ACVDD Voltage Range 2.37 2.63 V Supply Current (I + I) 16 18 mA ACVDD ADVDD CLKVDD Voltage Range 2.37 2.63 V Supply Current (ICLKVDD) 45 50 mA DVDD Voltage Range 2.37 2.63 V Supply Current (I) 80 90 mA DVDD DBVDD Voltage Range 3.13 3.47 V Supply Current (IDBVDD) 16 18 mA POWER DISSIPATION (PDISS) 575 mW Sleep Mode 465 mW Power-Down Mode ≤10 mW OPERATING TEMPERATURE RANGE −40 +85 °C 1 TAMB = 25°C. 2 Use buffer amplifier to drive external load. 3 Supply currents and power dissipation measured in SDR with fDAC = 400 MHz and fOUT = 1 MHz. Rev. B | Page 3 of 24 AD9726 AC SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference, TMIN to TMAX, unless otherwise specified. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Output Settling Time (tST) to 0.1% 10.5 ns Output Rise Time (10% to 90%) 500 ns Output Fall Time (90% to 10%) 500 ns Output Noise (I = 20 mA) 45 pA/√Hz OUTFS TOTAL HARMONIC DISTORTION (THD) f = 400 MHz, f = 1 MHz, 0 dBFS −95 dB DAC OUT SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 400 MHz, 0 dBFS f = 20 MHz 78 dBc OUT f = 70 MHz 68 dBc OUT fOUT = 140 MHz 62 dBc fDAC = 400 MHz, –3 dBFS fOUT = 20 MHz 80 dBc f = 70 MHz 70 dBc OUT f = 140 MHz 62 dBc OUT f = 200 MHz, 0 dBFS DAC fOUT = 20 MHz 84 dBc fOUT = 70 MHz 62 dBc fDAC = 200 MHz, –3 dBFS f = 20 MHz 82 dBc OUT f = 70 MHz 68 dBc OUT TWO-TONE INTERMODULATION DISTORTION (IMD) f = 400 MHz, 0 dBFS DAC f = 20 MHz, f = 21 MHz 86 dBc OUT1 OUT2 fOUT1 = 70 MHz, fOUT2 = 71 MHz 82 dBc fOUT1 = 140 MHz, fOUT2 = 141 MHz 74 dBc ADJACENT CHANNEL LEAKAGE RATIO (ACLR) fDATA = 245.76 MSPS, fCARRIER = 70 MHz, One-Carrier WCDMA 76 dBc fDATA = 245.76 MSPS, fCARRIER = 70 MHz, Two-Carrier WCDMA 70 dBc fDATA = 245.76 MSPS, fCARRIER1 = 70 MHz, Four-Carrier WCDMA 66 dBc f = 245.76 MSPS, f = 70 MHz, Eight-Carrier WCDMA 62 dBc DATA CARRIER1 NOISE SPECTRAL DENSITY (NSD) fDAC = 400 MHz, fOUT = 70 MHz, 0 dBFS −160 dBm/Hz f = 400 MHz, f = 70 MHz, –3 dBFS −163 dBm/Hz DAC OUT f = 400 MHz, f = 70 MHz, –6 dBFS −165 dBm/Hz DAC OUT UPDATE RATE 0 400 MSPS Rev. B | Page 4 of 24 AD9726 DIGITAL SIGNAL SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference, TMIN to TMAX, unless otherwise specified. Table 3. Parameter Min Typ Max Unit DAC CLOCK INPUTS (CLK±) Differential Voltage 0.5 1.0 V Common-Mode Voltage 1.0 1.25 V LVDS INPUTS (DB[15:0]±, DCLK_IN±) Input Voltage Range 825 1575 mV Differential Threshold Voltage 100 mV Differential Input Impedance 100 Ω LVDS OUTPUT (DCLK_OUT±) 1 Differential Output Voltage 250 400 mV Offset Voltage 1.0 1.2 V Short-Circuit Output Current 20 mA CMOS INPUTS (CSB, SCLK, SDIO, RESET) Logic 0 Voltage 0.5 V Logic 1 Voltage 2.5 V Input Current 1 nA CMOS OUTPUTS (SDO, SDIO) Logic 0 Voltage 0.5 V Logic 1 Voltage 3.0 V Short-Circuit Output Current 10 mA CONTROL INPUTS (SPI_DIS, SDR_EN) Logic 0 Voltage 0.5 V Logic 1 Voltage 2.0 V Input Current 1 nA 1 With 100 Ω external load. TIMING SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, I = 20 mA, internal reference, OUT-FS T to T , unless otherwise specified. MIN MAX Table 4. Parameter Min Typ Max Unit LVDS DATA BUS Data Synchronization Enabled (Default) DDR DCLK_OUT± Propagation Delay (t) 2000 ps DCPD-DDR DDR DB[15:0]± Setup Time (tDSU-DDR) −100 ps DDR DB[15:0]± Hold Time (tDH-DDR) 500 ps SDR DCLK_OUT± Propagation Delay (tDCPD-SDR) 300 ps SDR DB[15:0]± Setup Time (t) −100 ps DSU-SDR SDR DB[15:0]± Hold Time (t) 500 ps DH-SDR Data Synchronization Bypassed DB[15:0]± Setup Time (tDSU-BYPASS) 800 ps DB[15:0]± Hold Time (tDH-BYPASS) 50 ps CLK± to IOUT Propagation Delay (tPD-BYPASS) 0.85 ns DB[15:0]± to IOUT Pipeline Delay (t ) 4 DAC clock cycles PIPE-BYPASS Rev. B | Page 5 of 24 AD9726 Parameter Min Typ Max Unit SERIAL PORT INTERFACE SCLK Frequency (fSCLK) 15 MHz SCLK Rise/Fall Time 1 ms SCLK Pulse Width High (t) 30 ns CPWH SCLK Pulse Width Low (t) 30 ns CPWL SCLK Setup Time (t) 30 ns CSU SDIO Setup Time (tDSU) 30 ns SDIO Hold Time (tDH) 0 ns SDIO/SDO Valid Time (t) 30 ns DV RESET PULSE WIDTH 1.5 ns TIMING DIAGRAMS DAC CLOCK t DCPD-DDR DATACLOCK OUTPUT DATA BUS t t DSU-DDR DH-DDR DATACLOCK INPUT Figure 2. DDR Timing Diagram DAC CLOCK t DCPD-SDR DATACLOCK OUTPUT DATA BUS t t DSU-SDR DH-SDR DATACLOCK INPUT Figure 3. SDR Timing Diagram DB0 TO DB15 t t DSU-BYPASS DH-BYPASS CLK+/CLK– t PD-BYPASS IOUTA OR IOUTB Figure 4. Data Synchronization Bypass Timing Diagram Rev. B | Page 6 of 24 04540-100 04540-003 04540-002 AD9726 DB0 TO DB15 CLK+/CLK– t + t PIPE-BYPASS PD-BYPASS IOUTA OR IOUTB Figure 5. Data Synchronization Bypass Pipeline Delay CSB SCLK SET-UP TIME t CSU SCLK PULSE WIDTH HIGH/LOW TIME t t CPWH CPWL SCLK SDIO SET-UP TIME SDIO HOLD TIME SDIO (SD0) VALID TIME t t t DSU DH DV SDIO (SD0) Figure 6. SPI Timing Diagram Rev. B | Page 7 of 24 04540-101 04540-004 AD9726 ABSOLUTE MAXIMUM RATINGS Table 5. THERMAL RESISTANCE Parameter With Respect to Rating Thermal impedance can be lowered to 23°C/W by soldering the DBVDD, AVDD1, DBGND, AGND1, −0.3 V to 3.6 V exposed package pad to an external heat sink (for example, the AVDD2 AGND2 internal PCB copper ground plane). However, this is not necessary DVDD, CLKVDD, DGND, CLKGND, −0.3 V to 2.8 V for the power dissipation and operating temperature range of ACVDD, ADVDD ACGND, ADGND the AD9726. DBGND, AGND1, DBGND, AGND1, −0.3 V to +0.3 V AGND2 AGND2 Table 6. Thermal Resistance DGND, CLKGND, DGND, CLKGND, −0.3 V to +0.3 V Package Type θJA Unit ACGND, ADGND ACGND, ADGND 80-Lead TQFP_EP Package, Thermally Enhanced 32 °C/W REFIO, FSDAJ AGND1 −0.3 V to AVDD1 + 0.3 V IOUTA, IOUTB AGND1 −1.0 V to AVDD1 ESD CAUTION + 0.3 V CLK± CLKGND −0.3 V to CLKVDD + 0.3 V DB[15:0]±, DBGND −0.3 V to DBVDD DCLK_IN±, + 0.3 V DCLK_OUT± CSB, SCLK, SDIO, DBGND −0.3 V to DBVDD SDO, RESET, REXT + 0.3 V SDR_EN, SPI_DIS ADGND −0.3 V to ADVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 24 AD9726 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 CLKVDD FSADJ PIN 1 2 59 REXT REFIO 3 58 CLKVDD RESET 4 57 CLKGND CSB CLK+ 5 56 SCLK (SYNCUPD) CLK– 6 55 SDIO CLKGND 7 54 SDO (SYNCALRM) AD9726 DGND 8 53 DGND TOP VIEW DVDD 9 52 DVDD (Not to Scale) 10 51 DB15+ DB0– 11 50 DB15– DB0+ 12 49 DB14+ DB1– DB14– 13 48 DB1+ DB13+ 14 47 DB2– DB13– 15 46 DB2+ 16 45 DB12+ DB3– 17 44 DB12– DB3+ 18 43 DB11+ DB4– 19 42 DB11– DB4+ 20 41 DBVDD DBGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES. Figure 7. Pin Configuration Table 7. Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description 1 CLKVDD Clock Supply Voltage 22 DB10+ Data Bit 10 True 1 2 REXT Sets Data Clock Output Drive 23 DB10− Data Bit 10 Complement 3 CLKVDD Clock Supply Voltage 24 DB9+ Data Bit 9 True 4 CLKGND Clock Supply Common 25 DB9− Data Bit 9 Complement 5 CLK+ DAC Clock Input True 26 DB8+ Data Bit 8 True 6 CLK− DAC Clock Input Complement 27 DB8− Data Bit 8 Complement 7 CLKGND Clock Supply Common 28 DCLK_OUT+ Data Clock Output True 8 DGND Digital Supply Common 29 DCLK_OUT− Data Clock Output Complement 9 DVDD Digital Supply Voltage 30 DBVDD Data Bus Supply Voltage 10 DB15+ Data Bit 15 True 31 DBGND Data Bus Supply Common 11 DB15− Data Bit 15 Complement 32 DCLK_IN+ Data Clock Input True 12 DB14+ Data Bit 14 True 33 DCLK_IN− Data Clock Input Complement 13 DB14− Data Bit 14 Complement 34 DB7+ Data Bit 7 True 14 DB13+ Data Bit 13 True 35 DB7− Data Bit 7 Complement 15 DB13− Data Bit 13 Complement 36 DB6+ Data Bit 6 True 16 DB12+ Data Bit 12 True 37 DB6− Data Bit 6 Complement 17 DB12− Data Bit 12 Complement 38 DB5+ Data Bit 5 True 18 DB11+ Data Bit 11 True 39 DB5− Data Bit 5 Complement 19 DB11− Data Bit 11 Complement 40 DBVDD Data Bus Supply Voltage 20 DBVDD Data Bus Supply Voltage 41 DBGND Data Bus Supply Common 21 DBGND Data Bus Supply Common 42 DB4+ Data Bit 4 True Rev. B | Page 9 of 24 SPI_DIS DBGND DB10+ ADVDD DB10– ADGND DB9+ ACVDD DB9– ACGND DB8+ AVDD2 DB8– AGND2 DCLK_OUT+ AVDD1 DCLK_OUT– AGND1 DBVDD IOUTA DBGND IOUTB DCLK_IN+ AGND1 DCLK_IN– AVDD1 DB7+ AGND2 DB7– AVDD2 DB6+ ACGND DB6– ACVDD DB5+ ADGND DB5– ADVDD DBVDD SDR_EN 04540-005 AD9726 Pin Pin No. Mnemonic Description No. Mnemonic Description 43 DB4− Data Bit 4 Complement 69 AGND1 Analog Supply Common 44 DB3+ Data Bit 3 True 70 IOUTB Analog Current Output Complement 45 DB3− Data Bit 3 Complement 71 IOUTA Analog Current Output True 46 DB2+ Data Bit 2 True 72 AGND1 Analog Supply Common 47 DB2− Data Bit 2 Complement 73 AVDD1 Analog Supply Voltage 48 DB1+ Data Bit 1 True 74 AGND2 Analog Supply Common 49 DB1− Data Bit 1 Complement 75 AVDD2 Analog Supply Voltage 50 DB0+ Data Bit 0 True 76 ACGND Analog Supply Common 51 DB0− Data Bit 0 Complement 77 ACVDD Analog Supply Voltage 52 DVDD Digital Supply Voltage 78 ADGND Analog Supply Common 53 DGND Digital Supply Common 79 ADVDD Analog Supply Voltage 2 8 54 SDO (SYNCALRM) SPI Data Output (SYNCALRM) 80 SPI_DIS Serial Port Interface Disable 3 55 SDIO SPI Data Input/Output EPAD Analog Ground. Serves as an 4 electrical connection to the 56 SCLK (SYNCUPD) SPI Clock Input (SYNCUPD) substrate of the die and should be 57 CSB SPI Chip Select Bar (Active Low) connected to ground for electrical 58 RESET Hardware Reset (Active High) and thermal purposes. 5 59 REFIO Internal Reference Input/Output 1 6 Nominally 1 kΩ to DBGND (may be omitted if data clock output is unused). 60 FSADJ Output Current Full-Scale Adjust 2 SDO is output in 4-wire SPI mode and three-state in 3-wire SPI mode. If SPI is 7 61 SDR_EN Single Data Rate Mode Enable disabled (SPI_DIS = ADVDD), the alternate pin function is SYNCALRM output. 3 62 ADVDD Analog Supply Voltage SDIO is input only in 4-wire SPI mode and bidirectional in 3-wire SPI mode. 4 If SPI is disabled (SPI_DIS = ADVDD), the alternate pin function is SYNCUPD. 63 ADGND Analog Supply Common 5 Bypass with 0.1 μF to AGND1. Use the buffer amp to drive external circuitry. 64 ACVDD Analog Supply Voltage Limit the output current to 1 μA. Apply an external reference to this pin. 6 Nominally 2 kΩ to AGND1 for 20 mA full-scale output (internal reference). 65 ACGND Analog Supply Common 7 If SPI is disabled, tie the pin to ADVDD to enable SDR. Otherwise, tie to 66 AVDD2 Analog Supply Voltage ADGND. 8 Tie the pin to ADVDD to disable SPI; otherwise, tie to ADGND. 67 AGND2 Analog Supply Common 68 AVDD1 Analog Supply Voltage Rev. B | Page 10 of 24 AD9726 TERMINOLOGY Temperature Drift Integral Nonlinearity (INL) Temperature drift is specified as the maximum change in a The maximum deviation of the actual analog output from the parameter from ambient temperature (25°C) to either TMIN ideal output, as determined by a straight line drawn from zero or TMAX and is typically reported as ppm/°C. scale to full scale. Power Supply Rejection Differential Nonlinearity (DNL) The maximum change in the full-scale output as all power A measure of the maximum deviation in analog output associated supplies are varied over their respective operating voltage range. with any single value change in the digital input code relative to an ideal LSB. Spurious-Free Dynamic Range (SFDR) The difference in decibels between the peak amplitude of a test Offset Error tone and the peak amplitude of the largest spurious signal over The deviation of the output current from the ideal zero-scale the specified bandwidth. current. For differential outputs, 0 mA is expected at IOUTA when all inputs are low, and 0 mA is expected at IOUTB when all inputs Intermodulation Distortion (IMD) are high. The difference in decibels between the maximum peak amplitude of two test tones and the maximum peak amplitude Monotonicity of the distortion products created from the sum or difference A DAC is monotonic if the analog output increases or remains of integer multiples of the test tones. constant in response to an increase in the digital input. Adjacent Channel Leakage Ratio (ACLR) Gain Error The ratio between the measured power of a wideband signal The deviation of the output current from the ideal full-scale within a channel relative to the measured power in an empty current. Actual full-scale output current is determined by adjacent channel. subtracting the output when all inputs are low from the output when all inputs are high. Noise Spectral Density (NSD) The measured noise power over a 1 Hz bandwidth seen at the Output Compliance Range analog output. The range of allowable voltage seen by the analog output of a current output DAC. Operation beyond the compliance limits Total Harmonic Distortion (THD) may cause output stage saturation and/or breakdown resulting The ratio in decibels of the rms power sum of the first six in nonlinear performance. harmonic components to the rms power of the output signal. Rev. B | Page 11 of 24 AD9726 TYPICAL PERFORMANCE CHARACTERISTICS 100 630 620 90 –6dB 610 600 80 SDR –3dB 590 DDR 70 580 0dB 570 60 560 50 550 0 50 100 150 200 0 1224 36 48 607284 96 108 120 132 144 (MHz) f (MHz) f OUT OUT Figure 11. Power Consumption vs. fOUT at 400 MSPS Figure 8. SFDR vs. fOUT at 400 MSPS 100 RBW 1kHz RF ATT 40dB REF LVL VBW 1kHz 0dBm SWT 17s UNIT dBm 0 90 A –10 –6dB –20 80 –30 –3dB 1AVG 1AP –40 0dB –50 70 EXT –60 –70 60 –80 –90 50 –100 012 24 36 48 60 72 –110 f (MHz) OUT –120 START 750kHz 675kHz STOP 7.5MHz Figure 12. THD at 400 MSPS and f = 1 MHz (Diplexer Low-Pass Output Figure 9. SFDR vs. fOUT at 200 MSPS OUT Showing 0 dBm Fundamental (See the Performance Effects of Calibration Section)) 100 RBW 1kHz RF ATT 10dB VBW 1kHz REF LVL SWT 17s UNIT dBm 0dBm 0 90 A –10 f1 + f2 = 0dB –20 80 –30 1AVG 1AP –40 –50 70 EXT –60 –70 60 –80 –90 50 –100 20 30 40 50 60 70 80 90 100 110 120 130 140 –110 f (MHz) OUT –120 START 750kHz 675kHz STOP 7.5MHz Figure 10. Two-Tone IMD vs. f at 400 MSPS OUT Figure 13. THD at 400 MSPS and f = 1 MHz OUT (Diplexer High-Pass Output Showing Harmonics Before Calibration; (See the Performance Effects of Calibration Section)) Rev. B | Page 12 of 24 IMD (dBc) SFDR (dBc) SFDR (dBc) 04540-008 04540-007 04540-009 POWER CONSUMPTION (mW) 04540-019 04540-018 04540-006 AD9726 RBW 1kHz RF ATT 10dB REF –40dBm *ATTEN 6dB VBW 1kHz REF LVL *AVG SWT 17s UNIT dBm 0dBm Log 0 A 10dB/ –10 –20 EXT REF –30 1AVG 1AP –40 –50 EXT –60 –70 –80 –90 PAVG –100 10 W1 S2 –110 CENTER 70.00MHz SPAN 47.38MHz –120 *RES BW 10kHz VBW 100kHz SWEEP 1.383s (601 pts) START 750kHz 675kHz STOP 7.5MHz TOTAL CARRIER POWER -17.61dBm/7.68000MHz RRC FILTER: ON FILTER ALPHA 0.22 REF CARRIER POWER -20.72dBm/3.84000MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 1 –20.51dBm 5.000MHz 3.840MHz –70.61 –91.34 –70.74 –91.47 2 –20.72dBm 10.00MHz 3.840MHz –71.29 –92.01 –71.31 –92.03 15.00MHz 3.840MHz –71.36 –92.08 –71.06 –91.78 Figure 14. THD at 400 MSPS and f = 1 MHz (Diplexer High-Pass Output Figure 16. Two-Carrier WCDMA at 400 MSPS f = 70 MHz OUT OUT Showing Harmonics After Calibration, See the Performance Effects of Calibration Section) REF –35dBm *ATTEN 8dB REF –45dBm *ATTEN 4dB *AVG *AVG Log Log 10dB/ 10dB/ EXT REF EXT REF PAVG PAVG 10 10 W1 S2 W1 S2 CENTER 70.00MHz SPAN 34.68MHz CENTER 70.00MHz SPAN 59.58MHz *RES BW 10kHz VBW 100kHz SWEEP 1.012s (601 pts) *RES BW 10kHz VBW 100kHz SWEEP 1.739s (601 pts) LOWER UPPER TOTAL CARRIER POWER -20.62dBm/15.3600MHz RRC FILTER: ON FILTER ALPHA 0.22 RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm REF CARRIER POWER -26.43dBm/3.84000MHz CARRIER POWER 5.000MHz 3.840MHz –76.72 –91.30 –76.69 –91.27 LOWER UPPER –14.58dBm/ 10.00MHz 3.840MHz –76.96 –91.54 –77.04 –91.62 OFFSET FREQ INTEG BW dBc dBm dBc dBm 3.84000MHz 15.00MHz 3.840MHz –77.07 –91.65 –76.76 –91.34 5.000MHz 3.840MHz –66.59 –93.00 –67.07 –93.48 1 –26.43dBm 10.00MHz 3.840MHz –67.63 –94.04 –67.54 –93.95 2 –26.53dBm 15.00MHz 3.840MHz –67.59 –94.00 –67.44 –93.86 3 –26.74dBm 4 –26.88dBm Figure 15. One-Carrier WCDMA at 400 MSPS fOUT = 70 MHz Figure 17. Four-Carrier WCDMA at 400 MSPS fOUT = 70 MHz Rev. B | Page 13 of 24 04540-020 04540-014 04540-015 04540-016 AD9726 REF –50dBm *ATTEN 2dB *AVG Log 10dB/ EXT REF PAVG 10 W1 S2 CENTER 70.00MHz SPAN 83.98MHz *RES BW 10kHz VBW 100kHz SWEEP 2.451s (601 pts) TOTAL CARRIER POWER -20.62dBm/15.3600MHz RRC FILTER: ON FILTER ALPHA 0.22 REF CARRIER POWER -26.43dBm/3.84000MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 1 –32.21dBm 5.000MHz 3.840MHz –62.23 –94.82 –62.09 –94.68 2 –32.30dBm 10.00MHz 3.840MHz –62.87 –95.46 –62.36 –94.94 3 –32.44dBm 15.00MHz 3.840MHz –63.70 –96.28 –62.39 –94.98 4 –32.59dBm Figure 18. Eight-Carrier WCDMA at 400 MSPS fOUT = 70 MHz Rev. B | Page 14 of 24 04540-017 AD9726 SERIAL PORT INTERFACE Table 8. SPI Register Map Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 SDIODIR DATADIR SWRESET SLEEP PWRDWN EXTREF 0x02 DATAFMT DATARATE INVDCLKI INVDCLKO DISDCLKO SYNCMAN SYNCUPD SYNCALRM 0x0E CALMEM[1] CALMEM[0] CALCLK[2] CALCLK[1] CALCLK[0] 0x0F SCALSTAT SELFCAL XFERSTAT MEMXFER SMEMWR SMEMRD FMEMRD UNCAL 0x10 MEMADR[7] MEMADR[6] MEMADR[5] MEMADR[4] MEMADR[3] MEMADR[2] MEMADR[1] MEMADR[0] 0x11 MEMDAT[5] MEMDAT[4] MEMDAT[3] MEMDAT[2] MEMDAT[1] MEMDAT[0] 0x15 SYNCOUT[1] SYNCOUT[0] 0x16 BYPASS SYNCEXT SYNCIN[1] SYNCIN[0] Table 9. SPI Register Bit Default and Descriptions Values Addr Name Bits I/O Default Description 0x00 SDIODIR 7 I 0 0: SDIO is input only (4-wire SPI mode), and SDO is used for output. 1: SDIO is input/output (3-wire SPI mode), and SDO is unused. DATADIR 6 I 0 0: SPI serial data byte is MSB first format. 1: SPI serial data byte is LSB first format. 1 SWRESET 5 I 0 1: software reset: SPI registers (except 0x00) to default values. SLEEP 4 I 0 1: analog outputs temporarily disabled. PWRDWN 3 I 0 1: full device power-down; all circuits disabled except SPI. 2 EXTREF 0 I 0 1: power-down internal reference; use external reference source. 0x02 DATAFMT 7 I 0 0: input data-word is twos complement binary format. 1: input data-word is unsigned binary format. DATARATE 6 I 0 0: DDR mode. 1: SDR mode. INVDCLKI 5 I 0 1: inverts the polarity of the data clock input. INVDCLKO 4 I 0 1: inverts the polarity of the data clock output. DISDCLKO 3 I 0 1: disables the data clock output. SYNCMAN 2 I 0 1: enables sync manual mode; disables automatic update. SYNCUPD 1 I 0 1: forces manual sync update. SYNCALRM 0 O 0 1: indicates that sync logic requires update. 0x0E CALMEM [5:4] O 00 2-bit SMEM contents and calibration status indicator. 00: uncalibrated; SMEM contains default values (63). 01: self-calibrated; SMEM contains values from self-calibration. 10: factory-calibrated; SMEM values are transferred from FMEM. 11: user-calibrated; SMEM contains user-entered values. CALCLK [2:0] I 000 3-bit self-calibration clock divider ratio. Affects time available for algorithm settling. Each 3 value increase reduces time by 50%. 000: self-calibration clock is DAC clock/4096 (maximum self-calibration settling time for highest linearity accuracy). 001,010,011: self-calibration clock is DAC clock/2048,1024,512. 100,101,110: self-calibration clock is DAC clock/256,128,64. 111: self-calibration clock is DAC clock/32 (minimum self-calibration settling time for fastest algorithm completion). 0x0F SCALSTAT 7 O 0 1: indicates completion of self-calibration cycle. 4 SELFCAL 6 I 0 1: initiates self-calibration cycle. XFERSTAT 5 O 0 1: indicates completion of memory transfer cycle. 5 MEMXFER 4 I 0 1: initiates FMEM to SMEM transfer. SMEMWR 3 I 0 1: enables static memory (SMEM) write operation. SMEMRD 2 I 0 1: enable sstatic memory (SMEM) read operation. FMEMRD 1 I 0 1: enables factory memory (FMEM) read operation. 6 UNCAL 0 I 0 1: enables uncalibrated operation; all SMEM to default values. Rev. B | Page 15 of 24 AD9726 Addr Name Bits I/O Default Description 0x10 MEMADR [7:0] I 00000000 8-bit memory address value for read/write operations. 0x11 MEMDAT [5:0] I/O 000000 6-bit memory data value for read/write operations. 0x15 SYNCOUT [1:0] O 00 2-bit output value indicates current sync quadrant. 0x16 BYPASS 6 I 0 1: bypasses data synchronization circuitry. Data is sampled using the DAC clock (CLK±) SYNCEXT 5 I 0 1: enables sync external mode; disable auto quadrant select. SYNCIN [4:3] I 00 2-bit input value is used to specify the sync quadrant. 1 SWRESET also resets itself. SMEM contents are unaffected by SWRESET; however, CALMEM reports an uncalibrated state. 2 EXTREF is optional because the internal reference circuit is designed to be overdriven by an external source. 3 The self-calibration clock is also used for the memory transfer cycle; therefore, the CALCLK value affects the MEMXFER process time. 4 Register Bits 3:0 must all be 0 to assert SELFCAL. The time required for the self-calibration cycle is ~100 ms at 100 MHz with CALCLK = 0. 5 Register Bits 3:0 must all be 0 to assert MEMXFER. The time required for the memory transfer cycle is ~15 ms at 100 MHz with CALCLK = 0. 6 The UNCAL bit remains asserted after the cycle completes (SMEM contents held at default values) until the bit is cleared by the user. Rev. B | Page 16 of 24 AD9726 THEORY OF OPERATION The AD9726 uses LVDS for input data to enable high sample VCC = CLKVDD = 2.5V 1:1 CLK+ rates and high performance. LVDS technology uses differential 25Ω signals for noise rejection and small signal amplitude for fast 25Ω speed with lower power. Each LVDS input on the AD9726 has CLK– MC100LVEP16 an internal 100 Ω active load for proper termination. VBB = 1.0V AD9726 50Ω 50Ω DAC CLOCK AND DATA CLOCK OUTPUT VCC – 2V The AD9726 uses two clock inputs and offers one clock output. Figure 19. Active DAC Clock Drive Circuit All are differential signals. The AD9726 is driven by a master input clock that initiates con- The circuit option shown in Figure 19 uses a receiver/driver IC version and controls all on-chip activity. This signal is referred from the 2.5 V LVPECL logic family to provide complementary to as the DAC clock. It is not LVDS, and the CLK+ and CLK– outputs that fall within these guidelines. A transformer helps pins are high impedance inputs. ensure a 50% duty cycle and provides a single-ended to differ- ential conversion at the input. The DAC clock is then used to generate the data clock output. The DCLK_OUT+ and DCLK_OUT– pins form an LVDS The LVPECL device can be conveniently powered from the signal that can be used to drive an external FPGA or another same power supply as CLKVDD. The center tap of the trans- data pump. In SDR mode, the data clock output always runs at former secondary must be held at 1 V, the switching threshold the same frequency as the DAC clock. In DDR mode, the data of the receiver/driver inputs (use a resistive divider to generate clock output always runs at ½ the DAC clock frequency. this voltage or use the internal VBB source with a buffer amplifier). Based on a 1:1 impedance ratio, 25 Ω resistors across Use of the data clock output is optional. It is meant to serve as the secondary provide a matched load to a 50 Ω source. a convenient means of regulating the incoming data stream. The driver can be loaded by a 100 Ω differential termination. The driver outputs are terminated as close as possible to the An external 1 kΩ resistor from the REXT pin to DBGND is also AD9726 with 50 Ω to VCC − 2 V (or use a Thevenin equivalent required to set the drive strength. If unused, the data clock circuit). Controlled impedance PCB traces should be used to output pins can be left unconnected, and the 1 kΩ resistor at minimize reflections. Signal levels at the CLK+ and CLK– pins REXT can be omitted. transition between a high near 1500 mV to a low near 750 mV. The data clock output can also be inverted by asserting the 0.1μF CLK+ 1:1 INVDCLKO bit in SPI Register 0x02, or the driver can be disabled by asserting the DISDCLKO bit in the same register. 50Ω CLK– DATA CLOCK INPUT 0.1μF The remaining clock signal associated with the AD9726 is the AD9726 VDC BIAS = 1.25V data clock input. This LVDS signal is not optional and must Figure 20. Passive DAC Clock Drive Circuit accompany the 16-bit data bus. The data clock input is used to latch incoming data into the synchronization (sync) logic. An alternative circuit option for driving the DAC clock inputs employs a transmission line transformer (balun) to accomplish The data clock input always runs at the same frequency as the the single-ended to differential conversion. This all-passive data clock output in both SDR and DDR modes. A logical circuit is considerably simpler and less costly, and it provides inversion can be accomplished by asserting the INVDCLKI bit. acceptable performance over a limited range of frequencies. Driving the DAC Clock Inputs In this implementation, a sine wave (or other single-ended The DAC clock must be precise and spectrally pure to ensure source) is coupled directly to the differential DAC clock inputs the highest ac performance. A symmetrical 50% duty cycle through a 50 Ω transformer. Capacitors are used for isolation, should be maintained at all times. and each DAC clock pin must be dc-biased to a level of 1.25 V The CLK+ and CLK– input pins should be driven by a signal (a pair of simple resistive dividers can be used). with a common-mode voltage near ½ of CLKVDD. From this point, peak-to-peak signal amplitude should swing over a range of at least several hundred millivolts. Rev. B | Page 17 of 24 04540-013 04540-012 AD9726 The 50 Ω termination resistor should be placed as close as pos- the DAC using the DAC clock (CLK±) and following the timing sible to the input pins, and controlled impedance PCB traces presented in Figure 4, Figure 5, and Table 4. should be used. The data synchronization circuitry bypass is enabled by writing Good ac performance can be expected from either the active or 0x40 to Address 0x16. The AD9726 should also be configured passive DAC clock drive circuit. However, in a passive circuit, in single data rate mode by writing 0x80 to Address 0x02. In this the output slew rate is dependent on the frequency of the input; mode, the sync logic is bypassed, making its configurations and whereas an active circuit provides consistently high output slew status reporting irrelevant. rates over a wide range of input frequencies. ANALOG OUTPUT DATA SYNCHRONIZATION CIRCUITRY The AD9726 is based around a high dynamic range CMOS The high performance of the AD9726 requires maintaining core. The analog output consists of differential current sources, synchronization between the incoming bits and the DAC clock each capable of up to 20 mA full scale. Discrete output devices used to sample and convert the data. Despite the inherent dif- are PMOS and capable of sourcing current into an output ficulty in specifying the phase relationship of the DAC clock termination within a compliance voltage range of ±1 V. and the LVDS data clock input and the challenge presented by In a typical application, both outputs drive discrete resistors-to- the high operating speed of the interface, the AD9726 contains analog ground. From there, especially for higher frequency real-time logic to automatically monitor and align the data bus outputs, they feed the center-tap secondary of a 1:1 RF trans- with the DAC clock. former. A differential-to-single-ended conversion is accomplished Whether in SDR or DDR mode, input data is always provided that provides added gain and cancellation of even ordered at the same rate. Furthermore, the rate of incoming data always harmonics. equals the frequency period of the DAC clock. The data rate and IOUTA –3dBm 25Ω the DAC clock must also be frequency locked. To accomplish this, 25Ω the primary purpose of the data clock output is to provide a IOUTB time base for data that is derived directly from the DAC clock. Figure 21. Transformer Output Circuit The function of the data clock input is to latch incoming data into the sync block. From there, it is the function of the For maximum output power, resistor values can be increased to synchronization logic to position the data with respect to the 50 Ω to provide up to 0 dBm into a 50 Ω load without loss of DAC clock for optimal ac performance. performance for most transformers. R R GA FA Individual data bits must maintain close alignment with one another so that PCB traces have matched delays across the width of the 16-bit bus. In addition, a fixed setup and hold IOUTA timing relationship between the data clock input and the data 50Ω bus is required. However, because of the sync logic, the phase relationship between R R GB FB the data bus and the DAC clock is internally optimized. Furthermore, if the phase between the data bus and the DAC clock drifts over time or temperature, the sync logic automat- IOUTB ically updates and adjusts for it. After synchronization is 50Ω reached, the phase between the data bus and the DAC clock can vary by a full cycle without loss or corruption of data. NOTES 1. USE RF AND RG TO SET GAIN AND LIMIT BANDWIDTH More detailed explanations of sync operation and optional Figure 22. Op Amp Output Circuit programmable modes are presented in the Sync Logic Operation and Programming section, which also includes an As an alternative, an active output stage can be used in the explanation of how to use the sync logic without the SPI. classic instrumentation amplifier configuration. Here, each DAC output feeds the noninverting input of one of the Analog Data Synchronization Circuitry Bypass Devices, Inc., high speed transimpedance op amps. Due to internal design limitations, the data synchronization circuitry does not assure a fixed or predictable pipeline delay between the data input and the analog output after power-up. For designs where multichip synchronization or fixed pipeline delay is important, the AD9726 can be configured to bypass the resynchronization circuitry and assure a fixed pipeline delay of four DAC clock cycles. In this mode, the data is sampled into Rev. B | Page 18 of 24 04540-021 04540-011 AD9726 Communication Cycle INTERNAL REFERENCE AND FULL-SCALE OUTPUT All communication cycles have two phases. The first phase is The AD9726 contains an internal 1.2 V precision reference concerned with writing an instruction byte into the SPI source; this reference voltage appears at the REFIO pin. It can controller and always coincides with the first eight rising edges be used to drive external circuitry if properly buffered. of SCLK. The instruction byte provides the controller with Apply an external reference voltage source to the REFIO pin if information regarding the second phase of the cycle, namely the desired. The internal source is designed to be easily overdriven data transfer phase. The instruction byte contains the number by an external source; however, the internal reference can also of data bytes to be transferred (one to four), a register address, be powered down using the EXTREF bit in SPI Register 0x00. and a bit initiating a read or write operation. The reference voltage (either internal or external) is applied to INSTRUCTION CYCLE DATA TRANSFER CYCLE an external precision resistor at the FSADJ pin. The resulting CSB current is internally amplified to provide the full-scale current SCLK at the DAC output according to the following equation: R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D2 D1 D0 SDIO n n 0 0 0 SDO D7 D6 D2 D1 D0 n n 0 0 0 I = VREF/R × 32 OUTFS FSADJ Figure 23. SPI Communication Cycle Taking into account the binary value appearing at the data bus inputs, the output currents I and I can be determined OUTA OUTB Any communication cycle begins with CSB going low, which according to the following equations: also resets the SPI control logic. Similarly, any communication cycle ends with CSB going high, which aborts any incomplete IOUTA = IOUTFS × DB[15:0]/65536 data transfer. After a communication cycle begins, the next IOUTB = IOUTFS × (1 − DB[15:0])/65536 eight SCLK rising edges interpret data on the SDIO pin as the Note that the AD9726 features nonvolatile, factory-calibrated instruction byte. gain using the internal reference source and a precision 2 kΩ Instruction Byte load. Gain accuracy in any application is, therefore, dependent upon the accuracy of R . The instruction byte bits are shown in the following bit map. FSADJ B7 B6 B5 B4 B3 B2 B1 B0 RESET R/W N1 N0 A4 A3 A2 A1 A0 Following initial power-up and application of a valid DAC clock signal, the AD9726 should always be initialized with an active R/W high pulse on the RESET pin. This defaults the programmable Bit 7 of the instruction byte selects a read or write transfer. If registers, initializes volatile calibration memory, and prepares the bit is set high, a read operation is indicated. If the bit is low, the synchronization logic for data. The data bus should be static a write operation is indicated. prior to the reset pulse. After reset, LVDS data can flow. N1, N0 The default state of the AD9726 is DDR and twos complement binary input data. To use the AD9726 in this mode, it is not Bit 6 and Bit 5 of the instruction byte determine the number of necessary to program any device registers. However, the SPI is data bytes to be transferred, as shown in Table 10. enabled by default unless the SPI_DIS pin is connected high. If Table 10. not disabled, SPI input pins should not be left floating. N1 N0 Description SERIAL PORT INTERFACE 0 0 Transfer one data byte The serial port interface is a flexible and synchronous serial 0 1 Transfer two data bytes communications port allowing easy interface to many industry 1 0 Transfer three data bytes standard microcontroller and microprocessor protocols 1 1 Transfer four data bytes (including both Motorola SPI® and Intel® SSR). The interface A4, A3, A2, A1, A0 provides read/write access to registers that configure the operation of the AD9726. Bit 4 through Bit 0 of the instruction byte specify a 5-bit binary value corresponding to a valid register address. In the case of The AD9726 SPI supports single-byte and multibyte transfers as multibyte transfers, the location specified is either an initial or well as MSB- or LSB-justified data formats. The interface can be a concluding register address. The SPI controller increments configured in 3-wire mode (in which SDIO is bidirectional) or or decrements this value to generate successive address values the default 4-wire mode (in which SDIO and SDO function as depending on whether LSB or MSB justification is active. unidirectional data input and data output, respectively). Rev. B | Page 19 of 24 04540-010 AD9726 MSB/LSB Transfers and the first output bit is enabled on the immediately following falling SCLK edge. The SPI can support both MSB- and LSB-justified serial data byte formats. This functionality is determined by Bit 6 in SPI For multibyte read sequences, the controller adjusts the register Register 0x00. This bit defaults low, which is MSB justification. address when necessary, and subsequent data bit values appear In this mode, serial data bits are written to and/or read from at the output with each falling SCLK edge. registers sequentially from Bit 7 to Bit 0. Disabling the SPI If Bit 6 of SPI Register 0x00 is set high, the controller switches Tie the SPI_DIS pin high to ADVDD to disable the serial port to LSB justification. In this mode, data bits are written to or inteface. In this state, the default DDR operational mode can be read from registers sequentially from Bit 0 to Bit 7. Writing to changed to SDR by pulling the SDR_EN pin high to ADVDD. the instruction bytes is also affected by the active justification. In addition, with the SPI disabled, the sync logic no longer oper- For multibyte transfers with MSB justification, the address in ates in a fully automatic mode. See the Sync Logic Operation the instruction byte is interpreted as a final address, and its value and Programming section for a full explanation of sync opera- is decremented automatically by the controller. For multibyte tional modes. transfers with LSB justification, the address in the instruction SPI PIN DESCRIPTION byte is interpreted as an initial address, and its value is incremented The AD9726 SPI logic runs from the DBVDD supply rail, and automatically by the controller. input/output thresholds are based upon a nominal 3.3 V level. Care must be exercised when switching from MSB to LSB The maximum frequency of operation is 15 MHz. justification. The controller switches modes immediately once Chip Select (CSB) all eight bits of SPI Register 0x00 are written (even if in the The CSB pin is an active low input. It begins and ends any process of a multibyte transfer). For this reason, a single byte command is recommended when changing justification. communication cycle and must remain low during the entire cycle. An incomplete cycle is aborted if CSB is prematurely 3-Wire and 4-Wire Operation returned high. Bit 7 of SPI Register 0x00 defaults low, enabling 4-wire SPI Serial Clock (SCLK) operation. In this mode, serial data is input from the SDIO pin, The SCLK pin is used to synchronize data to and from the SPI and serial data is output on the SDO pin. Setting Bit 7 of SPI Register 0x00 high enables 3-wire operation. In this mode, registers, and the controller state machine runs from this input. SDIO becomes bidirectional and switches automatically from It is, therefore, possible to read and write register data (but not input to output when necessary. The SDO pin in this mode is SMEM/FMEM) without a valid DAC clock. All input data is unused and assumes a high impedance state. registered on the rising edge of SCLK, and output data bits are enabled on the falling edge of SCLK. As with MSB or LSB justification, care must be exercised when Serial Data Input/Output (SDIO) switching operational modes. The change occurs immediately once all eight bits of SPI Register 0x00 are written. Data is always written into the SPI on the SDIO pin. In 3-wire mode, however, data is also driven out using this pin. The Writing and Reading Register Data switch from input to output occurs automatically between the Bringing CSB low initiates a new communication cycle. The instruction and data transfer phases of a read operation. In the next eight rising edges of SCLK latch data from SDIO into the default 4-wire mode, SDIO is unidirectional and input only. instruction byte. If Bit 7 of the instruction byte is low, a write Serial Data Output (SDO) operation is enabled. If Bit 7 is high, a read operation is enabled. Serial data is driven out on the SDO pin when the SPI is in its For a write operation, a data byte is latched from the SDIO pin default 4-wire mode. In 3-wire mode (or whenever CSB is high), into a register on the next eight rising edges of SCLK. If the SDO is set to a high impedance state. instruction byte Bit 6 and Bit 5 are not both 0, a multibyte transfer latches data bytes into adjacent registers after each CALIBRATION successive set of eight rising SCLK edges. Depending upon To ensure linearity to the 16-bit level, the AD9726 incorporates MSB or LSB justification, the controller decrements or 132 calibration DACs (CALDACs), which are used to linearize increments the address value in the instruction byte during the current output transfer function. Each CALDAC is a 6-bit the cycle as necessary. device and takes its input directly from static memory (SMEM). If a read operation is enabled, data bits from the register being There are 127 CALDACs associated with each major transition addressed appear on SDO (or SDIO) with each falling edge of of the 16-bit input data-word (that is, any transition involving SCLK. Note that for a read operation, the eighth bit of the the upper 7 MSBs). A 128th CALDAC operates on the sum total instruction byte is latched on the eighth rising edge of SCLK, of the lower nine LSBs. The remaining four CALDACs (129 to 132) are used to adjust the DAC’s overall transfer function gain. Rev. B | Page 20 of 24 AD9726 Linearity CALDACs operate inversely from their input; that is, (CALMEM = 00b). Note that UNCAL remains asserted (and as their binary input value increases, the magnitude of their the contents of SMEM remains at default values) indefinitely. current contribution seen at the AD9726 output decreases. Gain UNCAL does not clear itself (like SWRESET) and must be cleared by the user. CALDACs are an exception to this. Their contribution seen at the AD9726 output is in direct proportion to their binary input. Note also that although SPI registers do not depend on the DAC Gain CALDACs are also half strength as compared to linearity clock (they use SCLK to sequence the controller state machine), CALDACs, but they are intended to be used together as a unit SMEM and/or FMEM access does require a valid DAC clock. and thus, together, provide twice the current adjustment range. SMEM/FMEM Read/Write Procedures Calibration Memory Static and factory memory is accessed through the SPI, but it is During production testing, the linearity of the AD9726 is not part of the SPI logic. For this reason, memory access requires measured and optimized. Values for all CALDACs are perma- a valid DAC clock, while SPI register access does not. nently stored in nonvolatile factory memory (FMEM). At Because the AD9726 SPI is so flexible, allowing single and reset, all factory memory contents are transferred to static multiple byte reads and writes as well as MSB or LSB justified memory. CALMEM, Bits[5:4] in Register 0x0E, indicates a data, there are a number of ways in which a user can access one factory calibrated state (CALMEM = 10b). or more SMEM or FMEM locations. It is also possible at any time to transfer the contents of FMEM To avoid potential errors, the following procedures for accessing to SMEM by asserting the MEMXFER bit in Register 0x0F. The static or factory memory should be followed. These procedures XFERSTAT indicator bit (Bit 5 in Register 0x0F) then reports use only single-byte SPI commands to ensure the enabling of the successful completion of the transfer cycle, and MEMXFER addresses and the sequencing of memory access. is cleared. To read from SMEM or FMEM, Note that the MEMXFER bit (and SELFCAL, Bit 6, Register 1. Ensure that Bits [3:0] of Register 0x0F are clear. 0x0F) cannot be asserted if any other memory access function is 2. Begin the sequence by writing the memory address value currently enabled (that is, if any one of Bits[3:0] in Register to Register 0x10 with a single-byte SPI write command. 0x0F is high). Attempting to assert MEMXFER (or SELFCAL) 3. Assert the SMEMRD or FMEMRD bit in Register 0x0F in this case clears any asserted bits in Register 0x0F, but the with another single-byte SPI write command. requested cycle does not commence. 4. Import the contents of Register 0x11 using a single-byte The factory-to-static memory data transfer cycle requires a SPI read command. number of DAC clock cycles. The total depends on the value of 5. Clear the SMEMRD or FMEMRD bit with another single- CALCLK. This value sets a divider used to create a slow version byte command. of the DAC clock, which is intended to extend the settling time To write to SMEM, available to the self-calibration cycle. However, this divided clock is also used to sequence a memory transfer cycle. 1. Ensure that Bits [3:0] of Register 0x0F are clear. 2. Begin the sequence by writing the data value to The divider is set to its maximum value with CALCLK at its Register 0x11 using a single-byte SPI write command. default value. A memory transfer cycle requires about 15 ms at a 3. Assert the SMEMWR bit using a single-byte SPI write DAC clock frequency of 100 MHz. This time can be reduced by command. 50% for every increase in the value of CALCLK. 4. Place the memory address value in Register 0x10 using a Accessing Calibration Memory single-byte SPI write command. SMEM or FMEM locations can be read at any time by setting 5. Clear the SMEMWR bit with a fourth single-byte SPI write the SMEMRD or FMEMRD bit in SPI Register 0x0F. Address command. and data information can be input and/or output through SPI Self-Calibration Register 0x10 and SPI Register 0x11, respectively. The AD9726 features an internal self-calibration engine to SMEM locations can also be written by setting the SMEMWR linearize the transfer function automatically. This can be very bit in Register 0x0F. Register 0x10 and Register 0x11 are again useful at temperature extremes where factory calibration no used for addresses and data. Any time after the SMEMWR bit longer applies. The automated cycle can be initiated by asserting has been asserted, the device reports a user-calibrated state the SELFCAL bit. (CALMEM = 11b) until another action changes the calibration memory status. The self-calibration process calibrates all linearity and gain CALDACs based upon a fixed internal reference current. Values To reset static memory at any time, assert the UNCAL bit in for all CALDACs are stored in volatile static memory. The Register 0x0F. All SMEM locations are then reset to their CALSTAT bit indicates the successful completion of the cycle, default values (63). CALMEM reports an uncalibrated state Rev. B | Page 21 of 24 AD9726 and the SELFCAL bit is cleared. Following the cycle, the device SYNC LOGIC OPERATION AND PROGRAMMING reports a self-calibrated state (CALMEM = 01b). Recall that a fixed setup and hold timing relationship between As with MEMXFER, successful assertion of the SELFCAL bit the data clock input and the data bus must be established and (Bit 6 in Register 0x0F)requires that Bits[3:0] in Register 0x0F maintained. Recall also that the data bus and the DAC clock be clear. If any of these bits are asserted (such that an must be frequency locked. Because of the sync logic, however, SMEM/FMEM read/write/clear state is enabled), the self- the phase relationship between the data bus and the DAC clock calibration cycle does not begin. is internally optimized. Therefore, data arrival propagation delays and concern about data transitions near the sampling The time required to self-calibrate is dependent on both the instant are eliminated. DAC clock frequency and the value of CALCLK (Bits[5:0] in Register 0x0E). Because self-calibration requires more time Synchronization is automatically enabled upon reset. After data than ordinary operation, the DAC clock is divided into a slower arrives and synchronization is achieved, the sync logic contin- version and used to step through the process. Time made uously monitors itself so that automatic adjustments are made if available to the self-calibration algorithm directly impacts its phase drifts occur over time and/or temperature. ability to provide accurate results. Note that the sync function and operation of the sync logic A maximum fixed division ratio (4096) corresponds to the block are transparent, automatic, and ongoing. No programming minimum default value of CALCLK (0). The division ratio can is required. For applications where it is useful, however, the be decreased by increasing the value of CALCLK. Each increase following programmable control is provided. in the value of CALCLK reduces the DAC clock division factor SYNC Operating States (and, therefore, the time made available to self-calibration) by The sync logic can operate in one of three possible modes. The 50%. With CALCLK at its maximum value (7), the divide ratio default mode is fully automatic. declines to its minimum value (32). Fully automatic synchronization is accomplished by demulti- With CALCLK at its default value, self-calibration requires plexing the incoming data stream into four channels, each approximately 100 ms at a DAC clock frequency of 100 MHz. containing every fourth data-word. Data-words are present for This time can be reduced to under 0.8 ms if CALCLK = 7. Time four DAC clock cycles. Data is remultiplexed by sampling each scales relative to DAC clock frequency. channel with the optimum DAC clock cycle. Performance Effects of Calibration Initial synchronization is first established through a hardware Harmonic distortion for low frequency outputs is primarily a reset. This also fully enables the synchronization logic to mon- function of DAC linearity. Figure 12 to Figure 14 show the itor and resynchronize, as necessary. The AD9726 resynchro- harmonic distortion performance of the AD9726. nizes only if conditions change enough to alter the phase Figure 12 shows a 1 MHz full-scale output tone. The output between the data bus and the DAC clock by more than one full drives a unique low-pass and high-pass filter called a diplexer. clock cycle. In this event, an internal alarm occurs and is This type of filter presents a uniform 50 Ω load to the DAC and followed by an automatic update. During resynchronization, splits the output signal into low and high frequency paths. The two data-words are typically lost or repeated. diplexer's low-pass output passes the 1 MHz fundamental but In addition to fully automatic mode, two semi-automatic modes attenuates higher frequencies, and the diplexer's high-pass out- are available. put passes higher frequencies and attenuates the 1 MHz funda- Sync Manual Mode mental. Figure 12 also shows the diplexer's low-pass output. Here the noise floor is higher than the harmonic distortion In fully automatic mode, the AD9726 both detects when a because with a high power input signal, attenuation is required resynchronization is necessary and initiates an update. In by the spectrum analyzer. manual mode, automatic updating is disabled. Enable manual mode by setting the SYNCMAN bit in SPI Register 0x02. Figure 13 shows the diplexer's high pass output where the In manual mode, the sync logic still monitors incoming data attenuated input signal can be seen. The spectrum analyzer attenuation is also reduced, which lowers the noise floor. and the DAC clock, but it indicates the need for an update by Harmonic products at integer multiples of the fundamental asserting the SYNCALRM bit (Bit 0 in Register 0x02). In this are thus revealed. This is the response using the AD9726 in mode, the user is expected to regularly poll the SYNCALRM an uncalibrated state. bit. When this bit is read back high, the user can issue a manual sync update also by asserting the SYNCUPD bit (Bit 1) in SPI Figure 14 shows a response using the AD9726 in a calibrated Register 0x02. state. Harmonic distortion due to the nonlinearities of the SYNCALRM does not indicate that data is being lost but that digital-to-analog conversion are virtually eliminated. conditions are close to the point where data may be lost. The Rev. B | Page 22 of 24 AD9726 sync logic should be resynchronized by asserting SYNCUPD The four channels into which each incoming data-word is at the next convenient time. multiplexed are called quadrants. In any mode, the current quadrant value can always be read back via SYNCOUT (Bits In manual mode, users can choose when to update the sync [1:0] of SPI Register 0x15). At sync update, the logic chooses the logic. When operating with burst data, issuing a sync update optimal quadrant and refreshes the value of SYNCOUT. between active bursts updates the system without risking the loss of any data. In fact, because SYNCUPD always forces a It is also possible to enter a value into SYNCIN (Bits [4:3] of SPI resynchronization regardless of operational mode, even users in Register 0x16). When external mode is enabled, the logic oper- fully automatic mode can reduce the possibility of data loss by ates as expected, except that the quadrant value in SYNCIN is occasionally forcing a sync update during idle activity. used following an update. This can be used to align delays between multiple device outputs. If either the data clock or the DAC clock is interrupted for any reason, a SYNCUPD should always be executed to ensure that Operating With SPI Disabled data bus and DAC clock phase alignment remains optimized. If the SPI_DIS pin is connected high to ADVDD and the SPI is disabled, the sync logic is placed into manual mode. SYNC External Mode Going beyond manual mode, sync external mode offers a SYNCALRM status can then be monitored in hardware via the greater level of control and can be useful if multiple DAC unused SPI pin SDO (54), and SYNCUPD requests can be channels are employed in an application. Enable sync external entered in hardware via the unused SPI pin SCLK (56). If these mode by asserting the SYNCEXT bit (Bit 5) in SPI Register two pins are connected together, fully automatic sync operation 0x16. Manual mode must also be enabled. can be achieved. Rev. B | Page 23 of 24 AD9726 OUTLINE DIMENSIONS 14.20 14.00 SQ 12.20 13.80 12.00 SQ 1.20 0.75 MAX 11.80 0.60 0.45 61 80 80 61 1 60 60 1 PIN 1 EXPOSED 6.00 TOP VIEW PAD BSC SQ (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 (PINS UP) 0.20 1.00 0.09 20 41 41 20 0.95 7° 40 40 21 21 3.5° VIEW A 0.15 0.50 BSC 0° SEATING 0.27 LEAD PITCH 0.05 0.08 MAX FOR PROPER CONNECTION OF PLANE 0.22 COPLANARITY THE EXPOSED PAD, REFER TO 0.17 THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 24. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9726BSVZ −40°C to +85°C 80-Lead TQFP_EP SV-80-1 AD9726BSVZRL −40°C to +85°C 80-Lead TQFP_EP SV-80-1 AD9726-EBZ Evaluation Board 1 Z = RoHS Compliant Part. © 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04540-0-2/10(B) Rev. B | Page 24 of 24 060806-A