ANALOG DEVICES AD9716

Dual, Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters AD9714/AD9715/AD9716/AD9717 FEATURES GENERAL DESCRIPTION Power dissipation @ 3.3 V, 2 mA output The AD9714/AD9715/AD9716/AD9717 are pin-compatible, 37 mW @ 10 MSPS dual, 8-/10-/12-/14-bit, low power digital-to-analog converters 86 mW @ 125 MSPS (DACs) that provide a sample rate of 125 MSPS. These TxDAC® Sleep mode: <3 mW @ 3.3 V converters are optimized for the transmit signal path of commu- Supply voltage: 1.8 V to 3.3 V nication systems. All the devices share the same interface, package, SFDR to Nyquist and pinout, providing an upward or downward component 84 dBc @ 1 MHz output selection path based on performance, resolution, and cost. 75 dBc @ 10 MHz output The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz dc performance and support update rates up to 125 MSPS. Differential current outputs: 1 mA to 4 mA The flexible power supply operating range of 1.8 V to 3.3 V and 2 on-chip auxiliary DACs low power dissipation of the AD9714/AD9715/AD9716/AD9717 CMOS inputs with single-port operation make them well-suited for portable and low power applications. Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package PRODUCT HIGHLIGHTS APPLICATIONS 1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power Wireless infrastructures consumption reduces to 35 mW at 125 MSPS with a 1.8 V Picocell, femtocell base stations supply. Sleep and power-down modes are provided for low Medical instrumentation power idle periods. Ultrasound transducer excitation 2. CMOS Clock Input. Portable instrumentation High speed, single-ended CMOS clock input supports a Signal generators, arbitrary waveform generators 125 MSPS conversion rate. 3. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common- mode levels greater than 0 V. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS Features .............................................................................................. 1  Estimating the Overall DAC Pipeline Delay........................... 42  Applications ....................................................................................... 1  Reference Operation .................................................................. 43  General Description ......................................................................... 1  Reference Control Amplifier .................................................... 43  Product Highlights ........................................................................... 1  DAC Transfer Function ............................................................. 44  Revision History ............................................................................... 3  Analog Output ............................................................................ 44  Functional Block Diagram .............................................................. 4 Self-Calibration ........................................................................... 45  Specif ica t ions ..................................................................................... 5  Coarse Gain Adjustment ........................................................... 46  DC Specifications ......................................................................... 5  Using the Internal Termination Resistors ............................... 47  Digital Specifications ................................................................... 7  Applications Information .............................................................. 48  AC Specifications .......................................................................... 8  Output Configurations .............................................................. 48  Absolute Maximum Ratings ............................................................ 9  Differential Coupling Using a Transformer ............................... 48  Thermal Resistance ...................................................................... 9  Single-Ended Buffered Output Using an Op Amp ................ 48  ESD Caution .................................................................................. 9  Differential Buffered Output Using an Op Amp ................... 49  Pin Configurations and Function Descriptions ......................... 10  Auxiliary DACs ........................................................................... 49  Typical Performance Characteristics ........................................... 18  DAC-to-Modulator Interfacing ................................................ 50  Terminology .................................................................................... 31  Correcting for Nonideal Performance of Quadrature Modulators on the IF-to-RF Conversion ................................ 50  Theory of Operation ...................................................................... 32  I/Q-Channel Gain Matching .................................................... 50  Serial Peripheral Interface (SPI) ................................................... 33  LO Feedthrough Compensation .............................................. 51  General Operation of the Serial Interface ............................... 33  Results of Gain and Offset Correction .................................... 51  Instruction Byte .......................................................................... 33  Modifying the Evaluation Board to Use the ADL5370 Serial Interface Port Pin Descriptions ..................................... 33  On-Board Quadrature Modulator ........................................... 52  MSB/LSB Transfers..................................................................... 34  Evaluation Board Shematics and Artwork .................................. 53  Serial Port Operation ................................................................. 34  Schematics ................................................................................... 53  Pin Mode ..................................................................................... 34  Silkscreens ................................................................................... 61  SPI Register Map ............................................................................. 35  Bill of Materials ............................................................................... 76  SPI Register Descriptions .............................................................. 36  Outline Dimensions ....................................................................... 79  Digital Interface Operation ........................................................... 40  Ordering Guide .......................................................................... 79  Digital Data Latching and Retimer Block ............................... 41  Rev. A | Page 2 of 80 AD9714/AD9715/AD9716/AD9717 REVISION HISTORY 3/09—Rev. 0 to Rev. A Changes to Digital Interface Operation Section and Figure 89 to Changes to Figure 1 ........................................................................... 4 Figure 93 ........................................................................................... 40 Changed DVDD = 3.3 V to DVDD = 1.8 V, Changes to Digital Data Latching and Retimer Block Section, Table 1 Conditions ............................................................................ 5 Figure 94, and Retimer Section ..................................................... 41 Changes to Table 1 ............................................................................ 5 Changes to Estimating the Overall DAC Pipeline Delay Changed DVDD = 3.3 V to DVDD = 1.8 V, Section .............................................................................................. 42 Added Reference Operation Section, Figure 96, Table 2 Conditions ............................................................................ 7 Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V Recommendations When Using an External Reference Section, to DVDDIO = 3.3 V, Table 3 Conditions ....................................... 8 and Reference Control Amplifier Section.................................... 43 Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to Added Table 17; Renumbered Sequentially ................................. 43 CVDD = 1.8 V, Table 4 Conditions ................................................. 8 Added DAC Transfer Function Section and Analog Output Changes to Table 5 and Table 6 ....................................................... 9 Section .............................................................................................. 44 Changes to Figure 2 and Table 7 ................................................... 10 Changes to Figure 99 and Figure 100 ........................................... 46 Changes to Figure 3 and Table 8 ................................................... 12 Changes to Auxiliary DACs Section and Figure 107.................. 49 Changes to Figure 4 and Table 9 ................................................... 14 Changes to DAC-to-Modulator Interfacing Section and Changes to Table 10 ........................................................................ 16 Figure 108 ......................................................................................... 49 Changes to Typical Performance Characteristics Section ......... 18 Changes to Figure 108 and Figure 109 ......................................... 50 Changes to Figure 84 and Theory of Operation Section ........... 32 Added Evaluation Board Schematics and Artwork Section, and Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34 Figure 112 to Figure 134 ................................................................. 53 Changes to Pin Mode Section ........................................................ 35 Added Bill of Materials Section and Table 18 ............................. 76 Changes to Table 13 ........................................................................ 36 Changes to Table 14 ........................................................................ 37 8/08—Revision 0: Initial Version Rev. A | Page 3 of 80 AD9714/AD9715/AD9716/AD9717 FUNCTIONAL BLOCK DIAGRAM AD9717 1V SPI DB11 INTERFACE QR IR SET SET 16kΩ 16kΩ IR CML DB10 1kΩ TO RLIN 250Ω 500Ω 10kΩ DB9 IOUTN I I DAC REF IOUTP 100µA DB8 500Ω BAND RLIP AUX1DAC GAP DVDDIO AVDD 1 INTO 2 INTERLEAVED AVSS AUX2DAC I DATA DATA DVSS RLQP INTERFACE 500Ω DVDD 1.8V QOUTP Q DATA LDO Q DAC QOUTN DB7 500Ω RLQN CLOCK DB6 DIST QR CML 1kΩ TO DB5 250Ω Figure 1. Rev. A | Page 4 of 80 DB4 DB12 DB3 DB13 (MSB) DB2 CS/PWRDN DB1 SDIO/FORMAT DB0 (LSB) SCLK/CLKMD DCLKIO RESET/PINMD REFIO CVDD FSADJQ/AUXQ CLKIN CVSS FSADJI/AUXI CMLQ CMLI 07265-001 AD9714/AD9715/AD9716/AD9717 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I = 2 mA, maximum sample rate, unless MIN MAX xOUTFS otherwise noted. Table 1. AD9714 AD9715 AD9716 AD9717 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 8 10 12 14 Bits ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.7 LSB Postcalibration ±0.003 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.13 ±0.4 ±1.8 LSB Postcalibration ±0.01 ±0.05 ±0.3 ±1.3 LSB ACCURACY, AVDD = DVDDIO = CVDD = 1.8 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.2 LSB Postcalibration ±0.005 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.12 ±0.4 ±1.5 LSB Postcalibration ±0.02 ±0.05 ±0.25 ±1.1 LSB MAIN DAC OUTPUTS Offset Error −1 0 +1 −1 0 +1 −1 0 +1 −1 0 +1 mV Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR 1 Full-Scale Output Current AVDD = 3.3 V 1 2 4 1 2 4 1 2 4 1 2 4 mA AVDD = 1.8 V 1 2 2.5 1 2 2.5 1 2 2.5 1 2 2.5 mA Output Compliance Range −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 V Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC f = 30 MHz 97 97 97 97 dB OUT f = 60 MHz 78 78 78 78 dB OUT MAIN DAC TEMPERATURE DRIFT Offset 0 0 0 0 ppm/°C Gain ±40 ±40 ±40 ±40 ppm/°C Reference Voltage ±25 ±25 ±25 ±25 ppm/°C AUXDAC OUTPUTS Resolution 10 10 10 10 Bits Full-Scale Output Current 125 125 125 125 μA (Current Sourcing Mode) Voltage Output Mode VSS VDD VSS VDD VSS VDD VSS VDD V Output Compliance Range VSS VDD − VSS VDD − VSS VDD − VSS VDD − V (Sourcing 1 mA) 0.25 0.25 0.25 0.25 Output Compliance Range VSS + VDD VSS + VDD VSS + VDD VSS + VDD V (Sinking 1 mA) 0.25 0.25 0.25 0.25 Output Resistance in Current 1 1 1 1 MΩ Output Mode, AVSS to 1 V AUX DAC Monotonicity 10 10 10 10 Bits Guaranteed REFERENCE OUTPUT Internal Reference Voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 V Output Resistance 10 10 10 10 kΩ Rev. A | Page 5 of 80 AD9714/AD9715/AD9716/AD9717 AD9714 AD9715 AD9716 AD9717 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit REFERENCE INPUT Voltage Compliance AVDD = 3.3 V 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 V AVDD = 1.8 V 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 V Input Resistance External 1 1 1 1 MΩ Reference Mode DAC MATCHING Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % FSR ANALOG SUPPLY VOLTAGES AVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V CVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V DIGITAL SUPPLY VOLTAGES DVDD 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 V DVDDIO 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz 86 86 86 86 mW IAVDD 10 10 10 10 mA IDVDD + IDVDDIO 11 11 11 11 mA ICVDD 3 3 3 3 mA Power-Down Mode with Clock 50 50 50 50 mW Power-Down Mode, No Clock 1.5 1.5 1.5 1.5 mW Power Supply Rejection Ratio −0.04 −0.04 −0.04 −0.04 % FSR/V POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 1.8 V. fDAC = 125 MSPS, IF = 12.5 MHz 35 35 35 35 mW IAVDD 10 10 10 10 mA IDVDD + IDVDDIO 8 8 8 8 mA ICVDD 1.5 1.5 1.5 1.5 mA Power-Down Mode with Clock 12 12 12 12 mW Power-Down Mode, No Clock 850 850 850 850 μW Power Supply Rejection Ratio −0.001 −0.001 −0.001 −0.001 % FSR/V OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 –40 +25 +85 °C 1 Based on a 10 kΩ external resistor. Rev. A | Page 6 of 80 AD9714/AD9715/AD9716/AD9717 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns INPUT DATA 1.8 V Q Channel or DCLKIO Falling Edge Setup 0.25 ns Hold 1.2 ns 1.8 V I Channel or DCLKIO Rising Edge Setup 0.13 ns Hold 1.1 ns 3.3 V Q Channel or DCLKIO Falling Edge Setup −0.2 ns Hold 1.5 ns 3.3 V I Channel or DCLKIO Rising Edge Setup −0.2 ns Hold 1.6 ns V 2.1 3 V IH VIL 0 0.9 V Rev. A | Page 7 of 80 AD9714/AD9715/AD9716/AD9717 AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 3. AD9714 AD9715 AD9716 AD9717 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 75 82 83 84 dBc fDAC = 125 MSPS, fOUT = 50 MHz 60 61 62 63 dBc TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 86 87 88 89 dBc fDAC = 125 MSPS, fOUT = 50 MHz 71 71 71 71 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f = 125 MSPS, f = 10 MHz −129 −141 −149 −152 dBc/Hz DAC OUT f = 125 MSPS, f = 50 MHz −123 −135 −137 −141 dBc/Hz DAC OUT W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz −71 −71 −71 −71 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −72 −72 −72 −72 dBc T to T , AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, I = 2 mA, maximum sample rate, unless MIN MAX xOUTFS otherwise noted. Table 4. AD9714 AD9715 AD9716 AD9717 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 125 MSPS, f = 10 MHz 75 78 79 80 dBc DAC OUT f = 125 MSPS, f = 50 MHz 55 56 57 58 dBc DAC OUT TWO TONE INTERMODULATION DISTORTION (IMD) f = 125 MSPS, f = 10 MHz 79 80 84 85 dBc DAC OUT f = 125 MSPS, f = 50 MHz 53 53 53 53 dBc DAC OUT NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz −132 −141 −146 −148 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −126 −131 −131 −132 dBc/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f = 61.44 MSPS, f = 20 MHz −68 −68 −68 −68 dBc DAC OUT f = 122.88 MSPS, f = 30 MHz −68 −68 −68 −68 dBc DAC OUT Rev. A | Page 8 of 80 AD9714/AD9715/AD9716/AD9717 ABSOLUTE MAXIMUM RATINGS maximum rating conditions for extended periods may affect Table 5. device reliability. Parameter Rating AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS −0.3 V to +3.9 V THERMAL RESISTANCE DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V Table 6. DVSS to AVSS, CVSS −0.3 V to +0.3 V 1 1 Package Type θ θ θ Unit JA JB JC CVSS to AVSS, DVSS −0.3 V to +0.3 V REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS −0.3 V to AVDD + 0.3 V 40-Lead LFCSP (with No Airflow 29.8 19.0 3.4 °C/W Movement) QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, −1.0 V to AVDD + 0.3 V RLIP, RLIN to AVSS 1 1 These calculations are intended to represent the thermal performance of the DBn (MSB) to DB0 (LSB), CS, SCLK, SDIO, −0.3 V to DVDDIO + 0.3 V indicated packages using a JEDEC multilayer test board. Do not assume the RESET to DVSS same level of thermal performance in actual applications without a careful CLKIN to CVSS −0.3 V to CVDD + 0.3 V inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. Junction Temperature 125°C Storage Temperature Range −65°C to +150°C ESD CAUTION 1 n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute Rev. A | Page 9 of 80 AD9714/AD9715/AD9716/AD9717 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 DB5 1 30 RLIN INDICATOR DB4 2 29 IOUTN 28 IOUTP DB3 3 DB2 4 27 RLIP AD9714 DVDDIO 5 26 AVDD DVSS 6 TOP VIEW 25 AVSS DVDD 7 (Not to Scale) 24 RLQP DB1 8 23 QOUTP DB0 (LSB) 9 22 QOUTN NC 10 21 RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. Figure 2. AD9714 Pin Configuration Table 7. AD9714 Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 DB1 Digital Inputs. 9 DB0 (LSB) Digital Input (LSB). 10 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (QR ) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a CML resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. A | Page 10 of 80 07265-066 DB6 NC 11 40 39 DB7 (MSB) NC 12 NC 13 38 CS/PWRDN NC 14 37 SDIO/FORMAT NC 15 36 SCLK/CLKMD DCLKIO 16 35 RESET/PINMD CVDD 17 34 REFIO CLKIN 18 33 FSADJI/AUXI CVSS 19 32 FSADJQ AUXQ / CMLQ 20 31 CMLI AD9714/AD9715/AD9716/AD9717 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QR ) is enabled, this pin is the auxiliary Q DAC SET output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IR ) is disabled, this pin is full-scale SET current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull- down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the two complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port. 39 DB7 (MSB) Digital Input (MSB). 40 DB6 Digital Input. 41 (EPAD) Exposed Pad The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. Rev. A | Page 11 of 80 AD9714/AD9715/AD9716/AD9717 PIN 1 DB7 1 30 RLIN INDICATOR DB6 2 29 IOUTN DB5 3 28 IOUTP DB4 4 27 RLIP AD9715 DVDDIO 5 26 AVDD DVSS 6 TOP VIEW 25 AVSS DVDD 7 (Not to Scale) 24 RLQP DB3 8 23 QOUTP DB2 9 22 QOUTN DB1 10 21 RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. Figure 3. AD9715 Pin Configuration Table 8. AD9715 Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 10 DB[3:1] Digital Inputs. 11 DB0 (LSB) Digital Input (LSB). 12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QR ) is enabled, this pin is connected to CML the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. A | Page 12 of 80 07265-067 DB0 (LSB) 11 40 DB8 NC 12 39 DB9 (MSB) NC 13 38 CS/PWRDN NC 14 37 SDIO/FORMAT 36 SCLK/CLKMD NC 15 DCLKIO 16 35 RESET/PINMD CVDD 17 34 REFIO CLKIN 18 33 FSADJI/AUXI CVSS 19 32 FSADJQ/AUXQ CMLQ 20 31 CMLI AD9714/AD9715/AD9716/AD9717 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QR ) is enabled, this pin is the auxiliary Q DAC SET output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IR ) is disabled, this pin is the full- SET scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB9 (MSB) Digital Input (MSB). 40 DB8 Digital Input. 41 (EPAD) Exposed Pad The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. Rev. A | Page 13 of 80 AD9714/AD9715/AD9716/AD9717 DB9 1 PIN 1 30 RLIN INDICATOR DB8 2 29 IOUTN DB7 3 28 IOUTP DB6 4 27 RLIP AD9716 DVDDIO 5 26 AVDD DVSS 6 TOP VIEW 25 AVSS DVDD 7 (Not to Scale) 24 RLQP DB5 8 23 QOUTP DB4 9 22 QOUTN DB3 10 21 RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. Figure 4. AD9716 Pin Configuration Table 9. AD9716 Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14, 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QR ) is enabled, this pin is connected to CML the on-chip QR resistor. It is recommended to leave this pin unconnected. When the internal on chip CML (QR ) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a CML resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. A | Page 14 of 80 07265-003 DB2 11 40 DB10 39 DB11 (MSB) DB1 12 DB0 (LSB) 13 38 CS/PWRDN NC 14 37 SDIO/FORMAT NC 15 36 SCLK/CLKMD DCLKIO 16 35 RESET/PINMD CVDD 17 34 REFIO CLKIN 18 33 FSADJI/AUXI CVSS 19 32 FSADJQ/AUXQ CMLQ 20 31 CMLI AD9714/AD9715/AD9716/AD9717 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QR ) is enabled, this pin is the auxiliary Q DAC SET output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IR ) is disabled, this pin is the full- SET scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB11 (MSB) Digital Input (MSB). 40 DB10 Digital Input. 41 (EPAD) Exposed Pad The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. Rev. A | Page 15 of 80 AD9714/AD9715/AD9716/AD9717 PIN 1 DB11 1 30 RLIN INDICATOR DB10 2 29 IOUTN DB9 3 28 IOUTP DB8 4 27 RLIP AD9717 DVDDIO 5 26 AVDD DVSS 6 TOP VIEW 25 AVSS DVDD 7 (Not to Scale) 24 RLQP DB7 8 23 QOUTP DB6 9 22 QOUTN DB5 10 21 RLQN NOTES 1. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. Figure 5. AD9717 Pin Configuration Table 10. AD9717 Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 14 DB[7:1] Digital Inputs. 15 DB0 (LSB) Digital Input (LSB). 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (QR ) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a CML resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. A | Page 16 of 80 07265-002 DB4 11 40 DB12 DB3 12 39 DB13 (MSB) DB2 13 38 CS/PWRDN DB1 14 37 SDIO/FORMAT DB0 (LSB) 15 36 SCLK/CLKMD DCLKIO 16 35 RESET/PINMD 34 REFIO CVDD 17 CLKIN 18 33 FSADJI/AUXI CVSS 19 32 FSADJQ/AUXQ CMLQ 20 31 CMLI AD9714/AD9715/AD9716/AD9717 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QR ) is enabled, this pin is the auxiliary Q DAC SET output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IR ) is disabled, this pin is the full- SET scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB13 (MSB) Digital Input (MSB). 40 DB12 Digital Input. 41 (EPAD) Exposed Pad The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. Rev. A | Page 17 of 80 AD9714/AD9715/AD9716/AD9717 TYPICAL PERFORMANCE CHARACTERISTICS IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. DVDD is always at 1.8 V. 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 6. AD9717 Precalibration INL at 1.8 V (DVDD = 1.8 V) Figure 9. AD9717 Postcalibration INL at 1.8 V (DVDD = 1.8 V) 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 7. AD9717 Precalibration DNL at 1.8 V (DVDD = 1.8 V) Figure 10. AD9717 Postcalibration DNL at 1.8 V (DVDD = 1.8 V) 1.75 1.75 1.25 1.25 0.75 0.75 0.25 0.25 –0.25 –0.25 –0.75 –0.75 –1.25 –1.25 –1.75 –1.75 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 8. AD9717 Precalibration INL at 3.3 V (DVDD = 1.8 V) Figure 11. AD9717 Postcalibration INL at 3.3 V (DVDD = 1.8 V) Rev. A | Page 18 of 80 PRECALIBRATION INL (LSB) PRECALIBRATION DNL (LSB) PRECALIBRATION INL (LSB) 07265-005 07265-004 07265-006 POSTCALIBRATION INL (LSB) POSTCALIBRATION DNL (LSB) POSTCALIBRATION INL (LSB) 07265-008 07265-007 07265-009 AD9714/AD9715/AD9716/AD9717 1.75 1.75 1.25 1.25 0.75 0.75 0.25 0.25 –0.25 –0.25 –0.75 –0.75 –1.25 –1.25 –1.75 –1.75 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 12. AD9717 Precalibration DNL at 3.3 V Figure 15. AD9717 Postcalibration DNL at 3.3 V 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 13. AD9716 Precalibration INL at 1.8 V Figure 16. AD9716 Postcalibration INL at 1.8 V 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 14. AD9716 Precalibration DNL at 1.8 V Figure 17. AD9716 Postcalibration DNL at 1.8 V Rev. A | Page 19 of 80 PRECALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) PRECALIBRATION INL (LSB) 07265-012 07265-011 07265-010 POSTCALIBRATION DNL (LSB) POSTCALIBRATION DNL (LSB) POSTCALIBRATION INL (LSB) 07265-015 07265-014 07265-013 AD9714/AD9715/AD9716/AD9717 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 18. AD9716 Precalibration INL at 3.3 V Figure 21. AD9716 Postcalibration INL at 3.3 V 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 19. AD9716 Precalibration DNL at 3.3 V Figure 22. AD9716 Postcalibration DNL at 3.3 V 0.13 0.13 0.08 0.08 0.03 0.03 –0.02 –0.02 –0.07 –0.07 –0.12 –0.12 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 20. AD9715 Precalibration INL at 1.8 V Figure 23. AD9715 Postcalibration INL at 1.8 V Rev. A | Page 20 of 80 PRECALIBRATION INL (LSB) PRECALIBRATION DNL (LSB) PRECALIBRATION INL (LSB) 07265-017 07265-016 07265-018 POSTCALIBRATION INL (LSB) POSTCALIBRATION DNL (LSB) POSTCALIBRATION INL (LSB) 07265-020 07265-019 07265-021 AD9714/AD9715/AD9716/AD9717 0.13 0.13 0.08 0.08 0.03 0.03 –0.02 –0.02 –0.07 –0.07 –0.12 –0.12 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 24. AD9715 Precalibration DNL at 1.8 V Figure 27. AD9715 Postcalibration DNL at 1.8 V 0.13 0.13 0.08 0.08 0.03 0.03 –0.02 –0.02 –0.07 –0.07 –0.12 –0.12 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 25. AD9715 Precalibration INL at 3.3 V Figure 28. AD9715 Postcalibration INL at 3.3 V 0.13 0.13 0.08 0.08 0.03 0.03 –0.02 –0.02 –0.07 –0.07 –0.12 –0.12 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 26. AD9715 Precalibration DNL at 3.3 V Figure 29. AD9715 Postcalibration DNL at 3.3 V Rev. A | Page 21 of 80 PRECALIBRATION DNL (LSB) PRECALIBRATION INL (LSB) PRECALIBRATION DNL (LSB) 07265-024 07265-023 07265-022 POSTCALIBRATION DNL (LSB) POSTCALIBRATION INL (LSB) POSTCALIBRATION DNL (LSB) 07265-027 07265-026 07265-025 AD9714/AD9715/AD9716/AD9717 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.010 0.005 0.005 0 0 –0.005 –0.005 –0.010 –0.010 –0.015 –0.015 –0.020 –0.020 –0.025 –0.025 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE CODE Figure 30. AD9714 Precalibration INL at 1.8 V Figure 33. AD9714 Postcalibration INL at 1.8 V 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.010 0.005 0.005 0 0 –0.005 –0.005 –0.010 –0.010 –0.015 –0.015 –0.020 –0.020 –0.025 –0.025 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE CODE Figure 31. AD9714 Precalibration DNL at 1.8 V Figure 34. AD9714 Postcalibration DNL at 1.8 V 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.010 0.005 0.005 0 0 –0.005 –0.005 –0.010 –0.010 –0.015 –0.015 –0.020 –0.020 –0.025 –0.025 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE CODE Figure 32. AD9714 Precalibration INL at 3.3 V Figure 35. AD9714 Postcalibration INL at 3.3 V Rev. A | Page 22 of 80 PRECALIBRATION INL (LSB) PRECALIBRATION DNL (LSB) PRECALIBRATION INL (LSB) 07265-030 07265-029 07265-028 POSTCALIBRATION INL (LSB) POSTCALIBRATION DNL (LSB) POSTCALIBRATION INL (LSB) 07265-033 07265-032 07265-031 AD9714/AD9715/AD9716/AD9717 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.010 0.005 0.005 0 0 –0.005 –0.005 –0.010 –0.010 –0.015 –0.015 –0.020 –0.020 –0.025 –0.025 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE CODE Figure 36. AD9714 Precalibration DNL at 3.3 V Figure 39. AD9714 Postcalibration DNL at 3.3 V –126 –126 AD9714 AD9714 –129 –132 –132 –135 –138 –138 AD9715 AD9715 –141 –144 –144 AD9716 –147 AD9717 AD9716 –150 –150 –153 AD9717 –156 –156 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 f (MHz) f (MHz) OUT OUT Figure 37. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 1.8 V Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 3.3 V –133 –133 –136 –136 –40°C +85°C –139 –139 +25°C –142 –142 +25°C –40°C –145 –145 +85°C –148 –148 –151 –151 –154 –154 5 1015 202530 354045 5055 5 1015 202530 354045 5055 f (MHz) f (MHz) OUT OUT Figure 38. AD9717 Noise Spectral Density at Three Temperatures, 1.8 V Figure 41. AD9717 Noise Spectral Density at Three Temperatures, 3.3 V Rev. A | Page 23 of 80 PRECALIBRATION DNL (LSB) NSD (dBc) NSD (dBc) 07265-138 07265-038 07265-034 POSTCALIBRATION DNL (LSB) NSD (dBc) NSD (dBc) 07265-141 07265-035 07265-037 AD9714/AD9715/AD9716/AD9717 –130 –130 –133 –133 –136 –136 –139 –139 3.3V, 1mA 1.8V, 1mA –142 –142 1.8V, 2mA –145 –145 3.3V, 4mA 3.3V, 2mA –148 –148 –151 –151 –154 –154 –157 –157 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 f (MHz) f (MHz) OUT OUT Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V Figure 45. AD9717 Noise Spectral Density at Three Output Currents, 3.3 V –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 START 1MHz 1.5MHz/DIV STOP 16MHz START 1MHz 1.4MHz/DIV STOP 15MHz Figure 43. AD9717 Two Tone Spectrum, 1.8 V Figure 46. AD9717 Two Tone Spectrum, 3.3 V 88 100 AD9717 82 94 AD9716 76 88 AD9715 70 AD9714 AD9715 82 AD9716 64 AD9717 AD9714 76 58 52 70 5 10 1520 25 30 3540 4550 5 1015 20 25 3035 40 45 50 f (MHz) f (MHz) OUT OUT Figure 44. AD9714/AD9715/AD9716/AD9717 IMD at 1.8 V Figure 47. AD9714/AD9715/AD9716/AD9717 IMD at 3.3 V Rev. A | Page 24 of 80 NSD (dBc) (dBm) IMD (dBc) 07265-098 07265-085 07265-142 NSD (dBc) IMD (dBc) (dBm) 07265-040 07265-088 07265-145 AD9714/AD9715/AD9716/AD9717 90 90 +85°C 84 84 +25°C +25°C 78 78 +85°C –40°C –40°C 72 72 66 66 60 60 54 54 5 101520253035404550 5 101520253035404550 f (MHz) OUT f (MHz) OUT Figure 48. AD9717 IMD at Three Temperatures, 1.8 V Figure 51. AD9717 IMD at Three Temperatures, 3.3 V 88 91 82 88 0dB –3dB 76 –3dB 85 –6dB 70 82 –6dB 64 0dB 79 58 52 76 5 10 1520 2530 35 40 45 50 5 10 1520 2530 35 40 45 50 f (MHz) f (MHz) IN IN Figure 49. AD9717 IMD at Three Digital Input Levels, 1.8 V Figure 52. AD9717 IMD at Three Digital Input Levels, 3.3 V 90 90 2mA 84 84 4mA 1mA 78 78 1mA 72 72 2mA 66 66 60 60 54 54 5 101520253035404550 5 101520253035404550 f (MHz) f (MHz) OUT OUT Figure 50. AD9717 IMD at Two Output Currents, 1.8 V Figure 53. AD9717 IMD at Three Output Currents, 3.3 V Rev. A | Page 25 of 80 IMD (dBc) IMD (dBc) IMD (dBc) 07265-150 07265-148 07265-089 IMD (dBc) IMD (dBc) IMD (dBc) 07265-153 07265-151 07265-090 AD9714/AD9715/AD9716/AD9717 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 START 1MHz 1.5MHz/DIV STOP 16MHz START 1MHz 1.4MHz/DIV STOP 15MHz Figure 54. AD9717 Single-Tone Spectrum, 1.8 V Figure 57. AD9717 Single-Tone Spectrum, 3.3 V 86 93 AD9717 AD9717 90 AD9716 AD9716 80 AD9715 AD9715 87 AD9714 AD9714 74 84 81 68 78 62 75 72 56 69 50 66 5 1015202530 354045505560 5 1015202530 354045505560 f (MHz) f (MHz) OUT OUT Figure 55. AD9714/AD9715/AD9716/AD9717 SFDR at 1.8 V Figure 58. AD9714/AD9715/AD9716/AD9717 SFDR at 3.3 V 90 90 84 84 3.3V, +85°C 78 +85°C 78 +25°C 72 72 66 3.3V, –40°C 3.3V, +25°C 66 –40°C 60 60 54 54 48 5 1015202530 354045505560 5 1015202530 354045505560 f (MHz) f (MHz) OUT OUT Figure 59. AD9717 SFDR at Three Temperatures, 3.3 V Figure 56. AD9717 SFDR at Three Temperatures, 1.8 V Rev. A | Page 26 of 80 (dBm) SFDR (dBc) SFDR (dBc) 07265-156 07265-155 07265-084 (dBm) SFDR (dBc) SFDR (dBc) 07265-159 07265-158 07265-087 AD9714/AD9715/AD9716/AD9717 90 90 85 85 –6dB 80 80 –6dB 75 75 70 70 0dB –3dB –3dB 65 65 0dB 60 60 55 55 50 50 0 10 20304050 60 0 10 20304050 60 f (MHz) f (MHz) IN IN Figure 60. SFDR at Three Digital Input Levels vs. f , 1.8 V Figure 63. SFDR at Three Digital Input Levels vs. f , 3.3 V IN IN 90 90 84 84 4mA 78 78 72 1mA 72 2mA 66 66 2mA 60 1mA 60 54 48 54 5 1015 2025 3035 4045 505560 5 1015 2025 3035 4045 505560 f (MHz) f (MHz) OUT OUT Figure 61. SFDR at Two Output Currents, 1.8 V Figure 64. SFDR at Three Output Currents, 3.3 V AC-COUPLED: UNSPECIFIED AC-COUPLED: UNSPECIFIED BELOW 20MHz BELOW 20MHz CENTER 22.90MHz SPAN 38.84MHz CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz VBW 300kHz RES BW 30kHz SWEEP 126ms (601pts) RES BW 30kHz SWEEP 126ms (601pts) TOTAL CARRIER POWER –19.81dBm/7.87420MHz TOTAL CARRIER POWER –25.42dBm/7.68000MHz REF CARRIER POWER –19.81dBm/4.03420MHz REF CARRIER POWER –25.42dBm/3.84000MHz RCC FILTER: OFF FILTER ALPHA 0.22 RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER OFFSET INTEG LOWER UPPER FREQ BW dBc dBm dBc dBm FREQ BW dBc dBm dBc dBm 1. –19.81dBm 5.000MHz 3.840MHz –70.32 –90.13 –72.61 –92.42 1. –25.42dBm 5.000MHz 3.840MHz –72.52 –97.94 –72.44 –97.86 2. –85.75dBm 10.00MHz 3.840MHz –71.81 –91.61 –71.60 –91.41 2. –88.16dBm 10.00MHz 3.840MHz –72.82 –98.24 –73.02 –98.44 15.00MHz 3.840MHz –72.59 –92.40 –65.50 –85.31 15.00MHz 3.840MHz –72.18 –97.60 –71.88 –97.30 Figure 62. AD9717 One-Carrier ACLR, 1.8 V Figure 65. AD9717 One-Carrier ACLR, 3.3 V Rev. A | Page 27 of 80 SFDR (dBc) SFDR (dBc) 10dB/DIV 07265-161 07265-160 07265-092 SFDR (dBc) SFDR (dBc) 10dB/DIV 07265-163 07265-162 07265-091 AD9714/AD9715/AD9716/AD9717 –60 –60 1mA PRECAL 1mA PRECAL –65 1mA POSTCAL –65 2mA POSTCAL 1mA POSTCAL –70 2mA POSTCAL 2mA PRECAL –70 4mA POSTCAL –75 2mA PRECAL 4mA PRECAL –75 –80 15 25 35 45 15 25 35 45 f (MHz) f (MHz) OUT OUT Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V Figure 69. AD9717 One-Carrier W-CDMA First ACLR, 3.3 V –60 –60 1mA PRECAL 1mA PRECAL –65 –65 2mA PRECAL 1mA POSTCAL 1mA POSTCAL –70 2mA PRECAL –70 2mA POSTCAL 4mA PRECAL –75 2mA POSTCAL 4mA POSTCAL –75 –80 15 25 35 45 15 25 35 45 f (MHz) f (MHz) OUT OUT Figure 67. AD9717 One-Carrier W-CDMA Second ACLR, 1.8 V Figure 70. AD9717 One-Carrier W-CDMA Second ACLR, 3.3 V –60 –60 1mA PRECAL 1mA PRECAL –65 –65 2mA POSTCAL 1mA POSTCAL 2mA PRECAL 1mA POSTCAL –70 4mA PRECAL –70 2mA POSTCAL –75 2mA PRECAL 4mA POSTCAL –75 –80 20 30 40 20 30 40 f (MHz) f (MHz) OUT OUT Figure 68. AD9717 One-Carrier W-CDMA Third ACLR, 1.8 V Figure 71. AD9717 One-Carrier W-CDMA Third ACLR, 3.3 V Rev. A | Page 28 of 80 ACLR (dBc) ACLR (dBc) ACLR (dBc) 07265-072 07265-071 07265-068 ACLR (dBc) ACLR (dBc) ACLR (dBc) 07265-075 07265-074 07265-070 AD9714/AD9715/AD9716/AD9717 AC-COUPLED:UNSPECIFIED AC-COUPLED: UNSPECIFIED BELOW 20MHz BELOW 20MHz CENTER 22.90MHz SPAN 38.84MHz CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz VBW 300kHz RES BW 30kHz SWEEP 126ms (601pts) RES BW 30kHz SWEEP 126ms (601pts) TOTAL CARRIER POWER –23.08dBm/7.87420MHz TOTAL CARRIER POWER –33.14dBm/7.87420MHz REF CARRIER POWER –25.84dBm/4.03420MHz REF CARRIER POWER –25.86dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER OFFSET INTEG LOWER UPPER dBc dBm dBc dBm dBc dBm dBc dBm FREQ BW FREQ BW 1. –25.84dBm 5.000MHz 3.840MHz –65.45 –91.30 –65.63 –91.47 1. –25.86dBm 5.000MHz 3.840MHz –66.28 –92.13 –66.68 –92.53 2. –26.35dBm 10.00MHz 3.840MHz –67.01 –92.85 –67.05 –92.89 2. –26.47dBm 10.00MHz 3.840MHz –68.17 –94.02 –66.93 –92.78 15.00MHz 3.840MHz –65.22 –91.06 –65.33 –91.18 15.00MHz 3.840MHz –64.89 –90.73 –65.84 –91.69 Figure 72. AD9717 Two-Carrier ACLR, 1.8 V Figure 75. AD9717 Two-Carrier ACLR, 3.3 V –55 –55 1mA POSTCAL 1mA PRECAL 1mA PRECAL 1mA POSTCAL –60 –60 2mA PRECAL 2mA PRECAL –65 2mA POSTCAL 2mA POSTCAL 4mA PRECAL –65 –70 4mA POSTCAL –70 –75 15 20 25 30 35 40 15 20 25 30 35 40 f (MHz) f (MHz) OUT OUT Figure 73. AD9717 Two-Carrier W-CDMA First ACLR, 1.8 V Figure 76. AD9717 Two-Carrier W-CDMA First ACLR, 3.3 V –55 –55 1mA PRECAL 1mA PRECAL –60 –60 1mA POSTCAL 2mA PRECAL 1mA POSTCAL –65 2mA PRECAL –65 2mA POSTCAL –70 2mA POSTCAL 4mA POSTCAL 4mA PRECAL –70 –75 15 20 25 30 35 40 15 20 25 30 35 40 f (MHz) f (MHz) OUT OUT Figure 74. AD9717 Two-Carrier W-CDMA Second ACLR, 1.8 V Figure 77. AD9717 Two-Carrier W-CDMA Second ACLR, 3.3 V Rev. A | Page 29 of 80 ACLR (dBc) ACLR (dBc) 10dB/DIV 07265-164 07265-077 07265-073 ACLR (dBc) ACLR (dBc) 10dB/DIV 07265-165 07265-080 07265-076 AD9714/AD9715/AD9716/AD9717 –55 –55 1mA PRECAL 1mA PRECAL –60 –60 1mA POSTCAL 2mA PRECAL 1mA POSTCAL 2mA PRECAL –65 –65 2mA POSTCAL –70 2mA POSTCAL 4mA POSTCAL 4mA PRECAL –70 –75 20 25 30 35 40 20 25 30 35 40 f (MHz) f (MHz) OUT OUT Figure 78. AD9717 Two-Carrier W-CDMA Third ACLR, 1.8 V Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3.3 V 0.4 1.0 0.3 0.8 0.6 0.2 0.4 0.1 0.2 0 0 –0.1 –0.2 –0.2 –0.4 –0.3 –0.6 –0.4 –0.8 –0.5 –1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 82. AUXDAC INL Figure 79. AUXDAC DNL 25 TOTAL CURRENT @ 1mA OUT 30 TOTAL CURRENT @ 2mA OUT 20 TOTAL CURRENT @ 4mA OUT TOTAL CURRENT @ 2mA OUT 20 15 AVDD @ 4mA OUT TOTAL CURRENT @ 1mA OUT 10 AVDD @ 2mA OUT AVDD @ 2mA OUT 10 AVDD @ 1mA OUT AVDD @ 1mA OUT 5 DVDD DVDD CVDD CVDD 0 0 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 f (MHz) CLK f (MHz) CLK Figure 80. Supply Current vs. Clock Frequency at 1.8 V Figure 83. Supply Current vs. Clock Frequency at 3.3 V Rev. A | Page 30 of 80 AUXDAC DNL (LSB) CURRENT (mA) ACLR (dBc) 07265-041 07265-078 07265-147 AUXDAC INL (LSB) CURRENT (mA) ACLR (dBc) 07265-044 07265-081 07265-144 AD9714/AD9715/AD9716/AD9717 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the Power supply rejection is the maximum change in the full-scale actual analog output from the ideal output, determined by output as the supplies are varied from minimum to maximum a straight line drawn from zero scale to full scale. specified voltages. Differential Nonlinearity (DNL) Settling Time DNL is the measure of the variation in analog value, normalized Settling time is the time required for the output to reach and to full scale, associated with a 1 LSB change in digital input code. remain within a specified error band around its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output either increases or remains Spurious Free Dynamic Range (SFDR) constant as the digital input increases. SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal Offset Error between dc and the frequency equal to half the input data rate. Offset error is the deviation of the output current from the ideal of zero. For I , 0 mA output is expected when the Total Harmonic Distortion (THD) OUTP inputs are all 0. For I , 0 mA output is expected when all THD is the ratio of the rms sum of the first six harmonic OUTN inputs are set to 1. components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Gain Error Gain error is the difference between the actual and the ideal Signal-to-Noise Ratio (SNR) output span. The actual span is determined by the difference SNR is the ratio of the rms value of the measured output signal between the output when all inputs are set to 1 and the output to the rms sum of all other spectral components below the when all inputs are set to 0. Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB). Output Compliance Range Output compliance range is the range of allowable voltage at Adjacent Channel Leakage Ratio (ACLR) the output of a current-output DAC. Operation beyond the ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. adjacent channel. Temperature Drift Complex Image Rejection Temperature drift is specified as the maximum change from In a traditional two-part upconversion, two images are created the ambient value (25°C) to the value at either T or T . around the second IF frequency. These images have the effect of MIN MAX For offset and gain drift, the drift is reported in ppm of full- wasting transmitter power and system bandwidth. By placing scale range per degree Celsius (ppm FSR/°C). For reference the real part of a second complex modulator in series with the drift, the drift is reported in parts per million per degree first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Celsius (ppm/°C). Rev. A | Page 31 of 80 AD9714/AD9715/AD9716/AD9717 THEORY OF OPERATION 1V AD9717 SPI DB11 INTERFACE QR IR SET SET IR CML 16kΩ 16kΩ DB10 1kΩ TO RLIN 250Ω 500Ω 10kΩ DB9 IOUTN I I DAC REF IOUTP 100µA DB8 500Ω BAND RLIP AUX1DAC GAP DVDDIO AVDD 1 INTO 2 INTERLEAVED AVSS AUX2DAC I DATA DATA DVSS RLQP INTERFACE 500Ω DVDD 1.8V QOUTP Q DATA LDO Q DAC QOUTN DB7 500Ω CLOCK RLQN DB6 DIST QR CML 1kΩ TO 250Ω DB5 Figure 84. Simplified Block Diagram Figure 84 shows a simplified block diagram of the AD9714/ LDO is provided for DVDDIO supplies greater than 1.8 V, or the AD9715/AD9716/AD9717 that consists of two DACs, digital 1.8 V can be supplied directly through DVDD. A 1.0 μF bypass capacitor at DVDD (Pin 7) is required when using the LDO. control logic, and a full-scale output current control. Each DAC contains a PMOS current source array capable of providing a The core is capable of operating at a rate of up to 125 MSPS. It nominal full-scale current (IxOUTFS) of 2 mA and a maximum of consists of edge-triggered latches and the segment decoding logic 4 mA. The arrays are divided into 31 equal currents that make circuitry. The analog section includes PMOS current sources, up the five most significant bits (MSBs). The next four bits, or associated differential switches, a 1.0 V band gap voltage middle bits, consist of 15 equal current sources whose value is reference, and a reference control amplifier. 1/16 of an MSB current source. The remaining LSBs are binary Each DAC full-scale output current is regulated by the reference weighted fractions of the current sources of the middle bits. control amplifier and can be set from 1 mA to 4 mA via an external Implementing the middle and lower bits with current sources, resistor, xR SET, connected to its full-scale adjust pin (FSADJx). instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the The external resistor, in combination with both the reference high output impedance of the DACs (that is, >200 MΩ). control amplifier and voltage reference, VREFIO, sets the reference current, IxREF, which is replicated to the segmented current sources All of these current sources are switched to one or the other with the proper scaling factor. The full-scale current, I , is xOUTFS of the two output nodes (I or I ) via PMOS differential OUTP OUTN 32 × I . xREF current switches. The switches are based on the architecture that Optional on-chip xR resistors are provided that can be pro- was pioneered in the AD976x family, with further refinements SET to reduce distortion contributed by the switching transient. This grammed between a nominal value of 8 kΩ to 32 kΩ (4 mA to switch architecture also reduces various timing errors and 1 mA IxOUTFS, respectively). provides matching complementary drive signals to the inputs The AD9714/AD9715/AD9716/AD9717 provide the option of of the differential current switches. setting the output common mode to a value other than AVSS The analog and digital I/O sections of the AD9714/AD9715/ via the output common-mode pins (CMLI and CMLQ). This AD9716/AD9717 have separate power supply inputs (AVDD and facilitates directly interfacing the output of the AD9714/AD9715/ DVDDIO) that can operate independently over a 1.8 V to 3.3 V AD9716/AD9717 to components that require common-mode levels greater than 0 V. range. The core digital section requires 1.8 V. An optional on-chip Rev. A | Page 32 of 80 DB4 DB12 DB3 DB13 (MSB) DB2 DB1 SDIO/FORMAT DB0 (LSB) SCLK/CLKMD DCLKIO RESET/PINMD REFIO CVDD FSADJQ/AUXQ CLKIN CVSS FSADJI/AUXI CMLQ CMLI 07265-046 CS/PWRDN AD9714/AD9715/AD9716/AD9717 SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9714/AD9715/AD9716/AD9717 is a INSTRUCTION BYTE flexible, synchronous serial communications port that allows easy The instruction byte contains the information shown in Table 11. interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchron- Table 11. ous transfer formats, including both the Motorola SPI and Intel® MSB LSB SSR protocols. The interface allows read/write access to all registers DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 that configure the AD9714/AD9715/AD9716/AD9717. Single or R/W N1 N0 A4 A3 A2 A1 A0 multiple byte transfers are supported, as well as MSB first or R/W (Bit 7 of the instruction byte) determines whether a read or a LSB first transfer formats. The serial interface port of the AD9714/ write data transfer occurs after the instruction byte write. Logic 1 AD9715/AD9716/AD9717 is configured as a single I/O pin on indicates a read operation. Logic 0 indicates a write operation. the SDIO pin. N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the GENERAL OPERATION OF THE SERIAL INTERFACE number of bytes to be transferred during the data transfer cycle. There are two phases to a communications cycle on the AD9714/ The bit decodes are shown in Table 12. AD9715/AD9716/AD9717. Phase 1 is the instruction cycle, which Table 12. Byte Transfer Count is the writing of an instruction byte into the AD9714/AD9715/ N1 N0 Description AD9716/AD9717, coinciding with the first eight SCLK rising 0 0 Transfer 1 byte edges. In Phase 2, the instruction byte provides the serial port 0 1 Transfer 2 bytes controller of the AD9714/AD9715/AD9716/AD9717 with infor- 1 0 Transfer 3 bytes mation regarding the data transfer cycle. The Phase 1 instruction 1 1 Transfer 4 bytes byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the address for the first byte of the data transfer. The first eight SCLK instruction byte) determine which register is accessed during the rising edges of each communication cycle are used to write the data transfer portion of the communications cycle. For multi- instruction byte into the AD9714/AD9715/AD9716/AD9717. byte transfers, this address is the starting byte address. The A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0, following register addresses are generated internally by the resets the SPI port timing to the initial state of the instruction AD9714/AD9715/AD9716/AD9717, based on the LSBFIRST bit cycle. This is true regardless of the present state of the internal (Register 0x00, Bit 6). registers or the other signal levels present at the inputs to the SERIAL INTERFACE PORT PIN DESCRIPTIONS SPI port. If the SPI port is in the midst of an instruction cycle SCLK—Serial Clock or a data transfer cycle, none of the present data is written. The serial clock pin is used to synchronize data to and from the The remaining SCLK edges are for Phase 2 of the communication AD9714/AD9715/AD9716/AD9717 and to run the internal state cycle. Phase 2 is the actual data transfer between the AD9714/ machines. The SCLK maximum frequency is 20 MHz. All data AD9715/AD9716/AD9717 and the system controller. Phase 2 of input to the AD9714/AD9715/AD9716/AD9717 is registered on the communication cycle is a transfer of one, two, three, or four the rising edge of SCLK. All data is driven out of the AD9714/ data bytes, as determined by the instruction byte. Using one multi- AD9715/AD9716/AD9717 on the falling edge of SCLK. byte transfer is the preferred method. Single-byte data transfers are useful to reduce CPU overhead when register access requires CS —Chip Select one byte only. Registers change immediately upon writing to the An active low input starts and gates a communications cycle. last bit of each transfer byte. It allows more than one device to be used on the same serial communications lines. The SDIO/FORMAT pin reaches a high impedance state when this input is high. Chip select should stay low during the entire communications cycle. SDIO—Serial Data I/O The SDIO pin is used as a bidirectional data line to transmit and receive data. Rev. A | Page 33 of 80 AD9714/AD9715/AD9716/AD9717 INSTRUCTION CYCLE DATA TRANSFER CYCLE MSB/LSB TRANSFERS CS The serial port of the AD9714/AD9715/AD9716/AD9717 can support both most significant bit (MSB) first or least significant SCLK bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first R/W N1 N0A4A3 A2 A1 A0 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDIO (LSBFIRST = 0). D7 SDO When LSBFIRST = 0 (MSB first), the instruction and data bytes Figure 86. Serial Register Interface Timing, MSB First Read must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most INSTRUCTION CYCLE DATA TRANSFER CYCLE CS significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, SCLK the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle. A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDIO When LSBFIRST = 1 (LSB first), the instruction and data bytes Figure 87. Serial Register Interface Timing, LSB First Write must be written from the least significant bit to the most signifi- cant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least INSTRUCTION CYCLE DATA TRANSFER CYCLE CS significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte SCLK of the multibyte communication cycle. The serial port controller data address of the AD9714/AD9715/ A0 A1 A2 A3 A4 N0 N1 R/W D1 D2 D4 D5 D6 D7 0 0 N N N N SDIO AD9716/AD9717 decrements from the data address written D0 toward 0x00 for multibyte I/O operations if the MSB first mode SDO is active. The serial port controller address increments from the Figure 88. Serial Register Interface Timing, LSB First Read data address written toward 0x1F for multibyte I/O operations PIN MODE if the LSB first mode is active. The AD9714/AD9715/AD9716/AD9717 can also be operated SERIAL PORT OPERATION without ever writing to the serial port. With the RESET/PINMD The serial port configuration of the AD9714/AD9715/AD9716/ pin tied high, the SCLK pin becomes CLKMD to provide for AD9717 is controlled by Register 0x00. It is important to note clock mode control (see the Retimer section), the SDIO pin that the configuration changes immediately upon writing to the becomes FORMAT and selects the input data format, and the last bit of the register. For multibyte transfers, writing to this CS/PWRDN pin serves to power down the device. register can occur during the middle of the communications Operation is otherwise exactly as defined by the default register cycle. Care must be taken to compensate for this new configu- values in Table 13; therefore, external resistors at FSADJI and ration for the remaining bytes of the current communications cycle. FSADJQ are needed to set the DAC currents, and both DACs The same considerations apply to setting the software reset bit are active. This is also a convenient quick checkout mode. (Register 0x00, Bit 5). All registers are set to their default values DAC currents can be externally adjusted in pin mode by sourcing except Register 0x00, which remains unchanged. or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ Use of single-byte transfers or initiating a software reset is pins as desired with the fixed resistors installed. An op amp recommended when changing serial port configurations to output with appropriate series resistance is one of many possibili- prevent unexpected device behavior. ties. This has the same effect as changing the resistor value. INSTRUCTION CYCLE DATA TRANSFER CYCLE Place at least 10 kΩ resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The CS REFIO pin can be adjusted ±25% in a similar manner, if desired. SCLK R/W N1N0A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N N 0 0 0 0 SDIO Figure 85. Serial Register Interface Timing, MSB First Write Rev. A | Page 34 of 80 07265-291 07265-289 07265-290 07265-288 AD9714/AD9715/AD9716/AD9717 SPI REGISTER MAP Table 13. Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 Reserved LSBFIRST Reset LNGINS Power-Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS Reserved IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 Reserved I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN Reserved IRSET[5:0] IRCML 0x05 0x00 IRCMLEN Reserved IRCML[5:0] Q DAC Gain 0x06 0x00 Reserved Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN Reserved QRSET[5:0] QRCML 0x08 0x00 QRCMLEN Reserved QRCML[5:0] AUXDAC Q 0x09 0x00 QAUXDAC[7:0] AUX CTLQ 0x0A 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] AUXDAC I 0x0B 0x00 IAUXDAC[7:0] AUX CTLI 0x0C 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reference Resistor 0x0D 0x00 Reserved RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CALSTATQ CALSTATI CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 Reserved MEMADDR[5:0] Memory Data 0x11 0x34 Reserved MEMDATA[5:0] Memory R/W 0x12 0x00 CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODE 0x14 0x00 CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version 0x1F 0x03 Version[7:0] Rev. A | Page 35 of 80 AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name Description SPI Control 0x00 6 LSBFIRST 0 (default): MSB first, per SPI standard. 1: LSB first, per SPI standard. Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. 5 Reset Execute software reset of SPI and controllers, reload default register values except Register 0x00. 1: sets software reset; write 0 on the next (or any following) cycle to release reset. 4 LNGINS 0 (default): the SPI instruction word uses a 5-bit address. 1: the SPI instruction word uses a 13-bit address. Power-Down 0x01 7 LDOOFF 0 (default): LDO voltage regulator on. 1: turns core LDO voltage regulator off. 6 LDOSTAT 0: indicates that the core LDO voltage regulator is off. 1 (default) : indicates that the core LDO voltage regulator is on. 5 PWRDN 0 (default): all analog and digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry except for SPI logic. 4 Q DACOFF 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 3 I DACOFF 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 2 QCLKOFF 0 (default): turns on Q DAC clock. 1: turns off Q DAC clock. 1 ICLKOFF 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 EXTREF 0 (default): turns on internal voltage reference. 1: powers down internal voltage reference (external reference required). Data Control 0x02 7 TWOS 0 (default): unsigned binary input data format. 1: twos complement input data format. 5 IFIRST 0: pairing of data—Q first of pair on data input pads. 1 (default): pairing of data—I first of pair on data input pads. 4 IRISING 0: Q data latched on DCLKIO rising edge. 1 (default): I data latched on DCLKIO rising edge. 3 SIMULBIT 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. 2 DCI_EN Controls the use of the DCLKIO pad for data clock input. 0: data clock input disabled. 1 (default): data clock input enabled. 1 DCOSGL Controls the use of the DCLKIO pad for data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 DCODBL Controls the use of the DCLKIO pad for data clock output. 0 (default): DCODBL data clock output disabled. 1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current. I DAC Gain 0x03 5:0 I DACGAIN[5:0] DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100. Default IDACGAIN = 0x00. Rev. A | Page 36 of 80 AD9714/AD9715/AD9716/AD9717 Register Address Bit Name Description IRSET 0x04 7 IRSETEN 0 (default): IRSET resistor value for I channel is set by an external resistor connected to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ. 1: enables the on-chip IRSET value to be changed for I channel. 5:0 IRSET[5:0] Changes the value of the on-chip IRSET resistor for I channel; this scales the full-scale current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99. 000000 (default): IR = 16 kΩ. SET 011111: IR = 32 kΩ. SET 100000: IRSET = 8 kΩ. 111111: IRSET = 16 kΩ. IRCML 0x05 7 IRCMLEN 0 (default): IR resistor value for the I channel is set by an external resistor CML connected to the CMLI pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip IRCML adjustment for I channel. 5:0 IRCML[5:0] Changes the value of the on-chip IRCML resistor for I channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): IR = 250 Ω. CML 100000: IR = 625 Ω. CML 111111: IR = 1 kΩ. CML Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] DAC Q fine gain adjustment; alters the full-scale current as shown in Figure 100. Default QDACGAIN = 0x00. QRSET 0x07 7 QRSETEN 0 (default): QR resistor value for Q channel is set by an external resistor connected SET to the FADJQ/AUXQ pin. Recommended value for this external resistor is 16 kΩ. 1: enables on-chip QR adjustment for Q channel. SET 5:0 QRSET[5:0] Changes the value of the on-chip QRSET resistor for Q channel; this scales the full- scale current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99. 000000 (default): QR = 16 kΩ. SET 011111: QR = 32 kΩ. SET 100000: QR = 8 kΩ. SET 111111: QRSET = 16 kΩ. QRCML 0x08 7 QRCMLEN 0 (default): QR resistor value for the Q channel is set by an external resistor CML connected to CMLQ pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip QRCML adjustment for Q channel. 5:0 QRCML[5:0] Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): QR = 250 Ω. CML 100000: QR = 625 Ω. CML 111111: QRCML = 1 kΩ. AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUXDAC Q output voltage adjustment word LSBs. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. AUX CTLQ 0x0A 7 QAUXEN 0 (default): AUXDAC Q output disabled. 1: enables AUXDAC Q output. 6:5 QAUXRNG[1:0] 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 4:2 QAUXOFS[2:0] 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V. 011: sets AUXDAC Q top of range to 2.5 V. 100: sets AUXDAC Q top of range to 2.9 V. 1:0 QAUXDAC[9:8] AUXDAC Q output voltage adjustment word MSBs (default = 00). Rev. A | Page 37 of 80 AD9714/AD9715/AD9716/AD9717 Register Address Bit Name Description AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUXDAC I output voltage adjustment word LSBs. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. AUX CTLI 0x0C 7 IAUXEN 0 (default): AUXDAC I output disabled. 1: enables AUXDAC I output. 6:5 IAUXRNG[1:0] 00 (default): sets AUXDAC I output voltage range to 2 V. 01: sets AUXDAC I output voltage range to 1.5 V. 10: sets AUXDAC I output voltage range to 1.0 V. 11: sets AUXDAC I output voltage range to 0.5 V. 4:2 IAUXOFS[2:0] 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V. 011: sets AUXDAC I top of range to 2.5 V. 100: sets AUXDAC I top of range to 2.9 V. 1:0 IAUXDAC[9:8] AUXDAC I output voltage adjustment word MSBs (default = 00). 0x0D 5:0 RREF[5:0] Reference Permits an adjustment of the on-chip reference voltage and output at REFIO (see Resistor Figure 98) twos complement. 000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V. 011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V. 100000: sets the value of R to 8 kΩ, V = 0.8 V. REF REF 111111: sets the value of R to 10 kΩ, V = 1.0 V. REF REF Cal Control 0x0E 7 PRELDQ 0 (default): preload Q DAC calibration reference set to 32. 1: preload Q DAC calibration reference set by user (Cal Address 1). 6 PRELDI 0 (default): preload I DAC calibration reference set to 32. 1: preload I DAC calibration reference set by user (Cal Address 1). 5 CALSELQ 0 (default): Q DAC self-calibration done. 1: select Q DAC self-calibration. 4 CALSELI 0 (default): I DAC self-calibration done. 1: select I DAC self-calibration. 3 CALCLK 0 (default): calibration clock disabled. 1: calibration clock enabled. 2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate. 000 (default): divide by 256. 001: divide by 128. … 110: divide by 4. 111: divide by 2. Cal Memory 0x0F 7 CALSTATQ 0 (default): Q DAC calibration in progress. 1: calibration of Q DAC complete. 6 CALSTATI 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. 3:2 CALMEMQ[1:0] Status of Q DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user calibrated. 1:0 CALMEMI[1:0] Status of I DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user calibrated. Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed. Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access. Rev. A | Page 38 of 80 AD9714/AD9715/AD9716/AD9717 Register Address Bit Name Description Memory R/W 0x12 7 CALRSTQ 0 (default): no action. 1: clear CALSTATQ. 6 CALRSTI 0 (default): no action. 1: clear CALSTATI. 4 CALEN 0 (default): no action. 1: initiate device self-calibration. 3 SMEMWR 0 (default): no action. 1: write to static memory (calibration coefficients). 2 SMEMRD 0 (default): no action. 1: read from static memory (calibration coefficients). 1 UNCALQ 0 (default): no action. 1: reset Q DAC calibration coefficients to default (uncalibrated). 0 UNCALI 0 (default): no action. 1: reset I DAC calibration coefficients to default (uncalibrated). CLKMODE 0x14 7:6 CLKMODEQ[1:0] Depending on the CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if needed to better synchronize the DACs (see the Retimer section). 4 Searching Data path retimer status bit. 0 (default): clock relationship established. 1: indicates that the internal data path retimer is searching for clock relationship (device output is not usable while this bit is high). 3 Reacquire Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship. 2 CLKMODEN 0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read back in CLKMODEI[1:0] and CLKMODEQ[1:0]. 1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. 1:0 CLKMODEI[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if needed to better synchronize the DACs (see the Retimer section). Version 0x1F 7:0 Version[7:0] Hardware version of the device. This register is set to 0x03 for the latest version of the device. Rev. A | Page 39 of 80 AD9714/AD9715/AD9716/AD9717 DIGITAL INTERFACE OPERATION Digital data for the I and Q DACs is supplied over a single DCLKIO parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) DB[n:0]ZA B C D E F G H accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is I DATA Z B D F 250 MSPS with a 125 MHz clock. The order of data pairing and the sampling edge selection is user programmable using Q DATA A C E G the IFIRST and IRISING data control bits, resulting in four NOTES: possible timing diagrams. These are shown in Figure 89, 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE 'JHVSF
90, Figure 91, and Figure 92. AD9716, AND 13 FOR THE AD9717. Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0 DCLKIO DCLKIO DB[n:0] ZA B C D E F G H DB[n:0]ZA B C D E F G H I DATA Z B D F I DATA Y A C E Q DATA Y A C E NOTES: Q DATA Z B D F 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. NOTES: Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1 DCLKIO Ideally, the rising and falling edges of the clock fall in the center of the keep-in-window formed by the setup and hold times, t S DB[n:0]ZA B C D E F G H and tH. Refer to Table 2 for setup and hold times. A detailed timing diagram is shown in Figure 93. I DATA Y A C E DCLKIO Q DATA X Z B D t t t t S H S H NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. DB[n:0] Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1 NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 93. Setup and Hold Times for All Input Modes In addition to the different timing modes listed in Table 2, the input data can also be presented to the device in either unsigned binary or twos complement format. The format type is chosen via the TWOS data control bit. Rev. A | Page 40 of 80 07265-048 07265-047 07265-051 07265-050 07265-049 AD9714/AD9715/AD9716/AD9717 OR RETIMER-CLK D-FF D-FF D-FF D-FF D-FF 0 1 2 3 4 TO DAC CORE I OUT DB[n:0] (INPUT) DCLKIO-INT CLKIN-INT I OUT NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED. IE IE OE DELAY2 DCLKIO CLKIN (INPUT/OUTPUT) (INPUT) NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL, DIGITAL DATA LATCHING AND RETIMER BLOCK respectively, to logic high allows the user to obtain a DCLKIO The AD9714/AD9715/AD9716/AD9717 have two clock inputs, output from the CLKIN input for use in the user’s PCB system. DCLKIO and CLKIN. The CLKIN is the analog clock whose It is strongly recommended that DCI_EN = DCOSGL = high or jitter affects DAC performance, and the DCLKIO is a digital DCI_EN = DCODBL = high not be used even though the clock from an FPGA that needs to have a fixed relationship with device may appear to function correctly. Similarly, do not set the input data to ensure that the data is picked up correctly by the flip-flops on the pads. DCOSGL and DCODBL to logic high simultaneously. Figure 94 is a simplified diagram of the entire data capture Retimer system in the AD9714/AD9715/AD9716/AD9717. The double The AD9714/AD9715/AD9716/AD9717 have an internal data data rate input data (DB[n:0), where n is 7 for the AD9714, 9 retimer circuit that compares the CLKIN-INT and DCLKIO-INT for the AD9715, 11 for the AD9716, and 13 for the AD9717) is clocks and, depending on their phase relationship, selects a latched at the pads/pins either on the rising edge or the falling edge retimer clock (RETIMER-CLK) to safely transfer data from of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of the DCLKIO used at the chip’s input interface to the CLKIN SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines used to clock the analog DAC cores (D-FF 4). which channel data is latched first (that is, I or Q). The captured The retimer selects one of the three phases shown in Figure 95. data is then retimed to the internal clock (CLKIN-INT) in the The retimer is controlled by the CLKMODE SPI bits, as shown retimer block before being sent to the final analog DAC core in Table 15. (D-FF 4), which controls the current steering output switches. All RETIMER-CLKs delay blocks depicted in Figure 94 are noninverting, and any wires 1/2 PERIOD DATA 180° without an explicit delay block can be assumed to have no delay. CLOCK 90° Only one channel is shown in Figure 94 with the data pads 270° (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for 1/4 PERIOD 1/2 PERIOD the AD9716, and 13 for the AD9717) serving as double data Figure 95. RETIMER-CLK Phases rate pads for both channels. Note that, in most cases, more than one retimer phase works The default PINMD and SPI settings are IE = high (closed) and ,in such cases, the retimer arbitrarily picks one phase that and OE = low (open). These settings are enabled when RESET/ works. The retimer cannot pick the best or safest phase. If the PINMD (Pin 35) is held high. In this mode, the user has to supply user has a working knowledge of the exact phase relationship both DCLKIO and CLKIN. In PINMD, it is also recommended between DCLKIO and CLKIN (and thus DCLKIO-INT and that the DCLKIO and the CLKIN be in phase for proper func- CLKIN-INT because the delay is approximately the same for tioning of the DAC, which can easily be ensured by tying the both clocks and equal to DELAY1), then the retimer can be pins together on the PCB. If the user can access the SPI, setting forced to this phase with CLKMODEN = 1, as described in Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the Table 15 and the following paragraphs. CLKIN to be used as the DCLKIO also. Rev. A | Page 41 of 80 DELAY1 RETIMER-CLK DELAY1 07265-052 07265-042 AD9714/AD9715/AD9716/AD9717 Table 15. Timer Register List Bit Name Description CLKMODEQ[1:0] Q data path retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship. CLKMODEN 0: uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both I and Q retimers (that is, force the retimer). CLKMODEI[1:0] I data path retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both the I and Q automatic retimer values. Table 16. CLKMODEI/CLKMODEQ Details CLKMODEI[1:0]/CLKMODEQ[1:0] DCLKIO-to-CLKIN Phase Relationship RETIMER-CLK Selected 00 0° to 90° Phase 2 01 90° to 180° Phase 3 10 180° to 270° Phase 3 11 270° to 360° Phase 1 When RESET is pulsed high and then returns low (the part is in ESTIMATING THE OVERALL DAC PIPELINE DELAY SPI mode), the retimer runs and automatically selects a suitable DAC pipeline latency is affected by the phase of the RETIMER- clock phase for the RETIMER-CLK within 128 clock cycles. The CLK that is selected. If latency is critical to the system and must SPI searching bit, Bit 4 of SPI Address 0x14, returns to low, be constant, the retimer should be forced to a particular phase and indicating that the retimer has locked and the part is ready for not be allowed to automatically select a phase each time. use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to Consider the case in which DCLKIO = CLKIN (that is, in reinitiate phase detection in the I and Q retimers at any time. phase), and the RETIMER-CLK is forced to Phase 2. Assume CLKMODEQ[1:0] and CLKMODEI[1:0] of SPI Address 0x14 that IRISING is 1 (that is, Q data is latched on the rising edge provide readback for the values picked by the internal phase and I data is latched on the falling edge). Then the latency to the detectors in the retimer (see Table 16). output for the I channel is three clock cycles (D-FF 1, D-FF 3, To force the two retimers (I and Q) to pick a particular phase and D-FF 4, but not D-FF 2 because it is latched on the half for the retimer clock (they must both be forced to the same clock cycle or 180°). The latency to the output for the Q channel value), CLKMODEN, Bit 2 of SPI Address 0x14, should be set from the time the falling edge latches it at the pads in D-FF 0 high and the required phase value is written into CLKMODEI[1:0] is 2.5 clock cycles (½ clock cycle to D-FF 1, 1 clock cycle to and CLKMODEQ[1:0]. For example, if the DCLKIO and the D-FF 3, and 1 clock cycle to D-FF 4). This latency for the AD9714/ CLKIN are in phase to the first order, the user can safely force the AD9715/AD9716/AD9717 is case specific and needs to be calcu- retimers to pick Phase 2 for the RETIMER-CLK. This forcing lated based on the RETIMER-CLK phase that is automatically function may be useful for synchronizing multiple devices. selected or manually forced. In pin mode, it is expected that the user tie CLKIN and DCLKIO together. The device has a small amount of programmable functionality using the unused SPI pins (SCLK, SDIO, and CS). If the two chip clocks are tied together, the SCLK pin can be tied to ground, and the chip uses a clock for the retimer that is 180° out of phase with the two input clocks (that is, Phase 2, which is the safest and best option). The chip has an additional option in pin mode when the redefined SCLK pin is high. Use this mode if using pin mode, but CLKIN and DCLKIO are not tied together (that is, not in phase). Holding SCLK high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable RETIMER-CLK phase). The action of taking SCLK high causes the internal phase detector to reexamine the two clocks and determine the relative phase. Whenever the user wants to reevaluate the relative phase of the two clocks, the SCLK pin can be taken low and then high again. Rev. A | Page 42 of 80 AD9714/AD9715/AD9716/AD9717 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9714/AD9715/AD9716/AD9717 contain an internal The AD9714/AD9715/AD9716/AD9717 contain a control 1.0 V band gap reference. The internal reference can be disabled amplifier that regulates the full-scale output current, IxOUTFS. by setting Bit 0 (EXTREF) of the power-down register (Address The control amplifier is configured as a V-I converter, as shown 0x01) through the SPI interface. To use the internal reference, in Figure 96. The output current, I , is determined by the xREF decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable ratio of the V and an external resistor, xR , as stated in REFIO SET the internal reference, and clear Bit 0 of the power-down register Equation 4 (see the DAC Transfer Function section). I , is xREF (Address 0x01) through the SPI interface. Note that this is the mirrored to the segmented current sources with the proper scale default configuration. The internal reference voltage is present factor to set IxOUTFS, as stated in Equation 3. at REFIO. If the voltage at REFIO is to be used anywhere else in The control amplifier allows a 2.5:1 adjustment span of IxOUTFS the circuit, an external buffer amplifier with an input bias current from 1 mA to 4 mA by setting IxREF between 125 μA and 31.25 μA of less than 100 nA must be used to avoid loading the reference. (set xR between 8 kΩ and 32 kΩ). The wide adjustment span SET An example of the use of the internal reference is shown in of I provides several benefits. The first relates directly to xOUTFS Figure 96. the power dissipation of the AD9714/AD9715/AD9716/AD9717, which is proportional to I (see the DAC Transfer Function xOUTFS AD9714/AD9715/ I DAC section). The second benefit relates to the ability to adjust the AD9716/AD9717 OR V BG Q DAC output over a 8 dB range with 0.25 dB steps, which is useful for 1.0V controlling the transmitted power. The small signal bandwidth REFIO – of the reference control amplifier is approximately 500 kHz. FSADJx CURRENT + 0.1µF SCALING This allows the device to be used for low frequency, small signal I ×32 xOUTFS xR SET multiplying applications. When an external resistor greater than 16 kΩ is used on the I xREF AVSS FSADJx pins, care must be taken to maintain the high frequency Figure 96. Internal Reference Configuration equivalent circuit to an impedance lower than 16 kΩ by splitting the resistor into two resistors in series with a 10 nF REFIO serves as either an input or an output, depending on capacitor in parallel with the resistor to AVSS (see Figure 97). whether the internal or an external reference is used. Table 17 summarizes the reference operation. AD9714/AD9715/ AD9716/AD9717 Table 17. Reference Operation REFIO Reference Mode REFIO Pin Register Setting FSADJx Internal 0.1µF Connect 0.1 μF Register 0x01, Bit 0 = 0 capacitor (default) R < 16kΩ External Apply external Register 0x01, Bit 0 = 1 xR SET capacitor (for power saving) 10nF An external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. Also, a AVSS variable external voltage reference can be used to implement a Figure 97. xR Configuration for Values > 16 kΩ SET method for gain control of the DAC output. Recommendations When Using an External Reference Apply the external reference to the REFIO pin. The internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consumption The external 0.1 μF compensation capacitor on REFIO is not required unless specified by the external voltage reference manufacturer. The input impedance of REFIO is 10 kΩ when the internal reference is powered up and 1 MΩ when it is powered down. Rev. A | Page 43 of 80 07265-218 07265-219 AD9714/AD9715/AD9716/AD9717 Substituting the values of IOUTP, IOUTN, and I , V can DAC TRANSFER FUNCTION xREF IDIFF be expressed as The AD9714/AD9715/AD9716/AD9717 provide two differen- N N V = {(2 × IDAC CODE – (2 − 1))/2 } × (8) tial current outputs, IOUTP/IOUTN and QOUTP/QOUTN. IDIFF IOUTP and QOUTP provide a near full-scale current output, (32 × VREFIO/IRSET) × IRLOAD N I , when all bits are high (that is, DAC CODE = 2 − 1, xOUTFS Equation 8 highlights some of the advantages of operating the where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716, AD9714/AD9715/AD9716/AD9717 differentially. First, the and AD9717, respectively), while IOUTN and QOUTN, the differential operation helps cancel common-mode error sources complementary outputs, provide no current. The current associated with IOUTP and IOUTN, such as noise, distortion, outputs appearing at the positive DAC outputs, IOUTP and and dc offsets. Second, the differential code-dependent current and QOUTP, and at the negative DAC outputs, IOUTN and QOUTN, subsequent voltage, V , is twice the value of the single-ended IDIFF are a function of both the input code and IxOUTFS and can be voltage output (that is, V or V ), thus providing twice IOUTP IOUTN expressed as follows: the signal power to the load. Note that the gain drift temperature N IOUTP = (IDAC CODE/2 ) × I (1) IOUTFS performance for a single-ended output (VIOUTP and VIOUTN) or N QOUTP = (QDAC CODE/2 ) × I differential output (VIDIFF) of the AD9714/AD9715/AD9716/ QOUTFS AD9717 can be enhanced by selecting temperature-tracking N N IOUTN = ((2 − 1) − IDAC CODE)/2 × IIOUTFS (2) resistors for xR and xR because of their ratiometric LOAD SET N N QOUTN = ((2 − 1) − QDAC CODE)/2 × IQOUTFS relationship, as shown in Equation 8. where: ANALOG OUTPUT N IDAC CODE and QDAC CODE = 0 to 2 − 1 (that is, decimal The complementary current outputs in each DAC, IOUTP/ representation). IOUTN and QOUTP/QOUTN, can be configured for single- I and I are functions of the reference currents, I IOUTFS QOUTFS IREF ended or differential operation. IOUTP/IOUTN and QOUTP/ and I , respectively, which are nominally set by a reference QREF QOUTN can be converted into complementary single-ended voltage, VREFIO, and external resistors, IRSET and QRSET, respec- voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN tively. IIOUTFS and IQOUTFS can be expressed as follows: via a load resistor, xRLOAD, as described in the DAC Transfer IIOUTFS = 32 × IIREF (3) Function section by Equation 6 through Equation 8. The differen- IQOUTFS = 32 × IQREF tial voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN, and V and V , can also be converted to a single-ended QOUTP QOUTN where: voltage via a transformer or a differential amplifier configuration. I = V /IR (4) IREF REFIO SET The ac performance of the AD9714/AD9715/AD9716/AD9717 I = V /QR is optimum and is specified using a differential transformer- QREF REFIO SET coupled output in which the voltage swing at IOUTP and IOUTN or is limited to ±0.5 V. The distortion and noise performance of IIOUTFS = 32 × VREFIO/IRSET (5) the AD9714/AD9715/AD9716/AD9717 can be enhanced when IQOUTFS = 32 × VREFIO/QRSET it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) can be significantly reduced by the common-mode rejection typically drives a resistive load directly or via a transformer. If of a transformer or differential amplifier. These common-mode dc coupling is required, the differential pair (IOUTP/IOUTN or error sources include even-order distortion products and noise. QOUTP/QOUTN) should be connected to matching resistive The enhancement in distortion performance becomes more loads, xR , that are tied to analog common, AVSS. The LOAD significant as the frequency content of the reconstructed wave- single-ended voltage output appearing at the positive and form increases and/or its amplitude increases. This is due to negative nodes is the first-order cancellation of various dynamic common-mode VIOUTP = IOUTP × IRLOAD (6) distortion mechanisms, digital feedthrough, and noise. Performing VQOUTP = QOUTP × QRLOAD a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal V = IOUTN × IR (7) IOUTN LOAD power to the load (assuming no source termination). Because V = QOUTN × QR QOUTN LOAD the output currents of IOUTP/IOUTN and QOUTP/QOUTN To achieve the maximum output compliance of 1 V at the are complementary, they become additive when processed nominal 4 mA output current, IRLOAD = QRLOAD must be set differentially. to 250 Ω. Rev. A | Page 44 of 80 AD9714/AD9715/AD9716/AD9717 The AD9714/AD9715/AD9716/AD9717 allow reading and SELF-CALIBRATION writing of the calibration coefficients. There are 32 coefficients The AD9714/AD9715/AD9716/AD9717 have a self-calibration in total. The read/write feature of the coefficients can be useful feature that improves the DNL of the device. Performing a self- for improving the results of the self-calibration routine by calibration on the device improves device performance in low averaging the results of several self-calibration cycles and frequency applications. The device performance in applications loading the averaged results back into the device. where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, To read the calibration coefficients, use the following steps: in these cases, self-calibration is unlikely to provide much benefit. 1. Select which DAC core to read by setting either Bit 4 The calibration clock frequency is equal to the DAC clock (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the divided by the division factor chosen by the DIVSEL value. Each Q DAC in Register 0x0E. Write the address of the first calibration clock cycle is between 32 and 2048 DAC input clock coefficient (0x01) to Register 0x10. cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, 2. Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04 Bits[2:0]). The frequency of the calibration clock should be to Register 0x12. between 0.5 MHz and 4 MHz for reliable calibrations. Best 3. Read the 6-bit value of the first coefficient by reading the results are obtained by setting DIVSEL[2:0] (Register 0x0E, contents of Register 0x11. Bits[2:0]) to produce a calibration clock frequency between 4. Clear the SMEMRD bit by writing 0x00 to Register 0x12. these values. Separate self-calibration hardware is included 5. Repeat Step 2 through Step 4 for each of the remaining 31 for each DAC. The DACs can be self-calibrated individually or coefficients by incrementing the address by 1 for each read. simultaneously. 6. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in To perform a device self-calibration, the following procedure can be used: Register 0x0E. 1. Write 0x00 to Register 0x12. This ensures that the To write the calibration coefficients to the device, use the UNCALI and UNCALQ bits are reset. following steps: 2. Set up a calibration clock between 0.5 MHz and 4 MHz 1. Select which DAC core to write to by setting either Bit 4 using DIVSEL[2:0], and then enable the calibration clock (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q by setting the CALCLK bit (Register 0x0E, Bit 3). DAC in Register 0x0E. 3. Select the DAC(s) to self-calibrate by setting either Bit 4 2. Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the to Register 0x12. Q DAC in Register 0x0E. Note that each DAC contains 3. Write the address of the first coefficient (0x01) to independent calibration hardware so that they can be Register 0x10. calibrated simultaneously. 4. Write the value of the first coefficient to Register 0x11. 4. Start self-calibration by setting the CALEN bit (Register 0x12, 5. Repeat Step 2 through Step 4 for each of the remaining 31 Bit 4). Wait approximately 300 calibration clock cycles. coefficients by incrementing the address by one for each 5. Check if the self-calibration has completed by reading write. the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in 6. Clear the SMEMWR bit by writing 0x00 to Register 0x12. Register 0x0F. Logic 1 indicates that the calibration has 7. Deselect the DAC core by clearing either Bit 4 (CALSELI) completed. for the I DAC or Bit 5 (CALSELQ) for the Q DAC in 6. When the self-calibration has completed, write 0x00 to Register 0x0E. Register 0x12. 7. Disable the calibration clock by clearing the CALCLK bit (Register 0x0E, Bit 3). Rev. A | Page 45 of 80 AD9714/AD9715/AD9716/AD9717 Option 3 COARSE GAIN ADJUSTMENT Option 1 Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJx pins. A coarse full-scale output current adjustment can be achieved Any noise injected here appears as amplitude modulation of the using the lower six bits in Register 0x0D. This adds or subtracts output. Thus, a portion of the required series resistance (at least up to 20% from the band gap voltage on Pin 34 (REFIO), and 20 kΩ) must be installed right at the pin. A range of ±10% is the voltage on the FSADJx resistors tracks this change. As a quite practical using this method. result, the DAC full-scale current varies by the same amount. A secondary effect to changing the REFIO voltage is that the Option 4 full-scale voltage in the AUXDAC also changes by the same As in Option 3, when the device is in pin mode, both full-scale magnitude. The register uses twos complement format, in values can be adjusted by sourcing or sinking current from the which 011111 maximizes the voltage on the REFIO node REFIO pin. Noise injected here appears as amplitude modulation and 100000 minimizes the voltage. of the output; therefore, a portion of the required series resis- 1.30 tance (at least 10 kΩ) must be installed at the pin. A range of 1.25 ±25% is quite practical when using this method. 1.20 Fine Gain 1.15 Each main DAC has independent fine gain control using the 1.10 lower six bits in Register 0x03 (I DAC gain) and Register 0x06 (Q DAC gain). Unlike Coarse Gain Option 1, this impacts only 1.05 the main DAC full-scale output current. These registers use straight 1.00 binary format. One application in which straight binary format 0.95 is critical is for side-band suppression while using a quadrature 0.90 modulator. This is described in more detail in the Applications 0.85 Information section. 0.80 2.22 0 8 16 24 32 40 48 56 3.3V DAC1 CODE 3.3V DAC2 2.20 Figure 98. Typical V Voltage vs. Code REF 1.8V DAC1 1.8V DAC2 Option 2 2.18 While using the internal FSADJx resistors, each main DAC can 2.16 achieve independently controlled coarse gain using the lower six bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only 2.14 the main DAC full-scale output current. The register uses twos complement format and allows the output current to be changed 2.12 in approximately 0.25 dB steps. 4.0 2.10 0 8 16 24 32 40 48 56 64 GAIN DAC CODE 3.5 Figure 100. Typical DAC Gain Characteristics 3.0 V _ OR V _ OUT Q OUT I 2.5 2.0 1.5 1.0 0.5 0 0 1020 3040 50 60 xR CODE SET Figure 99. Effect of xR Code SET Rev. A | Page 46 of 80 V REF OUTPUT OF I/V CONVERTER (V) 07265-055 07265-054 I (mA) OUTFS 07265-056 AD9714/AD9715/AD9716/AD9717 1200 USING THE INTERNAL TERMINATION RESISTORS 1100 The AD9717/AD9716/AD9715/AD9714 have four 500 Ω 1000 termination internal resistors (two for each DAC output). 900 To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. 800 For example, on the I DAC, IOUTP must be shorted to RLIP 700 and IOUTN must be shorted to RLIN. In addition, the CMLI 600 or CMLQ pin must be connected to ground directly or through 500 a resistor. If the output current is at the nominal 2 mA and the 400 CMLI or CMLQ pin is tied directly to ground, this produces a dc common-mode bias voltage on the DAC output equal to 0.5 V. 300 If the DAC dc bias must be higher than 0.5 V, an external 200 0 8 16 24 32 40 48 56 resistor can be connected between the CMLI or CMLQ pin and CODE ground. This part also has an internal common-mode resistor Figure 102. Typical CML Resistor Value vs. Register Code that can be enabled. This is explained in the Using the Internal Using the CMLx Pins for Optimal Performance Common-Mode Resistor section. CML The CMLx pins also serve to change the DAC bias voltages in the parts allowing them to run at higher dc output bias voltages. When running the bias voltage below 0.9 V and an R CML RLIN AVDD of 3.3 V, the parts perform optimally when the CMLx 500Ω IOUTN I DAC pins are tied to ground. When the dc bias increases above 0.9 V, OR set the CMLx pins at 0.5 V for optimal performance. The maxi- Q DAC IOUTP 500Ω mum dc bias on the DAC output should be kept at or below 1.2 V RLIP when the supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V and connect the CMLx pins directly to ground. Figure 101. Simplified Internal Load Options Using the Internal Common-Mode Resistor These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs. By default, the common-mode resistor is not con- nected. When enabled, it can be adjusted from ~250 Ω to ~1 kΩ. Each main DAC has an independent adjustment using the lower six bits in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]). Rev. A | Page 47 of 80 07265-057 RESISTANCE (Ω) 07265-058 AD9714/AD9715/AD9716/AD9717 APPLICATIONS INFORMATION A differential resistor, RDIFF, can be inserted in applications OUTPUT CONFIGURATIONS where the output of the transformer is connected to the load, The following sections illustrate some typical output confi- RLOAD, via a passive reconstruction filter or cable. RDIFF, as gurations for the AD9714/AD9715/AD9716/AD9717. Unless reflected by the transformer, is chosen to provide a source otherwise noted, it is assumed that I is set to a nominal xOUTFS termination that results in a low voltage standing wave ratio 2 mA. For applications requiring the optimum dynamic perfor- (VSWR). Note that approximately half the signal power is mance, a differential output configuration is suggested. A dissipated across R . DIFF differential output configuration can consist of either an RF transformer or a differential op amp configuration. The SINGLE-ENDED BUFFERED OUTPUT USING transformer configuration provides the optimum high fre- AN OP AMP quency performance and is recommended for any application An op amp such as the ADA4899-1 can be used to perform that allows ac coupling. The differential op amp configuration a single-ended current-to-voltage conversion, as shown in is suitable for applications requiring dc coupling, signal gain, Figure 104. The AD9714/AD9715/AD9716/AD9717 are config- and/or a low output impedance. ured with a pair of series resistors, R , off each output. For best S A single-ended output is suitable for applications in which low distortion performance, R should be set to 0 Ω. The feedback S cost and low power consumption are primary concerns. resistor, R , determines the peak-to-peak signal swing by the FB formula DIFFERENTIAL COUPLING USING A TRANSFORMER VOUT = RFB × IFS An RF transformer can be used to perform a differential-to- single-ended signal conversion, as shown in Figure 103. The The common-mode voltage of the output is determined by the distortion performance of a transformer typically exceeds formula that available from standard op amps, particularly at higher   R R I FB FS FB frequencies. Transformer coupling provides excellent rejection   V V  1  CM REF   R 2 B of common-mode distortion (that is, even-order harmonics)   over a wide frequency range. It also provides electrical isolation The maximum and minimum voltages out of the amplifier are, and can deliver voltage gain without adding noise. Transformers respectively, with different impedance ratios can also be used for impedance  R  matching purposes. The main disadvantages of transformer FB   V V  1 MAX REF   R coupling are low frequency roll-off, lack-of-power gain, and B   high output impedance. V = V – I × R MIN MAX FS FB C F 29 IOUTN R R FB B AD9714/AD9715/ +5V AD9716/AD9717 AD9714/AD9715/ R LOAD AD9716/AD9717 R S 28 – IOUTP IOUTP 28 ADA4899-1 V OUT OPTIONAL R DIFF REFIO 34 + C R S –5V Figure 103. Differential Output Using a Transformer IOUTN 29 The center tap on the primary side of the transformer must be AVSS 25 connected to a voltage that keeps the voltages on IOUTP and IOUTN within the output common-mode voltage range of the Figure 104. Single-Supply Single-Ended Buffer device. Note that the dc component of the DAC output current is equal to I and flows out of both IOUTP and IOUTN. xOUTFS The center tap of the transformer should provide a path for this dc current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The complemen- tary voltages appearing at IOUTP and IOUTN (that is, VIOUTP and VIOUTN) swing symmetrically around AGND and should be maintained with the specified output compliance range of the AD9714/AD9715/AD9716/AD9717. Rev. A | Page 48 of 80 07265-059 07265-060 AD9714/AD9715/AD9716/AD9717 To keep the pin count reasonable, these auxiliary DACs each DIFFERENTIAL BUFFERED OUTPUT share a pin with the corresponding FSADJx resistor. They are, USING AN OP AMP therefore, usable only when enabled and when that DAC is A dual op amp (see the circuit shown in Figure 105) can be used operated on its internal full-scale resistors. A simple I-to-V in a differential version of the single-ended buffer shown in converter is implemented on chip with selectable shunt resistors Figure 104. The same RC network is used to form a one-pole (3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2 differential, low-pass filter to isolate the op amp inputs from equals 0.5 V and the following equation describes the no load the high frequency images produced by the DAC outputs. The output voltage: feedback resistors, R , determine the differential peak-to-peak FB signal swing by the formula   1.5   V  0.5 V I  16 k OUT DAC   V = 2 × R × I R OUT FB FS S   The maximum and minimum single-ended voltages out of the Figure 106 illustrates the function of all the SPI bits controlling amplifier are, respectively, these DACs with the exception of the QAUXEN (Register 0x0A, Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to   R FB   V V  1 < 3.2 kΩ. MAX REF prohibit RS   R  B  AVDD RNG0 RNG1 VMIN = VMAX − RFB × IFS RNG: 00 = > 125µA f S 01 = > 62µA f S AUXDAC 10 = > 31µA f The common-mode voltage of the differential output is S [9:0] 11 = > 16µA f S determined by the formula (OFS > 4 = 4) V = V − R × I CM MAX FB FS OFS2 OFS1 C OFS0 F 16kΩ AUX PIN R R B FB 4kΩ 8kΩ 16kΩ 16kΩ – AD9714/AD9715/ OP AMP AD9716/AD9717 R S IOUTP 28 – + REFIO ADA4841-2 2 REFIO 34 + C V OUT Figure 106. AUXDAC Simplified Circuit Diagram AVSS 25 + R S The SPI speed limits the update rate of the auxiliary DACs. The IOUTN 29 ADA4841-2 data is inverted such that IAUXDAC is full scale at 0x000 and zero – at 0x1FF, as shown in Figure 107. C F 3.0 OP AMP OUTPUT VOLTAGE vs. CHANGES 2.8 R R B FB IN R AND DAC CURRENT IN µA OFFSET 2.6 R = 3.3kΩ OFFSET 2.4 R = 4kΩ OFFSET Figure 105. Single-Supply Differential Buffer 2.2 R = 5.3kΩ OFFSET 2.0 R = 8kΩ OFFSET AUXILIARY DACs 1.8 R = 16kΩ OFFSET 1.6 The DACs of the AD9714/AD9715/AD9716/AD9717 feature 1.4 two versatile and independent 10-bit auxiliary DACs suitable 1.2 for dc offset correction and similar tasks. 1.0 0.8 Because the AUXDACs are driven through the SPI port, they 0.6 should never be used in timing-critical applications, such 0.4 0.2 as inside analog feedback loops. 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 I (µA) AUXDAC Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load, AUXDAC 0x1FF to 0x000 Rev. A | Page 49 of 80 07265-061 OUTPUT (V) 07265-045 07265-043 AD9714/AD9715/AD9716/AD9717 ADL537x Two registers are assigned to each DAC with 10 bits for the actual AD9714/AD9715/ OPTIONAL FAMILY 1kΩ AD9716/AD9717 LOW-PASS I OR Q DAC current to be generated, a 3-bit offset (and gain) adjust- I OR Q DAC FILTERING INPUTS ment, a 2-bit current range adjustment, and an enable/disable 500Ω 500Ω bit. Setting the QAUXOFS (Register 0x0A, Bits[4:2]) and AD9714/AD9715/ AD9716/AD9717 IAUXOFS (Register 0x0C, Bits[4:2]) bits to all 1s disables the 50kΩ AUX DAC respective op amp and routes the DAC current directly to the Figure 109. Simplified DC Coupling to Quadrature Modulator ADL537x respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is Family or Equivalent Is Enabled By Using Internal Components especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier. CORRECTING FOR NONIDEAL PERFORMANCE OF QUADRATURE MODULATORS ON THE IF-TO-RF When not enabled (QAUXEN or IAUXEN = 0), the respective CONVERSION DAC output is in open circuit. Analog quadrature modulators make it very easy to realize DAC-TO-MODULATOR INTERFACING single sideband radios. However, there are several nonideal The auxiliary DACs can be used for local oscillator (LO) cancella- aspects of quadrature modulator performance. Among these tion when the DAC output is followed by a quadrature modulator. analog degradations are gain mismatch and LO feedthrough. This LO feedthrough is caused by the input referred dc offset Gain Mismatch voltage of the quadrature modulator (and the DAC output offset The gain in the real and imaginary signal paths of the quad- voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 108 rature modulator may not be matched perfectly. This leads and Figure 109, with the series resistor value chosen to give an to less than optimal image rejection because the cancellation of appropriate adjustment range. Figure 108 also shows external the negative frequency image is less than perfect. load resistors in use. Often, the input common-mode voltage for LO Feedthrough the modulator is much higher than the output compliance range The quadrature modulator has a finite dc referred offset, as well of the DAC, so that ac coupling or a dc level shift is necessary. If as coupling from its LO port to the signal inputs. These can lead the required common-mode input voltage on the quadrature to a significant spectral spur at the frequency of the quadrature modulator matches that of the DAC, the dc blocking capacitors in modulator LO. Figure 108 can be removed and the on-chip resistors can be The AD9714/AD9715/AD9716/AD9717 have the capability connected. to correct for both of these analog degradations. However, MODULATOR V+ understand that these degradations drift over temperature; 0.1µF therefore, if close to optimal single sideband performance QUADRATURE AD9714/AD9715/ OPTIONAL MODULATOR AD9716/AD9717 PASSIVE is desired, a scheme for sensing these degradations over I OR Q I OR Q DAC FILTERING INPUTS 0.1µF temperature and correcting them may be necessary. I/Q-CHANNEL GAIN MATCHING AD9714/AD9715/ AD9716/AD9717 5kΩ AUX DAC Fine gain matching is achieved by adjusting the values in the TO 499Ω 499Ω 100kΩ DAC fine gain adjustment registers. For the I DAC, these values are in the I DAC gain register (Register 0x03). For the Q DAC, these values are in the Q DAC gain register (Register 0x06). These Figure 108. Typical Use of Auxiliary DACs and External Components for Coupling to Quadrature Modulators are 6-bit values that cover ±2% of full scale. To perform gain compensation starting from the default values of zero, raise the Figure 109 shows a greatly simplified circuit that takes full value of one of these registers a few steps until it can be deter- advantage of the internal components supplied in the DAC. A mined if the amplitude of the unwanted image is increased or low-pass or band-pass passive filter is recommended when decreased. If the unwanted image increases in amplitude, remove spurious signals from the DAC (distortion and DAC images) the step and try the same adjustment on the other DAC control at the quadrature modulator inputs can affect the system register. Iterate register changes until the rejection cannot be performance. In the example shown in Figure 109, the filter improved further. If the fine gain adjustment range is not sufficient must be able to pass dc to properly bias the modulator. Placing to find a null (that is, the register goes full scale with no null the filter at the location shown in Figure 108 and Figure 109 apparent), adjust the course gain settings of the two DACs allows easy design of the filter because the source and load imped- accordingly and try again. Variations on this simple method ances can easily be designed close to 500 Ω for a 2 mA full-scale are possible. output. Once the resistance at the modulator inputs is known, the user can easily look up the range of input offsets that may be encountered and compute a value for the series resistor on the AUXDAC output. Rev. A | Page 50 of 80 07265-166 07265-167 AD9714/AD9715/AD9716/AD9717 5 Note that LO feedthrough compensation is independent of 0 –5 phase compensation. However, gain compensation can affect –10 the LO compensation because the gain compensation may –15 –20 change the common-mode level of the signal. The dc offset of –25 –30 some modulators is common-mode level dependent. Therefore, –35 –40 it is recommended that the gain adjustment be performed prior –45 to LO compensation. –50 –55 –60 LO FEEDTHROUGH COMPENSATION –65 –70 To achieve LO feedthrough compensation in a circuit, each –75 output of the two AUXDACs must be connected through a –80 –85 100 kΩ resistor to one side of the differential DAC output. See –90 –95 the Auxiliary DACS section for details of how to use AUXDACs. 447.5 449.0 450.0 451.0 452.5 The purpose of these connections is to drive a very small amount FREQUENCY (MHz) of current into the nodes at the quadrature modulator inputs, Figure 110. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single- Tone Signal at 450 MHz, No Gain or LO Compensation thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs. 5 0 To achieve LO feedthrough compensation, the user should start –5 –10 with the default conditions of the AUXDAC registers, and then –15 increment the magnitude of one or the other AUXDAC output –20 –25 voltages. While this is being done, the amplitude of the LO –30 –35 feedthrough at the quadrature modulator output should be –40 sensed. If the LO feedthrough amplitude increases, try either –45 –50 decreasing the output voltage of the AUXDAC being adjusted, –55 –60 or try adjusting the output voltage of the other AUXDAC. It –65 –70 may take practice before an effective algorithm is achieved. The –75 AD9714/AD9715/AD9716/AD9717 evaluation board can be –80 –85 used to adjust the LO feedthrough down to the noise floor, –90 –95 although this is not stable over temperature. 447.5 449.0 450.0 451.0 452.5 FREQUENCY (MHz) RESULTS OF GAIN AND OFFSET CORRECTION Figure 111. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single- The results of gain and offset correction can be seen in Figure 110 Tone Signal at 450 MHz, Gain and LO Compensation Optimized and Figure 111. Figure 110 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 111 shows the output spectrum after correction. The LO feedthrough spur at 450 MHz has been suppressed to the noise level. This result can be achieved by applying the correc- tion, but the correction must be repeated after a large change in temperature. Note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the DACs and quadrature modulators. Phase mismatch is frequency depen- dent; therefore, routines must be developed to adjust it if wideband signals are desired. Rev. A | Page 51 of 80 (dB) (dB) 07265-065 07265-064 AD9714/AD9715/AD9716/AD9717 To evaluate the ADL5370 on this board, the population of these MODIFYING THE EVALUATION BOARD TO same components should be reversed so that they are in the USE THE ADL5370 ON-BOARD QUADRATURE following positions: MODULATOR  JP55, JP56, JP76, JP82—soldered The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/  R13, R14, R52, R53—populated AD9716/AD9717 and the ADL5370 provide an easy-to-  R50, R57, T1, T2—unpopulated interface DAC/modulator combination that can be easily The AUXDAC outputs can be connected to Test Point TP44 and characterized on the evaluation board. Solderable jumpers Test Point TP45 if LO feedthrough compensation is necessary. can be configured to evaluate the single-ended or differential outputs of the AD9714/AD9715/AD9716/AD9717. This setup is the default configuration from the factory and consists of the following population of the components:  JP55, JP56, JP76, JP82—unsoldered  R13, R14, R52, R53—unpopulated  R50, R57, T1, T2—populated Rev. A | Page 52 of 80 AD9714/AD9715/AD9716/AD9717 EVALUATION BOARD SHEMATICS AND ARTWORK SCHEMATICS Figure 112. Power Supplies and Filters Rev. A | Page 53 of 80 JP6 5VGND;3,4,5 L1 SMAEDGE CVDD 31 CVDD_IN LC1812 1 J2 BA EXC-CL4532U1 TP12 2 C14 0.1UF C2 0.1UF 2 CC0603 CC0603 ACASE CC0603 RED IN4 OUT5 10UF R2 4 5 C13 5V 100PF CVDD_IN 1UF EXC-CL4532U1 6.3V IN3 OUT6 76.8K C3 C10 TP14 C12 L5 3 6 BLK CC0603 5V SD U2 FB LC1812 2 7 5V C 1UF GND NC R8 64.9K 1 8 2 ADP3334 L2 5V 5V A B RC0603 13 DVDD DVDD_IN LC1812 JP22 EXC-CL4532U1 78.7K R5 TP13 3.3 1.8 0.1UF C4 0.1UF CC0603 ACASE 10UF CC0603 RED RC0603 EXC-CL4532U1 5VGND;3,4,5 6.3V SMAEDGE 5V C7 C6 TP4 JP10 L6 3 1 BLK 1 J4 BA LC1812 5V C17 2 2 IN3 CC0603 OUT5 R23 L3 4 5 C19 5V 100PF 1UF DVDD_IN IN4 76.8K AVDD OUT6 AVDD_IN LC1812 C18 3 6 EXC-CL4532U1 CC0603 5V SD TP5 U4 FB 0.1UF C5 0.1UF 2 7 1UF CC0603 ACASE CC0603 RED GND R12 64.9K 10UF NC EXC-CL4532U1 1 8 2 ADP3334 6.3V 5V 5V C9 C8 TP6 A B L7 1 3 BLK JP26 LC1812 78.7K R10 5V 3.3 1.8 RC0603 L4 5VGND;3,4,5 5V SMAEDGE JP54 DVDDX DVDDX_IN LC1812 31 1 EXC-CL4532U1 J5 TP8 B A 0.1UF C1 0.1UF C20 2 CC0603 ACASE CC0603 RED 10UF 2 EXC-CL4532U1 IN3 CC0603 OUT5 4 5 R31 6.3V C30 5V 100PF C15 C16 TP9 1UF AVDD_IN L12 IN4 OUT6 76.8K BLK C21 3 6 LC1812 CC0603 5V 5V SD FB U6 2 7 1UF GND R30 64.9K NC 1 8 L16 2 ADP3334 5V 5V CVDDX A B RC0603 CVDDX_IN LC1812 13 EXC-CL4532U1 JP29 TP24 C57 0.1UF 0.1UF 78.7K R29 3.3 1.8 ACASE RED CC0603 10UF CC0603 EXC-CL4532U1 RC0603 6.3V 5VGND;3,4,5 C61 C60 TP23 L19 SMAEDGE 5V JP15 BLK 3 1 1 LC1812 J8 5V B A C C31 2 2 IN3 OUT5 CC0603 R36 4 5 C38 5V 100PF 1UF DVDDX_IN IN4 OUT6 76.8K CVDDX_IN C37 3 6 CC0603 5V 5VGND;3,4,5 SD FB U7 2 7 SMAEDGE 1UF GND NC R32 64.9K 2 1 1 8 2 J11 B A ADP3334 5V 5V 31 A B RC0603 C86 1 3 JP78 2 JP88 CC0603 IN4 OUT5 R25 4 5 C89 5V 3.3 1.8 100PF 1UF 78.7K R3 IN3 OUT6 76.8K C88 3 6 CC0603 SD U11 FB RC0603 2 7 1UF 5V GND NC R92 64.9K 1 8 2 5VINT 5V ADP3334 5V A B RC0603 13 5VGND;3,4,5 5VIN JP89 SMAEDGE JP28 JP3 3.3 1.8 1 78.7K R4 J3 5VUSB RC0603 2 5V 5V CC0603 CC0603 CC0603 CC0603 RC0603 RC0603 RC0603 RC0603 CC0603 RC0603 07265-184 AD9714/AD9715/AD9716/AD9717 RP1 DNP 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 RNETCTS743-8 Figure 113. Digital Inputs Rev. A | Page 54 of 80 TP22 TP10 WHT BLK R6 RC0402 0 2 MSB No stub Match length to path from S5 to Pin 18 1 of U1. RP3 22 116 PCB Bottom Side 2 15 DB13X DB13 1 2 3 14 DB12X DB12 DB13X 3 4 4 13 DB11X DB11 DB12X 5 6 5 12 DB11X DB10X DB10 7 8 6 11 DB9X DB9 DB10X 9 10 7 10 DB8X DB8 DB9X 11 12 8 9 DB8X DB7X DB7 RNETCTS743-8 13 14 DB7X 15 16 RP4 DB6X 22 17 18 1 16 DB5X DB6X DB6 19 20 215 DB5X DB5 DB4X 21 22 3 14 DB4X DB4 DB3X 23 24 4 13 DB2X DB3X DB3 25 26 5 12 DB2X DB2 DB1X 27 28 6 11 DB1X DB1 DB0X 29 30 7 10 DB0X DB0 31 32 8 9 RNETCTS743-8 33 34 35 36 37 38 39 40 SSW-120-02-SM-D-R-A 1 J1 DIGITAL INPUTS 1 IN J1 AND RP3, THE MSB IS DB13, DB11, DB9, OR DB7, DEPENDING ON THE PART. HEADER RIGHT ANGLE FEMALE RP5 DNP 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 RNETCTS743-8 07265-185 AD9714/AD9715/AD9716/AD9717 Figure 114. Clock Input and DUT Rev. A | Page 55 of 80 = SHARE COMPONENT PAD. DVDDX CLKIN C59 00.1UF 1NF DCLKIO ACASE 4.7UF CC0402 CC0402 OUT0R R33 DNP R122 R64 R65 C55 C56 00 0 6.3V OUT2R DVDDX RC0402 RC0402 RC0402 CVDDX R66 R70 R34 TP25 DNP TP26 10K DGND;3 0 WHT WHT DVDDX;5 C34 00.1UF DNP R110 0 R72 24 S5 S11 00.1UF 00.01UF RC0402 RC0402 R108 CC0402 CC0402 SN74LVC1G34DCK CGND;3,4,5 DGND;3,4,5 10K C77 C78 R68 R17 C101 00.1UF U8 C R71 DNP DNP CC 10K C R67 U12 R107 RC0402 1 4 0 DNP EN OVCC Keep parallel R18 49.9 23 GND OUT C R69 OSC-S1703 C DNP R46 0 RC0402 R47 0 R48 0 RC0402 RC0402 C CVDD DNP R80 1 40 DB11 DB11 DB12 DB12 REFIO RC0402 2 39 DB10 DB10 DB13 (MSB) DB13 0.1UF 0.01UF DVDD 3 38 CC0603 CC0603 DB9 DB9 CS/PWRDN SLEEP-CSB 4 37 JP11 C27 C28 DB8 DB8 SDIO/FORMAT MODE-SDIO 5 36 DVDDIO DVDDIO SCLK/CLKMD RMODE-SCLK TP30 6 35 SW1 DVSS RESET/PINMD WHT 7 34 42 TP3 AVDD DVDD REFIO 8 33 WHT 3 1 DB7 DB7 FSADJI/AUXI FSADJ1 C11 9 32 1UF DB6 DB6 FSADJQ/AUXQ FSADJ2 0.1UF 0.01UF 0.1UF CC0603 DGND;5 10 31 CC0603 CC0603 CC0603 DB5 DB5 CMLI IOTC C39 11 30 JP35 10K C26 C25 DB4 DB4 RLIN 12 29 DB3 DB3 IOUTN IOUTB 13 28 DB2 DB2 IOUTP IOUTA 14 27 40-LEAD LFCSP DB1 DB1 RLIP DVDD JP34 AD9717 15 26 DB0 (LSB) DB0 (LSB) AVDD AVDD 0 R19 16 25 DCLKIO DCLKIO AVSS IOTC IOT_CML RC0402 0.1UF 0.01UF 17 24 JP33 CC0603 CC0603 CVDD CVDD RLQP DNP R20 18 23 RC0402 C24 C23 CLKIN QOUTP QOUTA CLKIN AGND;41 19 22 CVSS QOUTN QOUTB 0 R21 20 21 QOTC CMLQ U1 RLQN QOTC QOT_CML RC0402 JP32 DNP R26 C THE AD9714/AD9715/AD9716 RC0402 CAN BE USED IN U1. RC0402 RC0402 CC0402 CC0402 RC0402 RC0402 RC0402 R7 RC0603 RC0402 RC0402 07265-186 AD9714/AD9715/AD9716/AD9717 RC0603 RC0805 RC0805 RC0603 RC0805 Figure 115. IOUT Network and FSADJ1 Rev. A | Page 56 of 80 TP32 OPAMPIN JP55 DNP D1P AGND;3,4,5 R11 0 R111 10-DNP S3 RC0603 0 R9 DNP DNP IOUTA RC0603 RC0603 R93 TP31 R118 WHT T8 TP33 ADTL1-12 6SP 1 JP56 DNP R57 34 5 2 453 PS D1N 4 3 1 6 T2 ADT9-1T AGND;3,4,5 R79 0 DNP 0 S4 RC0603 RC0603 IOUTB RC0603 R119 R35 100K R94 R37 R123 DNP R14 RC0603 0-DNP R13 WHT DNP DNP TP44 WHEN R13 AND R14 ARE NOT DNP, 499 IS RECOMMENDED IOT_CML C22 0.1UF R22 R15 CC0603 DNP 0-DNP TP40 TP39 C102 TP1 0.2NF DNP ORG RED WHT JP90 FSADJ1 N5V P5V S9 R113 499 AGND;3,4,5 10V C104 RC0402 R116 0 ACASE 10UF ACASE 10UF P5V C103 10V TP41 C106 TP34 OPAMPIN 0.1UF RC0402 BLK WHT R115 499 R1 R49 R51 7 R99 R98 8 +V RC0402 100K DNP 2 -IN 1 DIS DNP FB R114 15 32K 16K 8K ADA4899-1 C105 1UF 1 R97 OUT U13 R117 0 -V2 S12 0.1% 0.1% 0.1% RC0402 6 DNP -V1 3 DNP +IN REFIO 2 AGND;3,4,5 RC0402 5 DNP CC0603 CERAMIC 4 AGND;9 C95 0.1UF CC0603 C108 0.1UF C107 WHEN C95 IS NOT FSADJ resistors must have low TC DNP, 10pF TO 1nF IS RECOMMENDED N5V IOUT NETWORK AND FSADJ1 ERA6YEB323V, ERA6Y JP7 ERA6YEB323V, ERA6Y JP8 RC0603 ERA6YEB323V, ERA6Y JP9 RC0603 RC0603 JP12 RC0603 RC0603 RC0603 RC0603 CC0402 CC0603 CC0603 RC0603 CC0805 RC0603 RC0603 07265-187 AD9714/AD9715/AD9716/AD9717 RC0805 RC0805 RC0805 Figure 116. QOUT Network and FSADJ2 Rev. A | Page 57 of 80 OPAMPIN TP36 JP76 DNP D2P R38 0 WHEN R112 IS NOT DNP, R112 DNP 10 IS RECOMMENDED S6 RC0603 AGND;3,4,5 R105 0 R42 R120 DNP QOUTA DNP RC0603 RC0603 TP38 WHT T1 ADT9-1T TP37 16 JP82 DNP R50 4 3 D2N 453 P S 5 2 34 SP ADTL1-12 6 1 T5 AGND;3,4,5 R83 0 R106 0 R121 DNP S8 RC0603 QOUTB RC0603 RC0603 R56 R55 100k 0 R52 R53 DNP R124 DNP DNP RC0603 WHT WHEN R52 AND R53 ARE NOT TP45 DNP, 499 IS RECOMMENDED QOT_CML C48 0.1UF R54 R16 CC0603 0 DNP TP17 DNP WHT JP91 1 FSADJ2 S10 AGND;3,4,5 2 TP35 WHT R58 R59 R60 R102 R101 100K DNP 32K 16K 8K 0.1% 0.1% 0.1% R100 DNP DNP CC0603 C96 WHEN C96 IS NOT DNP, 10pF TO 1nF IS RECOMMENDED FSADJ resistors must have low TC QOUT NETWORK AND FSADJ2 ERA6YEB323V, ERA6Y JP21 RC0603 RC0603 ERA6YEB323V, ERA6Y JP16 RC0603 ERA6YEB323V, ERA6Y JP20 RC0603 RC0603 RC0603 JP77 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 07265-188 AD9714/AD9715/AD9716/AD9717 MLX-0532610571 Figure 117. SPI Port Rev. A | Page 58 of 80 5VUSB 0.1UF 0.1UF 0.1UF 0.1UF C32 CC0603 CC0603 CC0603 CC0603 10UF C99 C98 C97 C84 6.3V L15 EXC-CL3225U1 2 PIC18F4450 GND-4 5 1 44 RC7-RX-DT 5V MOSI RC6-TX-CK ID-X 4 2 43 RD4 D+ EN1 RC5-D+-VP pcb Top side 3 3 42 RD5 D- EN2 RC4-D--VM 2 4 41 RD6 RD3 5VUSB VBUS 1 5 40 RD7 P1 RD2 U3 6 39 VSS1 RD1 7 38 499 R63 AVDD1 5VGND;45 RD0 RC0403 8 37 VDD1 5VUSB VUSB 2 9 36 RB0-AN12-INT0 MISO RC2-CCP1 470NF 10 35 RB1-AN10-INT1 CC0603 D1 SCK RC1-T1OSI-UOE 11 34 1 C110 RB2-AN8-INT2-VMO LNJ312G8TRA SSEL1 RC0-TIOSO-T1CKI 12 33 RB3-AN9-VPO SSEL2 OSC2-CLKO-RA6 13 32 5V N31C OSC1-CLK1 MP1 0R82 1M R27 14 31 RB4-AN11-KBI0 VSS2 RC0402 CC0603 1 15 30 RB5-KBI1-PGM Y1 5VUSB AVSS 2 20.000MHZ 16 29 RB6-KBI2-PGC VDD2 5VUSB 3 3 17 28 RB7-KBI3-PGD AVDD2 5VGND;2 4 18 27 MCLR-VPP-RE3 RE2-AN7 10PF-1% 10PF-1% 5 19 26 RA0-AN0 CC0603 CC0603 RA0 RE1-AN6 0.1UF MP2 0 R62 20 25 C49 C33 RA1-AN1 CC0603 RE0-AN5 RC0402 21 24 C114 RA2-AN2-VREF- P3 RA5-AN4-HLVDIN 5V 22 23 pcb bottom side RA3-AN3-VREF+ RA4-T0CKI-RCV 5V TP2 TP7 R87 0 DNP BLK DVDD DVDDX 5VUSB 5VUSB 0.1UF 0.1UF 0.1UF 0.1UF RC1206 CC0603 CC0603 CC0603 CC0603 C100 C109 C111 C112 5V R43 0 MISO MOSI RC0402 TP18 1 1 14 14 VCCA VCCY VCCA VCCY WHT 22 R103 22 R28 2 13 2 13 Y1 A1 A1 Y1 MODE-SDO MISO SDIO MISO RC0402 22 R39 3 12 3 12 U5 U14 A2 Y2 TP19 A2 Y2 MODE-SDIO MOSI MOSI 22 R44 22 R40 4 WHT 4 11 11 Y3 RMODE-SCLK A3 SCK SCLK A3 Y3 SCK ADG3304 ADG3304 RC0402 RC0402 22 R45 22 R41 5 10 5 10 SLEEP-CSB A4 Y4 SSEL1 CSB A4 Y4 SSEL2 RC0402 6 9 6 9 NCA NCY TP20 NCA 7 WHT 7 8 8 GND EN GND EN EN1 EN2 S1 S3 GRN 07265-189 AD9714/AD9715/AD9716/AD9717 34 T4 2 SP 1 5 ETC1-1-13 Figure 118. Modulated Output Rev. A | Page 59 of 80 MOD_IP MOD_IN 4.7PF 7.5PF DNP 0 R73 CC0805 CC0805 CC0805 MOD_IP MOD_QN RC0603 C82 C92 T6 C81 MOD_QP VDDM 1.8UH DNP L10 L17 1 6 D1N LC1008 LC1008 PS NC=2,5 C52 C51 L11 L14 1.8UH DNP 3 4 C44 D1P DNP CC0402 CC0402 LC1008 LC1008 ADTL1-12 ACASE 1 24 10UF DNP 0.1UF 100PF COM1A QBBP 10V CC0805 CC0805 CC0805 2 23 0 R74 VDDM COM1B QBBN C80 C79 C91 MOD_IN 3 22 RC0603 VPS1A COM4B 4.7PF 7.5PF 4 21 VPS1B COM4A 5 20 C43 CC0402 CC0402 VPS1C IBBN C83 ACASE 6 19 10UF CC0402 C50 VPS1D IBBP C47 7 18 10V 100PF 100PF COM2A VPS5 0.1UF 8 17 LOIP VPS4 VDDM ADL5370 9 16 LOIN U9 VPS3 10 15 C90 COM2B VPS2B CC0402 11 14 C87 0.1UF COM3A VPS2A CC0402 12 13 CC0402 CC0402 COM3B VOUT 100PF 0 R75 AGND;25 4.7PF 7.5PF DNP MOD_QN RC0603 CC0805 CC0805 CC0805 C74 C75 C94 T3 VDDM 1.8UH DNP L8 L20 CC0402 1 6 D2N C72 LC1008 LC1008 C63 C41 PS NC=2,5 CC0402 CC0402 L9 L18 ACASE 1.8UH DNP 34 D2P 10UF 0.1UF 100PF LC1008 LC1008 ADTL1-12 AGND;3,4,5 AGND;3,4,5 10V SMAEDGE SMAEDGE DNP 1 1 CC0805 CC0805 CC0805 0 R78 J6 J7 MOD_QP C65 C64 C93 RC0603 2 2 4.7PF 7.5PF RED RED TP16 TP42 L13 VDDM VDDM_IN LC1812 EXC-CL4532U1 C35 0.1UF 0.1UF ACASE CC0402 22UF CC0402 BLK BLK 16V TP21 C36 C29 TP43 MODULATED OUTPUT R61 R24 RC0603 RC0603 1k 1k 100PF C53 100PF C54 100PF C73 07265-190 AD9714/AD9715/AD9716/AD9717 Figure 119. Clock Driver Chip Rev. A | Page 60 of 80 1 48 VS18 CVDDX DSYNC 2 47 DSYNCB VS17 CVDDX 3 46 CVDDX VS1 GND6 4.12K R81 4 45 CVDDX RSET VS2 RC0402 5 44 C CVDDX NC1 VS16 6 43 CVDDX VS3 GND5 7 42 OUT0 CLK2 8 41 OUT0B CLK2B C45 0.1UF 9 40 CGND;3,4,5 T9 CVDDX VS4 VS15 CVDDX 1 6 10 39 P S J10 VS14 CVDDX CLK1 2 5 11 38 GND4 CLK1B 3 3 4 12 37 FUNC GND3 R91 13 36 49.9 VS13 CVDDX STATUS JTX-4-10T+ C C 14 35 0 R88 12 D3 RMODE-SCLK OUT3 OUT0R 1:4 SCLK RC0402 C46 0.1UF 15 34 DNP R90 MODE-SDIO SDIO OUT3B 16 33 RC0402 MODE-SDO SDO VS12 CVDDX C 17 32 C SLEEP-CSB VS11 CVDDX CSB AD9512BCPZ 1.8K R77 1.8K R76 0 R89 18 31 CVDDX CVDDX VS5 OUT4 OUT2R RC0402 RC0402 RC0402 19 30 CGND;49 GND1 OUT4B 1NF DNP R109 20 29 CC0402 VS10 CVDDX OUT2B SW2 RC0402 C62 2 4 21 28 OUT2 VS9 CVDDX U10 C WHEN R90 AND R109 13 22 27 CVDDX VS6 OUT1 ARE NOT DNP, 49.9 C 23 26 IS RECOMMENDED C CGND;5 CVDDX OUT1B VS7 24 25 VS8 CVDDX GND2 C C 0R86 RA0 RC0402 CVDDX 0.1UF 0.1UF 0.1UF 0.1UF CC0402 CC0402 CC0402 CC0402 C42 C66 C67 C68 0.1UF 0.1UF 0.1UF 0.1UF CC0402 CC0402 CC0402 CC0402 C69 C70 C71 C76 0.1UF 0.1UF 0.1UF 0.1UF CC0402 CC0402 CC0402 CC0402 C113 C85 C58 C40 C CLOCK DRIVER CHIP RC0805 HSMS-281C CC0402 CC0402 07265-191 AD9714/AD9715/AD9716/AD9717 SILKSCREENS Figure 120. Layer 2, Ground Plane Rev. A | Page 61 of 80 07265-203 AD9714/AD9715/AD9716/AD9717 Figure 121. Layer 3, Power Plane Rev. A | Page 62 of 80 07265-204 AD9714/AD9715/AD9716/AD9717 Figure 122. Assembly—Primary Side Rev. A | Page 63 of 80 07265-205 AD9714/AD9715/AD9716/AD9717 Figure 123. Assembly—Secondary Side Rev. A | Page 64 of 80 07265-206 AD9714/AD9715/AD9716/AD9717 Figure 124. Solder Mask—Primary Side with Socket Rev. A | Page 65 of 80 07265-217 AD9714/AD9715/AD9716/AD9717 Figure 125. Solder Mask—Secondary Side Rev. A | Page 66 of 80 07265-207 AD9714/AD9715/AD9716/AD9717 Figure 126. Hard Gold Plated with Bumps and Socket Rev. A | Page 67 of 80 07265-208 AD9714/AD9715/AD9716/AD9717 Figure 127. Primary Side Paste Rev. A | Page 68 of 80 07265-209 AD9714/AD9715/AD9716/AD9717 Figure 128. Secondary Side Paste Rev. A | Page 69 of 80 07265-210 AD9714/AD9715/AD9716/AD9717 Figure 129. Silkscreen—Primary Side Rev. A | Page 70 of 80 07265-211 AD9714/AD9715/AD9716/AD9717 Figure 130. Silkscreen—Secondary Side Rev. A | Page 71 of 80 07265-212 AD9714/AD9715/AD9716/AD9717 Figure 131. Layer 1—Primary Side Rev. A | Page 72 of 80 07265-213 AD9714/AD9715/AD9716/AD9717 Figure 132. Layer 4—Secondary Side Rev. A | Page 73 of 80 07265-214 AD9714/AD9715/AD9716/AD9717 Figure 133. Immersion Gold, No Socket, No Bumps Rev. A | Page 74 of 80 07265-215 AD9714/AD9715/AD9716/AD9717 Figure 134. Solder Mask—Primary Side, No Socket Rev. A | Page 75 of 80 07265-216 AD9714/AD9715/AD9716/AD9717 BILL OF MATERIALS Table 18. Part No./ Qty Reference Designator Device Package Description Manufacturer 6 C1, C2, C4, C5, C32, C57 CAPSMDA ACASE 10 μF, 6.3 V capacitor 17 C3, C6, C7, C8, C9, C10, C11, CC0603 CC0603 0.1 μF capacitor C15, C16, C22, C24, C26, C27, C48, C60, C61, C107 11 C12, C14, C17, C18, C20, CC0603 CC0603 1 μF capacitor C21, C31, C37, C39, C86, C88 5 C13, C19, C30, C38, C89 CC0603 CC0603 100 pF capacitor 3 C23, C25, C28 CC0603 CC0603 0.01 μF capacitor 6 C29, C36, C47, C52, C72, C90 CC0402 CC0402 0.1 μF capacitor 2 C33, C49 CC0603 CC0603 10 pF, 1% capacitor 18 C34, C40, C42, C45, C46, CC0402 CC0402 0.1 μF capacitor C55, C58, C66, C67, C68, C69, C70, C71, C76, C77, C85, C101, C113 1 C35 CAPSMDA ACASE 22 μF,16 V capacitor 3 C41, C43, C44 CAPSMDB ACASE 10 μF, 10 V capacitor 8 C50, C51, C53, C54, C63, CC0402 CC0402 100 pF capacitor C73, C83, C87 2 C56, C62 CC0402 CC0402 1 nF capacitor 1 C59 CAPSMDA ACASE 4.7 μF, 6.3 V capacitor 4 C64, C75, C79, C82 CC0805 CC0805 7.5 pF, 1% capacitor 4 C65, C74, C80, C81 CC0805 CC0805 4.7 pF, 1% capacitor 1 C78 CC0402 CC0402 0.01 μF capacitor 11 C84, C97, C98, C99, C100, CC0603 CC0603 0.1 μF capacitor C106, C108, C109, C111, C112, C114 4 C91, C92, C93, C94 CC0805 CC0805 DNP 2 C95, C96 CC0603 CC0603 DNP 1 C102 CC0402 CC0402 0.2 nF capacitor 2 C103, C104 CAPSMDA ACASE 10 μF, 10 V capacitor 1 C105 CC0805 CC0805 1 μF ceramic capacitor 1 C110 CC0603 CC0603 470 nF capacitor 1 D1 Panasonic LNJ312G8TRA 1.6 mm x 0.8 mm LED-SMD-TSS-GRN LNJ312G8TRA 1 D3 HSMS-281C SOT323-3 HSMS-281C HSMS-281C 1 J1 Samtec 40-pin through 40-pin right angle SSW-120-02-SM-D-RA/ SSW-120-02-SM-D-RA hole header female Samtec 6 J2, J3, J4, J5, J8, J11 SMAEDGE SMAEDGE DNP SMA connector edge right angle 2 J6, J7 SMAEDGE SMAEDGE SMA connector edge right angle 5 J10, S3, S5, S6, S11 SMAUPA04 SMA200UP SMA connector RF 5-pin upright 5 S4, S8, S9, S10, S12 SMAUPA04 SMA200UP DNP 11 JP3, JP7, JP8, JP9, JP11, JP12, JPRBLK02 JPRBLK02 2-pin jumper header JP16, JP20, JP21, JP28, JP77 10 JP6, JP10, JP15, JP22, JP26, JPRBLK03 JPRBLK03 3-pin jumper header JP29, JP54, JP78, JP88, JP89 10 JP32, JP33, JP34, JP35, JP55, JPRSLD02 JPRSLD02 Solder jumper JP56, JP76, JP82, JP90, JP91 Rev. A | Page 76 of 80 AD9714/AD9715/AD9716/AD9717 Part No./ Qty Reference Designator Device Package Description Manufacturer 11 L1, L2, L3, L4, L5, L6, L7, IND1812 LC1812 EXC-CL4532U1 EXC-CL4532U1 L12, L13, L16, L19 4 L8, L9, L10, L11 IND1008 LC1008 1.8 μH, 10% 4 L14, L17, L18, L20 IND1008 LC1008 DNP 1 L15 IND1210 LC1210 EXC-CL3225U1 EXC-CL3225U1 1 P1 USB-MINIB USB-MINIB USB mini 5-pin 1 P3 Molex 0532610571 Molex 0532610571 1.25 mm, 5-pin wire- 0532610571/ to-board connector Molex 2 R1, R58 RC0805 RC0805 32 kΩ, 0.1% resistor ERA6YEB323V, ERA6Y 5 R2, R23, R25, R31, R36 RC0603 RC0603 76.8 kΩ resistor 5 R3, R4, R5, R10, R29 RC0603 RC0603 78.7 kΩ resistor 6 R6, R33, R34, R64, R65, R67 RC0402 RC0402 0 Ω resistor 7 R17, R66, R68, R69, R107, RC0402 RC0402 DNP R110, R122 1 R7 RC0603 RC0603 10 kΩ resistor 5 R8, R12, R30, R32, R92 RC0603 RC0603 64.9 kΩ resistor 8 R9, R37, R42, R56, R97, R98, RC0603 RC0603 DNP R100, R101 4 R11, R38, R79, R83 RC0603 RC0603 0 Ω resistor 4 R13, R14, R52, R53 RC0603 RC0603 DNP 10 R15, R16, R123, R124, RC0603 RC0603 0 Ω resistor R73 to R75, R78, R93, R94, R105, R106 6 R22, R54, R118, R119, RC0603 RC0603 DNP R120, R121 1 R18 RC0402 RC0402 49.9 Ω resistor 2 R19, R21 RC0402 RC0402 0 Ω resistor 3 R20 , R26, R80 RC0402 RC0402 DNP 2 R24, R61 RC0603 RC0603 1 kΩ resistor 1 R27 RC0603 RC0603 1 MΩ resistor 7 RC0402 RC0402 22 Ω resistor R28, R39, R40, R41, R44, R45, R103 4 R35, R55, R99, R102 RC0603 RC0603 100 kΩ resistor 1 R43 RC0402 RC0402 0 Ω resistor 8 R46, R47, R48, R62, R82, RC0402 RC0402 0 Ω resistor R86, R116, R117 2 R49, R59 RC0805 RC0805 16 kΩ, 0.1% resistor ERA6YEB323V, ERA6Y 2 R50, R57 RC0603 RC0603 453 Ω resistor 2 R51, R60 RC0805 RC0805 8 kΩ, 0.1% resistor ERA6YEB323V, ERA6Y 3 R63, R113, R115 RC0402 RC0402 499 Ω resistor 3 R70, R71, R108 RC0402 RC0402 10 kΩ resistor 1 R72 RC0402 RC0402 25 Ω resistor 2 R76, R77 RC0402 RC0402 1.8 kΩ resistor 1 R81 RC0402 RC0402 4.12 kΩ resistor 1 R87 RC1206 RC1206 0 Ω resistor 2 R88, R89 RC0402 RC0402 0 Ω resistor 2 R90, R109 RC0402 RC0402 DNP 1 R91 RC0805 RC0805 49.9 Ω resistor 2 R111, R112 RC0603 RC0603 DNP 1 R114 RC0402 RC0402 15 Ω resistor 2 RP1, RP5 RNETCTS743-8 RNETCTS743-8 DNP Rev. A | Page 77 of 80 AD9714/AD9715/AD9716/AD9717 Part No./ Qty Reference Designator Device Package Description Manufacturer 2 RP3, RP4 RNETCTS743-8 RNETCTS743-8 22 Ω resistor 2 SW1, SW2 KEYBDSWG OMRONB3SG B3S-1100 push-button 4 T1, T2, T3, T6 ADTL1-12 MINI_CD542 DNP 1 T4 ETC1-1-13 SM-22 M/A COM ETC1-1-13 ETC1-1-13/ M/A-COM 2 T5, T8 ADT9-1T MINI_CD542 ADT9-1T ADT9-1T/ Mini-Circuits 1 T9 JTX-4-10T MINI_BH292 JTX-4-10T+ JTX-4-10T/ Mini-Circuits 16 TP1, TP3, TP17, TP18, LOOPMINI LOOPMINI White test point TP19, TP20, TP22, TP25, TP26, TP30, TP31, TP34, TP35, TP38, TP44, TP45 4 TP32, TP33, TP36, TP37 LOOPMINI LOOPMINI DNP 8 LOOPMINI LOOPMINI Red test point TP5, TP8, TP12, TP13, TP16, TP24, TP39, TP42 1 TP2 LOOPMINI LOOPMINI DNP 12 TP4, TP6, TP7, TP9, TP10, LOOPMINI LOOPMINI Black test point TP11, TP14, TP15, TP21, TP23, TP41, TP43 1 TP40 LOOPMINI LOOPMINI Orange test point 1 U1 40-lead LFCSP, AD9717 LFCSP040-CP1 40-lead LFCSP, AD9717/ AD9717 Analog Devices 5 U2, U4, U6, U7, U11 ADP3334 8-lead SOIC ADP3334 voltage ADP3334/ regulator Analog Devices 1 U3 USB-PIC18F4550-I/ML-ND QFN044P65MM-EP1 PIC18F4550, PIC18F4550 microchip USB port chip QFN44 8X8MM 2 U5, U14 ADG3304BRUZ 14-lead TSSOP ADG3304, ADG3304BRUZ/ 14-lead TSSOP Analog Devices 1 U8 74LVC1G34 SC70-05 SN74LVC1G34DCK, TI-DCK = TI buffer SC70_05 PKG 1 U9 ADL5370 LFCSP024P5MM-EP1 ADL5370ACPZ ADL5370ACPZ/ Analog Devices 1 U10 AD9512 LFCSP048-CP1 AD9512BCPZ AD9512BCPZ/ Analog Devices 1 U12 OSC-S1703 OSC-S1703 DNP 1 U13 8-lead SOIC, ADA4899-1 SOIC8-N-EP Op amp, ADA4899-1 ADA4899-1/ Analog Devices 1 Y1 ABM3B-20.000MHZ-10-1-U-T SMD 3.2 mm × 5.0 mm 20 MHz 300-8214-1-ND/ Digi-Key Rev. A | Page 78 of 80 AD9714/AD9715/AD9716/AD9717 OUTLINE DIMENSIONS 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 1 30 PIN 1 0.50 INDICATOR TOP 4.25 BSC 5.75 EXPOSED VIEW 4.10 SQ BSC SQ PAD (BOT TOM VIEW) 3.95 0.50 21 10 0.40 20 11 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.02 NOM 1.00 THE PIN CONFIGURATION AND 0.30 0.85 FUNCTION DESCRIPTIONS 0.20 REF COPLANARITY SECTION OF THIS DATA SHEET. 0.23 0.80 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 135. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9714BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9714BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9715BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9715BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9716BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9716BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9717BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9717BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 1 AD9714-EBZ Evaluation Board 1 AD9715-EBZ Evaluation Board 1 AD9716-EBZ Evaluation Board 1 AD9717-EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 79 of 80 072108-A AD9714/AD9715/AD9716/AD9717 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07265-0-3/09(A) Rev. A | Page 80 of 80