ANALOG DEVICES AD9709

8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD1/ DCOM1/ 8-bit dual transmit digital-to-analog converter (DAC) DVDD2 DCOM2 AVDD ACOM CLK1 125 MSPS update rate I OUTA1 1 1 Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc PORT1 LATCH DAC I OUTB1 Excellent gain and offset matching: 0.1% REFIO Fully independent or single-resistor gain control FSADJ1 REFERENCE WRT1/IQWRT FSADJ2 Dual port or interleaved data DIGITAL AD9709 GAINCTRL INTERFACE WRT2/IQSEL On-chip 1.2 V reference BIAS SLEEP GENERATOR Single 5 V or 3.3 V supply operation I Power dissipation: 380 mW @ 5 V 2 2 OUTA2 PORT2 LATCH DAC I Power-down mode: 50 mW @ 5 V OUTB2 48-lead LQFP MODE CLK2/IQ RESET Figure 1. APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound glitch energy and to maximize dynamic accuracy. Each DAC GENERAL DESCRIPTION provides differential current output, thus supporting single- 1 The AD9709 is a dual-port, high speed, 2-channel, 8-bit CMOS ended or differential applications. Both DACs can be DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage simultaneously updated and provide a nominal full-scale reference, and digital interface circuitry into a small 48-lead LQFP current of 20 mA. The full-scale currents between each DAC package. The AD9709 offers exceptional ac and dc performance are matched to within 0.1%. while supporting update rates of up to 125 MSPS. The AD9709 is manufactured on an advanced low-cost CMOS The AD9709 has been optimized for processing I and Q data in process. It operates from a single supply of 3.3 V or 5 V and communications applications. The digital interface consists of two consumes 380 mW of power. double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent PRODUCT HIGHLIGHTS of one another. Separate clocks control the update rate of the DACs. 1. The AD9709 is a member of a pin-compatible family of A mode control pin allows the AD9709 to interface to two separate dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. data ports, or to a single interleaved high speed data port. In inter- 2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance leaving mode, the input data stream is demuxed into its original DACs optimized for low distortion performance provide I and Q data and then latched. The I and Q data is then converted for flexible transmission of I and Q information. by the two DACs and updated at half the input data rate. 3. Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. The GAINCTRL pin allows two modes for setting the full-scale 4. Low Power. Complete CMOS dual DAC function operates current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set at 380 mW from a 3.3 V or 5 V single supply. The DAC independently using two external resistors, or IOUTFS for both full-scale current can be reduced for lower power operation, DACs can be set by using a single external resistor. See the Gain and a sleep mode is provided for low power idle periods. Control Mode section for important date code information on 5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V this feature. temperature-compensated band gap voltage reference. The DACs utilize a segmented current source architecture 6. Dual 8-Bit Inputs. The AD9709 features a flexible dual- combined with a proprietary switching technique to reduce port interface, allowing dual or interleaved input data. 1 Patent pending. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00606-001 AD9709 TABLE OF CONTENTS Features .............................................................................................. 1  Analog Outputs .......................................................................... 14  Applications ....................................................................................... 1  Digital Inputs .............................................................................. 15  Functional Block Diagram .............................................................. 1  DAC Timing ................................................................................ 15  General Description ......................................................................... 1  Sleep Mode Operation ............................................................... 18  Product Highlights ........................................................................... 1  Power Dissipation....................................................................... 18  Revision History ............................................................................... 2  Applying the AD9709 .................................................................... 19  Specif ica t ions ..................................................................................... 3  Output Configurations .............................................................. 19  DC Specifications ......................................................................... 3  Differential Coupling Using a Transformer ............................ 19  Dynamic Specifications ............................................................... 4  Differential Coupling Using an Op Amp ................................ 19  Digital Specifications ................................................................... 5  Single-Ended, Unbuffered Voltage Output ............................. 20  Absolute Maximum Ratings ............................................................ 6  Single-Ended, Buffered Voltage Output Configuration ........ 20  Thermal Resistance ...................................................................... 6  Power and Grounding Considerations .................................... 20  ESD Caution .................................................................................. 6  Applications Information .............................................................. 22  Pin Configuration and Function Descriptions ............................. 7  Quadrature Amplitude Modulation (QAM) Using the AD9709 ........................................................................................ 22  Typical Performance Characteristics ............................................. 8  CDMA ......................................................................................... 23  Terminology .................................................................................... 11  Evaluation Board ............................................................................ 24  Theory of Operation ...................................................................... 12  General Description ................................................................... 24  Functional Description .............................................................. 12  Schematics ................................................................................... 24  Reference Operation .................................................................. 13  Evaluation Board Layout ........................................................... 30  Gain Control Mode .................................................................... 13  Outline Dimensions ....................................................................... 32  Setting the Full-Scale Current ................................................... 13  Ordering Guide .......................................................................... 32  DAC Transfer Function ............................................................. 14  REVISION HISTORY 9/09—Rev. A to Rev. B Replaced Reference Control Amplifier Section with Setting Changes to Power and Grounding Considerations Section ..... 20 the Full-Scale Current Section ...................................................... 13 Changes to Schematics Section ..................................................... 24 Changes to DAC Transfer Function Section............................... 14 Changes to Evaluation Board Layout Section ............................. 30 Changes to Interleaved Mode Timing Section ........................... 16 Added Figure 28 ............................................................................. 16 1/08—Rev. 0 to Rev. A Changes to Power and Grounding Considerations Section ..... 20 Updated Format .................................................................. Universal Changes to Figure 44 ...................................................................... 22 Changed Single Supply Operation to 5 V or 3.3 V ........ Universal Deleted Figure 43 ............................................................................ 17 Changes to Figure 1 .......................................................................... 1 Changes to CDMA Section ........................................................... 23 Added Timing Diagram Section .................................................... 5 Changes to Figure 45 Caption ...................................................... 23 Changes to Figure 3 and Table 6 ..................................................... 7 Changes to Figure 46 ...................................................................... 24 Change to Figure 12 ......................................................................... 9 Changes to Figure 48 ...................................................................... 26 Changes to Figure 18 to Figure 20 ................................................ 10 Updated Outline Dimensions ....................................................... 30 Changes to Functional Description Section ............................... 13 Changes to Ordering Guide .......................................................... 30 Changes to Reference Operation Section .................................... 13 Changes to Figure 23 and Figure 24 ............................................. 13 5/00—Revision 0: Initial Version Changes to Gain Control Mode Section ...................................... 13 Rev. B | Page 2 of 32 AD9709 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 8 Bits 1 DC ACCURACY Integral Linearity Error (INL) −0.5 ±0.1 +0.5 LSB Differential Nonlinearity (DNL) −0.5 ±0.1 +0.5 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 +1 +5 % of FSR Gain Match T = 25°C −0.3 ±0.1 +0.3 % of FSR A TMIN to TMAX −1.6 +1.6 % of FSR TMIN to TMAX −0.14 +0.14 dB 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range −1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ Small-Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 V Analog Supply Current (IAVDD) 71 75 mA 4 Digital Supply Current (IDVDD) 5 7 mA 5 Digital Supply Current (IDVDD) 15 mA Supply Current Sleep Mode (I) 8 12 mA AVDD 4 Power Dissipation (5 V, I = 20 mA) 380 410 mW OUTFS 5 Power Dissipation (5 V, IOUTFS = 20 mA) 420 450 mW 6 Power Dissipation (5 V, IOUTFS = 20 mA) 450 mW 7 Power Supply Rejection Ratio —AVDD −0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio —DVDD1, DVDD2 −0.025 +0.025 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f = 25 MSPS and f = 1.0 MHz. CLK OUT 5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz. 6 Measured as unbuffered voltage output with I = 20 mA and R = 50 Ω at I and I , f = 100 MSPS, and f = 40 MHz. OUTFS LOAD OUTA OUTB CLK OUT 7 ±10% power supply variation. Rev. B | Page 3 of 32 AD9709 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLK) 125 MSPS 1 Output Settling Time (tST) to 0.1% 35 ns Output Propagation Delay (t) 1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (90% to 10%) 2.5 ns Output Noise (IOUTFS = 20 mA) 50 pA/√Hz Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 100 MSPS, f = 1.00 MHz CLK OUT 0 dBFS Output 63 68 dBc –6 dBFS Output 62 dBc –12 dBFS Output 56 dBc –18 dBFS Output 50 dBc fCLK = 65 MSPS, fOUT = 1.00 MHz 68 dBc f = 65 MSPS, f = 2.51 MHz 68 dBc CLK OUT f = 65 MSPS, f = 5.02 MHz 66 dBc CLK OUT fCLK = 65 MSPS, fOUT = 14.02 MHz 60 dBc fCLK = 65 MSPS, fOUT = 25 MHz 50 dBc fCLK = 125 MSPS, fOUT = 25 MHz 63 dBc f = 125 MSPS, f = 40 MHz 55 dBc CLK OUT Signal to Noise and Distortion Ratio f = 50 MHz, f = 1 MHz 50 dB CLK OUT Total Harmonic Distortion fCLK = 100 MSPS, fOUT = 1.00 MHz −67 −63 dBc fCLK = 50 MSPS, fOUT = 2.00 MHz −63 dBc f = 125 MSPS, f = 4.00 MHz −63 dBc CLK OUT f = 125 MSPS, f = 10.00 MHz −63 dBc CLK OUT Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 58 dBc –6 dBFS Output 51 dBc –12 dBFS Output 46 dBc –18 dBFS Output 41 dBc Channel Isolation fCLK = 125 MSPS, fOUT = 10 MHz 85 dBc fCLK = 125 MSPS, fOUT = 40 MHz 77 dBc 1 Measured single-ended into 50 Ω load. Rev. B | Page 4 of 32 AD9709 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (t) 1.5 ns H Latch Pulse Width (t , t) 3.5 ns LPW CPW Timing Diagram See Table 3 and the DAC Timing section for more information about the timing specifications. t t S H DATA IN (WRT2) (WRT1/IQWRT) t LPW (CLK2) (CLK1/IQCLK) t CPW I OUTA OR I OUTB t PD Figure 2. Timing for Dual and Interleaved Modes Rev. B | Page 5 of 32 00606-002 AD9709 ABSOLUTE MAXIMUM RATINGS Table 4. THERMAL RESISTANCE With Parameter Respect To Rating θ is specified for the worst-case conditions, that is, a device JA AVDD ACOM −0.3 V to +6.5 V soldered in a circuit board for surface-mount packages. DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V Table 5. Thermal Resistance ACOM DCOM1/DCOM2 −0.3 V to +0.3 V Package Type θ Unit JA AVDD DVDD1/DVDD2 −6.5 V to +6.5 V 48-Lead LQFP 91 °C/W MODE, CLK1/IQCLK, DCOM1/DCOM2 −0.3 V to DVDD1/ CLK2/IQRESET, DVDD2 + 0.3 V WRT1/IQWRT, ESD CAUTION WRT2/IQSEL Digital Inputs DCOM1/DCOM2 −0.3 V to DVDD1/ DVDD2 + 0.3 V I /I , ACOM −1.0 V to AVDD + 0.3 V OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ACOM −0.3 V to AVDD + 0.3 V FSADJ2 GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V Junction Temperature 150°C Storage Temperature −65°C to +150°C Range Lead Temperature 300°C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 6 of 32 AD9709 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 DB7P1 (MSB) 1 36 NC PIN 1 DB6P1 2 INDICATOR 35 NC DB5P1 3 34 NC 4 33 DB4P1 NC 5 32 DB3P1 NC AD9709 6 31 DB2P1 NC TOP VIEW 7 DB1P1 (Not to Scale) 30 DB0P2 (LSB) DB0P1 8 29 DB1P2 NC 9 28 DB2P2 10 27 DB3P2 NC 11 26 DB4P2 NC 12 25 DB5P2 NC 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 DB7P1 to DB0P1 Data Bit Pins (Port 1) 9 to 14, 31 to 36 NC No Connection 15, 21 DCOM1, DCOM2 Digital Common 16, 22 DVDD1, DVDD2 Digital Supply Voltage 17 WRT1/IQWRT Input Write Signal for Port 1 (IQWRT in Interleaving Mode) 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode) 20 WRT2/IQSEL Input Write Signal for Port 2 (IQSEL in Interleaving Mode) 23 to 30 DB7P2 to DB0P2 Data Bit Pins (Port 2) 37 SLEEP Power-Down Control Input 38 ACOM Analog Common 39, 40 I , I Port 2 Differential DAC Current Outputs OUTA2 OUTB2 41 FSADJ2 Full-Scale Current Output Adjust for DAC2 42 GAINCTRL Master/Slave Resistor Control Mode. 43 REFIO Reference Input/Output 44 FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 I , I Port 1 Differential DAC Current Outputs OUTB1 OUTA1 47 AVDD Analog Supply Voltage 48 MODE Mode Select (1 = dual port, 0 = interleaved) Rev. B | Page 7 of 32 NC MODE NC AVDD DCOM1 I OUTA1 DVDD1 I OUTB1 FSADJ1 WRT1/IQWRT CLK1/IQCLK REFIO CLK2/IQRESET GAINCTRL WRT2/IQSEL FSADJ2 I DCOM2 OUTB2 I DVDD2 OUTA2 DB7P2 (MSB) ACOM DB6P2 SLEEP 00606-003 AD9709 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist, unless otherwise noted. 75 75 f = 25MSPS 70 70 CLK 0dBFS 65 65 f = 5MSPS CLK –6dBFS 60 60 f = 65MSPS 55 CLK 55 –12dBFS f = 125MSPS CLK 50 50 45 45 0.1 1 10 100 0 5 10 15 20 25 30 35 f (MHz) f (MHz) OUT OUT Figure 4. SFDR vs. f @ 0 dBFS Figure 7. SFDR vs. f @ 65 MSPS OUT OUT 75 75 70 70 0dBFS 0dBFS 65 65 –6dBFS –6dBFS 60 60 –12dBFS –12dBFS 55 55 50 50 45 45 0 1020 3040506070 0 0.5 1.0 1.5 2.0 2.5 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. f @ 125 MSPS Figure 5. SFDR vs. f @ 5 MSPS OUT OUT 75 75 70 70 I = 20mA OUTFS 0dBFS 65 65 –6dBFS 60 60 I = 10mA OUTFS 55 55 I = 5mA OUTFS –12dBFS 50 50 45 45 02468 10 12 0 5 10 15 20 25 30 35 f (MHz) OUT f (MHz) OUT Figure 6. SFDR vs. f @ 25 MSPS OUT Figure 9. SFDR vs. f and I @ 65 MSPS and 0 dBFS OUT OUTFS Rev. B | Page 8 of 32 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00606-007 00606-006 00606-005 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00606-010 00606-009 00606-008 AD9709 75 70 5MSPS/0.46MHz 70 65 65 10MSPS/0.91MHz 60 60 I = 20mA 55 OUTFS 25MSPS/2.27MHz 55 65MSPS/5.91MHz 50 50 45 I = 5mA OUTFS 45 125MSPS/11.37MHz I = 10mA OUTFS 40 40 –25 –22 –19 –16 –13 –10 –7 –4 –1 2 0 20 40 60 80 100 120 140 A (dBFS) f (MSPS) OUT CLK Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11 Figure 13. SINAD vs. f and I @ f = 5 MHz and 0 dBFS CLK OUTFS OUT 75 0.06 0.04 70 5MSPS/1.0MHz 0.02 65 0 60 –0.02 55 125MSPS/5.0MHz –0.04 10MSPS/2.0MHz 50 –0.06 65MSPS/13.0MHz 45 –0.08 25MSPS/5.0MHz 40 –0.10 –25 –20 –15 –10 –5 0 0 32 64 96 128 160 192 224 256 A (dBFS) CODE OUT Figure 11. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5 Figure 14. Typical INL 75 0.07 0.06 70 0.965MHz/1.035MHz @ 7MSPS 0.05 65 0.04 60 0.03 55 0.02 16.9MHz/19.1MHz @ 125MSPS 50 0.01 8.8MHz/9.8MHz @ 65MSPS 45 0 3.3MHz/3.4MHz @ 25MSPS 40 –0.01 –25 –20 –15 –10 –5 0 0 50 100 150 200 250 A (dBFS) CODE OUT Figure 12. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7 Figure 15. Typical DNL Rev. B | Page 9 of 32 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00606-013 00606-012 00606-011 DNL (LSBs) INL (LSBs) SINAD (dBc) 00606-016 00606-015 00606-014 AD9709 75 0 –10 70 f = 10MHz OUT –20 65 –30 f = 25MHz OUT –40 60 f = 40MHz OUT –50 55 –60 f = 60MHz OUT –70 50 –80 45 –90 –50 –30 –10 10 30 50 70 90 06 10 20 30 40 500 TEMPERATURE (°C) FREQUENCY (MHz) Figure 16. SFDR vs. Temperature @ f = 125 MSPS, 0 dBFS Figure 19. Dual-Tone SFDR @ f = 125 MSPS CLK CLK 0 0.05 1.0 –10 –20 GAIN ERROR 0.03 0.5 –30 OFFSET ERROR –40 0 0 –50 –60 –0.03 –0.5 –70 –80 –0.05 –1.0 –90 –40 –20 0 20 40 60 80 06 10 20 30 40 500 TEMPERATURE (°C) FREQUENCY (MHz) Figure 17. Gain and Offset Error vs. Temperature @ f = 125 MSPS Figure 20. Four-Tone SFDR @ f = 125 MSPS CLK CLK 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 06 10 20 30 40 500 FREQUENCY (MHz) Figure 18. Single-Tone SFDR @ f = 125 MSPS CLK Rev. B | Page 10 of 32 OFFSET ERROR (%FS) SFDR (dBc) SFDR (dBm) 00606-019 00606-017 GAIN ERROR (%FS) 00606-018 SFDR (dBm) SFDR (dBm) 00606-021 00606-020 AD9709 TERMINOLOGY Temperature Drift Linearity Error (Integral Nonlinearity or INL) Temperature drift is specified as the maximum change from the Linearity error is defined as the maximum deviation of the ambient (25°C) value to the value at either TMIN or TMAX. For offset actual analog output from the ideal output, determined by a and gain drift, the drift is reported in part per million (ppm) of straight line drawn from zero to full-scale. full-scale range (FSR) per degree Celsius. For reference drift, the Differential Nonlinearity (DNL) drift is reported in ppm per degree Celsius (pm/°C). DNL is the measure of the variation in analog value, normalized Power Supply Rejection (PSR) to full scale, associated with a 1 LSB change in digital input code. PSR is the maximum change in the full-scale output as the Monotonicity supplies are varied from nominal to minimum and maximum A DAC is monotonic if the output either increases or remains specified voltages. constant as the digital input increases. Settling Time Offset Error Settling time is the time required for the output to reach and Offset error is the deviation of the output current from the ideal of remain within a specified error band about its final value, zero. For I , 0 mA output is expected when the inputs are all 0s. OUTA measured from the start of the output transition. For I , 0 mA output is expected when all inputs are set to 1s. OUTB Glitch Impulse Gain Error Asymmetrical switching times in a DAC give rise to undesired Gain error is the difference between the actual and ideal output output transients that are quantified by a glitch impulse. It is spans. The actual span is determined by the output when all specified as the net area of the glitch in picovolts per second (pV-s). inputs are set to 1s minus the output when all inputs are set to 0s. Spurious-Free Dynamic Range Output Compliance Range The difference, in decibels (dB), between the rms amplitude of The output compliance range is the range of allowable voltage at the output signal and the peak spurious signal over the specified the output of a current-output DAC. Operation beyond the bandwidth. maximum compliance limits may cause either output stage Total Harmonic Distortion (THD) saturation or breakdown resulting in nonlinear performance. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Rev. B | Page 11 of 32 AD9709 THEORY OF OPERATION 5V CLK1/IQCLK CLK2/IQRESET SLEEP AVDD Mini-Circuits TO HP3589A CLK AD9709 T1-1T OR EQUIVALENT DIVIDER FSADJ1 PMOS SPECTRUM/ I OUTA1 50Ω R 1 CURRENT NETWORK SET SEGMENTED REFIO SOURCE ANALYZER 2kΩ LSB I SWITCHES FOR ARRAY OUTB1 SWITCH DAC1 DAC1 0.1µF LATCH PMOS 50Ω I OUTA2 CURRENT FSADJ2 SEGMENTED SOURCE LSB SWITCHES FOR I ARRAY OUTB2 R 2 SWITCH SET DAC2 DAC2 2kΩ LATCH MODE MULTIPLEXING LOGIC 1.2V REF DVDD1/ 5V DVDD2 WRT1/ DCOM1/ CHANNEL 1 LATCH CHANNEL 2 LATCH GAINCTRL IQWRT DCOM2 ACOM PORT 1 PORT 2 WRT2/ IQSEL DVDD1/DVDD2 50Ω DCOM1/DCOM2 DIGITAL RETIMED CLOCK OUTPUT* DATA LECROY 9210 TEKTRONIX *AWG2021 CLOCK RETIMED SUCH THAT PULSE AWG2021 DIGITAL DATA TRANSITIONS ON FALLING GENERATOR WITH OPTION 4 EDGE OF 50% DUTY CYCLE CLOCK. Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 5V CLK1/IQCLK CLK2/IQRESET AVDD SLEEP V = V A – V B R 1 CLK DIFF OUT OUT SET DIVIDER 2kΩ FSADJ1 PMOS V 1A I OUT OUTA1 CURRENT I 1 REF 0.1µF SEGMENTED REFIO SOURCE LSB V 1B SWITCHES FOR I OUT R 1A ARRAY OUTB1 L SWITCH DAC1 DAC1 50Ω LATCH R 1B L PMOS V 2A R 2 50Ω SET I OUT CURRENT OUTA2 2kΩ FSADJ2 SEGMENTED SOURCE LSB V 2B R 2A SWITCHES FOR I OUT ARRAY OUTB2 L I 2 DAC2 SWITCH REF DAC2 50Ω LATCH R 2B L DVDD1/ 50Ω 5V MULTIPLEXING LOGIC DVDD2 AD9709 1.2V REF ACOM CHANNEL 1 LATCH CHANNEL 2 LATCH DCOM1/ DCOM2 GAINCTRL WRT1/ PORT 1 PORT 2 WRT2/ MODE IQWRT IQSEL DIGITAL DATA INPUTS Figure 22. Simplified Block Diagram All of these current sources are switched to one of the two FUNCTIONAL DESCRIPTION output nodes (that is, IOUTA or IOUTB) via the PMOS differential Figure 22 shows a simplified block diagram of the AD9709. The current switches. The switches are based on a new architecture AD9709 consists of two DACs, each one with its own independent that drastically improves distortion performance. This new digital control logic and full-scale output current control. Each switch architecture reduces various timing errors and provides DAC contains a PMOS current source array capable of providing matching of complementary drive signals to the inputs of the up to 20 mA of full-scale current (I ). OUTFS differential current switches. The array is divided into 31 equal currents that make up the five The analog and digital sections of the AD9709 have separate most significant bits (MSBs). The next four bits, or middle bits, power supply inputs (that is, AVDD and DVDD1/DVDD2) that th consist of 15 equal current sources whose value is 1/16 of an can operate independently over a 3.3 V to 5 V range. The digital MSB current source. The remaining LSB is a binary weighted section, which is capable of operating up to a 125 MSPS clock fraction of the middle bit current sources. Implementing the rate, consists of edge-triggered latches and segment decoding middle and lower bits with current sources instead of an R-2R logic circuitry. The analog section includes the PMOS current ladder enhances the dynamic performance for multitone or low sources, the associated differential switches, a 1.20 V band gap amplitude signals and helps maintain the high output impedance voltage reference, and two reference control amplifiers. of each DAC (that is, >100 kΩ). Rev. B | Page 12 of 32 00606-004 00606-022 AD9709 The full-scale output current of each DAC is regulated by GAIN CONTROL MODE separate reference control amplifiers and can be set from 2 mA The AD9709 allows the gain of each channel to be set to 20 mA via an external network connected to the full-scale independently by connecting one RSET resistor to FSADJ1 and adjust (FSADJ) pin. The external network in combination with another RSET resistor to FSADJ2. To add flexibility and reduce both the reference control amplifier and voltage reference system cost, a single R resistor can be used to set the gain of SET (VREFIO) sets the reference current (IREF), which is replicated to both channels simultaneously. the segmented current sources with the proper scaling factor. When GAINCTRL is low (that is, connected to analog ground), The full-scale current (IOUTFS) is 32 × IREF. the independent channel gain control mode using two resistors REFERENCE OPERATION is enabled. In this mode, individual RSET resistors should be The AD9709 contains an internal 1.20 V band gap reference. connected to FSADJ1 and FSADJ2. When GAINCTRL is high This can easily be overridden by a low noise external reference (that is, connected to AVDD), the master/slave channel gain with no effect on performance. REFIO serves as either an input control mode using one network is enabled. In this mode, a or output depending on whether the internal or an external single network is connected to FSADJ1, and the FSADJ2 pin reference is used. To use the internal reference, simply decouple must be left unconnected. the REFIO pin to ACOM with a 0.1 μF capacitor. The internal Note that only parts with a date code of 9930 or later have the reference voltage will be present at REFIO. If the voltage at master/slave gain control function. For parts with a date code REFIO is to be used elsewhere in the circuit, an external buffer before 9930, Pin 42 must be connected to AGND, and the part amplifier with an input bias current of less than 100 nA should operates in the two-resistor, independent gain control mode. be used. An example of the use of the internal reference is SETTING THE FULL-SCALE CURRENT shown in Figure 23. OPTIONAL Both of the DACs in the AD9709 contain a control amplifier EXTERNAL GAINCTRL AVDD REFERENCE that is used to regulate the full-scale output current (IOUTFS). The BUFFER AD9709 control amplifier is configured as a V-I converter, as shown in 1.2V REFERENCE REF SECTION Figure 23, so that its current output (IREF) is determined by the ratio REFIO CURRENT ADDITIONAL of the V and an external resistor, R . REFIO SET SOURCE EXTERNAL 0.1µF ARRAY LOAD FSADJ1/ V 256Ω REFIO FSADJ2 I = I ACOM REF REF 22nF R SET R SET The DAC full-scale current, I , is an output current 32 times OUTFS Figure 23. Internal Reference Configuration larger than the reference current, I . REF An external reference can be applied to REFIO as shown in I = 32× I OUTFS REF Figure 24. The external reference can provide either a fixed The control amplifier allows a wide (10:1) adjustment span of reference voltage to enhance accuracy and drift performance or IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and a varying reference voltage for gain control. Note that the 0.1 μF 625 μA. The wide adjustment range of IOUTFS provides several compensation capacitor is not required because the internal benefits. The first relates directly to the power dissipation of reference is overridden and the relatively high input impedance the AD9709, which is proportional to IOUTFS (refer to the Power of REFIO minimizes any loading of the external reference. Dissipation section). The second relates to the 20 dB adjustment, GAINCTRL AVDD which is useful for system gain control purposes. AD9709 AVDD 1.2V REFERENCE It should be noted that when the R resistors are 2 kΩ or less, SET REF SECTION the 22 nF capacitor and 256 Ω resistor shown in Figure 23 and REFIO EXTERNAL CURRENT REFERENCE Figure 24 are not required and the reference current can be set SOURCE ARRAY FSADJ1/ by the RSET resistors alone. For RSET values greater than 2 kΩ, the 256Ω FSADJ2 I ACOM REF 22 nF capacitor and 256 Ω resistor networks are required to 22nF R SET ensure the stability of the reference control amplifier(s). Regardless of the value of R , however, if the R resistor is SET SET Figure 24. External Reference Configuration located more than ~10 cm away from the pin, use of the 22 nF capacitor and 256 Ω resistor is recommended. Rev. B | Page 13 of 32 00606-024 00606-023 AD9709 differential amplifier configuration. The ac performance of the DAC TRANSFER FUNCTION AD9709 is optimum and specified using a differential Both DACs in the AD9709 provide complementary current out- transformer-coupled output in which the voltage swing at I OUTA puts, IOUTA and IOUTB. IOUTA provides a near full-scale current and IOUTB is limited to ±0.5 V. If a single-ended unipolar output output, IOUTFS, when all bits are high (that is, DAC CODE = 256) is desirable, IOUTA should be selected. while I , the complementary output, provides no current. OUTB The current output appearing at I and I is a function of The distortion and noise performance of the AD9709 can be OUTA OUTB both the input code and I and can be expressed as enhanced when it is configured for differential operation. The OUTFS common-mode error sources of both I and I can be OUTA OUTB IOUTA = (DAC CODE/256) × IOUTFS (1) significantly reduced by the common-mode rejection of a IOUTB = (255 − DAC CODE)/256 × IOUTFS (2) transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. where DAC CODE = 0 to 255 (that is, decimal representation). The enhancement in distortion performance becomes more IOUTFS is a function of the reference current (IREF), which is significant as the frequency content of the reconstructed nominally set by a reference voltage (V ) and an external REFIO waveform increases. This is due to the first-order cancellation of resistor (R ). It can be expressed as SET various dynamic common-mode distortion mechanisms, digital I = 32 × I (3) OUTFS REF feedthrough, and noise. where Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the IREF = VREFIO/RSET (4) reconstructed signal power to the load (that is, assuming no The two current outputs typically drive a resistive load directly source termination). Because the output currents of IOUTA and or via a transformer. If dc coupling is required, IOUTA and IOUTB IOUTB are complementary, they become additive when processed should be connected directly to matching resistive loads, R , LOAD differentially. A properly selected transformer allows the AD9709 that are tied to the analog common, ACOM. Note that R LOAD to provide the required power and voltage levels to different loads. can represent the equivalent load resistance seen by I or OUTA I , as would be the case in a doubly terminated 50 Ω or 75 Ω The output impedance of I and I is determined by the OUTB OUTA OUTB equivalent parallel combination of the PMOS switches cable. The single-ended voltage output appearing at the IOUTA associated with the current sources and is typically 100 kΩ in and IOUTB nodes is parallel with 5 pF. It is also slightly dependent on the output VOUTA = IOUTA × RLOAD (5) voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS V = I × R (6) OUTB OUTB LOAD device. As a result, maintaining IOUTA and/or IOUTB at a virtual Note the full-scale value of V and V must not exceed the ground via an I-V op amp configuration results in the optimum OUTA OUTB specified output compliance range to maintain the specified dc linearity. Note that the INL/DNL specifications for the distortion and linearity performance. AD9709 are measured with I maintained at a virtual ground OUTA via an op amp. VDIFF = (IOUTA − IOUTB) × RLOAD (7) I and I also have a negative and positive voltage OUTA OUTB Equation 7 highlights some of the advantages of operating the compliance range that must be adhered to in order to achieve AD9709 differentially. First, the differential operation helps cancel optimum performance. The negative output compliance range common-mode error sources associated with IOUTA and IOUTB, of −1.0 V is set by the breakdown limits of the CMOS process. such as noise, distortion, and dc offsets. Second, the differential Operation beyond this maximum limit may result in a code-dependent current and subsequent voltage, V , is twice DIFF breakdown of the output stage and affect the reliability of the the value of the single-ended voltage output (that is, V or OUTA AD9709. V ), thus providing twice the signal power to the load. OUTB The positive output compliance range is slightly dependent on Note that the gain drift temperature performance for a single- the full-scale output current, IOUTFS. When IOUTFS is decreased ended (VOUTA and VOUTB) or differential output (VDIFF) of the from 20 mA to 2 mA, the positive output compliance range AD9709 can be enhanced by selecting temperature tracking degrades slightly from its nominal 1.25 V to 1.00 V. The optimum resistors for RLOAD and RSET due to their ratiometric relationship. distortion performance for a single-ended or differential output ANALOG OUTPUTS is achieved when the maximum full-scale signal at I and I OUTA OUTB does not exceed 0.5 V. Applications requiring the AD9709 output The complementary current outputs, IOUTA and IOUTB, in each (that is, V and/or V ) to extend its output compliance range DAC can be configured for single-ended or differential OUTA OUTB should size R accordingly. Operation beyond this compliance operation. I and I can be converted into complementary LOAD OUTA OUTB single-ended voltage outputs, V and V , via a load range adversely affects the linearity performance of the AD9709 OUTA OUTB resistor, R , as described in Equation 5 through Equation 7. and subsequently degrade its distortion performance. LOAD The differential voltage, V , existing between V and V DIFF OUTA OUTB can be converted to a single-ended voltage via a transformer or Rev. B | Page 14 of 32 AD9709 The rising edge of CLK should occur before or simultaneously DIGITAL INPUTS with the rising edge of WRT. If the rising edge of CLK occurs The digital inputs of the AD9709 consist of two independent after the rising edge of WRT, a minimum delay of 2 ns should channels. For the dual port mode, each DAC has its own be maintained from rising edge of WRT to rising edge of CLK. dedicated 8-bit data port: WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins Timing specifications for dual port mode are given in Figure 26 changes as described in the Interleaved Mode Timing section. and Figure 27. The 8-bit parallel data inputs follow straight binary coding t t S H where DB7P1 and DB7P2 are the most significant bits (MSBs) DATA IN and DB0P1 and DB0P2 are the least significant bits (LSBs). IOUTA produces a full-scale output current when all data bits are WRT1/WRT2 t LPW at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of CLK1/CLK2 t CPW the input code. I OUTA The digital interface is implemented using an edge-triggered OR I OUTB master slave latch. The DAC outputs are updated following t PD either the rising edge or every other rising edge of the clock, Figure 26. Dual Port Mode Timing depending on whether dual or interleaved mode is used. The DAC outputs are designed to support a clock rate as high as DATA IN D1 D2 D3 D4 D5 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times WRT1/WRT2 can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition CLK1/CLK2 edges may affect digital feedthrough and distortion performance. I OUTA Best performance is typically achieved when the input data D3 XX D2 D4 OR D1 transitions on the falling edge of a 50% duty cycle clock. I OUTB Figure 27. Dual Mode Timing DAC TIMING Interleaved Mode Timing The AD9709 can operate in two timing modes, dual and interleaved, which are described in the following sections. The When the MODE pin is at Logic 0, the AD9709 operates in block diagram in Figure 25 represents the latch architecture in interleaved mode (refer to Figure 25). In addition, WRT1 the interleaved timing mode. functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. PORT 1 DAC1 INTERLEAVED INPUT LATCH DATA IN, PORT 1 LATCH Data enters the device on the rising edge of IQWRT. The DAC1 logic level of IQSEL steers the data to either Channel Latch 1 DEINTERLEAVED DATA OUT (IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper PORT 2 IQWRT INPUT DAC2 IQSEL operation, IQSEL should only change state when IQWRT and LATCH LATCH IQCLK are low. DAC2 IQCLK ÷2 IQRESET When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the next rising edge on IQCLK updates both DAC Figure 25. Latch Structure in Interleaved Mode latches with the data present at their inputs. In the interleaved Dual Port Mode Timing mode, IQCLK is divided by 2 internally. Following this first When the MODE pin is at Logic 1, the AD9709 operates in dual rising edge, the DAC latches are only updated on every other port mode (refer to Figure 21). The AD9709 functions as two rising edge of IQCLK. In this way, IQRESET can be used to distinct DACs. Each DAC has its own completely independent synchronize the routing of the data to the DACs. digital input and control lines. Similar to the order of CLK and WRT in dual port mode, The AD9709 features a double-buffered data path. Data enters the IQCLK should occur before or simultaneously with IQWRT. device through the channel input latches. This data is then trans- ferred to the DAC latch in each signal path. After the data is loaded into the DAC latch, the analog output settles to its new value. For general consideration, the WRT lines control the channel input latches, and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. Rev. B | Page 15 of 32 00606-027 00606-026 00606-025 AD9709 Timing specifications for interleaved mode are shown in Figure 28 INTERLEAVED xx D1 D2 D3 D4 D5 DATA and Figure 30. IQSEL The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDDx) or IQWRT VTHRESHOLD = DVDDx/2 (±20%) IQCLK t t S H IQRESET DATA IN DAC OUTPUT xx D3 PORT 1 D1 500 ps xx DAC OUTPUT D4 PORT 2 D2 IQSEL Figure 30. Interleaved Mode Timing The internal digital circuitry of the AD9709 is capable of operating t * H IQWRT at a digital supply of 3.3 V or 5 V. As a result, the digital inputs t LPW can also accommodate TTL levels when DVDD1/DVDD2 is set to accommodate the maximum high level voltage (VOH(MAX)) of the IQCLK TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper compatibility with most TTL logic families. Figure 31 shows the 500 ps equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that it I OUTA t PD OR contains an active pull-down circuit, thus ensuring that the I OUTB AD9709 remains enabled if this input is left disconnected. *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. DVDD1 Figure 28. 5 V or 3.3 V Interleaved Mode Timing At 5 V it is permissible to drive IQWRT and IQCLK together as DIGITAL shown in Figure 29, but at 3.3 V the interleaved data transfer is INPUT not reliable. t t S H Figure 31. Equivalent Digital Input DATA IN Because the AD9709 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9709 IQSEL with reduced logic swings and a corresponding digital supply (DVDD1/DVDD2) results in the lowest data feedthrough and t * H on-chip digital noise. The drivers of the digital data interface IQWRT circuitry should be specified to meet the minimum setup and t LPW hold times of the AD9709 as well as its required minimum and maximum input logic level thresholds. IQCLK t I PD OUTA OR I OUTB *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure 29. 5 V Only Interleaved Mode Timing Rev. B | Page 16 of 32 00606-028 00606-056 00606-030 00606-029 AD9709 Digital signal paths should be kept short, and run lengths should be Input Clock and Data Timing Relationship matched to avoid propagation delay mismatch. The insertion of SNR in a DAC is dependent on the relationship between the a low value (that is, 20 Ω to 100 Ω) resistor network between position of the clock edges and the point in time at which the the AD9709 digital inputs and driver outputs may be helpful in input data changes. The AD9709 is rising-edge triggered and reducing any overshooting and ringing at the digital inputs that therefore exhibits SNR sensitivity when the data transition is contribute to digital feedthrough. For longer board traces and close to this edge. In general, the goal when applying the AD9709 is high data update rates, stripline techniques with proper to make the data transition close to the falling clock edge. This impedance and termination resistors should be considered to becomes more important as the sample rate increases. Figure 32 maintain “clean” digital inputs. shows the relationship of SNR to clock/data placement. The external clock driver circuitry provides the AD9709 with a 60 low-jitter clock input meeting the minimum and maximum logic 50 levels while providing fast edges. Fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform. 40 Therefore, the clock input should be driven by the fastest logic family suitable for the application. 30 Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, DVDDx/2) and 20 meets the minimum and maximum logic threshold. This typically results in a slight degradation in the phase noise, which becomes 10 more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the 20% tolerance of the 0 digital logic threshold should be considered because it affects –4 –3 –2 –1 0 1 2 3 4 TIME OF DATA CHANGE RELATIVE TO the effective clock duty cycle and, subsequently, cut into the RISING CLOCK EDGE (ns) required data setup and hold times. Figure 32. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS Rev. B | Page 17 of 32 SNR (dBc) 00606-031 AD9709 80 SLEEP MODE OPERATION The AD9709 has a power-down function that turns off the 70 output current and reduces the supply current to less than 60 8.5 mA over the specified supply range of 3.3 V to 5 V and temperature range. This mode can be activated by applying a 50 Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital input also contains an active 40 pull-down circuit that ensures the AD9709 remains enabled if 30 this input is left disconnected. The AD9709 requires less than 50 ns to power down and approximately 5 μs to power back up. 20 POWER DISSIPATION 10 The power dissipation, P , of the AD9709 is dependent on several 02 5 10 15 205 D I (mA) OUTFS factors, including Figure 33. I vs. I AVDD OUTFS • the power supply voltages (AVDD and DVDD1/DVDD2) 35 • the full-scale current output (IOUTFS) • the update rate (fCLK) 30 125MSPS • the reconstructed digital input waveform 25 100MSPS The power dissipation is directly proportional to the analog 20 supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 33, and is 65MSPS 15 insensitive to fCLK. Conversely, I is dependent on the digital input waveform, 10 DVDD 25MSPS f , and digital supply (DVDD1/DVDD2). Figure 34 and CLK 5 Figure 35 show IDVDD as a function of full-scale sine wave output 5MSPS ratios (fOUT/fCLK) for various update rates with DVDD1 = 0 00 0.1 0.2 0.3 0.4.5 DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. RATIO (f /f ) OUT CLK Note how IDVDD is reduced by more than a factor of 2 when Figure 34. I vs. Ratio @ DVDD1 = DVDD2 = 5 V DVDD DVDD1/DVDD2 is reduced from 5 V to 3.3 V. 18 125MSPS 16 14 100MSPS 12 10 65MSPS 8 6 25MSPS 4 5MSPS 2 0 00 0.1 0.2 0.3 0.4.5 RATIO (f /f ) OUT CLK Figure 35. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V Rev. B | Page 18 of 32 I (mA) I (mA) I (mA) DVDD DVDD AVDD 00606-032 00606-034 00606-033 AD9709 APPLYING THE AD9709 RDIFF, can be inserted in applications where the output of the OUTPUT CONFIGURATIONS transformer is connected to the load, RLOAD, via a passive The following sections illustrate some typical output configura- reconstruction filter or cable. RDIFF is determined by the tions for the AD9709. Unless otherwise noted, it is assumed that transformer’s impedance ratio and provides the proper source I is set to a nominal 20 mA. For applications requiring the OUTFS termination that results in a low VSWR. Note that approximately optimum dynamic performance, a differential output half the signal power will be dissipated across R . DIFF configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp DIFFERENTIAL COUPLING USING AN OP AMP configuration. The transformer configuration provides the An op amp can also be used as shown in Figure 37 to perform a optimum high frequency performance and is recommended for differential-to-single-ended conversion. The AD9709 is configured any application allowing for ac coupling. The differential op with two equal load resistors, R , of 25 Ω each. The differential LOAD amp configuration is suitable for applications requiring dc voltage developed across I and I is converted to a single- OUTA OUTB coupling, bipolar output, signal gain, and/or level shifting, ended signal via the differential op amp configuration. An optional within the bandwidth of the chosen op amp. capacitor can be installed across IOUTA and IOUTB, forming a real pole A single-ended output is suitable for applications requiring a in a low-pass filter. The addition of this capacitor also enhances the unipolar voltage output. A positive unipolar output voltage results op amp’s distortion performance by preventing the DAC’s high- if IOUTA and/or IOUTB is connected to an appropriately sized load slewing output from overloading the op amp’s input. resistor, R , referred to ACOM. This configuration may be 500Ω LOAD AD9709 more suitable for a single-supply system requiring a dc-coupled, 225Ω I ground-referred output voltage. Alternatively, an amplifier can be OUTA AD8047 configured as an I-V converter, thus converting IOUTA or IOUTB into a 225Ω I OUTB negative unipolar voltage. This configuration provides the best dc C OPT linearity because IOUTA or IOUTB is maintained at a virtual ground. 500Ω 25Ω 25Ω Note that IOUTA provides slightly better performance than IOUTB. DIFFERENTIAL COUPLING USING A Figure 37. DC Differential Coupling Using an Op Amp TRANSFORMER The common-mode rejection of this configuration is typically An RF transformer can be used as shown in Figure 36 to perform determined by the resistor matching. In this circuit, the differential a differential-to-single-ended signal conversion. A differentially op amp circuit using the AD8047 is configured to provide some coupled transformer output provides the optimum distortion additional signal gain. The op amp must operate from a dual performance for output signals whose spectral content lies within supply because its output is approximately ±1.0 V. A high speed the pass band of the transformer. An RF transformer such as the amplifier capable of preserving the differential performance of Mini-Circuits® T1-1T provides excellent rejection of common- the AD9709 while meeting other system level objectives (that is, mode distortion (that is, even-order harmonics) and noise over cost and power) should be selected. The op amp’s differential a wide frequency range. It also provides electrical isolation and gain, gain setting resistor values, and full-scale output swing the ability to deliver twice the power to the load. Transformers capabilities should be considered when optimizing this circuit. with different impedance ratios can also be used for impedance The differential circuit shown in Figure 38 provides the matching purposes. Note that the transformer provides ac necessary level shifting required in a single-supply system. In coupling only. this case, AVDD, which is the positive analog supply for both AD9709 Mini-Circuits the AD9709 and the op amp, is used to level shift the differential T1-1T I OUTA output of the AD9709 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. R LOAD 500Ω I OUTB AD9709 OPTIONAL 225Ω R I DIFF OUTA AD8041 Figure 36. Differential Output Using a Transformer 225Ω I OUTB C OPT The center tap on the primary side of the transformer must be 1kΩ AVDD connected to ACOM to provide the necessary dc current path 25Ω 25Ω 500Ω for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically Figure 38. Single-Supply DC Differential Coupled Circuit around ACOM and should be maintained with the specified output compliance range of the AD9709. A differential resistor, Rev. B | Page 19 of 32 00606-035 00606-036 00606-037 AD9709 SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT POWER AND GROUNDING CONSIDERATIONS Power Supply Rejection Figure 39 shows the AD9709 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated Many applications seek high speed and high performance under 50 Ω cable, because the nominal full-scale current, IOUTFS, of 20 mA less than ideal operating conditions. In these applications, the flows through the equivalent R of 25 Ω. In this case, R LOAD LOAD implementation and construction of the printed circuit board is represents the equivalent load resistance seen by I or I . OUTA OUTB as important as the circuit design. Proper RF techniques must The unused output (I or I ) can be connected directly to OUTA OUTB be used for device selection, placement, and routing as well as ACOM or via a matching RLOAD. Different values of IOUTFS and power supply bypassing and grounding to ensure optimum RLOAD can be selected as long as the positive compliance range is performance. Figure 52 and Figure 53 illustrate the recommended adhered to. One additional consideration in this mode is the circuit board layout, including ground, power, and signal INL (see the Analog Outputs section). For optimum INL input/output. performance, the single-ended, buffered voltage output One factor that can measurably affect system performance is configuration is suggested. the ability of the DAC output to reject dc variations or ac noise AD9709 superimposed on the analog or digital dc power distribution. I = 20mA OUTFS V = 0V TO 0.5V OUTA This is referred to as the power supply rejection ratio (PSRR). I OUTA For dc variations of the power supply, the resulting performance 50Ω 50Ω I OUTB of the DAC directly corresponds to a gain error associated with 25Ω the DAC’s full-scale current, I . AC noise on the dc supplies OUTFS is common in applications where the power distribution is Figure 39. 0 V to 0.5 V Unbuffered Voltage Output generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum from tens of SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT kilohertz to several megahertz. The PSRR vs. frequency of the CONFIGURATION AD9709 AVDD supply over this frequency range is shown in Figure 40 shows a buffered single-ended output configuration Figure 41. in which the U1 op amp performs an I-V conversion on the 90 AD9709 output current. U1 maintains I (or I ) at a OUTA OUTB virtual ground, thus minimizing the nonlinear output impedance effect on the INL performance of the DAC, as 85 discussed in the Analog Outputs section. Although this single- ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC 80 update rates may be limited by the slewing capabilities of U1. U1 provides a negative unipolar output voltage, and its full- scale output voltage is simply the product of R and I . The FB OUTFS 75 full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS because 70 0.20.3 0.40.50.60.70.80.91.01.1 the signal current U1 has to sink will be subsequently reduced. FREQUENCY (MHz) C OPT Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency R FB Note that the data in Figure 41 is given in terms of current out 200Ω AD9709 vs. voltage in. Noise on the analog power supply has the effect I = 10mA OUTFS of modulating the internal current sources and therefore the I OUTA output current. The voltage noise on AVDD, therefore, is added U1 V = I × R OUT OUTFS FB I OUTB in a nonlinear manner to the desired I . PSRR is very code OUT 200Ω dependent, thus producing mixing effects that can modulate low frequency power supply noise to higher frequencies. Worst- Figure 40. Unipolar Buffered Voltage Output case PSRR for either one of the differential DAC outputs occurs when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 41 represents a worst- case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. Rev. B | Page 20 of 32 00606-038 00606-039 PSRR (dB) 00606-040 AD9709 An example serves to illustrate the effect of supply noise on the (AVDD) to the analog common (ACOM) as close to the chip as analog supply. Suppose a switching regulator with a switching physically possible. Similarly, decouple DVDD1/DVDD2, the frequency of 250 kHz produces 10 mV of noise and, for simplicity’s digital supply (DVDD1/DVDD2) to the digital common (DCOM1/DCOM2) as close to the chip as possible. sake, all of this noise is concentrated at 250 kHz (that is, ignore harmonics). To calculate how much of this undesired noise will For applications that require a single 5 V or 3.3 V supply for appear as current noise superimposed on the DAC full-scale both the analog and digital supplies, a clean analog supply can current, IOUTFS, one must determine the PSRR in decibels using be generated using the circuit shown in Figure 42. The circuit Figure 41 at 250 kHz. To calculate the PSRR for a given R , LOAD consists of a differential LC filter with separate power supply such that the units of PSRR are converted from A/V to V/V, and return lines. Lower noise can be attained by using low-ESR adjust the curve in Figure 41 by the scaling factor 20 × log(R ). LOAD type electrolytic and tantalum capacitors. For instance, if R is 50 Ω, the PSRR is reduced by 34 dB LOAD FERRITE ELECTROLYTIC CERAMIC BEADS (that is, the PSRR of the DAC at 250 kHz, which is 85 dB in AVDD TTL/CMOS Figure 41, becomes 51 dB VOUT/VIN). 10µF LOGIC TO 100µF 0.1µF CIRCUITS 22µF Proper grounding and decoupling should be a primary ACOM objective in any high speed, high resolution system. The TANTALUM AD9709 features separate analog and digital supply and ground 5V pins to optimize the management of analog and digital ground POWER SUPPLY currents in a system. In general, decouple the analog supply Figure 42. Differential LC Filter for Single 5 V and 3.3 V Applications Rev. B | Page 21 of 32 00606-041 AD9709 APPLICATIONS INFORMATION QUADRATURE AMPLITUDE MODULATION (QAM) 8 DAC USING THE AD9709 DSP 0° CARRIER OR TO QAM is one of the most widely used digital modulation Σ FREQUENCY ASIC 90° MIXER schemes in digital communications systems. This modulation 8 DAC technique can be found in FDM as well as spread spectrum (that is, CDMA) based systems. A QAM signal is a carrier NYQUIST QUADRATURE FILTERS MODULATOR frequency that is modulated in both amplitude (that is, AM Figure 43. Typical Analog QAM Architecture modulation) and phase (that is, PM modulation). It can be generated by independently modulating two carriers of identical In this implementation, it is much more difficult to maintain frequency but with a 90° phase difference. This results in an proper gain and phase matching between the I and Q channels. in-phase (I) carrier component and a quadrature (Q) carrier The circuit implementation shown in Figure 44 helps improve component at a 90° phase shift with respect to the I component. the matching between the I and Q channels, and it shows a path The I and Q components are then summed to provide a QAM for upconversion using the AD8346 quadrature modulator. The signal at the specified carrier frequency. AD9709 provides both I and Q DACs with a common reference that will improve the gain matching and stability. RCAL can be A common and traditional implementation of a QAM used to compensate for any mismatch in gain between the two modulator is shown in Figure 43. The modulation is performed channels. The mismatch may be attributed to the mismatch in the analog domain in which two DACs are used to generate between R and R , the effective load resistance of each SET1 SET2 the baseband I and Q components. Each component is then channel, and/or the voltage offset of the control amplifier in each typically applied to a Nyquist filter before being applied to a DAC. The differential voltage outputs of both DACs in the quadrature mixer. The matching Nyquist filters shape and limit AD9709 are fed into the respective differential inputs of the each component’s spectral envelope while minimizing intersymbol AD8346 via matching networks. interference. The DAC is typically updated at the QAM symbol rate, or at a multiple of the QAM symbol rate if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature carrier frequencies and then sums the two outputs to provide the QAM signal. AVDD ROHDE & SCHWARZ FSEA30B 0.1µF OR EQUIVALENT DCOM1/ DVDD1/ ACOM AVDD RA RA RL RL SPECTRUM ANALYZER DCOM2 DVDD2 VPBF I A LA RB BBIP OUT TEKTRONIX I DAC I AWG2021 VOUT CA CB LATCH DAC WITH RB OPTION 4 + I B BBIN OUT LA RL RL WRT1/IQWRT AD9709 LOIP CLK1/IQCLK RA RA PHASE RL RL LA BBQP I A RB SPLITTER OUT LOIN Q DAC Q CA CB C LATCH DAC FILTER RB I B BBQN OUT LA RL RL WRT2/IQSEL AD8346 VDIFF = 1.82V p-p SLEEP MODE FSADJ1 FSADJ2 REFIO DIFFERENTIAL RLC FILTER ROHDE & SCHWARZ RL = 200Ω 0.1µF SIGNAL GENERATOR RA = 2500Ω 256Ω 256Ω 2kΩ 2kΩ RB = 500Ω RP = 200Ω 22nF 22nF 20kΩ 20kΩ CA = 280pF AVDD CB = 45pF LA = 10µH I = 11mA RA AD976x AD8346 OUTFS RL NOTES AVDD = 5.0V 1. DAC FULL-SCALE OUTPUT CURRENT = I . OUTFS VCM = 1.2V V 2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS MOD RB WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT. 0 TO I V OUTFS DAC Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346 Rev. B | Page 22 of 32 PORT Q PORT I DIGITAL INTERFACE 00606-045 00606-044 AD9709 I and Q digital data can be fed into the AD9709 in two ways. In Distortion in the transmit path can lead to power being transmitted dual port mode, the digital I information drives one input port, out of the defined band. The ratio of power transmitted in-band to and the digital Q information drives the other input port. If no out-of-band is often referred to as adjacent channel power (ACP). This is a regulatory issue due to the possibility of interference interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the with other signals being transmitted by air. Regulatory bodies AD9709. In interleaved mode, the digital input stream at Port 1 define a spectral mask outside of the transmit band, and the ACP contains the I and the Q information in alternating digital words. must fall under this mask. If distortion in the transmit path causes Using IQSEL and IQRESET, the AD9709 can be synchronized the ACP to be above the spectral mask, filtering or different to the I and Q data streams. The internal timing of the AD9709 component selection is needed to meet the mask requirements. routes the selected I and Q data to the correct DAC output. In Figure 45 displays the results of using the application circuit shown interleaved mode, if no interpolation filter precedes the AD9709, in Figure 44 to reconstruct a wideband CDMA (W-CDMA) test the symbol rate is half that of the system clock driving the digital vector using a bandwidth of 8 MHz that is centered at 2.4 GHz data stream and the IQWRT and IQCLK pins on the AD9709. and sampled at 65 MHz. The IF frequency at the DAC output is 15.625 MHz. The adjacent channel power ratio (ACPR) for the CDMA given test vector is measured at greater than 54 dB. Code division multiple access (CDMA) is an air transmit/receive –30 scheme where the signal in the transmit path is modulated with a –40 pseudorandom digital code (sometimes referred to as the spreading code). The effect of this is to spread the transmitted signal across –50 a wide spectrum. Similar to a discrete multitone (DMT) wave- –60 == form, a CDMA waveform containing multiple subscribers can –70 be characterized as having a high peak to average ratio (that is, –80 crest factor), thus demanding highly linear components in the –90 transmit signal path. The bandwidth of the spectrum is defined –100 by the CDMA standard being used, and in operation it is implemented by using a spreading code with particular –110 c11 c11 cu1 characteristics. –120 cu1 C0 C0 –130 CENTER 2.4GHz 3MHz SPAN 30MHz FREQUENCY Figure 45. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at 2.4 GHz, Adjacent Channel Power > 54 dB Rev. B | Page 23 of 32 (dB) 00606-046 AD9709 EVALUATION BOARD This board allows the user flexibility to operate the AD9709 in GENERAL DESCRIPTION various configurations. Possible output configurations include The AD9709-EB is an evaluation board for the AD9709 8-bit transformer coupled, resistor terminated, and single-ended and dual DAC. Careful attention to layout and circuit design, differential outputs. The digital inputs can be used in dual port combined with a prototyping area, allow the user to easily and or interleaved mode and are designed to be driven from various effectively evaluate the AD9709 in any application where high word generators, with the on-board option to add a resistor resolution, high speed conversion is required. network for proper load termination. When operating the AD9709, best performance is obtained when running the digital supply (DVDD1/DVDD2) at 3.3 V and the analog supply (AVDD) at 5 V. SCHEMATICS RED RED L1 L2 DVDDIN TB1 1 DVDD AVDDIN TB1 3 AVDD BEAD BEAD C9 C10 DCASE DCASE VAL VAL VOLT VOLT BLK BLK BLK BLK BLK BLK 2 4 TB1 TB1 BLK BLK DGND AGND 1 RCO M 1 RCO M 1 RCO M 1 RCO M 22 R1 22 R1 22 R1 22 R1 2 2 2 2 INP31 INP23 INP9 INP1 R2 R2 R2 R2 3 3 3 3 INP32 INP24 INP10 INP2 R3 R3 R3 R3 4 4 4 4 INP33 INP25 INP11 INP3 R4 R4 R4 R4 5 5 5 5 INP34 INP26 INP12 INP4 R5 R5 R5 R5 6 6 6 6 INP35 INP27 INP13 INP5 R6 R6 R6 R6 7 7 7 7 INP36 INP28 INP14 INP6 R7 R7 R7 R7 8 8 8 8 INP29 INP7 R8 R8 R8 R8 9 9 9 9 INCK2 INP30 INCK1 INP8 R9 R9 R9 R9 10 10 10 10 RP15 RP10 RP9 RP16 Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1) Rev. B | Page 24 of 32 00606-146 AD9709 B C 2 1 A 3 Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2) Rev. B | Page 25 of 32 R16 R19 1K 1K JP9 DVDD RC0603 RC0603 JP2 DCLKIN1 DCLKIN2 DVDD DVDD DVDD R17 1K R1 8 1K C8 C7 DVDD CC0805 CC0805 RC0603 RC0603 .1UF .01UF C33 C34 SW1 CC0805 CC0805 .1UF .01UF T1-1TCUP C19 .1 4 10 7 6 1 +IN 1 PRE PRE +IN 3 5 11 9 J Q J Q JP1 5 2 15 U2 10 C18 .1 OUT U2 1 13 U6 U6 OUT CLK CLK 4 3 SO16 T3 -IN 26 12 7 SO16 K Q_ K Q_ JP13 -IN 8 DVDD DS90LV048B 2 CLR CLR DS90LV048B 15 SN74F112 14 R6 3 50 5 SN74F112 +IN DGND;8 DGND;8 U2 11 RC0603 DVDD;16 DVDD;16 OUT JP17 SO16 SW2 WHT -IN 6 DS90LV048B SMA200UP JP14 S1 3 WRT1IN +IN DGND;3,4,5 JP16 IQWRT U2 14 OUT DVDD SO16 SMA200UP -IN JP5 4 DS90LV048B WHT CLK1IN S2 1QCLK DGND;3,4,5 DVDD SMA200UP JP4 WHT CLK2IN S3 R30 VAL RESET /2 CLOCK DIVIDER DGND;3,4,5 16 13 SMA200UP JP3 EN VCC DVDD WHT WRT2IN S4 U2 IQSEL 9 12 DGND;3,4,5 EN GND SO16 R1 R2 R3 R4 DS90LV048B 50 50 50 50 WRT1 CLK1 CLK2 WRT2 WHT SLEEP SLEEP R13 50 RC0805 RC0805 CC0805 RC0805 CC0805 RC0805 RC0805 RC0603 B 2 C 3 1 A 00606-147 AD9709 L6 DNP R23 51 C31 DNP O2N LC0805 RC0603 DNP DNP JP19 CC0805 CC0805 C24 C23 L5 DNP R21 51 R22 DNP O2P LC0805 RC0603 RC0603 MODULATED OUTPUT AGND2;3,4,5 SMAEDGE R27 0 C28 AVDD2 J1 RC0603 .1UF 100PF C29 C20 CC0603 CC0603 BCASE AVDD2 10UF 2 C27 2 10V TP6 RED 100PF AVDD2 AGND2;17 2 R28 1K AGND2 TP5 JP18 BLK .1UF LOCAL OSC INPUT 2 CC0603 AGND2;3,4,5 SMAEDGE C30 R29 0 ETC1-1-13 3 4 J2 RC0603 SP 2 C26 100PF 1 5 T4 R20 C25 100PF 50 2 JP21 2 JP22 2 L4 DNP R26 51 C32 DNP O1N RC0603 LC0805 DNP DNP JP20 CC0805 CC0805 C22 C21 L3 DNP R25 51 R24 DNP O1P RC0603 RC0603 LC0805 Figure 48. Modulator on AD9709 Evaluation Board Rev. B | Page 26 of 32 1 16 IBBP QBBP 2 15 IBBN QBBN 3 14 G1A G4B 4 13 G1B G4A 5 12 LOIN VPS2 6 11 U3 LOIP VOUT 7 10 VPS1 G3 AD834 9 8 9 CC0603 CC0603 ENBL G2 RC0603 CC0603 CC0603 CC0603 RC0603 00606-148 AD9709 RIBBON RA Figure 49. Digital Input Signaling (1) Rev. B | Page 27 of 32 R62 R61 R60 R59 R58 R57 R56 R55 R54 R53 R52 R51 R50 R49 R33 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 P1 INP1 2 1 1 16 INP2 RP5 10 4 3 2 15 INP3 RP5 10 65 3 14 INP4 RP5 10 87 4 13 INP5 DUTP1 10 9 RP5 10 5 12 INP6 RP5 10 DUTP2 12 11 6 11 INP7 RP5 10 DUTP3 14 13 7 10 INP8 RP5 10 DUTP4 16 15 8 9 INP9 DUTP5 18 17 RP5 10 116 INP10 RP6 10 DUTP6 20 19 2 15 INP11 RP6 10 DUTP7 22 21 314 INP12 RP6 10 DUTP8 24 23 4 13 INP13 DUTP9 26 25 RP6 10 512 INP14 RP6 10 DUTP10 28 27 6 11 RP6 10 DUTP11 30 29 DUTP12 32 31 INCK1 DUTP13 34 33 8 9 RP6 10 DUTP14 36 35 DCLKIN1 38 37 40 39 SPARES 10 7 10 RP6 HDR040RA HDR040RA RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 00606-149 AD9709 RIBBON RA Figure 50. Digital Input Signaling (2) Rev. B | Page 28 of 32 P2 R41 R42 2 1 R34 R35 R48 R36 R37 R47 R38 R39 R46 R45 R44 R43 R40 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 4 3 6 5 8 7 10 9 12 11 INP23 DUTP23 14 13 116 RP7 10 INP24 16 15 DUTP24 2 15 INP25 RP7 10 DUTP25 18 17 314 INP26 RP7 10 DUTP26 20 19 4 13 INP27 RP7 10 DUTP27 22 21 512 RP7 10 INP28 DUTP28 24 23 6 11 RP7 10 INP29 DUTP29 26 25 710 RP7 10 INP30 28 27 DUTP30 8 9 INP31 RP7 10 DUTP31 30 29 116 INP32 RP8 10 DUTP32 32 31 2 15 INP33 RP8 10 DUTP33 34 33 314 INP34 RP8 10 INCK2 DUTP34 36 35 4 13 RP8 10 INP35 8 9 RP8 10 DUTP35 38 37 512 RP8 10 INP36 40 39 DUTP36 6 11 RP8 10 DCLKIN2 HDR040RA HDR040RA SPARES 10 7 10 RP8 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 00606-150 AD9709 Figure 51. Device Under Test/Analog Output Signal Conditioning Rev. B | Page 29 of 32 R31 10 BL1 DVDD RC0805 ACOM JP15 AGND;3,4,5 1 3 JP23 SMA200UP A B C1 C2 C3 T5 WHT 2 34 CC0805 CC0805 CC0805 R11 OUT1 AVDD 2 VAL .01UF 5 .1UF VAL S6 1 6 R5 R6 O1P C5 T1-1TCUP 50 50 C4 CC0805 MODE O1N JP8 CC0805 13 A B DVDD 10PF 10PF JP6 JP7 2 1 48 DUTP1 DB13P1MSB MODE R9 1.92K 2 47 WHT DUTP2 DB12P1 AVDD BL2 RC0805 3 46 DUTP3 DB11P1 IA1 REFIO 4 45 DUTP4 DB10P1 IB1 C16 R15 256 22NF 5 44 WHT DUTP5 DB9P1 FSADJ1 RC0805 6 43 DUTP6 DB8P1 REFIO 7 42 C17 DUTP7 DB7P1 ACOM1 R14 256 22NF C14 8 41 DUTP8 DB6P1 FSADJ2 RC0805 CC0805 9 40 DUTP9 DB5P1 IB2 .1UF R10 1.92K 10 39 JP10 DUTP10 DB4P1 IA2 11 38 C6 RC0805 WHT DUTP11 DB3P1 ACOM C15 JP12 JP11 12 37 CC0805 DUTP12 DB2P1 SLEEP SLEEP CC0805 U1 10PF 13 36 10PF DUTP13 DB1P1 DB0P2 DUTP36 AD9763/65/67 BL3 14 35 DUTP14 DB0P1 DB1P2 DUTP35 15 34 DCOM1 DB2P2 DUTP34 O2N R7 R8 16 33 50 DVDD1 DB3P2 DUTP33 50 T6 O2P 17 32 34 WRT1 WRT1 DB4P2 DUTP32 R32 10 18 31 2 5 CLK1 CLK1 DB5P2 DUTP31 R12 19 30 1 6 RC0805 VAL CLK2 CLK2 DB6P2 DUTP30 AGND;3,4,5 20 29 SMA200UP WRT2 WRT2 DB7P2 DUTP29 JP24 T1-1TCUP WHT 21 28 DCOM2 DB8P2 DUTP28 OUT2 22 27 DVDD2 DB9P2 DUTP27 S11 23 26 DUTP23 DB13P2MSB DB10P2 DUTP26 BL4 24 25 DUTP24 DB12P2 DB11P2 DUTP25 AVDD C11 C12 C13 .01UF .1UF CC0805 CC0805 CC0805 VAL RC0805 RC0805 RC0805 RC0805 RC07CUP RC07CUP CC0805 CC0805 00606-151 AD9709 EVALUATION BOARD LAYOUT Figure 52. Assembly, Top Side Rev. B | Page 30 of 32 00606-152 AD9709 Figure 53. Assembly, Bottom Side Rev. B | Page 31 of 32 00606-153 AD9709 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9709ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD9709ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD9709-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00606-0-9/09(B) Rev. B | Page 32 of 32 051706-A