ANALOG DEVICES AD9708

8-Bit, 100 MSPS+ ® a TxDAC D/A Converter AD9708 FUNCTIONAL BLOCK DIAGRAM FEATURES Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1mF 8-Bit Resolution Linearity: 1/4 LSB DNL AVDD REFLO COMP1 ACOM Linearity: 1/4 LSB INL +1.20V REF AD9708 Differential Current Outputs 50pF 0.1mF 0.1mF REF IO SINAD @ 5 MHz Output: 50 dB COMP2 CURRENT SOURCE Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V FS ADJ ARRAY R Power-Down Mode: 20 mW @ 5 V SET IOUTA +5V DVDD On-Chip 1.20 V Reference SEGMENTED DCOM IOUTB SWITCHES Single +5 V or +3 V Supply Operation CLOCK Packages: 28-Lead SOIC and 28-Lead TSSOP CLOCK LATCHES SLEEP Edge-Triggered Latches Fast Settling: 35 ns Full-Scale Settling to 0.1% DIGITAL DATA INPUTS (DB7–DB0) APPLICATIONS Differential current outputs are provided to support single- Communications ended or differential applications. The current outputs may be Signal Reconstruction directly tied to an output resistor to provide two complemen- Instrumentation tary, single-ended voltage outputs. The output voltage compliance PRODUCT DESCRIPTION range is 1.25 V. The AD9708 is the 8-bit resolution member of the TxDAC The AD9708 contains a 1.2 V on-chip reference and reference series of high performance, low power CMOS digital-to-analog control amplifier, which allows the full-scale output current to converters (DACs). The TxDAC family, which consists of pin be simply set by a single resistor. The AD9708 can be driven by compatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti- a variety of external reference voltages. The AD9708’s full-scale mized for the transmit signal path of communication systems. All current can be adjusted over a 2 mA to 20 mA range without of the devices share the same interface options, small outline any degradation in dynamic performance. Thus, the AD9708 package and pinout, thus providing an upward or downward may operate at reduced power levels or be adjusted over a 20 dB component selection path based on performance, resolution and range to provide additional gain ranging capabilities. cost. The AD9708 offers exceptional ac and dc performance The AD9708 is available in 28-lead SOIC and 28-lead TSSOP while supporting update rates up to 125 MSPS. packages. It is specified for operation over the industrial tem- The AD9708’s flexible single-supply operating range of +2.7 V perature range. to +5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be PRODUCT HIGHLIGHTS further reduced to 45 mW, without a significant degradation in 1. The AD9708 is a member of the TxDAC product family, which performance, by lowering the full-scale current output. In addi- provides an upward or downward component selection path tion, a power-down mode reduces the standby power dissipa- based on resolution (8 to 14 bits), performance and cost. tion to approximately 20 mW. 2. Manufactured on a CMOS process, the AD9708 uses a pro- The AD9708 is manufactured on an advanced CMOS process. prietary switching technique that enhances dynamic perfor- A segmented current source architecture is combined with a mance well beyond 8- and 10-bit video DACs. proprietary switching technique to reduce spurious components 3. On-chip, edge-triggered input CMOS latches readily interface and enhance dynamic performance. Edge-triggered input latches to +3 V and +5 V CMOS logic families. The AD9708 can and a temperature compensated bandgap reference have been inte- support update rates up to 125 MSPS. grated to provide a complete monolithic DAC solution. Flexible 4. A flexible single-supply operating range of +2.7 V to +5.5 V supply options support +3 V and +5 V CMOS logic families. and a wide full-scale current adjustment span of 2 mA to The AD9708 is a current-output DAC with a nominal full-scale 20 mA allows the AD9708 to operate at reduced power levels output current of 20 mA and > 100 kW output impedance. (i.e., 45 mW) without any degradation in dynamic performance. TxDAC is a registered trademark of Analog Devices, Inc. 5. A temperature compensated, 1.20 V bandgap reference is included on-chip providing a complete DAC solution. An external reference may be used. REV. B 6. The current output(s) of the AD9708 can easily be config- ured for various single-ended or differential applications. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9708–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 8 Bits MONOTONICITY GUARANTEED OVER SPECIFIED TEMPERATURE RANGE 1 DC ACCURACY Integral Linearity Error (INL) –1/2–1/4 +1/2 LSB Differential Nonlinearity (DNL) –1/2–1/4 +1/2 LSB ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –10–2 +10 % of FSR Gain Error (With Internal Reference) –10–1 +10 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW 4 Small Signal Bandwidth (w/o C ) 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C (With Internal Reference)–100 ppm of FSR/°C Gain Drift Reference Voltage Drift–50 ppm/°C POWER SUPPLY Supply Voltages 5 2.7 5.0 5.5 V AVDD DVDD 2.7 5.0 5.5 V )2530mA Analog Supply Current (I AVDD 6 ) 36 mA Digital Supply Current (I DVDD ) 8.5 mA Supply Current Sleep Mode (I AVDD 6 (5 V, I = 20 mA) 140 175 mW Power Dissipation OUTFS 7 (5 V, I = 20 mA) 190 mW Power Dissipation OUTFS 7 (3 V, I = 2 mA) 45 mW Power Dissipation OUTFS Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 · the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at f = 50 MSPS and f = 1.0 MHz. CLOCK OUT 7 Measured as unbuffered voltage output into 50W R at IOUTA and IOUTB, f = 100 MSPS and f = 40 MHz. LOAD CLOCK OUT Specifications subject to change without notice. –2– REV. B AD9708 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Single-Ended Output, IOUTA, 50 V Doubly MIN MAX OUTFS DYNAMIC SPECIFICATIONS Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 100 125 MSPS CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion Ratio f = 10 MSPS; f = 1.00 MHz 50 dB CLOCK OUT f = 50 MSPS; f = 1.00 MHz 50 dB CLOCK OUT f = 50 MSPS; f = 12.51 MHz 48 dB CLOCK OUT f = 100 MSPS; f = 5.01 MHz 50 dB CLOCK OUT f = 100 MSPS; f = 25.01 MHz 45 dB CLOCK OUT Total Harmonic Distortion f = 10 MSPS; f = 1.00 MHz –67 dBc CLOCK OUT f = 50 MSPS; f = 1.00 MHz –67 –62 dBc CLOCK OUT f = 50 MSPS; f = 12.51 MHz –59 dBc CLOCK OUT f = 100 MSPS; f = 5.01 MHz –64 dBc CLOCK OUT f = 100 MSPS; f = 25.01 MHz –48 dBc CLOCK OUT Spurious-Free Dynamic Range to Nyquist f = 10 MSPS; f = 1.00 MHz 68 dBc CLOCK OUT f = 50 MSPS; f = 1.00 MHz 62 68 dBc CLOCK OUT f = 50 MSPS; f = 12.51 MHz 63 dBc CLOCK OUT f = 100 MSPS; f = 5.01 MHz 67 dBc CLOCK OUT f = 100 MSPS; f = 25.01 MHz 50 dBc CLOCK OUT NOTES 1 Measured single ended into 50W load. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5pF Input Setup Time (t)2.0 ns S Input Hold Time (t)1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW Specifications subject to change without notice. DB0–DB7 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram REV. B –3– AD9708 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS With Pin No. Name Description Parameter Respect to Min Max Units 1 DB7 Most Significant Data Bit (MSB). AVDD ACOM –0.3 +6.5 V 2–7 DB6–DB1 Data Bits 1–6. DVDD DCOM –0.3 +6.5 V 8 DB0 Least Significant Data Bit (LSB). ACOM DCOM –0.3 +0.3 V 9–14, 25 NC No Internal Connection. AVDD DVDD –6.5 +6.5 V 15 SLEEP Power-Down Control Input. Active CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V High. Contains active pull-down circuit, Digital Inputs DCOM –0.3 DVDD + 0.3 V thus may be left unterminated if not IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V used. COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V 16 REFLO Reference Ground when Internal 1.2 V REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V Reference Used. Connect to AVDD to REFLO ACOM –0.3 +0.3 V disable internal reference. Junction Temperature +150 °C 17 REFIO Reference Input/Output. Serves as Storage Temperature –65 +150 °C reference input when internal reference Lead Temperature disabled (i.e., Tie REFLO to AVDD). (10 sec) +300 °C Serves as 1.2 V reference output when *Stresses above those listed under Absolute Maximum Ratings may cause perma- internal reference activated (i.e., Tie nent damage to the device. This is a stress rating only; functional operation of the REFLO to ACOM). Requires 0.1mF device at these or any other conditions above those indicated in the operational capacitor to ACOM when internal sections of this specification is not implied. Exposure to absolute maximum reference activated. ratings for extended periods may effect device reliability. 18 FS ADJ Full-Scale Current Output Adjust. 19 COMP1 Bandwidth/Noise Reduction Node. THERMAL CHARACTERISTICS Add 0.1 mF to AVDD for optimum Thermal Resistance performance. 28-Lead 300 mil SOIC 20 ACOM Analog Common.q = 71.4°C/W JA 21 IOUTB Complementary DAC Current Output.q = 23°C/W JC Full-scale current when all data bits 28-Lead TSSOP are 0s. q = 97.9°C/W JA 22 IOUTA DAC Current Output. Full-scale q = 14.0°C/W JC current when all data bits are 1s. 23 COMP2 Internal Bias Node for Switch Driver PIN CONFIGURATION Circuitry. Decouple to ACOM with 0.1mF capacitor. 24 AVDD Analog Supply Voltage (+2.7 V to 28 (MSB) DB7 1 CLOCK +5.5 V). DB6 2 27 DVDD 26 DCOM Digital Common. DB5 3 26 DCOM 27 DVDD Digital Supply Voltage (+2.7 V to 4 DB4 25 NC +5.5 V). DB3 5 24 AVDD AD9708 28 CLOCK Clock Input. Data latched on positive DB2 6 23 COMP2 TOP VIEW (Not to Scale) edge of clock. 22 DB1 7 IOUTA DB0 8 21 IOUTB NC 9 20 ACOM ORDERING GUIDE 19 COMP1 NC 10 18 NC 11 FS ADJ Temperature Package Package NC 12 17 REFIO Model Range Descriptions Options* NC 13 16 REFLO AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 NC 14 15 SLEEP AD9708ARU –40°C to +85°C 28-Lead TSSOP RU-28 NC = NO CONNECT AD9708-EB Evaluation Board *R = Small Outline IC; RU = Thin Small Outline IC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9708 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –4– AD9708 DEFINITIONS OF SPECIFICATIONS offset and gain drift, the drift is reported in ppm of full-scale Linearity Error (Also Called Integral Nonlinearity or INL) range (FSR) per degree C. For reference drift, the drift is Linearity error is defined as the maximum deviation of the reported in ppm per degree C. actual analog output from the ideal output, determined by a Power Supply Rejection straight line drawn from zero to full scale. The maximum change in the full-scale output as the supplies Differential Nonlinearity (or DNL) are varied from nominal to minimum and maximum specified DNL is the measure of the variation in analog value, normalized voltages. to full scale, associated with a 1 LSB change in digital input code. Settling Time Monotonicity The time required for the output to reach and remain within a A D/A converter is monotonic if the output either increases or specified error band about its final value, measured from the remains constant as the digital input increases. start of the output transition. Offset Error Glitch Impulse The deviation of the output current from the ideal of zero is Asymmetrical switching times in a DAC give rise to undesired called offset error. For IOUTA, 0 mA output is expected when output transients that are quantified by a glitch impulse. It is the inputs are all 0s. For IOUTB, 0 mA output is expected specified as the net area of the glitch in pV-s. when all inputs are set to 1s. Spurious-Free Dynamic Range Gain Error The difference, in dB, between the rms amplitude of the output The difference between the actual and ideal output span. The signal and the peak spurious signal over the specified bandwidth. actual span is determined by the output when all inputs are set Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio to 1s minus the output when all inputs are set to 0s. S/N+D is the ratio of the rms value of the measured output Output Compliance Range signal to the rms sum of all other spectral components below the The range of allowable voltage at the output of a current-output Nyquist frequency, including harmonics but excluding dc. The DAC. Operation beyond the maximum compliance limits may value for S/N+D is expressed in decibels. cause either output stage saturation or breakdown resulting in Total Harmonic Distortion nonlinear performance. THD is the ratio of the rms sum of the first six harmonic Temperature Drift components to the rms value of the measured output signal. It is Temperature drift is specified as the maximum change from the expressed as a percentage or in decibels (dB). ambient (+25°C) value to the value at either T or T . For MIN MAX +5V 0.1mF REFLO COMP1 AVDD ACOM 50pF +1.20V REF AD9708 0.1mF REF IO COMP2 CURRENT SOURCE FS ADJ 0.1mF ARRAY R SET 2kV IOUTA +5V DVDD TO HP3589A SEGMENTED IOUTB SPECTRUM/ DCOM SWITCHES NETWORK CLOCK ANALYZER 50V 20pF LATCHES 50V INPUT DVDD SLEEP 50V DCOM 50V 20pF RETIMED CLOCK DIGITAL OUTPUT* DATA CLOCK * AWG2021 CLOCK RETIMED OUTPUT SUCH THAT DIGITAL DATA LECROY 9210 TEKTRONIX TRANSITIONS ON FALLING EDGE PULSE GENERATOR AWG-2021 OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Setup REV. B –5– AD9708 Typical AC Characterization Curves (AVDD = +5 V or +3 V, DVDD = +5 V or +3 V, 50 V Doubly Terminated Load, Single-Ended Output, I , I = 20 mA, T = +258C, unless otherwise noted) OUTA OUTFS A 70 70 55 THD @ 10MSPS THD @ 50MSPS THD @ 10MSPS I = 20mA OUTFS 65 65 THD 50 THD I = 10mA OUTFS @ 100MSPS @ 100MSPS 60 60 45 I = 5mA OUTFS THD @ 50MSPS 55 55 40 I = 2.5mA OUTFS 50 50 SINAD @ 10MSPS SINAD @ 10MSPS SINAD @ 50MSPS 35 SINAD @ 50MSPS 45 45 SINAD @ 100MSPS SINAD @ 100MSPS 40 40 30 0.1 1 10 100 0.1 1 10 100 1 10 100 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 3. SINAD/THD vs. f (AVDD Figure 4. SINAD/THD vs. f (Differ- Figure 5. SINAD vs. I OUT OUT OUTFS and DVDD = 5.0 V) ential Output, AVDD and DVDD = 5.0 V) @ 100 MSPS 52 70 70 THD I = 20mA OUTFS @ 10MSPS THD @ 10MSPS THD 65 65 I = 10mA OUTFS 50 THD @ 50MSPS @ 100MSPS I = 5mA OUTFS 60 60 48 THD @ 50MSPS 55 55 THD @ 100MSPS I = 2.5mA OUTFS 46 50 50 SINAD @ 10MSPS SINAD @ 10MSPS SINAD @ 50MSPS SINAD @ 50MSPS 44 45 45 SINAD @ 100MSPS SINAD @ 100MSPS 40 40 42 0.1 1 10 100 0.1 1 10 100 0.1 1 10 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 6. SINAD/THD vs. f (AVDD Figure 7. SINAD/THD vs. f (Differ- Figure 8. SINAD vs. I OUT OUT OUTFS and DVDD = 3.0 V) ential Output, AVDD and DVDD = 3.0 V) @ 20 MSPS 0 0 0.6 f = 25MSPS CLOCK f = 125MSPS CLOCK f = 7.81MHz OUT 0.5 f = 27.0MHz OUT SFDR = +60.7dBc SFDR = +52.7dBc AMPLITUDE = 0dBFS 0.4 AMPLITUDE = 0dBc 0.3 0.2 0.1 0.0 –0.1 –100 –100 –0.2 START: 0Hz STOP: 12.5MHz START: 0Hz STOP: 62.5MHz TIME – 5ns/Div Figure 9. Single-Tone Spectral Plot Figure 10. Single-Tone Spectral Figure 11. Step Response @ 25 MSPS Plot @ 125 MSPS REV. B –6– 10dB – Div SINAD/THD – dB SINAD/THD – dB SINAD/THD – dB SINAD/THD – dB 10dB – Div VOLTS SINAD – dB SINAD – dB AD9708 FUNCTIONAL DESCRIPTION As previously mentioned, I is a function of the reference OUTFS Figure 12 shows a simplified block diagram of the AD9708. The current I , which is nominally set by a reference voltage REF AD9708 consists of a large PMOS current source array capable of V and external resistor R . It can be expressed as: REFIO SET providing up to 20 mA of total current. The array is divided into I = 32 · I (3) OUTFS REF 31 equal currents that make up the five most significant bits where (MSBs). The remaining 3 LSBs are also implemented with equally I = V /R (4) REF REFIO SET weighted current sources whose sum total equals 7/8th of an MSB current source. Implementing the upper and lower bits The two current outputs will typically drive a resistive load with current sources helps maintain the DAC’s high output directly. If dc coupling is required, IOUTA and IOUTB should impedance (i.e. > 100 kW). All of these current sources are be directly connected to matching resistive loads, R , which LOAD switched to one or the other of the two output nodes (i.e., IOUTA are tied to analog common, ACOM. Note, R may repre- LOAD or IOUTB) via PMOS differential current switches. The switches sent the equivalent load resistance seen by IOUTA or IOUTB are based on a new architecture that drastically improves as would be the case in a doubly terminated 50W or 75W cable. distortion performance. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: The analog and digital sections of the AD9708 have separate power supply inputs (i.e., AVDD and DVDD) that can operate V = I · R (5) OUTA OUTA LOAD independently over a 2.7 volt to 5.5 volt range. The digital section, V = I · R (6) OUTB OUTB LOAD which is capable of operating up to a 125 MSPS clock rate, Note the full-scale value of V and V should not exceed OUTA OUTB consists of edge-triggered latches and segment decoding logic the specified output compliance range to maintain specified circuitry. The analog section includes the PMOS current distortion and linearity performance. sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. The differential voltage, V , appearing across IOUTA and DIFF IOUTB is: The full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 mA to 20 mA via an exter- V = (I – I ) · R (7) DIFF OUTA OUTB LOAD . The external resistor, in combination with nal resistor, R SET Substituting the values of I , I , and I ; V can be OUTA OUTB REF DIFF both the reference control amplifier and voltage reference expressed as: , sets the reference current I , which is mirrored over to V REFIO REF V = {(2 DAC CODE – 255)/256}/ · (32 R /R ) the segmented current sources with the proper scaling factor. DIFF LOAD SET , is thirty-two times the value of I .· V (8) The full-scale current, I REFIO OUTFS REF DAC TRANSFER FUNCTION VOLTAGE REFERENCE AND CONTROL AMPLIFIER The AD9708 provides complementary current outputs, IOUTA The AD9708 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external refer- and IOUTB. IOUTA will provide a near full-scale current output, , when all bits are high (i.e., DAC CODE = 255), while ence. REFIO serves as either an input or output depending on I OUTFS whether the internal or an external reference is selected. If IOUTB, the complementary output, provides no current. The REFLO is tied to ACOM, as shown in Figure 13, the internal current output appearing at IOUTA and IOUTB are a function and can be expressed as: reference is activated and REFIO provides a 1.20 V output. In of both the input code and I OUTFS this case, the internal reference must be compensated externally I = (DAC CODE/256) · I (1) OUTA OUTFS with a ceramic chip capacitor of 0.1mF or greater from REFIO I = (255 – DAC CODE)/256 · I (2) OUTB OUTFS to REFLO. Note that REFIO is not designed to drive any ex- ternal load. It should be buffered with an external amplifier where DAC CODE = 0 to 255 (i.e., Decimal Representation). having an input bias current less than 100 nA if any additional loading is required. +5V 0.1mF REFLO COMP1 AVDD ACOM +1.20V REF 50pF AD9708 0.1mF V REFIO REFIO COMP2 CURRENT SOURCE I REF 0.1mF FS ADJ ARRAY R SET V = V – V DIFF OUTA OUTB 2kV DVDD +5V I IOUTA OUTA V OUTA SEGMENTED I DCOM IOUTB OUTB SWITCHES V OUTB R LOAD CLOCK 50V R LOAD CLOCK LATCHES 50V SLEEP DIGITAL DATA INPUTS (DB7–DB0) Figure 12. Functional Block Diagram REV. B –7– AD9708 +5V The small signal bandwidth of the reference control amplifier is 0.1mF approximately 1.8 MHz and can be reduced by connecting an OPTIONAL EXTERNAL external capacitor between COMP1 and AVDD. The output of REF BUFFER REFLO COMP1 AVDD the control amplifier, COMP1, is internally compensated via a +1.2V REF 50 pF capacitor that limits the control amplifier small-signal 50pF bandwidth and reduces its output impedance. Any additional REFIO CURRENT ADDITIONAL external capacitance further limits the bandwidth and acts as SOURCE FS ADJ LOAD 0.1mF ARRAY a filter to reduce the noise contribution from the reference 2kV AD9708 amplifier. If I is fixed for an application, a 0.1mF ceramic chip REF capacitor is recommended. Figure 13. Internal Reference Configuration I can be varied for a fixed R by disabling the internal REF SET reference and varying the common-mode voltage over its The internal reference can be disabled by connecting REFLO to compliance range of 1.25 V to 0.10 V. REFIO can be driven by AVDD. In this case, an external reference may then be applied a single-supply amplifier or DAC, thus allowing I to be var- REF to REFIO as shown in Figure 14. The external reference may ied for a fixed R . Since the input impedance of REFIO is SET provide either a fixed reference voltage to enhance accuracy and approximately 1 MW, a simple R-2R ladder DAC configured in drift performance or a varying reference voltage for gain control. the voltage mode topology may be used to control the gain. This Note that the 0.1mF compensation capacitor is not required circuit is shown in Figure 15 using the AD7524 and an external since the internal reference is disabled, and the high input 1.2 V reference, the AD1580. Note another AD9708 could also impedance (i.e., 1 MW) of REFIO minimizes any loading of the be used as the gain control DAC since it can also provide a external reference. programmable unipolar output up to 1.2 V. AVDD ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS 0.1mF The AD9708 produces two complementary current outputs, I and I , which may be converted into complementary OUTA OUTB single-ended voltage outputs, V and V , via a load resistor, REFLO COMP1 AVDD OUTA OUTB AVDD R , as described in the DAC TRANSFER FUNCTION +1.2V REF LOAD 50pF section. Figure 16 shows the AD9708 configured to provide a V REFIO REFIO EXTERNAL CURRENT positive unipolar output range of approximately 0 V to +0.5 V REF SOURCE FS ADJ ARRAY for a double terminated 50 W cable for a nominal full-scale R SET I = REF current, I , of 20 mA. In this case, R represents the OUTFS LOAD V /R REFERENCE REFIO SET AD9708 equivalent load resistance seen by IOUTA or IOUTB and is CONTROL AMPLIFIER equal to 25 W. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching R . Different LOAD Figure 14. External Reference Configuration values of I and R can be selected as long as the posi- OUTFS LOAD tive compliance range is adhered to. The AD9708 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I . OUTFS The control amplifier is configured as a V-I converter, as shown AD9708 I = 20mA OUTFS V = 0 TO +0.5V OUTA in Figure 14, such that its current output, I , is determined by REF IOUTA 22 the ratio of the V and an external resistor, R , as stated REFIO SET 50V 50V in Equation 4. The control amplifier allows a wide (10:1) IOUTB 21 adjustment span of I over a 2 mA to 20 mA range by setting OUTFS 25V I between 62.5mA and 625mA. The wide adjustment span of REF I provides several application benefits. The first benefit OUTFS Figure 16. 0 V to +0.5 V Unbuffered Voltage Output relates directly to the power dissipation of the AD9708, which is proportional to I (refer to the POWER DISSIPATION OUTFS Alternatively, an amplifier could be configured as an I-V converter section). The second benefit relates to the 20 dB adjustment, thus converting IOUTA or IOUTB into a negative unipolar which is useful for system gain control purposes. AVDD OPTIONAL AVDD BANDLIMITING CAPACITOR REFLO COMP1 AVDD +1.2V REF R V FB DD 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V REF CURRENT OUT2 FS ADJ SOURCE AD1580 ARRAY AGND R I = SET REF AD9708 V /R REF SET DB7–DB0 Figure 15. Single-Supply Gain Control Circuit REV. B –8– AD9708 voltage. Figure 17 shows a buffered singled-ended output con- over a digital supply range of 2.7 V to 5.5 V. As a result, the figuration in which the op amp, U1, performs an I-V conversion digital inputs can also accommodate TTL levels when DVDD is on the AD9708 output current. U1 provides a negative unipolar set to accommodate the maximum high level voltage, V , OH(MAX) output voltage and its full-scale output voltage is simply the of the TTL drivers. A DVDD of 3 V to 3.3 V will typically product of R and I . The full-scale output should be set FB OUTFS ensure upper compatibility of most TTL logic families. within U1’s voltage output swing capabilities by scaling I OUTFS DVDD and/or R . An improvement in ac distortion performance may FB result with a reduced I , since the signal current U1 will be OUTFS required to sink and will be subsequently reduced. Note, the ac DIGITAL distortion performance of this circuit at higher DAC update INPUT rates may be limited by U1’s slewing capabilities. C OPT R FB Figure 18. Equivalent Digital Input 200V I = 10mA OUTFS AD9708 Since the AD9708 is capable of being updated up to 125 MSPS, 22 IOUTA the quality of the clock and data input signals are important in U1 V = I 3 R OUT OUTFS FB achieving the optimum performance. The drivers of the digital IOUTB 21 data interface circuitry should be specified to meet the minimum 200V setup-and-hold times of the AD9708 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result Figure 17. Unipolar Buffered Voltage Output in the lowest data feedthrough and noise. IOUTA and IOUTB also have a negative and positive voltage Digital signal paths should be kept short and run lengths matched compliance range that must be adhered to in order to achieve to avoid propagation delay mismatch. The insertion of a low optimum performance. The positive output compliance range is value resistor network (i.e., 20W to 100W) between the AD9708 slightly dependent on the full-scale output current, I . It OUTFS digital inputs and driver outputs may be helpful in reducing any degrades slightly from its nominal 1.25 V for an I = 20 mA OUTFS overshooting and ringing at the digital inputs that contribute to to 1.00 V for an I = 2 mA. Applications requiring the OUTFS data feedthrough. For longer run lengths and high data update AD9708’s output (i.e., V and/or V ) to extend up to its OUTA OUTB rates, strip line techniques with proper termination resistors output compliance range should size R accordingly. Operation LOAD should be considered to maintain “clean” digital inputs. Also, beyond this compliance range will adversely affect the AD9708’s operating the AD9708 with reduced logic swings and a corre- linearity. sponding digital supply (DVDD) will also reduce data feedthrough. The differential voltage, V , existing between V and DIFF OUTA The external clock driver circuitry should provide the AD9708 V may also be converted to a single-ended voltage via a OUTB with a low jitter clock input meeting the min/max logic levels transformer or differential amplifier configuration. Refer to the while providing fast edges. Fast clock edges will help minimize DIFFERENTIAL OUTPUT CONFIGURATION section for any jitter that will manifest itself as phase noise on a recon- more information. structed waveform. However, the clock input could also be driven by via a sine wave, which is centered around the digital DIGITAL INPUTS threshold (i.e., DVDD/2), and meets the min/max logic threshold. The AD9708’s digital input consists of eight data input pins and This may result in a slight degradation in the phase noise, which a clock input pin. The 8-bit parallel data inputs follow standard becomes more noticeable at higher sampling rates and output positive binary coding where DB7 is the most significant bit frequencies. Note, at higher sampling rates the 20% tolerance (MSB) and DB0 is the least significant bit (LSB). The digital of the digital logic threshold should be considered since it will interface is implemented using an edge-triggered master slave affect the effective clock duty cycle and subsequently cut into latch. The DAC output is updated following the rising edge of the required data setup-and-hold times. the clock as shown in Figure 1 and is designed to support a clock rate as high as 125 MSPS. The clock can be operated at SLEEP MODE OPERATION any duty cycle that meets the specified latch pulsewidth. The The AD9708 has a power-down function that turns off the setup-and-hold times can also be varied within the clock cycle as output current and reduces the supply current to less than 8.5 mA long as the specified minimum times are met; although the over the specified supply range of 2.7 V to 5.5 V and tempera- location of these transition edges may affect digital feedthrough ture range. This mode can be activated by applying a logic level and distortion performance. “1” to the SLEEP pin. This digital input also contains an active The digital inputs are CMOS compatible with logic thresholds, pull-down circuit that ensures the AD9708 remains enabled if V set to approximately half the digital positive supply THRESHOLD this input is left disconnected. The SLEEP input with active (DVDD) or pull-down requires <40mA of drive current. V = DVDD/2 (–20%) THRESHOLD The power-up and power-down characteristics of the AD9708 Figure 18 shows the equivalent digital input circuit for the data are dependent on the value of the compensation capacitor con- and clock inputs. The sleep mode input is similar, except that nected to COMP2 (Pin 23). With a nominal value of 0.1mF, the it contains an active pull-down circuit, thus ensuring that the AD9708 takes less than 5ms to power down and approximately AD9708 remains enabled if this input is left disconnected. The 3.25 ms to power back up. internal digital circuitry of the AD9708 is capable of operating REV. B –9– AD9708 18 8 30 125MSPS 125MSPS 16 25 100MSPS 14 100MSPS 6 20 12 10 4 15 8 50MSPS 50MSPS 10 6 2 25MSPS 25MSPS 4 5 2 5MSPS 5MSPS 0 0 0 22 46 8 10 12 14 16 180 0.01 0.1 1 0.01 0.1 1 RATIO (f /f ) I – mA RATIO (f /f ) OUT CLK OUTFS OUT CLK Figure 21. I vs. Ratio Figure 19. I vs. I Figure 20. I vs. Ratio DVDD AVDD OUTFS DVDD @ DVDD = 3 V @ DVDD = 5 V POWER DISSIPATION FERRITE BEADS The power dissipation, P , of the AD9708 is dependent on D AVDD TTL/CMOS several factors, including: (1) AVDD and DVDD, the power LOGIC 10-22mF 0.1mF 100mF CIRCUITS ELECT. TANT. CER. , the full-scale current output; (3) supply voltages; (2) I OUTFS ACOM , the update rate; (4) and the reconstructed digital input f CLOCK waveform. The power dissipation is directly proportional to the , and the digital supply current, analog supply current, I AVDD I is directly proportional to I , as shown in +5V OR +3V I DVDD. AVDD OUTFS POWER SUPPLY . Figure 19, and is insensitive to f CLOCK Conversely, I is dependent on both the digital input wave- Figure 22. Differential LC Filter for Single +5 V or +3 V DVDD , and digital supply DVDD. Figures 20 and 21 form, f Applications CLOCK as a function of full-scale sine wave output ratios show I DVDD Maintaining low noise on power supplies and ground is critical /f ) for various update rates with DVDD = 5 V and (f OUT CLOCK to obtaining optimum results from the AD9708. If properly is reduced by more DVDD = 3 V, respectively. Note, how I DVDD implemented, ground planes can perform a host of functions on than a factor of 2 when DVDD is reduced from 5 V to 3 V. high speed circuit boards: bypassing, shielding, current trans- port, etc. In mixed signal design, the analog and digital portions APPLYING THE AD9708 of the board should be distinct from each other, with the analog Power and Grounding Considerations ground plane confined to the areas covering the analog signal In systems seeking to simultaneously achieve high speed and traces, and the digital ground plane confined to areas covering high performance, the implementation and construction of the the digital interconnects. printed circuit board design is often as important as the circuit All analog ground pins of the DAC, reference and other analog design. Proper RF techniques must be used in device selection components, should be tied directly to the analog ground plane. placement and routing and supply bypassing and grounding. The two ground planes should be connected by a path 1/8 to The evaluation board for the AD9708, which uses a four layer 1/4 inch wide underneath or within 1/2 inch of the DAC to PC board, serves as a good example for the above mentioned maintain optimum performance. Care should be taken to ensure considerations. The evaluation board provides an illustration of that the ground plane is uninterrupted over crucial signal paths. the recommended printed circuit board ground, power and On the digital side, this includes the digital input lines running signal plane layouts. to the DAC as well as any clock signals. On the analog side, this Proper grounding and decoupling should be a primary objective includes the DAC output signal, reference signal and the supply in any high speed system. The AD9708 features separate analog feeders. and digital supply and ground pins to optimize the management The use of wide runs or planes in the routing of power lines is of analog and digital ground currents in a system. In general, also recommended. This serves the dual role of providing a low AVDD, the analog supply, should be decoupled to ACOM, the series impedance power supply to the part, as well as providing analog common, as close to the chip as physically possible. Simi- some “free” capacitive decoupling to the appropriate ground larly, DVDD, the digital supply, should be decoupled to DCOM plane. It is essential that care be taken in the layout of signal and as close as physically as possible. power ground interconnects to avoid inducing extraneous For those applications requiring a single +5 V or +3 V supply voltage drops in the signal ground paths. It is recommended that for both the analog and digital supply, a clean analog supply all connections be short, direct and as physically close to the may be generated using the circuit shown in Figure 22. The package as possible in order to minimize the sharing of conduc- circuit consists of a differential LC filter with separate power tion paths between different currents. When runs exceed an inch supply and return lines. Lower noise can be attained using low in length, strip line techniques with proper termination resistor ESR type electrolytic and tantalum capacitors. REV. B –10– I – mA AVDD I – mA DVDD I – mA DVDD AD9708 500V should be considered. The necessity and value of this resistor will be dependent upon the logic family used. AD9708 225V IOUTA 22 For a more detailed discussion of the implementation and AD8072 construction of high speed, mixed signal printed circuit boards, 225V IOUTB 21 refer to Analog Devices’ application notes AN-280 and AN-333. C OPT 500V DIFFERENTIAL OUTPUT CONFIGURATIONS 25V 25V For applications requiring the optimum dynamic performance and/or a bipolar output swing, a differential output configura- Figure 24. DC Differential Coupling Using an Op Amp tion is suggested. A differential output configuration may con- sists of either an RF transformer or a differential op amp The common-mode rejection of this configuration is typically configuration. The transformer configuration is well suited for determined by the resistor matching. In this circuit, the differ- ac coupling applications. It provides the optimum high fre- ential op amp circuit is configured to provide some additional quency performance due to its excellent rejection of common- signal gain. The op amp must operate off a dual supply since its mode distortion (i.e., even-order harmonics) and noise over a output is approximately –1.0 V. A high speed amplifier capable wide frequency range. It also provides electrical isolation and of preserving the differential performance of the AD9708 while the ability to deliver twice the power to the load (i.e., assuming meeting other system level objectives (i.e., cost, power) should no source termination). The differential op amp configuration is be selected. The op amps differential gain, its gain setting resis- suitable for applications requiring dc coupling, a bipolar output, tor values and full-scale output swing capabilities should all be signal gain, and/or level shifting. considered when optimizing this circuit. Figure 23 shows the AD9708 in a typical transformer coupled The differential circuit shown in Figure 25 provides the neces- output configuration. The center-tap on the primary side of the sary level-shifting required in a single supply system. In this transformer must be connected to ACOM to provide the necessary case, AVDD, which is the positive analog supply for both the dc current path for both IOUTA and IOUTB. The complemen- AD9708 and the op amp, is also used to level-shift the differ- tary voltages appearing at IOUTA and IOUTB (i.e., V and ential output of the AD9762 to midsupply (i.e., AVDD/2). OUTA V ) swing symmetrically around ACOM and should be OUTB 500V maintained within the specified output compliance range of the AD9708. A differential resistor, R , may be inserted in AD9708 DIFF 225V 22 applications in which the output of the transformer is connected IOUTA to the load, R , via a passive reconstruction filter or cable. AD8072 LOAD 225V 21 R is determined by the transformer’s impedance ratio and IOUTB DIFF C OPT 1kV provides the proper source termination. Note that approxi- AVDD mately half the signal power will be dissipated across R . DIFF 25V 25V 1kV MINI-CIRCUITS T1-1T IOUTA 22 Figure 25. Single-Supply DC Differential Coupled Circuit R AD9708 LOAD AD9708 EVALUATION BOARD IOUTB 21 General Description OPTIONAL R DIFF The AD9708-EB is an evaluation board for the AD9708 8-bit D/A converter. Careful attention to layout and circuit design, Figure 23. Differential Output Using a Transformer combined with a prototyping area, allows the user to easily and effectively evaluate the AD9708 in any application where high An op amp can also be used to perform a differential to single- resolution, high speed conversion is required. ended conversion as shown in Figure 24. The AD9708 is configured with two equal load resistors, R , of 25 W. The LOAD This board allows the user the flexibility to operate the AD9708 differential voltage developed across IOUTA and IOUTB is in various configurations. Possible output configurations include converted to a single-ended signal via the differential op amp transformer coupled, resistor terminated, inverting/noninverting configuration. An optional capacitor can be installed across and differential amplifier outputs. The digital inputs are IOUTA and IOUTB forming a real pole in a low-pass filter. designed to be driven directly from various word generators, The addition of this capacitor also enhances the op amps distortion with the on-board option to add a resistor network for proper performance by preventing the DACs high slewing output from load termination. Provisions are also made to operate the overloading the op amp’s input. AD9708 with either the internal or external reference, or to exercise the power-down feature. Refer to the application note AN-420 “Using the AD9760/ AD9762/AD9764-EB Evaluation Board” for a thorough description and operating instructions for the AD9708 evalua- tion board. REV. B –11– AD9708 Figure 26. Evaluation Board Schematic REV. B –12– DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP4 TP6 TP7 TP2 TP18 TP5 CLK TP1 J1 C3 C4 C5 C6 JP1 A A A AB 10mF 10mF 10mF 10mF EXTCLK 3 1 2 R15 DVDD DVDD 49.9V R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 1mF 0.1mF 0.1mF AD9708 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 1 C19 1 16 1 28 DB13 CLOCK A 4 3 C1 2 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD 11 C27 6 11 6 12 23 DB8 COMP2 OUT 1 C28 7 7 22 14 13 10 DB7 I OUTA OUT 2 C29 8 21 16 15 8 9 DB6 I OUTB 18 17 20 9 DB5 ACOM 20 19 10 19 COMP1 DB4 22 21 18 11 DB3 FS ADJ 24 23 16 PINDIP 17 12 DB2 REFIO 26 25 RES PK 16 13 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 30 29 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2kV 36 35 C33 4 13 C11 C10 38 37 A TP14 C34 5 12 0.1mF 0.1mF 1 40 39 C35 6 11 C36 7 10 2 JP4 JP2 3 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R2 R6 R4 R8 R17 49.9V DVDD DVDD AVCC R18 1kV AVCC AVCC U7 J3 A C21 C22 R42 3 B OUT1 JP6A JP7B 0.1mF 1mF REF43 C17 JP7A 1kV U4 2 6 JP3 0.1mF VIN VOUT 2 3 J6 J7 JP8 7 A R12 C18 C16 GND C12 6 U6 R20 1 A A OPEN AD8047 0.1mF 1mF 22pF B B B 49.9V 4 3 T1 7 2 R37 R43 4 C20 A 49.9V 5kV 4 6 R10 CW A 3 0 A A AD8047 A A 1kV 2 5 A A A R14 A 4 AVEE 0 JP6B A EXTREFIN R36 1 JP5 C14 J5 1kV R45 6 1mF 1kV 3 2 1 A R13 R9 R35 A J4 OPEN A C15 1kV 1kV R44 C23 C24 OUT2 0.1mF 50V R46 0.1mF 1mF JP9 A A A 1kV B A R38 C13 A A 22pF 49.9V AVEE A A AD9708 Figure 27. Silkscreen Layer—Top Figure 28. Component Side PCB Layout (Layer 1) REV. B –13– AD9708 Figure 29. Ground Plane PCB Layout (Layer 2) Figure 30. Power Plane PCB Layout (Layer 3) REV. B –14– AD9708 Figure 31. Solder Side PCB Layout (Layer 4) Figure 32. Silkscreen Layer—Bottom REV. B –15– AD9708 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 14 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) 3 458 0.0926 (2.35) 0.0098 (0.25) 88 0.0118 (0.30) 0.0500 0.0192 (0.49) SEATING 08 0.0500 (1.27) 0.0125 (0.32) (1.27) PLANE 0.0040 (0.10) 0.0138 (0.35) 0.0157 (0.40) 0.0091 (0.23) BSC 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0256 (0.65) 0.0118 (0.30) 0° 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) –16– REV. B 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) PRINTED IN U.S.A. C2979b–1–4/99