ANALOG DEVICES AD9649

14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter AD9649 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB DRVDD 1.8 V analog supply operation 1.8 V to 3.3 V output supply RBIAS SPI SNR VCM 74.3 dBFS at 9.7 MHz input OR PROGRAMMING DATA 71.5 dBFS at 200 MHz input D13 (MSB) VIN+ ADC SFDR CORE VIN– 93 dBc at 9.7 MHz input D0 (LSB) 80 dBc at 200 MHz input DCO VREF Low power SENSE 45 mW at 20 MSPS REF AD9649 87 mW at 80 MSPS SELECT Differential input with 700 MHz bandwidth MODE DIVIDE BY On-chip voltage reference and sample-and-hold circuit 1, 2, 4 CONTROLS 2 V p-p differential analog input DNL = ±0.35 LSB CLK+ CLK– PDWN DFS MODE Serial port control options Figure 1. Offset binary, gray code, or twos complement data format Integer 1, 2, or 4 input clock divider PRODUCT HIGHLIGHTS Built-in selectable digital test pattern generation Energy-saving power-down modes 1. The AD9649 operates from a single 1.8 V analog power Data clock out (DCO) with programmable clock and data supply and features a separate digital output driver supply alignment to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent APPLICATIONS performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. Communications 3. A standard serial port interface (SPI) supports various Diversity radio systems product features and functions, such as data output format- Multimode digital receivers ting, internal clock divider, power-down, DCO, data output GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA (D13 to D0) timing and offset adjustments, and voltage Smart antenna systems Battery-powered instruments reference modes. Handheld scope meters 4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP Portable medical imaging that is pin compatible with the AD9629 12-bit ADC and Ultrasound the AD9609 10-bit ADC, enabling a simple migration path Radar/LIDAR between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS. Rev. Rev. 0 0 IIn nffo orma rmattio ion n furn furniish she ed d b by y A An na allo og g D De ev viic ce es s is is be belliie ev ved ed tto o be be a ac cc cu ur ra atte e an and d r re elliia ab ble le. H . Ho ow we ev ve er r,, n no o r res esp pons onsi ib bi il li it ty y i is s a assu ssumed b med by y A An na al log og De Dev vi ic ce es f s fo or it r its use s use, , nor f nor fo or an r any y inf infrin ringe gemen ment ts s o of f p pa at ten ent ts s o or r o ot the her r O One T ne Te echnology chnology Way, Way, P P..O. O. B Bo ox 91 x 9106, 06, Nor Norw wood ood,, MA 020 MA 02062- 62-910 9106, 6, U. U.S S..A. A. r ri ig gh hts o ts of f th thir ird d par part ties ies th tha at t m ma ay y r re esu sul lt t f fr ro om m i it ts s use use. . S Sp pe eci cif fica icat tio ion ns s su subj bje ec ct t t to o c ch han ang ge e w wi ith tho ou ut n t no oti tic ce e. . N No o T Te el: l: 781. 781.329. 329.4 4700 700 w ww ww w. .analog analog.c .com om l li ic ce en ns se e i is s g gr ran ant te ed d b by y imp impl lic ica at tio ion n o or r o ot th he er rw wi is se e un und de er an r any y pa pat te en nt t o or r pa pat te en nt t r ri ig gh ht ts s o of f A An na al lo og g D De ev vi ic ce es s. . Fax: Fax: 781. 781.461. 461.31 3113 13 © ©2009 A 2009 Analog De nalog Devices, vices, I Inc. nc. Al All r l right ights r s re eser served ved. . T Tr radem ademar arks ks and and r reg egi ist ste er red ed tr trad adema emarks rks ar are e the the p pr ro op per ert ty y of of the thei ir r r re esp spe ec ct ti iv ve e o owne wners rs. . CMOS OUTPUT BUFFER 08539-001 AD9649 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 19  Applications ....................................................................................... 1  Clock Input Considerations ...................................................... 20  Functional Block Diagram .............................................................. 1  Power Dissipation and Standby Mode .................................... 21  Product Highlights ........................................................................... 1  Digital Outputs ........................................................................... 22  Revision History ............................................................................... 2  Timing ......................................................................................... 22  General Description ......................................................................... 3  Built-In Self-Test (BIST) and Output Test .................................. 23  Specif ica t ions ..................................................................................... 4  Built-In Self-Test (BIST) ............................................................ 23  DC Specifications ......................................................................... 4  Output Test Modes ..................................................................... 23  AC Specifications .......................................................................... 5  Serial Port Interface (SPI) .............................................................. 24  Digital Specifications ................................................................... 6  Configuration Using the SPI ..................................................... 24  Switching Specifications .............................................................. 7  Hardware Interface ..................................................................... 25  Timing Specifications .................................................................. 8  Configuration Without the SPI ................................................ 25  Absolute Maximum Ratings ............................................................ 9  SPI Accessible Features .............................................................. 25  Thermal Characteristics .............................................................. 9  Memory Map .................................................................................. 26  ESD Caution .................................................................................. 9  Reading the Memory Map Register Table ............................... 26  Pin Configuration and Function Descriptions ........................... 10  Open Locations .......................................................................... 26  Typical Performance Characteristics ........................................... 11  Default Values ............................................................................. 26  AD9649-80 .................................................................................. 11  Memory Map Register Table ..................................................... 27  AD9649-65 .................................................................................. 13  Memory Map Register Descriptions ........................................ 29  AD9649-40 .................................................................................. 14  Applications Information .............................................................. 30  AD9649-20 .................................................................................. 15  Design Guidelines ...................................................................... 30  Equivalent Circuits ......................................................................... 16  Outline Dimensions ....................................................................... 31  Theory of Operation ...................................................................... 17  Ordering Guide .......................................................................... 31  Analog Input Considerations .................................................... 17  REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9649 GENERAL DESCRIPTION deterministic and pseudorandom patterns, along with custom The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, user-defined test patterns entered via the serial port interface (SPI). 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip volt- A differential clock input with optional 1, 2, or 4 divide ratios age reference. controls all internal conversion cycles. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, gray code, or with output error correction logic to provide 14-bit accuracy at twos complement format. A data output clock (DCO) is provided 80 MSPS data rates and to guarantee no missing codes over the to ensure proper latch timing with receiving logic. Both 1.8 V and full operating temperature range. 3.3 V CMOS levels are supported. The ADC contains several features designed to maximize The AD9649 is available in a 32-lead RoHS-compliant LFCSP and flexibility and minimize system cost, such as programmable is specified over the industrial temperature range (−40°C to clock and data alignment and programmable digital test pattern +85°C). generation. The available digital test patterns include built-in Rev. 0 | Page 3 of 32 AD9649 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 1. AD9649-20/AD9649-40 AD9649-65 AD9649-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.40 +0.05 +0.50 −0.40 +0.05 +0.50 −0.40 +0.05 +0.50 % FSR 1 Gain Error Full −1.5 −1.5 −1.5 % FSR 2 Differential Nonlinearity (DNL) Full ±0.50 +0.55 ±0.65 LSB 25°C ±0.25 ±0.3 ±0.35 LSB 2 Integral Nonlinearity (INL) Full ±1.30 ±1.30 ±1.75 LSB 25°C ±0.50 ±0.50 ±0.60 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.984 0.996 1.008 0.984 0.996 1.008 0.984 0.996 1.008 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.98 0.98 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p 3 Input Capacitance Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 IAVDD Full 25.0/31.3 27.3/33.7 41.0 44.0 47.0 50.0 mA 2 IDRVDD (1.8 V) Full 1.6/2.9 4.7 5.6 mA 2 IDRVDD (3.3 V) Full 3.0/5.3 8.4 10.2 mA POWER CONSUMPTION DC Input Full 45.2/57.2 75.2 86.8 mW 2 Sine Wave Input (DRVDD = 1.8 V) Full 47.9/61.6 51.8/65.8 82.3 87.5 94.7 100 mW 2 Sine Wave Input (DRVDD = 3.3 V) Full 54.9/73.8 101.5 118.3 mW 4 Standby Power Full 34/34 34 34 mW Power-Down Power Full 0.5 0.5 0.5 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and ground. 4 Standby power is measured with a dc input and the CLK+, CLK− active. Rev. 0 | Page 4 of 32 AD9649 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 2. AD9649-20/AD9649-40 AD9649-65 AD9649-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 74.7 74.5 74.3 dBFS IN f = 30.5 MHz 25°C 74.4 74.3 74.1 dBFS IN Full 73.1 73.6 dBFS fIN = 70 MHz 25°C 73.7 73.7 73.6 dBFS Full 72.7 dBFS fIN = 200 MHz 25°C 71.5 71.5 71.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 74.6 74.4 74.1 dBFS fIN = 30.5 MHz 25°C 74.3 74.2 74.0 dBFS Full 73.0 73.5 dBFS f = 70 MHz 25°C 73.6 73.6 73.5 dBFS IN Full 72.6 dBFS fIN = 200 MHz 25°C 70.0 70.0 70.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.0 12.0 12.0 Bits fIN = 30.5 MHz 25°C 12.0 12.0 12.0 Bits fIN = 70 MHz 25°C 11.9 11.9 11.9 Bits f = 200 MHz 25°C 11.3 11.3 11.3 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −95 −93 dBc f = 30.5 MHz 25°C −95 −95 −93 dBc IN Full −82 −83 dBc fIN = 70 MHz 25°C −94 −94 −92 dBc Full −82 dBc fIN = 200 MHz 25°C −80 −80 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 94 94 93 dBc Full 82 83 dBc f = 70 MHz 25°C 93 93 92 dBc IN Full 82 dBc fIN = 200 MHz 25°C 80 80 80 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −100 −100 −100 dBc IN fIN = 30.5 MHz 25°C −100 −100 −100 dBc Full −90 −90 dBc f = 70 MHz 25°C −100 −100 −100 dBc IN Full −90 dBc f = 200 MHz 25°C −95 −95 −95 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc IN ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 32 AD9649 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 3. AD9649-20/AD9649-40/AD9649-65/AD9649-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (I) OH IOH = 50 μA Full 3.29 V IOH = 0.5 mA Full 3.25 V Low Level Output Voltage (IOL) I = 1.6 mA Full 0.2 V OL I = 50 μA Full 0.05 V OL DRVDD = 1.8 V High Level Output Voltage (IOH) IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V Low Level Output Voltage (I) OL I = 1.6 mA Full 0.2 V OL IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 32 AD9649 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 4. AD9649-20/AD9649-40 AD9649-65 AD9649-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 80/160 260 320 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period, Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (t) Full 3 3 3 ns DCO DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 8 8 8 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO t SKEW DATA N – 8 N – 7 N – 6 N – 5 N – 4 t PD Figure 2. CMOS Output Data Timing Rev. 0 | Page 7 of 32 08539-002 AD9649 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Rev. 0 | Page 8 of 32 AD9649 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip 1 AVDD to AGND −0.3 V to +2.0 V and must be soldered to the analog ground plane of the user’s 1 DRVDD to AGND −0.3 V to +3.9 V PCB. Soldering the exposed paddle to the user’s board also 1 VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V increases the reliability of the solder joints and maximizes the 1 CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. 1 VREF to AGND −0.3 V to AVDD + 0.2 V 1 Table 7. Thermal Resistance SENSE to AGND −0.3 V to AVDD + 0.2 V 1 Airflow VCM to AGND −0.3 V to AVDD + 0.2 V Package Velocity 1 RBIAS to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 1,2 Type (m/sec) θJA θJC θJB ΨJT Unit 1 CSB to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 0.3 °C/W 1 SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 0.5 °C/W 1 SDIO/PDWN to AGND −0.3 V to DRVDD + 0.3 V 2.5 29.1 0.8 °C/W 1 MODE/OR to AGND −0.3 V to DRVDD + 0.3 V 1 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. D0 through D13 to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 1 DCO to AGND −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Typical θJA is specified for a 4-layer PCB with a solid ground Storage Temperature Range (Ambient) −65°C to +150°C plane. As shown in Table 7, airflow improves heat dissipation, 1 AGND refers to the analog ground of the customer’s PCB. which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and Stresses above those listed under Absolute Maximum Ratings power planes, reduces the θ . JA may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any ESD CAUTION other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 32 AD9649 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 24 AVDD PIN 1 CLK– 2 23 MODE/OR INDICATOR AVDD 3 22 DCO CSB 4 21 D13 (MSB) AD9649 SCLK/DFS 5 20 D12 TOP VIEW SDIO/PDWN 6 19 D11 (Not to Scale) D0 (LSB) 7 18 D10 D1 8 17 D9 NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 (EP) GND Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise, and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for the ADC CORE Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. See Table 14 for details. 7 to 12, 14 to 21 D0 (LSB) to ADC Digital Outputs. D13 (MSB) 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input in SPI Mode (MODE). Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100). Chip stand-by (SPI Register 0x08, Bits[7:5] = 101). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111). In non-SPI mode, the pin operates only as an out-of-range (OR) digital output. 25 VREF 1.0 V Voltage Reference Input/Output. See Table 10. 26 SENSE Reference Mode Selection. See Table 10. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. 0 | Page 10 of 32 08539-003 D2 9 32 AVDD D3 10 31 VIN+ D4 11 30 VIN– D5 12 29 AVDD DRVDD 13 28 RBIAS D6 14 27 VCM D7 15 26 SENSE D8 16 25 VREF AD9649 TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 0 80MSPS 80MSPS 30.5MHz @ –1dBFS 9.7MHz @ –1dBFS –15 –15 SNR = 73.2dB (74.2dBFS) SNR = 73.4dB (74.4dBFS) SFDR = 94.4dBc SFDR = 93.6dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 3 3 2 5 6 4 2 5 6 4 –105 –105 –120 –120 4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9649-80 Single-Tone FFT with f = 9.7 MHz IN Figure 7. AD9649-80 Single-Tone FFT with fIN = 30.5 MHz 0 0 80MSPS 80MSPS 200MHz @ –1dBFS 70.3MHz @ –1dBFS –15 –15 SNR = 70.5dB (71.5dBFS) SNR = 72.1dB (73.1dBFS) SFDR = 80.2dBc SFDR = 93.5dBc –30 –30 –45 –45 –60 –60 –75 –75 23 –90 2 –90 3 6 4 5 –105 6 4 5 –105 –120 –120 4 8 12 16 2024283236 4 8 12 16 20 24283236 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9649-80 Single-Tone FFT with fIN = 70.3 MHz Figure 8. AD9649-80 Single-Tone FFT with f = 200 MHz IN 0 0 80MSPS 30.5MHz @ –7dBFS –15 32.5MHz @ –7dBFS –20 SFDR = 89.5dBc (96.5dBFS) –30 SFDR (dBc) –40 –45 IMD3 (dBc) –60 –60 –75 –80 –90 2F1 + F2 2F2 + F1 SFDR (dBFS) F2–F1 2F1 – F2 2F2 – F1 F1 + F2 –100 –105 IMD3 (dBFS) –120 –120 4 8 12 16 20 24 28 32 36 –90 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 6. AD9649-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz Figure 9. AD9649-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 30.5 MHz and f = 32.5 MHz IN1 IN2 Rev. 0 | Page 11 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08539-062 08539-033 08539-200 SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08539-036 08539-034 08539-054 AD9649 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 100 120 SFDR (dBc) 90 SFDRFS 100 80 70 80 SNR (dBFS) 60 SNRFS 60 50 SFDR 40 40 30 SNR 20 20 10 0 0 0 50 100 150 200 –90 –80 –60 –40 –20 0 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 13. AD9649-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 10. AD9649-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 450,000 120 400,000 SFDR (dBc) 100 350,000 SNR (dBFS) 300,000 80 250,000 60 200,000 40 150,000 100,000 20 50,000 0 0 10 20 30 40 50 60 70 80 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 OUTPUT CODE SAMPLE RATE (MSPS) Figure 14. AD9649-80 Grounded Input Histogram Figure 11. AD9649-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 2.0 0.5 0.4 1.5 0.3 1.0 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 –1.5 –0.4 –2.0 –0.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE OUTPUT CODE Figure 12. AD9649-80 DNL Error with f = 9.7 MHz Figure 15. AD9649-80 INL with f = 9.7 MHz IN IN Rev. 0 | Page 12 of 32 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08539-038 08539-055 08539-057 INL ERROR (LSB) NUMBER OF HITS SNR/SFDR (dBFS) 08539-061 08539-037 08539-048 AD9649 AD9649-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 120 65MSPS 9.7MHz @ –1dBFS –15 SFDRFS SNR = 73.5dB (74.5dBFS) 100 SFDR = 97.7dBc –30 80 –45 SNRFS –60 60 SFDR –75 40 –90 SNR 3 2 5 4 6 –105 20 –120 0 3 6 9 12 1518 21 2427 30 –90 –80 –60 –40 –20 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 16. AD9649-65 Single-Tone FFT with fIN = 9.7 MHz Figure 19.AD9649-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 100 0 65MSPS 70.3MHz @ –1dBFS 90 –15 SFDR (dBc) SNR = 72.6dB (73.6dBFS) SFDR = 94.1dBc 80 –30 70 SNR (dBFS) –45 60 –60 50 –75 40 30 –90 2 4 356 20 –105 10 –120 0 3 6 9 12 1518 21 2427 30 0 50 100 150 200 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. AD9649-65 Single-Tone FFT with f = 70.3 MHz Figure 20. AD9649-65 SNR/SFDR vs. Input Frequency (AIN) IN with 2 V p-p Full Scale 0 65MSPS 30.5MHz @ –1dBFS –15 SNR = 73.3dB (74.3dBFS) SFDR = 99.3dBc –30 –45 –60 –75 –90 3 2 5 –105 6 4 –120 3 6 9 12 1518 21 2427 30 FREQUENCY (MHz) Figure 18. AD9649-65 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 13 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08539-031 08539-030 08539-032 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS) 08539-056 08539-060 AD9649 AD9649-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 120 40MSPS 9.7MHz @ –1dBFS –15 SFDRFS SNR = 73.5dB (74.5dBFS) 100 SFDR = 95.4dBc –30 80 –45 SNRFS –60 60 SFDR –75 40 –90 SNR 2 4 5 3 6 –105 20 –120 0 2 4 6 8 10 12 14 16 18 –90 –80 –60 –40 –20 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 21. AD9649-40 Single-Tone FFT with fIN = 9.7 MHz Figure 23. AD9649-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 40MSPS 30.5MHz @ –1dBFS –15 SNR = 73.2dB (74.2dBFS) SFDR = 95.7dBc –30 –45 –60 –75 –90 4 5 3 2 –105 6 –120 2 4 6 8 10 12 14 16 18 FREQUENCY (MHz) Figure 22. AD9649-40 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 14 of 32 AMPLITUDE (dBFS) AMPLITUDE (dB) 08539-029 08539-028 SNR/SFDR (dBFS) 08539-059 AD9649 AD9649-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 120 20MSPS 9.7MHz @ –1dBFS –15 SFDR (dBFS) SNR = 73.5dBFS (74.5dBFS) 100 SFDR = 97.2dBc –30 80 SNR (dBFS) –45 –60 60 SFDR (dBc) –75 40 –90 SNR (dBc) 4 3 2 6 5 –105 20 –120 0 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 24. AD9649-20 Single-Tone FFT with fIN = 9.7 MHz Figure 26. AD9649-20 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN 0 20MSPS 30.5MHz @ –1dBFS –15 SNR = 73.2dB (74.2dBFS) SFDR = 98.1dBc –30 –45 –60 –75 –90 3 2 4 6 5 –105 –120 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) Figure 25. AD9649-20 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 15 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08539-026 08539-024 SNR/SFDR (dBc/dBFS) 08539-058 AD9649 EQUIVALENT CIRCUITS DRVDD AVDD VIN± Figure 27. Equivalent Analog Input Circuit Figure 31. Equivalent D0 to D13 and OR Digital Output Circuit DRVDD AVDD SCLK/DFS, 350Ω MODE, 375Ω SDIO/PDWN VREF 30kΩ 7.5kΩ Figure 32. Equivalent SCLK/DFS, MODE and SDIO/PDWN Input Circuit Figure 28. Equivalent VREF Circuit AVDD DRVDD AVDD 30kΩ 375Ω 350Ω SENSE CSB Figure 29. Equivalent SENSE Circuit Figure 33. Equivalent CSB Input Circuit 5Ω CLK+ 15kΩ 0.9V AVDD 15kΩ 5Ω CLK– 375Ω RBIAS AND VCM Figure 30. Equivalent Clock Input Circuit Figure 34. Equivalent RBIAS, VCM Circuit Rev. 0 | Page 16 of 32 08539-039 08539-046 08539-040 08539-047 08539-042 08539-045 08539-044 08539-043 AD9649 THEORY OF OPERATION high IF frequencies. Either a shunt capacitor or two single-ended The AD9649 architecture consists of a multistage, pipelined ADC. capacitors can be placed on the inputs to provide a matching pas- Each stage provides sufficient overlap to correct for flash errors in sive network. This ultimately creates a low-pass filter at the input the preceding stage. The quantized outputs from each stage are to limit unwanted broadband noise. See the AN-742 Application combined into a final 14-bit result in the digital correction logic. Note, the AN-827 Application Note, and the Analog Dialogue The pipelined architecture permits the first stage to operate with article, “Transformer-Coupled Front-End for Wideband A/D a new input sample, whereas the remaining stages operate with pre- Converters” (Volume 39, April 2005) for more information. In ceding samples. Sampling occurs on the rising edge of the clock. general, the precise values depend on the application. Each stage of the pipeline, excluding the last, consists of a low Input Common Mode resolution flash ADC connected to a switched-capacitor DAC The analog inputs of the AD9649 are not internally dc-biased. and an interstage residue amplifier (for example, a multiplying Therefore, in ac-coupled applications, the user must provide an digital-to-analog converter (MDAC)). The residue amplifier external dc bias. Setting the device so that VCM = AVDD/2 magnifies the difference between the reconstructed DAC output is recommended for optimum performance, but the device can and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction function over a wider range with reasonable performance, as of flash errors. The last stage consists of a flash ADC. shown in Figure 36 and Figure 37. 100 The output staging block aligns the data, corrects errors, and SFDR (dBc) passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjust- 90 ment of the output voltage swing. During power-down, the output buffers go into a high impedance state. 80 SNR (dBFS) ANALOG INPUT CONSIDERATIONS The analog input to the AD9649 is a differential switched- 70 capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range 60 while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize 50 signal-dependent errors and achieve optimum performance. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 INPUT COMMON-MODE VOLTAGE (V) Figure 36. SNR/SFDR vs. Input Common-Mode Voltage, f = 32.1 MHz, f = 80 MSPS IN S H C PAR H 100 VIN+ C SAMPLE SS SFDR (dBc) 90 SS C SAMPLE VIN– H C PAR 80 SNR (dBFS) H 70 Figure 35. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between 60 sample mode and hold mode (see Figure 35). When the input circuit is switched to sample mode, the signal source must be 50 capable of charging the sample capacitors and settling within one- 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 INPUT COMMON-MODE VOLTAGE (V) half of a clock cycle. A small resistor in series with each input Figure 37. SNR/SFDR vs. Input Common-Mode Voltage, can help reduce the peak transient current injected from the output fIN = 10.3 MHz, fS = 20 MSPS stage of the driving source. In addition, low Q inductors or ferrite An on-board, common-mode voltage reference is included in beads can be placed on each leg of the input to reduce high differ- the design and is available from the VCM pin. The VCM pin ential capacitance at the analog inputs and, therefore, achieve the must be decoupled to ground by a 0.1 μF capacitor, as described maximum bandwidth of the ADC. Such use of low Q inductors or in the Applications Information section. ferrite beads is required when driving the converter front end at Rev. 0 | Page 17 of 32 08539-006 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08539-050 08539-049 AD9649 Differential Input Configurations the true SNR performance of the AD9649. For applications above ~10 MHz where SNR is a key parameter, differential double balun Optimum performance is achieved while driving the AD9649 coupling is the recommended input configuration (see Figure 41). in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers An alternative to using a transformer-coupled input at frequencies provide excellent performance and a flexible interface to the ADC. in the second Nyquist zone is to use the AD8352 differential driver. The output common-mode voltage of the ADA4938-2 is easily An example is shown in Figure 42. See the AD8352 data sheet set with the VCM pin of the AD9649 (see Figure 38), and the for more information. driver can be configured in a Sallen-Key filter topology to In any configuration, the value of Shunt Capacitor C is dependent provide band limiting of the input signal. on the input frequency and source impedance and may need to 200Ω 33Ω be reduced or removed. Table 9 displays the suggested values to set VIN– VIN 76.8Ω AVDD the RC network. However, these values are dependent on the 90Ω 10pF ADA4938-2 ADC input signal and should be used only as a starting guide. 0.1µF 120Ω 33Ω VCM VIN+ Table 9. Example RC Network 200Ω R Series Frequency Range (MHz) (Ω Each) C Differential (pF) Figure 38. Differential Input Configuration Using the ADA4938-2 0 to 70 33 22 For baseband applications below ~10 MHz where SNR is a key 70 to 200 125 Open parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 39. To bias Single-Ended Input Configuration the analog input, the VCM voltage can be connected to the A single-ended input can provide adequate performance in cost- center tap of the secondary winding of the transformer. sensitive applications. In this configuration, SFDR and distortion VIN+ R performance degrade due to the large input common-mode swing. 2V p-p 49.9Ω If the source impedances on each input are matched, there should C ADC be little effect on SNR performance. Figure 40 shows a typical R VCM VIN– single-ended input configuration. 0.1µF 10µF AVDD 1kΩ R Figure 39. Differential Transformer-Coupled Configuration VIN+ 1V p-p 0.1µF 49.9Ω 1kΩ The signal characteristics must be considered when selecting AVDD C ADC a transformer. Most RF transformers saturate at frequencies 1kΩ R below a few megahertz (MHz). Excessive signal power can also VIN– 10µF 0.1µF 1kΩ cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the Figure 40. Single-Ended Input Configuration noise performance of most amplifiers is not adequate to achieve 0.1µF 0.1µF R VIN+ 2V p-p 25Ω P S S P C A ADC 0.1µF 25Ω 0.1µF R VCM VIN– Figure 41. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+ 2 200Ω C ADC R R AD8352 C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN– 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 42. Differential Input Configuration Using the AD8352 Rev. 0 | Page 18 of 32 08539-007 08539-008 08539-010 08539-011 08539-009 AD9649 0 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the –0.5 AD9649. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. –1.0 The various reference modes are summarized in the sections INTERNAL VREF = 0.996V that follow. The Reference Decoupling section describes the –1.5 best practices PCB layout of the reference. –2.0 Internal Reference Connection A comparator within the AD9649 detects the potential at the –2.5 SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the –3.0 reference amplifier switch is connected to the internal resistor 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 divider (see Figure 43), setting VREF to 1.0 V. LOAD CURRENT (mA) Figure 44. VREF Accuracy vs. Load Current VIN+ 4 VIN– 3 2 ADC VREF ERROR (mV) CORE 1 0 VREF –1 1.0µF 0.1µF SELECT –2 LOGIC –3 SENSE –4 0.5V –5 –6 ADC –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 43. Internal Reference Configuration Figure 45. Typical VREF Drift If the internal reference of the AD9649 is used to drive multiple When the SENSE pin is tied to AVDD, the internal reference is converters to improve gain matching, the loading of the reference disabled, allowing the use of an external reference. An internal by the other converters must be considered. Figure 44 shows reference buffer loads the external reference with an equivalent how the internal reference voltage is affected by loading. 7.5 kΩ load (see Figure 28). The internal buffer generates the External Reference Operation positive and negative full-scale references for the ADC core. The use of an external reference may be necessary to enhance Therefore, the external reference must be limited to a maximum the gain accuracy of the ADC or improve thermal drift charac- of 1.0 V. teristics. Figure 45 shows the typical drift characteristics of the internal reference in 1.0 V mode. Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. 0 | Page 19 of 32 08539-012 REFERENCE VOLTAGE ERROR (%) V ERROR (mV) REF 08539-052 08539-014 AD9649 This limit helps prevent the large voltage swings of the clock CLOCK INPUT CONSIDERATIONS from feeding through to other portions of the AD9649 while For optimum performance, clock the AD9649 sample clock inputs, preserving the fast rise and fall times of the signal that are critical CLK+ and CLK−, with a differential signal. The signal is typi- to a low jitter performance. cally ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 46) and If a low jitter clock source is not available, another option is to require no external bias. ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 49. The AD9510/AD9511/AD9512/ AVDD AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.9V CLK+ CLK– 0.1µF 0.1µF CLOCK CLK+ 2pF 2pF INPUT AD951x 100Ω ADC PECL DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 46. Equivalent Clock Input Circuit Clock Input Options Figure 49. Differential PECL Sample Clock (Up to 4× Rated Sample Rate) The AD9649 has a very flexible clock input structure. The clock A third option is to ac couple a differential LVDS signal to the input can be a CMOS, LVDS, LVPECL, or sine wave signal. sample clock input pins as shown in Figure 50. The AD9510/ Regardless of the type of signal being used, clock source jitter is AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 of great concern, as described in the Jitter Considerations section. clock drivers offer excellent jitter performance. Figure 47 and Figure 48 show two preferred methods for clock- ing the AD9649. The CLK inputs support up to 4× the rated sample 0.1µF 0.1µF rate when using the internal clock divider feature. A low jitter clock CLOCK CLK+ INPUT source is converted from a single-ended signal to a differential AD951x 100Ω ADC signal using either an RF transformer or an RF balun. LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT ® 50kΩ 50kΩ Mini-Circuits ADT1-1WT, 1:1 Z 0.1µF 0.1µF XFMR Figure 50. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate) CLOCK CLK+ INPUT 100Ω 50Ω ADC In some applications, it may be acceptable to drive the sample 0.1µF CLK– clock inputs with a single-ended 1.8 V CMOS signal. In such SCHOTTKY 0.1µF applications, drive the CLK+ pin directly from a CMOS gate, and DIODES: HSMS2822 bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 47. Transformer-Coupled Differential Clock (3 MHz to 200 MHz) Figure 51). V CC OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω 1nF 0.1µF CLOCK CMOS DRIVER CLK+ CLOCK CLK+ INPUT INPUT 1 1kΩ 50Ω 50Ω ADC ADC 0.1µF 1nF CLK– CLK– SCHOTTKY 0.1µF DIODES: HSMS2822 1 50Ω RESISTOR IS OPTIONAL. Figure 48. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate) Figure 51. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) The RF balun configuration is recommended for clock frequen- Input Clock Divider cies between 80 MHz and 320 MHz, and the RF transformer is recommended for clock frequencies from 3 MHz to 200 MHz. The AD9649 contains an input clock divider with the ability to divide the input clock by integer values of 1, 2, or 4. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9649 to ~0.8 V p-p differential. Rev. 0 | Page 20 of 32 08539-016 08539-018 08539-017 08539-021 08539-020 08539-019 AD9649 Clock Duty Cycle supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best Typical high speed ADCs use both clock edges to generate a clock sources. If the clock is generated from another type of source variety of internal timing signals and, as a result, may be sensitive (by gating, dividing, or another method), it should be retimed by to clock duty cycle. Commonly, a 50% duty cycle clock with ±5% the original clock at the last step. tolerance is required to maintain optimum dynamic performance, as shown in Figure 52. For more information, see the AN-501 Application Note and the AN-756 Application Note, which are available on www.analog.com. Jitter on the rising edge of the clock input can also impact dynamic performance and should be minimized, as discussed in the Jitter POWER DISSIPATION AND STANDBY MODE Considerations section of this datasheet. As shown in Figure 54, the analog core power dissipated by the 80 AD9649 is proportional to its sample rate. The digital power dis- sipation of the CMOS outputs are determined primarily by the 75 strength of the digital drivers and the load on each output bit. 70 The maximum DRVDD current (I ) can be calculated as DRVDD 65 I = V × C × f × N DRVDD DRVDD LOAD CLK 60 where N is the number of output bits (15, in the case of the 55 AD9649). This maximum current occurs when every output bit switches 50 on every clock cycle, that is, a full-scale square wave at the Nyquist 45 frequency of f /2. In practice, the DRVDD current is estab- CLK lished by the average number of output bits that are switching, 40 10 20 30 40 50 60 70 80 which is determined by the sample rate and the characteristics POSITIVE DUTY CYCLE (%) of the analog input signal. Figure 52. SNR vs. Clock Duty Cycle Reducing the capacitive load presented to the output drivers can Jitter Considerations minimize digital power consumption. The data in Figure 54 was High speed, high resolution ADCs are sensitive to the quality taken using the same operating conditions as those used for the of the clock input. The degradation in SNR from the low fre- Typical Performance Characteristics, with a 5 pF load on each quency SNR (SNR ) at a given input frequency (f ) due to LF INPUT output driver. jitter (tJRMS) can be calculated by 85 2 (−SNR /10) LF 80 SNRHF = −10 log[(2π × fINPUT × tJRMS) + 10 ] 75 In the previous equation, the rms aperture jitter represents the AD9649-80 clock input jitter specification. IF undersampling applications 70 are particularly sensitive to jitter, as illustrated in Figure 53. 65 80 AD9649-65 60 55 75 0.05ps 50 AD9649-40 70 45 0.2ps 65 40 AD9649-20 35 10 20 30 40 50 60 70 80 60 0.5ps CLOCK RATE (MSPS) 55 Figure 54. Analog Core Power vs. Clock Rate 1.0ps 1.5ps In SPI mode, the AD9649 can be placed in power-down mode 50 2.0ps directly via the SPI port or by using the programmable external 2.5ps 3.0ps 45 MODE pin. In non-SPI mode, power-down is achieved by assert- 1 10 100 1k ing the PDWN pin high. In this state, the ADC typically dissipates FREQUENCY (MHz) 500 μW. During power-down, the output drivers are placed in a Figure 53. SNR vs. Input Frequency and Jitter high impedance state. Asserting the PDWN pin (or the MODE pin The clock input should be treated as an analog signal in cases in in SPI mode) low returns the AD9649 to normal operating mode. which aperture jitter may affect the dynamic range of the AD9649. Note that PDWN is referenced to the digital output driver supply To avoid modulating the clock signal with digital noise, keep power (DRVDD) and should not exceed that supply voltage. Rev. 0 | Page 21 of 32 SNR (dBFS) SNR (dBFS) 08539-022 08539-053 ANALOG CORE POWER (mW) 08539-051 AD9649 Low power dissipation in power-down mode is achieved by shut- Digital Output Enable Function (OEB) ting down the reference, reference buffer, biasing networks, and When using the SPI interface, the data outputs and DCO can be clock. Internal capacitors are discharged when entering power- independently three-stated by using the programmable external down mode and then must be recharged when returning to normal MODE pin. The OEB function of the MODE pin is enabled via operation. As a result, wake-up time is related to the time spent Bits[6:5] of Register 0x08. in power-down mode, and shorter power-down cycles result in If the MODE pin is configured to operate in traditional OEB mode proportionally shorter wake-up times. and the MODE pin is low, the output data drivers and DCOs are When using the SPI port interface, the user can place the ADC enabled. If the MODE pin is high, the output data drivers and in power-down mode or standby mode. Standby mode allows DCOs are placed in a high impedance state. This OEB function the user to keep the internal reference circuitry powered when is not intended for rapid access to the data bus. Note that the faster wake-up times are required. See the Memory Map section for MODE pin is referenced to the digital output driver supply more details. (DRVDD) and should not exceed that supply voltage. DIGITAL OUTPUTS TIMING The AD9649 output drivers can be configured to interface with The AD9649 provides latched data with a pipeline delay of eight 1.8 V to 3.3 V CMOS logic families. Output data can also be multi- clock cycles. Data outputs are available one propagation delay (tPD) plexed onto a single output bus to reduce the total number of traces after the rising edge of the clock signal. required. Minimize the length of the output data lines and loads placed on The CMOS output drivers are sized to provide sufficient output them to reduce transients within the AD9649. These transients may current to drive a wide variety of logic families. However, large degrade converter dynamic performance. drive currents tend to cause current glitches on the supplies and The lowest typical conversion rate of the AD9649 is 3 MSPS. may affect converter performance. At clock rates below 3 MSPS, dynamic performance may degrade. Applications requiring the ADC to drive large capacitive loads Data Clock Output (DCO) or large fanouts may require external buffers or latches. The AD9649 provides a data clock output (DCO) signal that is The output data format can be selected to be either offset binary intended for capturing the data in an external register. The CMOS or twos complement by setting the SCLK/DFS pin when operating data outputs are valid on the rising edge of DCO, unless the DCO in the external pin mode (see Table 11). clock polarity has been changed via the SPI. See Figure 2 for a As detailed in the AN-877 Application Note, Interfacing to High graphical timing description. Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 11. SCLK/DFS and SDIO/PDWN Mode Selection (External Pin Mode) Voltage at Pin SCLK/DFS SDIO/PDWN GND Offset binary (default) Normal operation (default) DRVDD Twos complement Outputs disabled Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1 Rev. 0 | Page 22 of 32 AD9649 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9649 includes a built-in test feature designed to enable runs the BIST, enabling Bit 0 (BIST enable) of Register 0x0E verification of the integrity of each channel, as well as facilitate and resetting the PN sequence generator, Bit 2 (BIST init) of board-level debugging. Also included is a built-in self-test (BIST) Register 0x0E. Upon completion of the BIST, Bit 0 of Register 0x24 feature that verifies the integrity of the digital datapath of the is automatically cleared. The PN sequence can be continued from AD9649. Various output test options are also provided to place its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the predictable values on the outputs of the AD9649. PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. The user must BUILT-IN SELF-TEST (BIST) then rely on verifying the output data. The BIST is a thorough test of the digital portion of the selected OUTPUT TEST MODES AD9649 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During the BIST test, data from The output test options are described in Table 16 at Address 0x0D. an internal pseudorandom noise (PN) source is driven through When an output test mode is enabled, the analog section of the the digital datapath of both channels, starting at the ADC block ADC is disconnected from the digital back end blocks and the output. At the datapath output, CRC logic calculates a signature test pattern is run through the output formatting block. Some of from the data. The BIST sequence runs for 512 cycles and then the test patterns are subject to output formatting, and some are stops. When the BIST sequence is complete, the BIST compares not. The PN generators from the PN sequence tests can be reset the signature results with a predetermined value. If the signatures by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be per- match, the BIST sets Bit 0 of Register 0x24, signifying that the formed with or without an analog signal (if present, the analog test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared. signal is ignored), but they do require an encode clock. For more The outputs are connected during this test so that the PN sequence information, see the AN-877 Application Note, Interfacing to can be observed as it runs. Writing the value 0x05 to Register 0x0E High Speed ADCs via SPI. Rev. 0 | Page 23 of 32 AD9649 SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of The AD9649 SPI allows the user to configure the converter for SCLK, determines the start of the framing. An example of the specific functions or operations through a structured register space serial timing and its definitions can be found in Figure 55 and provided inside the ADC. The SPI gives the user added flexibility Table 5. and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via Other modes involving the CSB are available. The CSB can be the port. Memory is organized into bytes that can be further held low indefinitely, which permanently enables the device; divided into fields, which are documented in the Memory Map this is called streaming. The CSB can stall high between bytes to section. For detailed operational information, see the AN-877 allow for additional external timing. When CSB is tied high, SPI Application Note, Interfacing to High Speed ADCs via SPI. functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK (SCLK/DFS, Data follows the instruction phase, and its length is determined the SDIO (SDIO/PDWN), and the CSB (see Table 13). The SCLK by the W0 and W1 bits, as shown in Figure 55. (a serial clock) is used to synchronize the read and write data All data is composed of 8-bit words. The first bit of the first byte in presented from and to the ADC. The SDIO (serial data input/ a multibyte serial data transfer frame indicates whether a read com- output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB mand or a write command is issued. This allows the serial data (chip select bar) is an active-low control that enables or disables input/output (SDIO) pin to change direction from an input to the read and write cycles. an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines Table 13. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial clock. The serial shift clock input, which is used to the contents of the on-chip memory. If the instruction is a readback synchronize serial interface reads and writes. operation, performing a readback causes the serial data input/ SDIO Serial data input/output. A dual-purpose pin that output (SDIO) pin to change direction from an input to an output typically serves as an input or an output, depending on the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip select bar. An active-low control that gates the read first is the default on power-up and can be changed via the SPI and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 55. Serial Port Interface Timing Diagram Rev. 0 | Page 24 of 32 08539-023 AD9649 In this mode, connect the CSB chip select to DRVDD, which HARDWARE INTERFACE disables the serial port interface. The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port Table 14. Mode Selection of the AD9649. The SCLK pin and the CSB pin function as inputs External when using the SPI interface. The SDIO pin is bidirectional, Pin Voltage Configuration functioning as an input during write phases and as an output SDIO/PDWN DRVDD Chip power-down mode during readback. AGND (default) Normal operation (default) SCLK/DFS DRVDD Twos complement enabled The SPI interface is flexible enough to be controlled by either AGND (default) Offset binary enabled FPGAs or microcontrollers. For detailed information about one method for SPI configuration, refer to the AN-812 Application SPI ACCESSIBLE FEATURES Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Table 15 provides a brief description of the general features that The SPI port should not be active during periods when the full are accessible via the SPI. These features are described in detail dynamic performance of the converter is required. Because the in the AN-877 Application Note, Interfacing to High Speed ADCs SCLK signal, the CSB signal, and the SDIO signal are typically via SPI. The AD9649 part-specific features are described in detail asynchronous to the ADC clock, noise from these signals can in Table 16. degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this Table 15. Features Accessible Using the SPI bus and the AD9649 to prevent these signals from transitioning Feature Description at the converter inputs during critical sampling periods. Modes Allows the user to set either power-down mode or standby mode The SDIO/PDWN and SCLK/DFS pins serve a dual function when Offset Adjust Allows the user to digitally adjust the converter the SPI interface is not being used. When the pins are strapped offset to DRVDD or ground during device power-on, they are associated Test Mode Allows the user to set test modes to have known with a specific function. The Digital Outputs section describes data on output bits the strappable functions supported on the AD9649. Output Mode Allows the user to set up outputs CONFIGURATION WITHOUT THE SPI Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay In applications that do not interface to the SPI control registers, the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the power-down and output data format feature control. Rev. 0 | Page 25 of 32 AD9649 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) contains After the AD9649 is reset, critical registers are loaded with default eight bit locations. The memory map is roughly divided into four values. The default values for the registers are given in the memory sections: the chip configuration registers (Address 0x00 to map register table (see Table 16). Address 0x02); the device transfer registers (Address 0xFF); the Logic Levels program registers, including setup, control, and test (Address 0x08 An explanation of logic level terminology follows: to Address 0x2A); and the digital feature control registers (Address 0x101). • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 16 documents the default hexadecimal value for each • “Clear a bit” is synonymous with “bit is set to Logic 0” or hexadecimal address shown. The column with the heading Bit 7 “writing Logic 0 for the bit.” (MSB) is the start of the default hexadecimal value given. For example, Address 0x2A, the OR/MODE select register, has a hexa- Transfer Register Map decimal default value of 0x01. This means that in Address 0x2A, Address 0x08 to Address 0x18 are shadowed. Writes to these Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE addresses do not affect part operation until a transfer command setting. The default value results in the programmable external is issued by writing 0x01 to Address 0xFF, setting the transfer bit. MODE/OR pin (Pin 23) functioning as an out-of-range digital This allows these registers to be updated internally and simulta- output. For more information on this function and others, see the neously when the transfer bit is set. The internal update takes AN-877 Application Note, Interfacing to High Speed ADCs via SPI. place when the transfer bit is set, and then the bit autoclears. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x101, is docu- mented in the Memory Map Register Descriptions section that follows Table 16. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these loca- tions is required only when part of an address location is open (for example, Address 0x2A). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. 0 | Page 26 of 32 AD9649 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Def. Default Value Addr. (MSB) (LSB) Notes/ (Hex) Bit 7 Bit 0 (Hex) Comments Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Chip configuration registers 0x00 SPI port 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles are configuration reset reset mirrored so that LSB or MSB first mode registers correctly, regard- less of shift mode. 0x01 Chip ID 8-bit chip ID, Bits[7:0] Read Unique chip ID AD9649 = 0x6F only used to differen- tiate devices; read only. 0x02 Chip grade Open Speed grade ID, Bits[6:4] Open Read Unique speed (identify device variants of chip ID) only grade ID used to differentiate 20 MSPS = 000 devices; read 40 MSPS = 001 only. 65 MSPS = 010 80 MSPS = 011 Device transfer registers 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave. Program registers 0x08 Modes External External Pin 23 Open Open Open 00 = chip run 0x00 Determines Pin 23 function when high 01 = full power-down various generic MODE 00 = full power-down 10 = standby modes of chip input 01 = standby 11 = chip wide operation. enable 10 = normal mode, digital reset output disabled 11 = normal mode, output enabled 0x0B Clock divide Open Clock divider, Bits[2:0] 0x00 The divide ratio Clock divide ratio is the value + 1. 000 = divide-by-1 001 = divide-by-2 011 = divide-by-4 0x0D Test mode User test mode Reset PN Reset PN Output test mode, Bits[3:0] (local) 0x00 When set, the 00 = single long gen short test data is 0000 = off (default) 01 = alternate gen placed on the 0001 = midscale short 10 = single once output pins in 0010 = positive FS 11 = alternate once place of normal 0011 = negative FS data. 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle 1000 = user input 1001 = 1/0 bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x0E BIST enable Open Open Open Open Open BIST init Open BIST 0x00 When Bit 0 is set, enable the built-in self- test function is initiated. 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) 0x00 Device offset Offset adjust in LSBs from +127 to −128 (twos complement format) trim. Rev. 0 | Page 27 of 32 AD9649 Def. Default Value Addr. (MSB) (LSB) Notes/ (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0x14 Output mode 00 = 3.3 V CMOS Open Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS disable invert 01 = twos outputs and the complement format of the 10 = gray code data. 11 = offset binary 0x15 Output adjust 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data 0x22 Determines drive strength drive strength drive strength drive strength CMOS output 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe drive strength (default) 01 = 2 stripes (default) 01 = 2 stripes properties. 01 = 2 stripes 10 = 3 stripes 01 = 2 stripes 10 = 3 stripes 10 = 3 stripes (default) 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 Output phase DCO Open Open Open Open Input clock phase adjust, 0x00 On devices that output Bits[2:0] use global clock polarity (Value is number of input clock divide, deter- cycles of phase delay) mines which 0 = phase of the normal 000 = no delay divider output is 1 = inv 001 = 1 input clock cycle used to supply 010 = 2 input clock cycles the output clock; 011 = 3 input clock cycles internal latching 100 = 4 input clock cycles is unaffected. 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 Output delay Enable Open Enable Open DCO/data delay, Bits[2:0] 0x00 Sets the fine DCO data 000 = 0.56 ns output delay of delay delay 001 = 1.12 ns the output clock 010 = 1.68 ns but does not 011 = 2.24 ns change internal 100 = 2.80 ns timing. 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined Pattern 1 LSB. 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined Pattern 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined Pattern 2 LSB. 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined Pattern 2 MSB. 0x24 BIST signature LSB BIST signature, Bits[7:0] 0x00 Least significant byte of BIST sig- nature, read only. 0x2A OR/MODE select Open Open Open Open Open Open Open 0 = 0x01 Selects I/O MODE functionality in 1 = OR conjunction with (default) Address 0x08 for MODE (input) or OR (output) on External Pin 23. Digital feature control register 0x101 USR2 1 Open Open Open Enable Run Open Disable 0x88 Enables internal GCLK GCLK SDIO oscillator for detect pull- clock rates of down <5 MHz. Rev. 0 | Page 28 of 32 AD9649 Bit 2—Run GCLK MEMORY MAP REGISTER DESCRIPTIONS Bit 2 enables the GCLK oscillator. For some applications with For additional information about functions controlled in encode rates below 10 MSPS, it may be preferable to set this bit Register 0x00 to Register 0xFF, see the AN-877 Application high to supersede the GCLK detector. Note, Interfacing to High Speed ADCs via SPI. Bit 0—Disable SDIO Pull-Down USR2 (Register 0x101) Bit 0 can be set high to disable the internal 30 kΩ pull-down on Bit 3—Enable GCLK Detect the SDIO pin, which can be used to limit the loading when many Normally set high, Bit 3 enables a circuit that detects encode devices are connected to the SPI bus. rates below ~5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled, ensuring the proper oper- ation of several circuits. If set low, the detector is disabled. Rev. 0 | Page 29 of 32 AD9649 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting the design and layout of the AD9649 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements needed for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9649, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V supply (LFCSP), at www.analog.com. for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and Encode Clock DRVDD supply must be used, the AVDD and DRVDD domains For optimum dynamic performance, use a low jitter encode must be isolated with a ferrite bead or filter choke and separate clock source with a 50% duty cycle (±5%) to clock the AD9649. decoupling capacitors. Several different decoupling capacitors can VCM be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close The VCM pin should be decoupled to ground with a 0.1 μF to the pins of the part, with minimal trace length. capacitor, as shown in Figure 39. A single PCB ground plane should be sufficient when using the RBIAS AD9649. With proper decoupling and smart partitioning of the The AD9649 requires that a 10 kΩ resistor be placed between PCB analog, digital, and clock sections, optimum performance the RBIAS pin and ground. This resistor sets the master current is easily achieved. reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations Reference Decoupling The exposed paddle (Pin 0) is the only ground connection for Externally decouple the VREF pin to ground with a low ESR, the AD9649; therefore, it must be connected to analog ground 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic (AGND) on the customer’s PCB. To achieve the best electrical capacitor. and thermal performance, mate an exposed (no solder mask) SPI Port continuous copper plane on the PCB to the AD9649 exposed The SPI port should not be active during periods when the full paddle, Pin 0. dynamic performance of the converter is required. Because the The copper plane should have several vias to achieve the lowest SCLK, CSB, and SDIO signals are typically asynchronous to the possible resistive thermal path for heat dissipation to flow through ADC clock, noise from these signals can degrade converter the bottom of the PCB. Fill or plug these vias with nonconduc- performance. If the on-board SPI bus is used for other devices, tive epoxy. it may be necessary to provide buffers between this bus and the AD9649 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 30 of 32 AD9649 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 EXPOSED 3.65 BSC TOP 4.75 PAD VIEW 3.50 SQ BSC SQ (BOTTOM VIEW) 3.35 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 FUNCTION DESCRIPTIONS 0.30 COPLANARITY SECTION OF THIS DATA SHEET. 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 56. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1, 2 AD9649BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9649BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1 AD9649-80EBZ Evaluation Board 1 AD9649-65EBZ Evaluation Board 1 AD9649-40EBZ Evaluation Board 1 AD9649-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. Rev. 0 | Page 31 of 32 100608-A AD9649 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08539-0-10/09(0) Rev. 0 | Page 32 of 32