ANALOG DEVICES AD9648

14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9648 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SPI SNR = 74.5 dBFS @ 70 MHz ORA SFDR = 91 dBc @ 70 MHz PROGRAMMING DATA D13A Low power: 78 mW/channel ADC core @ 125 MSPS VIN+A ADC Differential analog input with 650 MHz bandwidth VIN–A D0A IF sampling frequencies to 200 MHz DCOA On-chip voltage reference and sample-and-hold circuit VREF 2 V p-p differential analog input SENSE DRVDD AD9648 DNL = ±0.35 LSB REF VCM SELECT Serial port control options ORB RBIAS Offset binary, gray code, or twos complement data format D13B VIN–B Optional clock duty cycle stabilizer ADC VIN+B Integer 1-to-8 input clock divider D0B Data output multiplex option DCOB Built-in selectable digital test pattern generation DIVIDE DUTY CYCLE MODE Energy-saving power-down modes 1 TO 8 STABILIZER CONTROLS Data clock out with programmable clock and data alignment CLK+ CLK– SYNC DCS PDWN DFS OEB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; APPLICATIONS SEE FIGURE 7 FOR LVDS PIN NAMES. Communications Figure 1. Diversity radio systems Multimode digital receivers PRODUCT HIGHLIGHTS GSM, EDGE, W-CDMA, LTE, 1 CDMA2000, WiMAX, TD-SCDMA 1. The AD9648 operates from a single 1.8 V analog I/Q demodulation systems power supply and features a separate digital output Smart antenna systems driver supply to accommodate 1.8 V CMOS or LVDS Broadband data applications logic families. Battery-powered instruments 2. The patented sample-and-hold circuit maintains Hand held scope meters excellent performance for input frequencies up to Portable medical imaging 200 MHz and is designed for low cost, low power, and Ultrasound ease of use. Radar/LIDAR 3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments. 4. The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9650/ AD9269/AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9628/AD9231 12-bit ADCs, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. 1 This product is protected by a U.S patent. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. 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MUX OPTION CMOS/LVDS CMOS/LVDS OUTPUT BUFFER OUTPUT BUFFER 09975-001 AD9648 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 27  Applications ....................................................................................... 1  Clock Input Considerations ...................................................... 28  Functional Block Diagram .............................................................. 1  Channel/Chip Synchronization ................................................ 30  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 30  Revision History ............................................................................... 2  Digital Outputs ........................................................................... 31  General Description ......................................................................... 3  Timing ......................................................................................... 31  Specif ica t ions ..................................................................................... 4  Built-In Self-Test (BIST) and Output Test .................................. 32  DC Specifications ........................................................................... 4  Built-In Self-Test (BIST) ............................................................ 32  AC Specifications ........................................................................... 5  Output Test Modes ..................................................................... 32  Digital Specifications ................................................................... 6  Serial Port Interface (SPI) .............................................................. 33  Switching Specifications ................................................................ 8  Configuration Using the SPI ..................................................... 33  Timing Specifications .................................................................. 9  Hardware Interface ..................................................................... 34  Absolute Maximum Ratings .......................................................... 12  Configuration Without the SPI ................................................ 34  Thermal Characteristics ............................................................ 12  SPI Accessible Features .............................................................. 34  ESD Caution ................................................................................ 12  Memory Map .................................................................................. 35  Pin Configurations and Function Descriptions ......................... 13  Reading the Memory Map Register Table ............................... 35  Typical Performance Characteristics ........................................... 19  Memory Map Register Table ..................................................... 36  AD9648-125 ................................................................................ 20  Memory Map Register Descriptions ........................................ 39  AD9648-105 ................................................................................ 22  Applications Information .............................................................. 41  Equivalent Circuits ......................................................................... 24  Design Guidelines ...................................................................... 41  Theory of Operation ...................................................................... 25  Outline Dimensions ....................................................................... 42  ADC Architecture ...................................................................... 25  Ordering Guide .......................................................................... 42  Analog Input Considerations .................................................... 25  REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 44 AD9648 GENERAL DESCRIPTION The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, A differential clock input controls all internal conversion cycles. 105 MSPS/125 MSPS analog-to-digital converter (ADC). It An optional duty cycle stabilizer (DCS) compensates for wide features a high performance sample-and-hold circuit and on- variations in the clock duty cycle while maintaining excellent chip voltage reference. overall ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, Gray code, or with output error correction logic to provide 14-bit accuracy at twos complement format. A data output clock (DCO) is provided 125 MSPS data rates and to guarantee no missing codes over the for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. full operating temperature range. Output data can also be multiplexed onto a single output bus. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable The AD9648 is available in a 64-lead RoHS compliant LFCSP and clock and data alignment and programmable digital test pattern is specified over the industrial temperature range (−40°C to generation. The available digital test patterns include built-in +85°C). This product is protected by a U.S. patent. deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 0 | Page 3 of 44 AD9648 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. AD9648-105 AD9648-125 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.8 −0.3 +0.2 −0.8 −0.3 +0.2 % FSR Gain Error Full −4.20 ±1.3 +4.2 −5.1 ±1.3 +5.1 % FSR 1 Differential Nonlinearity (DNL) Full −0.5 +1.2 −0.5 +1.2 LSB 25°C ±0.5 ±0.5 LSB 1 Integral Nonlinearity (INL) Full −2.3 +2.3 −2.3 +2.3 LSB 25°C ±1.0 ±1.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.01 ±0.58 ±0.01 ±0.58 % FSR Gain Error Full ±0.5 ±4.0 ±0.5 ±4.0 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.98 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p 2 Input Capacitance Full 5 5 pF Input Resistance (Differential) Full 7.5 7.5 kΩ Input Common-Mode Voltage Full 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 I Full 81 86 95 100 mA AVDD 1 I (1.8 V CMOS) Full 19.2 22.5 mA DRVDD 1 I (1.8 V LVDS) Full 63.5 65.0 mA DRVDD Rev. 0 | Page 4 of 44 AD9648 AD9648-105 AD9648-125 Parameter Temp Min Typ Max Min Typ Max Unit POWER CONSUMPTION DC Input Full 135.4 155.5 mW Sine Wave Input (DRVDD = 1.8 V CMOS Full 172.3 181.3 202.5 211.5 mW Output Mode) Sine Wave Input (DRVDD = 1.8 V LVDS Full 180.4 189.4 211.5 220.5 mW Output Mode) 3 Standby Power Full 108 120 mW Power-Down Power Full 2.0 2.0 mW 1 Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode). AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. AD9648-105 AD9648-125 1 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) f = 9.7 MHz 25°C 75.4 75.0 dBFS IN f = 30.5 MHz 25°C 75.2 74.7 dBFS IN f = 70 MHz 25°C 74.8 74.5 dBFS IN Full 73.8 73.0 dBFS 25°C 73.8 73.9 dBFS f = 100 MHz IN f = 200 MHz 25°C 71.0 71.5 dBFS IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 9.7 MHz 25°C 74.3 73.9 dBFS IN f = 30.5 MHz 25°C 74.0 73.4 dBFS IN f = 70 MHz 25°C 73.4 73.3 dBFS IN Full 73.0 72.8 dBFS f = 100 MHz 25°C 72.8 72.8 dBFS IN 69.6 70.3 f = 200 MHz 25°C dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) 25°C 12.0 11.9 Bits f = 9.7 MHz IN 25°C 12.0 11.9 Bits f = 30.5 MHz IN 25°C 11.8 11.8 Bits f = 70 MHz IN 25°C 11.8 11.8 Bits f = 100 MHz IN 25°C 11.3 11.4 Bits f = 200 MHz IN WORST SECOND OR THIRD HARMONIC 25°C dBc f = 9.7 MHz −98 −96 IN 25°C dBc f = 30.5 MHz −90 −90 IN 25°C dBc f = 70 MHz −93 −91 IN Full dBc −86 −82 25°C dBc f = 100 MHz −92 −90 IN 25°C dBc f = 200 MHz −81 −84 IN Rev. 0 | Page 5 of 44 AD9648 AD9648-105 AD9648-125 1 Parameter Temp Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) 25°C dBc f = 9.7 MHz 98 96 IN 25°C dBc f = 30.5 MHz 90 90 IN 25°C dBc f = 70 MHz 93 91 IN Full dBc 86 82 25°C dBc fIN = 100 MHz 92 90 25°C dBc fIN = 200 MHz 81 84 WORST OTHER (HARMONIC OR SPUR) 25°C dBc fIN = 9.7 MHz −98 −97 25°C dBc fIN = 30.5 MHz −96 −97 25°C dBc f = 70 MHz −96 −97 IN Full dBc −91 −90 25°C dBc fIN = 100 MHz −92 −92 25°C dBc fIN = 200 MHz −90 −90 TWO-TONE SFDR 25°C dBc fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 84 84 2 Full dB CROSSTALK −95 −95 25°C MHz ANALOG INPUT BANDWIDTH 650 650 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. AD9628-105/125 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND - 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF Rev. 0 | Page 6 of 44 AD9648 AD9628-105/125 Parameter Temp Min Typ Max Unit 2 LOGIC INPUT (SCLK/DFS/SYNC) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUT/OUTPUT (SDIO/DCS) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 2 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V Low Level Output Voltage I = 1.6 mA Full 0.2 V OL I = 50 μA Full 0.05 V OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (V ), Reduced Swing Mode Full 160 200 230 mV OD Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.25 1.35 V OS 1 Pull up. 2 Pull down. Rev. 0 | Page 7 of 44 AD9648 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. AD9648-105 AD9648-125 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 1000 MHz 1 Conversion Rate DCS Enabled Full 20 105 20 125 MSPS DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (t ) Full 9.52 8 ns CLK CLK Pulse Width High (t ) Full 4.76 4 ns CH Aperture Delay (t ) Full 1.0 1.0 ns A Aperture Uncertainty (Jitter, t ) Full 0.07 0.07 ps rms J DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns PD 2 DCO Propagation Delay (t ) Full 2.0 3.1 4.4 2.0 3.1 4.4 ns DCO −0.1 −0.1 DCO to Data Skew (t ) Full −1.2 +1.0 −1.2 +1.0 ns SKEW LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 2.4 2.4 ns PD 2 DCO Propagation Delay (t ) Full 2.4 2.4 ns DCO DCO to Data Skew (t ) Full −0.20 +0.03 +0.25 −0.20 +0.03 +0.25 ns SKEW CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 16/16.5 Cycles 3 Wake-Up Time (Power Down) Full 350 350 µs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. 0 | Page 8 of 44 AD9648 TIMING SPECIFICATIONS Table 5. Unit Parameter Description Limit SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time 0.24 ns typ SSYNC t SYNC to rising edge of CLK+ hold time 0.40 ns typ HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns min DS t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S t Hold time between CSB and SCLK 2 ns min H t SCLK pulse width high 10 ns min HIGH t SCLK pulse width low 10 ns min LOW t Time required for the SDIO pin to switch from an input to an output relative 10 ns min EN_SDIO to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an input relative 10 ns min DIS_SDIO to the SCLK rising edge Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 t PD Figure 2. CMOS Default Output Mode Data Output Timing Rev. 0 | Page 9 of 44 09975-002 AD9648 N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A DATA N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 t PD CH B CH A CH B CH A CH B CH A CH B CH A CH B CH B DATA N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 Figure 3. CMOS Interleaved Output Mode Data Output Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO+ DCO– t SKEW t PD D0+ (LSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D0– (LSB) PARALLEL INTERLEAVED MODE D13+ (MSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D13– (MSB) D1+/0+ (LSB) CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CHANNEL N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D1–/D0– (LSB) MULTIPLEXED MODE D13+/D12+ (MSB) CHANNEL A CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D13–/D12– (MSB) D1+/D0+ (LSB) CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CHANNEL N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D1–/D0– (LSB) MULTIPLEXED MODE D13+/D12+ (MSB) CHANNEL B CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH A12 CH A13 CH A12 N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 D13–/D12– (MSB) Figure 4. LVDS Modes for Data Output Timing Rev. 0 | Page 10 of 44 09975-003 09975-004 AD9648 CLK+ t t SSYNC HSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. 0 | Page 11 of 44 09975-005 AD9648 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating 1 the LFCSP package. Soldering the exposed paddle to the PCB Electrical increases the reliability of the solder joints and maximizes the AVDD to AGND −0.3 V to +2.0 V thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Airflow Velocity SYNC to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 1,2 Package Type (m/sec) θ θ θ Ψ Unit JA JC JB JT VCM to AGND −0.3 V to AVDD + 0.2 V 64-Lead LFCSP 0 22.3 1.4 N/A 0.1 °C/W RBIAS to AGND −0.3 V to AVDD + 0.2 V 9 mm × 9 mm 1.0 19.5 N/A 11.8 0.2 °C/W CSB to AGND −0.3 V to DRVDD + 0.2 V (CP-64-4) 2.5 17.5 N/A N/A 0.2 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 OEB −0.3 V to DRVDD + 0.2 V Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). PDWN −0.3 V to DRVDD + 0.2 V D0A/D0B through D13A/D13B to −0.3 V to DRVDD + 0.2 V Typical θ is specified for a 4-layer PCB with a solid ground JA AGND plane. As shown Table 7, airflow improves heat dissipation, DCOA/DCOB to AGND −0.3 V to DRVDD + 0.2 V which reduces θ . In addition, metal in direct contact with the JA Environmental package leads from metal traces, through holes, ground, and Operating Temperature Range −40°C to +85°C power planes reduces θ . JA (Ambient) Maximum Junction Temperature 150°C Under Bias ESD CAUTION Storage Temperature Range −65°C to +150°C (Ambient) 1 The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) + 0.2 V but should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 12 of 44 AD9648 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS D0B (LSB) 6 43 ORA D1B 7 42 D13A (MSB) AD9648 D2B 8 41 D12A PARALLEL CMOS D3B 9 40 D11A TOP VIEW DRVDD 10 39 D10A (Not to Scale) D4B 11 38 D9A D5B 12 37 DRVDD D6B 13 36 D8A D7B 14 35 D7A D8B 15 34 D6A D9B 16 33 D5A NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 4, 5, 25, 26 NC No Connect. Do not connect to these pins. 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 | Page 13 of 44 D10B 17 64 AVDD D11B 18 63 AVDD DRVDD 19 62 VIN+B D12B 20 61 VIN–B D13B (MSB) 21 60 AVDD ORB 22 59 AVDD DCOB 23 58 RBIAS DCOA 24 57 VCM NC 25 56 SENSE NC 26 55 VREF D0A (LSB) 27 54 AVDD DRVDD 28 53 AVDD D1A 29 52 VIN–A D2A 30 51 VIN+A D3A 31 50 AVDD D4A 32 49 AVDD 09975-006 AD9648 Pin No. Mnemonic Type Description Digital Outputs 27 D0A (LSB) Output Channel A CMOS Output Data. 29 D1A Output Channel A CMOS Output Data. 30 D2A Output Channel A CMOS Output Data. 31 D3A Output Channel A CMOS Output Data. 32 D4A Output Channel A CMOS Output Data. 33 D5A Output Channel A CMOS Output Data. 34 D6A Output Channel A CMOS Output Data. 35 D7A Output Channel A CMOS Output Data. 36 D8A Output Channel A CMOS Output Data. 38 D9A Output Channel A CMOS Output Data. 39 D10A Output Channel A CMOS Output Data. 40 D11A Output Channel A CMOS Output Data. 41 D12A Output Channel A CMOS Output Data. 42 D13A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 6 D0B (LSB) Output Channel B CMOS Output Data. 7 D1B Output Channel B CMOS Output Data. 8 D2B Output Channel B CMOS Output Data. 9 D3B Output Channel B CMOS Output Data. 11 D4B Output Channel B CMOS Output Data. 12 D5B Output Channel B CMOS Output Data. 13 D6B Output Channel B CMOS Output Data. 14 D7B Output Channel B CMOS Output Data. 15 D8B Output Channel B CMOS Output Data. 16 D9B Output Channel B CMOS Output Data. 17 D10B Output Channel B CMOS Output Data. 18 D11B Output Channel B CMOS Output Data. 20 D12B Output Channel B CMOS Output Data. 21 D13B (MSB) Output Channel B CMOS Output Data. 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 14 of 44 AD9648 CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS NC 6 43 OR+ NC 7 42 OR– AD9648 D0– (LSB) 8 41 D13+ (MSB) INTERLEAVED PARALLEL LVDS D0+ (LSB) 9 40 D13– (MSB) TOP VIEW DRVDD 10 39 D12+ (Not to Scale) D1– 11 38 D12– D1+ 12 37 DRVDD D2– 13 36 D11+ D2+ 14 35 D11– D3– 15 34 D10+ D3+ 16 33 D10– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 4, 5, 6, 7 NC No Connect. Do not connect to these pins. 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground for Exposed Pad the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 9 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 8 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. Rev. 0 | Page 15 of 44 D4– 17 64 AVDD D4+ 18 63 AVDD DRVDD 19 62 VIN+B D5– 20 61 VIN–B D5+ 21 60 AVDD D6– 22 59 AVDD D6+ 23 58 RBIAS DCO– 24 57 VCM DCO+ 25 56 SENSE D7– 26 55 VREF D7+ 27 54 AVDD DRVDD 28 53 AVDD D8– 29 52 VIN–A D8+ 30 51 VIN+A D9– 31 50 AVDD D9+ 49 AVDD 32 09975-007 AD9648 Pin No. Mnemonic Type Description 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 18 D4+ Output Channel A/Channel B LVDS Output Data 4 —True. 17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 21 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 23 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 27 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 30 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 29 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 32 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 34 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 36 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 39 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True. 40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 16 of 44 AD9648 CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS NC 6 43 OR+ NC 7 42 OR– AD9648 B D1–/D0– (LSB) 8 41 A D13+/D12+ (MSB) CHANNEL MULTIPLEXED LVDS B D1+/D0+ (LSB) 9 40 A D13–/D12– (MSB) TOP VIEW DRVDD 10 39 A D11+/D10+ (Not to Scale) B D3–/D2– 11 38 A D11–/D10– B D3+/D2+ 12 37 DRVDD B D5–/D4– 13 36 A D9+/D8+ B D5+/D4+ 14 35 A D9–/D8– B D7–/D6– 15 34 A D7+/D6+ B D7+/D6+ 16 33 A D7–/D6– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View) Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 4, 5, 6, 7 NC Do Not Connect. 0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 | Page 17 of 44 B D9–/D8– 17 64 AVDD B D9+/D8+ 18 63 AVDD DRVDD 19 62 VIN+B B D11–/D10– 20 61 VIN–B B D11+/D10+ 21 60 AVDD B D13–/D12– (MSB) 22 59 AVDD B D13+/D12+ (MSB) 23 58 RBIAS DCO– 24 57 VCM DCO+ 25 56 SENSE A D1–/D0– (LSB) 26 55 VREF A D1+/D0+ (LSB) 54 AVDD 27 DRVDD 28 53 AVDD A D3–/D2– 29 52 VIN–A A D3+/D2+ 30 51 VIN+A A D5–/D4– 31 50 AVDD A D5+/D4+ 32 49 AVDD 09975-008 AD9648 Pin No. Mnemonic Type Description Digital Outputs 8 B D1−/D0− (LSB) Output Channel B LVDS Output Data 1/Data 0—Complement. 9 B D1+/D0+ (LSB) Output Channel B LVDS Output Data 1/Data 0—True. 11 B D3−/D2− Output Channel B LVDS Output Data 3/Data 2—Complement. 12 B D3+/D2+ Output Channel B LVDS Output Data 3/Data 2—True. 13 B D5−/D4− Output Channel B LVDS Output Data 5/Data 4—Complement. 14 B D5+/D4+ Output Channel B LVDS Output Data 5/Data 4—True. 15 B D7−/D6− Output Channel B LVDS Output Data 7/Data 6—Complement. 16 B D7+/D6+ Output Channel B LVDS Output Data 7/Data 6—True. 17 B D9−/D8− Output Channel B LVDS Output Data 9/Data 8—Complement. 18 B D9+/D8+ Output Channel B LVDS Output Data 9/Data 8—True. 20 B D11−/D10− Output Channel B LVDS Output Data 11/Data 10—Complement. 21 B D11+/D10+ Output Channel B LVDS Output Data 11/Data 10—True. 22 B D13−/D12− (MSB) Output Channel B LVDS Output Data 13/Data 12—Complement. 23 B D13+/D12+ (MSB) Output Channel B LVDS Output Data 13/Data 12—True. 26 A D1−/D0− (LSB) Output Channel A LVDS Output Data 1/Data 0—Complement. 27 A D1+/D0+ (LSB) Output Channel A LVDS Output Data 1/Data 0—True. 29 A D3−/D2− Output Channel A LVDS Output Data 3/Data 2—Complement. 30 A D3+/D2+ Output Channel A LVDS Output Data 3/Data 2—True. 32 A D5+/D4+ Output Channel A LVDS Output Data 5/Data 4—Complement. 31 A D5−/D4− Output Channel A LVDS Output Data 5/Data 4—True. 34 A D7+/D6+ Output Channel A LVDS Output Data 7/Data 6—Complement. 33 A D7−/D6− Output Channel A LVDS Output Data 7/Data 6—True. 36 A D9+/D8+ Output Channel A LVDS Output Data 9/Data 8—Complement. 35 A D9−/D8− Output Channel A LVDS Output Data 9/Data 8—True. 39 A D11+/D10+ Output Channel A LVDS Output Data 11/Data 10—Complement. 38 A D11−/D10− Output Channel A LVDS Output Data 11/Data 10—True. 41 A D13+/D12+ (MSB) Output Channel A LVDS Output Data 13/Data 12—Complement. 40 A D13−/D12− (MSB) Output Channel A LVDS Output Data 13/Data 12—True. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 18 of 44 AD9648 TYPICAL PERFORMANCE CHARACTERISTICS AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 0 125MSPS 125MSPS 9.7MHz AT –1dBFS 100.5MHz AT –1dBFS SNR = 74.4dB (75.4dBFS) SNR = 73.3dB (74.3dBFS) –20 SFDR = 95.4dBc –20 SFDR = 92.3dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Single-Tone FFT with f = 9.7 MHz Figure 12. Single-Tone FFT with f = 100.5 MHz IN IN 0 0 125MSPS 125MSPS 30.5MHz AT –1dBFS 200.5MHz AT –1dBFS SNR = 74.0dB (75.0dBFS) SNR = 70.9dB (71.9dBFS) SFDR = 86.0dBc –20 –20 SFDR = 83.6dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 0 10 20 30 40 50 60 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Single-Tone FFT with f = 30.5 MHz Figure 13. Single-Tone FFT with f = 200.5 MHz IN IN 0 125MSPS 70.1MHz AT –1dBFS SNR = 73.8dB (74.8dBFS) –20 SFDR = 95.8dBc –40 –60 –80 –100 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 11. Single-Tone FFT with f = 70.1 MHz IN Rev. 0 | Page 19 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09975-022 09975-023 09975-014 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09975-024 09975-025 AD9648 AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 0 –10 SFDR (dBc) –15 –15 –30 –30 –30 IMD3(dBc) –45 –45 –60 –60 –50 –75 –75 2F1 – F2 2F2 – F1 2F1 + F2 –90 –90 –70 –105 –105 –120 –120 –90 SFDR (dBFS) –135 –135 IMD3 (dBFS) –110 6M 6M 12M 12M 18M 18M 24M 24M 30M 30M 36M 36M 42M 42M 48M 48M 54M 54M 60M 60M –90 –80 –70 –60 –50 –40 –30 –20 –10 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 14. Two-Tone FFT with f = 29 MHz and f = 32 MHz IN1 IN2 Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 29 MHz IN1 and f = 32 MHz IN2 120 100 95 SFDR (dBc) 100 90 SFDR (dBc) 85 80 SNR (dBFS) 80 SNR (dBFS) 60 75 70 40 65 60 20 55 0 50 5 15 25 35 45 55 65 75 85 95 105 115 125 0 50 100 150 200 250 SAMPLE RATE (MSPS) ANALOG INPUT FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 18. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 120 120 SFDRFS 100 100 SFDR (dBc) 80 SNRFS 80 SNR (dBFS) 60 60 SFDR 40 40 SNR 20 20 0 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 5 15 25 35 45 55 65 75 85 95 105 115 125 SAMPLE RATE (MSPS) INPUT AMPLITUDE (dBFS) Figure 16. SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN Figure 19. SNR/SFDR vs. Sample Rate with AIN = 70.1 MHz Rev. 0 | Page 20 of 44 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS) AMPLITUDE (Hz) 09975-068 09975-067 09975-069 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SFDR/IMD3 (dBc/dBFS) 09975-065 09975-021 09975-020 AD9648 2 2.0 1.5 1.5 1 1.0 0.5 0.5 0 0 –0.5 -0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE OUTPUT CODE Figure 22. INL Error with f = 9.7 MHz Figure 20. DNL Error with f = 9.7 MHz IN IN 450,000 400,000 350,000 300,000 250,000 200,000 150,000 100,000 50,000 0 OUTPUT CODE Figure 21. Shorted Input Histogram Rev. 0 | Page 21 of 44 NUMBER OF HITS DNL ERROR (LSB) N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 09975-074 09975-019 INL ERROR (LSB) 09975-018 AD9648 AD9648-105 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 0 105MSPS 105MSPS 9.7MHz AT –1dBFS 100.5MHz AT –1dBFS SNR = 74.7dB (75.7dBFS) SNR = 73.4dB (74.4dBFS) SFDR = 98.7dBc SFDR = 94.9dBc –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 0 10 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. Single-Tone FFT with f = 100.5 MHz Figure 23. Single-Tone FFT with f = 9.7 MHz IN IN 0 0 105MSPS 105MSPS 200.5MHz AT –1dBFS 30.5MHz AT –1dBFS SNR = 74.5dB (75.5dBFS) SNR = 69.5dB (70.5dBFS) SFDR = 89.9dBc –20 –20 SFDR = 82.6dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 0 10 20 30 40 50 –120 0 10 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Single-Tone FFT with f = 30.5 MHz IN Figure 27. Single-Tone FFT with f = 200.5 MHz IN 0 105MSPS 70.1MHz AT –1dBFS SNR = 73.9dB (74.9dBFS) SFDR = 94.9dBc –20 –40 –60 –80 –100 –120 0 10 20 30 40 50 FREQUENCY (MHz) Figure 25. Single-Tone FFT with f = 70.1 MHz IN Rev. 0 | Page 22 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09975-015 09975-014 09975-013 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09975-016 09975-017 AD9648 100 120 95 SFDRFS SFDR (dBc) 100 90 85 80 SNRFS 80 75 SNR (dBFS) 60 70 SFDR 40 65 SNR 60 20 55 50 0 0 50 100 150 200 250 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 ANALOG INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 28. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 31. SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN 120 120 SFDR (dBc) 100 100 SFDR (dBc) 80 SNR (dBFS) 80 SNR (dBFS) 60 60 40 40 20 20 0 0 5 15 25 35 45 55 65 75 85 95 105 5 15 25 35 45 55 65 75 85 95 105 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70.1 MHz Figure 29. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE OUTPUT CODE Figure 33. INL Error with f = 9.7 MHz Figure 30. DNL Error with f = 9.7 MHz IN IN Rev. 0 | Page 23 of 44 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 09975-010 09975-012 09975-075 INL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 09975-009 09975-011 09975-077 AD9648 EQUIVALENT CIRCUITS DRVDD AVDD 350Ω SCLK/DFS, SYNC, VIN±x OEB, AND PDWN 30kΩ Figure 38. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 34. Equivalent Analog Input Circuit AVDD 5Ω CLK+ 15kΩ 375Ω SENSE 0.9V 15kΩ 5Ω CLK– Figure 39. Equivalent SENSE Circuit Figure 35. Equivalent Clock Input Circuit DRVDD DRVDD AVDD 30kΩ 350Ω PAD CSB Figure 36. Equivalent Digital Output Circuit Figure 40. Equivalent CSB Input Circuit AVDD DRVDD AVDD 30kΩ 350Ω SDIO/DCS 30kΩ 375Ω VREF 7.5kΩ Figure 37. Equivalent SDIO/DCS Input Circuit Figure 41. Equivalent VREF Circuit Rev. 0 | Page 24 of 44 09975-039 09975-047 09975-040 09975-042 09975-043 09975-044 09975-048 09975-045 AD9648 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9648 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically The analog input to the AD9648 is a differential switched- on the same carrier but from two separate antennae. The ADCs capacitor circuit designed for processing differential input can also be operated with independent analog inputs. The user signals. This circuit can support a wide common-mode range can sample any f /2 frequency segment from dc to 200 MHz, while maintaining excellent performance. By using an input S using appropriate low-pass or band-pass filtering at the ADC common-mode voltage of midsupply, users can minimize inputs with little loss in ADC performance. Operation to signal-dependent errors and achieve optimum performance. 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9648 can be used as a base- H band or direct downconversion receiver, where one ADC is C PAR used for I input data and the other is used for Q input data. H VIN+x C Synchronization capability is provided to allow synchronized SAMPLE S S timing between multiple channels or multiple devices. S S Programming and control of the AD9648 is accomplished using C SAMPLE a 3-bit SPI-compatible serial interface. VIN–x H C PAR ADC ARCHITECTURE H The AD9648 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in Figure 42. Switched-Capacitor Input Circuit the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The clock signal alternately switches the input circuit between The pipelined architecture permits the first stage to operate with a sample-and-hold mode (see Figure 42). When the input circuit new input sample while the remaining stages operate with is switched to sample mode, the signal source must be capable preceding samples. Sampling occurs on the rising edge of of charging the sample capacitors and settling within one-half the clock. of a clock cycle. A small resistor in series with each input can Each stage of the pipeline, excluding the last, consists of a low help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite resolution flash ADC connected to a switched-capacitor DAC beads can be placed on each leg of the input to reduce high and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier differential capacitance at the analog inputs and, therefore, magnifies the difference between the reconstructed DAC output achieve the maximum bandwidth of the ADC. Such use of low and the flash input for the next stage in the pipeline. One bit of Q inductors or ferrite beads is required when driving the converter redundancy is used in each stage to facilitate digital correction front end at high IF frequencies. Either a shunt capacitor or two of flash errors. The last stage simply consists of a flash ADC. single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass The output staging block aligns the data, corrects errors, and filter at the input to limit unwanted broadband noise. See the passes the data to the CMOS/LVDS output buffers. The output AN-742 Application Note, the AN-827 Application Note, and the buffers are powered from a separate (DRVDD) supply, allowing Analog Dialogue article “Transformer-Coupled Front-End for digital output noise to be separated from the analog core. During Wideband A/D Converters” (Volume 39, April 2005) for more power-down, the output buffers go into a high impedance state. information. In general, the precise values depend on the application. Rev. 0 | Page 25 of 44 09975-049 AD9648 Input Common Mode driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. The analog inputs of the AD9648 are not internally dc-biased. 200Ω Therefore, in ac-coupled applications, the user must provide a 33Ω VIN–x VIN 76.8Ω AVDD dc bias externally. Setting the device so that VCM = AVDD/2 is 90Ω recommended for optimum performance, but the device can 10pF ADC ADA4938 0.1µF function over a wider range with reasonable performance, as 120Ω 33Ω VCM VIN+x shown in Figure 43. 200Ω An on-board, common-mode voltage reference is included in Figure 44. Differential Input Configuration Using the ADA4938-2 the design and is available from the VCM pin. The VCM pin For baseband applications below ~10 MHz where SNR is a key must be decoupled to ground by a 0.1 µF capacitor, as described parameter, differential transformer-coupling is the recommended in the Applications Information section. input configuration. An example is shown in Figure 45. To bias 100 the analog input, the VCM voltage can be connected to the SFDR (dBc) 90 center tap of the secondary winding of the transformer. 80 SNR (dBFS) VIN+x R 70 2V p-p 49.9Ω C ADC 60 R VCM VIN–x 50 0.1µF 40 Figure 45. Differential Transformer-Coupled Configuration 30 The signal characteristics must be considered when selecting 20 a transformer. Most RF transformers saturate at frequencies 10 below a few megahertz (MHz). Excessive signal power can also 0 cause core saturation, which leads to distortion. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 At input frequencies in the second Nyquist zone and above, the INPUT COMMON-MODE VOLTAGE (V) noise performance of most amplifiers is not adequate to achieve Figure 43. SNR/SFDR vs. Input Common-Mode Voltage, f = 70 MHz, f = 125 MSPS the true SNR performance of the AD9648. For applications above IN S ~10 MHz where SNR is a key parameter, differential double balun Differential Input Configurations coupling is the recommended input configuration (see Figure 46). Optimum performance is achieved while driving the AD9648 in a differential input configuration. For baseband applications, the An alternative to using a transformer-coupled input at frequencies AD8138, ADA4937-2, and ADA4938-2 differential drivers provide in the second Nyquist zone is to use the AD8352 differential driver. excellent performance and a flexible interface to the ADC. An example is shown in Figure 47. See the AD8352 data sheet for more information. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9648 (see Figure 44), and the 0.1µF 0.1µF R VIN+x 2V p-p 25Ω P S S P C ADC A 0.1µF 25Ω 0.1µF R VCM VIN–x Figure 46. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+x 2 200Ω C ADC AD8352 R R C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN–x 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 47. Differential Input Configuration Using the AD8352 Rev. 0 | Page 26 of 44 SNR/SFDR (dBFS/dBc) 09975-072 09975-053 09975-054 09975-051 09975-050 AD9648 In any configuration, the value of Shunt Capacitor C is dependent the reference amplifier switch is connected to the internal resistor on the input frequency and source impedance and may need to divider (see Figure 49), setting VREF to 1.0 V. be reduced or removed. Table 11 displays the suggested values to VIN+A/VIN+B set the RC network. However, these values are dependent on the VIN–A/VIN–B input signal and should be used only as a starting guide. Table 11. Example RC Network ADC R Series CORE Frequency Range (MHz) (Ω Each) C Differential (pF) 0 to 70 33 22 VREF 70 to 200 125 Open 1.0µF 0.1µF SELECT LOGIC Single-Ended Input Configuration SENSE A single-ended input can provide adequate performance in 0.5V cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common- mode swing. If the source impedances on each input are matched, ADC there should be little effect on SNR performance. Figure 48 Figure 49. Internal Reference Configuration shows a typical single-ended input configuration. 10µF AVDD If the internal reference of the AD9648 is used to drive multiple 1kΩ converters to improve gain matching, the loading of the reference R VIN+x by the other converters must be considered. Figure 50 shows 1V p-p 0.1µF 49.9Ω 1kΩ how the internal reference voltage is affected by loading. AVDD ADC C 1kΩ 0 R VIN–x 10µF 0.1µF 1kΩ –0.5 Figure 48. Single-Ended Input Configuration –1.0 VOLTAGE REFERENCE INTERNAL V = 1.00V REF A stable and accurate 1.0 V voltage reference is built into the –1.5 AD9648. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. –2.0 The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. –2.5 Internal Reference Connection –3.0 A comparator within the AD9648 detects the potential at the 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SENSE pin and configures the reference into two possible LOAD CURRENT (mA) modes, which are summarized in Table 12. If SENSE is grounded, Figure 50. V Accuracy vs. Load Current REF Table 12. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. 0 | Page 27 of 44 09975-052 REFERENCE VOLTAGE ERROR (%) 09975-055 09975-078 AD9648 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance The AD9648 has a very flexible clock input structure. The clock the gain accuracy of the ADC or improve thermal drift charac- input can be a CMOS, LVDS, LVPECL, or sine wave signal. teristics. Figure 51 shows the typical drift characteristics of the Regardless of the type of signal being used, clock source jitter is internal reference in 1.0 V mode. of the most concern, as described in the Jitter Considerations section. 4 Figure 53 and Figure 54 show two preferred methods for clock- 3 ing the AD9648 (at clock rates up to 1 GHz prior to internal CLK 2 divider). A low jitter clock source is converted from a single- V ERROR (mV) REF 1 ended signal to a differential signal using either an RF transformer or an RF balun. 0 The RF balun configuration is recommended for clock frequencies –1 between 125 MHz and 1 GHz, and the RF transformer is recom- –2 mended for clock frequencies from 10 MHz to 200 MHz. The –3 back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9648 to –4 approximately 0.8 V p-p differential. –5 This limit helps prevent the large voltage swings of the clock –6 from feeding through to other portions of the AD9648 while –40 –20 0 20 40 60 80 TEMPERATURE (°C) preserving the fast rise and fall times of the signal that are critical to a low jitter performance. Figure 51. Typical V Drift REF When the SENSE pin is tied to AVDD, the internal reference is ® Mini-Circuits ADT1-1WT, 1:1 Z disabled, allowing the use of an external reference. An internal 0.1µF 0.1µF reference buffer loads the external reference with an equivalent XFMR CLOCK CLK+ INPUT 7.5 kΩ load (see Figure 41). The internal buffer generates the 100Ω 50Ω ADC 0.1µF positive and negative full-scale references for the ADC core. CLK– Therefore, the external reference must be limited to a maximum SCHOTTKY 0.1µF DIODES: of 1.0 V. HSMS2822 Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz) CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9648 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal 1nF 0.1µF is typically ac-coupled into the CLK+ and CLK− pins via a CLOCK CLK+ transformer or capacitors. These pins are biased internally INPUT 50Ω ADC (see Figure 52) and require no external bias. 0.1µF 1nF CLK– AVDD SCHOTTKY DIODES: HSMS2822 0.9V Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz) CLK+ CLK– 2pF 2pF Figure 52. Equivalent Clock Input Circuit Rev. 0 | Page 28 of 44 V ERROR (mV) REF 09975-058 09975-079 09975-060 09975-059 AD9648 If a low jitter clock source is not available, another option is to Input Clock Divider ac couple a differential PECL signal to the sample clock input The AD9648 contains an input clock divider with the ability pins, as shown in Figure 55. The AD9510/AD9511/AD9512/ to divide the input clock by integer values between 1 and 8. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer The AD9648 clock divider can be synchronized using the excellent jitter performance. external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or 0.1µF 0.1µF only on the first SYNC signal after the register is written. A CLOCK CLK+ INPUT valid SYNC causes the clock divider to reset to its initial state. AD951x 100Ω ADC This synchronization feature allows multiple parts to have their PECL DRIVER 0.1µF 0.1µF CLOCK CLK– clock dividers aligned to guarantee simultaneous input sampling. INPUT 240Ω 240Ω 50kΩ 50kΩ Clock Duty Cycle Figure 55. Differential PECL Sample Clock (Up to 1 GHz) Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be A third option is to ac couple a differential LVDS signal to the sensitive to clock duty cycle. Commonly, a ±5% tolerance is sample clock input pins, as shown in Figure 56. The AD9510/ required on the clock duty cycle to maintain dynamic AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 performance characteristics. clock drivers offer excellent jitter performance. The AD9648 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock 0.1µF 0.1µF signal with a nominal 50% duty cycle. This allows the user to CLOCK CLK+ INPUT provide a wide range of clock input duty cycles without affecting AD951x 100Ω ADC LVDS DRIVER 0.1µF the performance of the AD9648. Noise and distortion perform- 0.1µF CLOCK CLK– INPUT ance are nearly flat for a wide range of duty cycles with the DCS 50kΩ 50kΩ on, as shown in Figure 58. Figure 56. Differential LVDS Sample Clock (Up to 1 GHz) Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty In some applications, it may be acceptable to drive the sample cycle control loop does not function for clock rates less than clock inputs with a single-ended 1.8 V CMOS signal. In such 20 MHz, nominally. The loop has a time constant associated applications, drive the CLK+ pin directly from a CMOS gate, and with it that must be considered in applications in which the bypass the CLK− pin to ground with a 0.1 μF capacitor (see clock rate can change dynamically. A wait time of 1.5 µs to 5 µs Figure 57). is required after a dynamic clock frequency increase or decrease V before the DCS loop is relocked to the input signal. CC OPTIONAL 0.1µF 0.1µF 80 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER INPUT 1 SNR (DCS ON) 1kΩ 50Ω 75 ADC CLK– 70 0.1µF SNR (DCS OFF) 65 1 50Ω RESISTOR IS OPTIONAL. Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 60 55 50 45 40 35 40 45 50 55 60 65 POSITIVE DUTY CYCLE (%) Figure 58. SNR vs. DCS On/Off Rev. 0 | Page 29 of 44 09975-061 09975-063 09975-062 SNR (dBFS) 09975-076 AD9648 Jitter Considerations primarily by the strength of the digital drivers and the load on each output bit. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low fre- The maximum DRVDD current (IDRVDD) can be calculated as quency SNR (SNR ) at a given input frequency (f ) due to LF INPUT I = V × C × f × N DRVDD DRVDD LOAD CLK jitter (t ) can be calculated by JRMS where N is the number of output bits (30, in the case of the 2 (−SNR /10) LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS AD9648). In the previous equation, the rms aperture jitter represents the This maximum current occurs when every output bit switches clock input jitter specification. IF undersampling applications on every clock cycle, that is, a full-scale square wave at the Nyquist are particularly sensitive to jitter, as illustrated in Figure 59. frequency of f /2. In practice, the DRVDD current is estab- CLK 80 lished by the average number of output bits switching, which is determined by the sample rate and the characteristics of the 75 0.05ps analog input signal. Reducing the capacitive load presented to the output drivers can 70 minimize digital power consumption. The data in Figure 60 was 0.2ps taken in CMOS mode using the same operating conditions as those 65 used for the Power Supplies and Power Consumption specifications in Table 1, with a 5 pF load on each output driver. 60 0.5ps 100 220 55 90 200 1.0ps 80 180 1.5ps 50 70 2.0ps I 160 AVDD 3.0ps 2.5ps 60 45 140 1 10 100 1k 50 FREQUENCY (MHz) TOTAL POWER 120 40 Figure 59. SNR vs. Input Frequency and Jitter 100 30 The clock input should be treated as an analog signal in cases 80 20 where aperture jitter may affect the dynamic range of the AD9648. I DRVDD 60 10 To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output 0 40 5 25 45 65 85 105 125 driver supplies. Low jitter, crystal-controlled oscillators make the ENCODE RATE (MSPS) best clock sources. If the clock is generated from another type of Figure 60. AD9648-125 Power and Current vs. Clock Rate (1.8 V CMOS source (by gating, dividing, or another method), it should be Output Mode) retimed by the original clock at the last step. 90 200 See the AN-501 Application Note and the AN-756 Application 80 180 Note, available on www.analog.com for more information. 70 160 CHANNEL/CHIP SYNCHRONIZATION 60 The AD9648 has a SYNC input that offers the user flexible 140 I AVDD synchronization options for synchronizing sample clocks 50 120 across multiple ADCs. The input clock divider can be enabled 40 TOTAL POWER to synchronize on a single occurrence of the SYNC signal or on 100 30 every occurrence. The SYNC input is internally synchronized 80 to the sample clock; however, to ensure there is no timing 20 uncertainty between multiple parts, the SYNC input signal should I DRVDD 60 10 be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input 0 40 5 25 45 65 85 105 using a single-ended CMOS-type signal. ENCODE RATE (Msps) POWER DISSIPATION AND STANDBY MODE Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS Output Mode) As shown in Figure 60, the analog core power dissipated by the AD9648 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined Rev. 0 | Page 30 of 44 SNR (dBFS) 09975-080 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) POWER (mW) POWER (mW) 09975-066 09975-070 AD9648 The AD9648 is placed in power-down mode either by the SPI As detailed in the AN-877 Application Note, Interfacing to High port or by asserting the PDWN pin high. In this state, the ADC Speed ADCs via SPI, the data format can be selected for offset typically dissipates less than 2 mW. During power-down, the binary, twos complement, or gray code when using the SPI control. output drivers are placed in a high impedance state. Asserting Table 13. SCLK/DFS Mode Selection (External Pin Mode) the PDWN pin low returns the AD9648 to its normal operating Voltage at Pin SCLK/DFS SDIO/DCS mode. Note that PDWN is referenced to the digital output AGND Offset binary (default) DCS disabled driver supply (DRVDD) and should not exceed that supply DRVDD Twos complement DCS enabled (default) voltage. Low power dissipation in power-down mode is achieved by Digital Output Enable Function (OEB) shutting down the reference, reference buffer, biasing networks, The AD9648 has a flexible three-state ability for the digital and clock. Internal capacitors are discharged when entering power- output pins. The three-state mode is enabled through the SPI down mode and then must be recharged when returning to normal interface and can subsequently be controlled using the OEB pin operation. As a result, wake-up time is related to the time spent or through the SPI. Once enabled via SPI (Bit 7) in Register 0x101, in power-down mode, and shorter power-down cycles result in and the OEB pin is low, the output data drivers and DCOs are proportionally shorter wake-up times. enabled. If the OEB pin is high, the output data drivers and When using the SPI port interface, the user can place the ADC DCOs are placed in a high impedance state. This OEB function in power-down mode or standby mode. Standby mode allows is not intended for rapid access to the data bus. Note that OEB the user to keep the internal reference circuitry powered when is referenced to the digital output driver supply (DRVDD) and faster wake-up times are required. See the Memory Map section should not exceed that supply voltage. for more details. When using the SPI interface, the data outputs and DCO of DIGITAL OUTPUTS each channel can be independently three-stated by using the output disable bit (Bit 4) in Register 0x14. The AD9648 output drivers can be configured to interface with either 1.8 V CMOS or 1.8 V LVDS logic families. The default TIMING output mode is CMOS, with each channel output on separate The AD9648 provides latched data with a pipeline delay of busses as shown in Figure 2. 16 clock cycles. Data outputs are available one propagation In CMOS output mode, the CMOS output drivers are sized to delay (t ) after the rising edge of the clock signal. PD provide sufficient output current to drive a wide variety of logic Minimize the length of the output data lines and loads placed families. However, large drive currents tend to cause current on them to reduce transients within the AD9648. These glitches on the supplies and may affect converter performance. transients can degrade converter dynamic performance. Applications requiring the ADC to drive large capacitive loads The lowest typical conversion rate of the AD9648 is 10 MSPS. or large fanouts may require external buffers or latches. At clock rates below 10 MSPS, dynamic performance can degrade. The CMOS output can also be configured for interleaved CMOS Data Clock Output (DCO) output mode via the SPI port. In interleaved CMOS mode, the The AD9648 provides two data clock output (DCO) signals data for both channels is output onto a single output bus to intended for capturing the data in an external register. In CMOS reduce the total number of traces required. The timing diagram for output mode, the data outputs are valid on the rising edge of DCO, interleaved CMOS output mode is shown in Figure 3. unless the DCO clock polarity has been changed via the SPI. In The interleaved CMOS output mode is enabled globally onto both LVDS output mode, the DCO and data output switching edges output channels via Bit 5 in Register 0x14. The unused channel are closely aligned. Additional delay can be added to the DCO output can be disabled by selecting the appropriate Device Index output using SPI Register 0x17 to increase the data setup time. (Bit 1 or Bit 0) in Register 0x05, then writing a 1 to local (channel In this case, the Channel A output data is valid on the rising specific) output port disable bit in Register 0x14. edge of DCO, and the Channel B output data is valid on the The output data format can be selected to be either offset binary falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for or twos complement by setting the SCLK/DFS pin when operating a graphical timing description of the output modes. in the external pin mode (see Table 13). Table 14. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1 Rev. 0 | Page 31 of 44 AD9648 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST OUTPUT TEST MODES The AD9648 includes a built-in test feature designed to enable The output test options are described in Table 18 at Address 0x0D. verification of the integrity of each channel, as well as to When an output test mode is enabled, the analog section of the facilitate board level debugging. A built-in self-test (BIST) feature ADC is disconnected from the digital back-end blocks and the that verifies the integrity of the digital datapath of the AD9648 test pattern is run through the output formatting block. Some of is included. Various output test options are also provided to place the test patterns are subject to output formatting, and some are predictable values on the outputs of the AD9648. not. The PN generators from the PN sequence tests can be reset BUILT-IN SELF-TEST (BIST) by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be The BIST is a thorough test of the digital portion of the selected performed with or without an analog signal (if present, the AD9648 signal path. Perform the BIST test after a reset to ensure analog signal is ignored), but they do require an encode clock. the part is in a known state. During BIST, data from an internal For more information, see the AN-877 Application Note, pseudorandom noise (PN) source is driven through the digital Interfacing to High Speed ADCs via SPI. datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. Once completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying the test passed. If the BIST test fails, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (initialize BIST sequence) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user needs to rely on verifying the output data. Rev. 0 | Page 32 of 44 AD9648 SERIAL PORT INTERFACE (SPI) The AD9648 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 62 gives the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK/DFS pin, the Data follows the instruction phase, and its length is determined SDIO/DCS pin, and the CSB pin (see Table 15). The SCLK/DFS by the W0 and W1 bits. (a serial clock) is used to synchronize the read and write data In addition to word length, the instruction phase determines presented from and to the ADC. The SDIO/DCS (serial data whether the serial frame is a read or write operation, allowing input/output) is a dual-purpose pin that allows data to be sent the serial port to be used both to program the chip and to read to and read from the internal ADC memory map registers. The the contents of the on-chip memory. The first bit of the first byte in CSB (chip select bar) is an active low control that enables or a multibyte serial data transfer frame indicates whether a read disables the read and write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial Table 15. Serial Port Interface Pins data input/output (SDIO) pin to change direction from an input to Pin Function an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB- SDIO Serial data input/output. A dual-purpose pin that first mode or in LSB-first mode. MSB first is the default on typically serves as an input or an output, depending on power-up and can be changed via the SPI port configuration the instruction being sent and the relative position in the timing frame. register. For more information about this and other features, CSB Chip select bar. An active low control that gates the read see the AN-877 Application Note, Interfacing to High Speed and write cycles. ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 62. Serial Port Interface Timing Diagram Rev. 0 | Page 33 of 44 09975-046 AD9648 When the device is in SPI mode, the PDWN and OEB Pins (if HARDWARE INTERFACE enabled) remain active. For SPI control of output enable and The pins described in Table 15 comprise the physical interface power-down, the OEB and PDWN pins should be set to their between the user programming device and the serial port of the default states. AD9648. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, Table 16. Mode Selection functioning as an input during write phases and as an output Pin External Voltage Configuration during readback. SDIO/DCS DRVDD (default) Duty cycle stabilizer enabled The SPI interface is flexible enough to be controlled by either AGND Duty cycle stabilizer disabled FPGAs or microcontrollers. One method for SPI configuration SCLK/DFS DRVDD Twos complement enabled is described in detail in the AN-812 Application Note, Micro- AGND (default) Offset binary enabled controller-Based Serial Port Interface (SPI) Boot Circuit. OEB DRVDD Outputs in high impedance AGND (default) Outputs enabled The SPI port should not be active during periods when the full PDWN DRVDD Chip in power-down or dynamic performance of the converter is required. Because the standby SCLK signal, the CSB signal, and the SDIO signal are typically AGND (default) Normal operation asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for SPI ACCESSIBLE FEATURES other devices, it may be necessary to provide buffers between this bus and the AD9648 to prevent these signals from transi- Table 17 provides a brief description of the general features that tioning at the converter inputs during critical sampling periods. are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs Some pins serve a dual function when the SPI interface is not via SPI. The AD9648 part-specific features are described in detail being used. When the pins are strapped to DRVDD or ground following Table 18, the external memory map register table. during device power-on, they are associated with a specific function. Table 16 describes the strappable functions supported Table 17. Features Accessible Using the SPI on the AD9648. Feature Name Description CONFIGURATION WITHOUT THE SPI Mode Allows the user to set either power-down mode or standby mode In applications that do not interface to the SPI control registers, Clock Allows the user to access the DCS, set the the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin clock divider, set the clock divider phase, and serve as standalone CMOS-compatible control pins. When the enable the sync device is powered up, it is assumed that the user intends to use the Offset Allows the user to digitally adjust the pins as static control lines for the duty cycle stabilizer, output converter offset data format, and power-down feature control. In this mode, the Test I/O Allows the user to set test modes to have CSB chip select bar should be connected to AVDD, which known data on output bits disables the serial port interface. Output Mode Allows the user to set the output mode including LVDS Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay Rev. 0 | Page 34 of 44 AD9648 MEMORY MAP is open (for example, Address 0x13), this address location should READING THE MEMORY MAP REGISTER TABLE not be written to. Each row in the memory map register table has eight bit locations. Default Values The memory map is roughly divided into three sections: the chip After the AD9648 is reset, critical registers are loaded with configuration registers (Address 0x00 to Address 0x02); the default values. The default values for the registers are given in channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, the memory map register table, Table 18. control, and test (Address 0x08 to Address 0x102). Logic Levels The memory map register table (see Table 18) lists the default An explanation of logic level terminology follows: hexadecimal value for each hexadecimal address shown. The • “Bit is set” is synonymous with “bit is set to Logic 1” or column with the heading Bit 7 (MSB) is the start of the default “writing Logic 1 for the bit.” hexadecimal value given. For example, Address 0x05, the device • “Clear a bit” is synonymous with “bit is set to Logic 0” or index register, has a hexadecimal default value of 0x03. This “writing Logic 0 for the bit.” means that in Address 0x05 Bits[7:2] = 0, and Bits[1:0] = 1. This setting is a default channel index setting. The default value Channel-Specific Registers results in both ADC channels receiving the next write Some channel setup functions, such as the signal monitor command. For more information on this function and others, see thresholds, can be programmed differently for each channel. In the AN-877 Application Note, Interfacing to High Speed ADCs via these cases, channel address locations are internally duplicated for SPI. This application note details the functions controlled by each channel. These registers and bits are designated in Table 18 Register 0x00 to Register 0xFF. The remaining registers, are as local. These local registers and bits can be accessed by setting documented in the Memory Map Register Description section. the appropriate Channel A or Channel B bits in Register 0x05. Open Locations If both bits are set, the subsequent write affects the registers of All address and bit locations that are not included in Table 18 both channels. In a read cycle, only Channel A or Channel B are not currently supported for this device. Unused bits of a should be set to read one of the two registers. If both bits are set valid address location should be written with 0s. Writing to these during an SPI read cycle, the part returns the value for Channel A. locations is required only when part of an address location is Registers and bits designated as global in Table 18 affect the entire part or the channel features for which independent settings are not open (for example, Address 0x05). If the entire address location allowed between channels. Rev. 0 | Page 35 of 44 AD9648 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 18 are not currently supported for this device. Table 18. Memory Map Registers Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port Open LSB first Soft reset 1 1 Soft reset LSB first Open 0x18 The nibbles config are mirrored so (global) LSB-first mode or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID[7:0] Read Unique chip ID used to AD9648 = 0x88 only (global) differentiate devices; read only 0x02 Chip Open Speed grade ID Open Read Unique grade only speed 100 = 105 MSPS grade ID (global) 101 = 125 MSPS used to differentiate devices; read only Channel Index and Transfer Registers 0x05 Device Open Open Open Open Open Open Data Data 0x03 Bits are set index Channel B Channel A to (global) determine which device on the chip receives the next write command; applies to local registers only 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchron- (global) ously transfers data from the master shift register to the slave ADC Functions 0x08 Power Open Open External Open Open Open Internal power-down 0x00 Determines modes power- mode various down pin generic (local) 00 = normal operation function modes of 01 = full power-down chip 0 = PDWN 10 = standby operation 1 = standby 11 = digital reset 0x09 Global Open Open Open Open Open Open Open Duty cycle 0x01 clock stabilizer 0 = (global) Disabled 1 = enabled Rev. 0 | Page 36 of 44 AD9648 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0B Clock Open Open Open Open Open Clock divide ratio 0x00 The divide divide ratio is 000 = divide by 1 value plus 1 (global) 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0C Enhance- Open Open Open Open Open Chop Open Open 0x00 Chop mode ment enabled if 0 = control Bit 2 is disabled (global) enabled 1 = enabled 0x0D Test mode User test mode control Reset PN Reset PN Output test mode 0x00 When this register is (local) long gen short gen 00 = single pattern mode 0000 = off (default) set, the test 01 = alternate 0001 = midscale short data is continuous/repeat 0010 = positive FS placed on pattern mode 0011 = negative FS the output 10 = single once pattern 0100 = alternating checkerboard pins in mode 0101 = PN long sequence place of 11 = alternate once 0110 = PN short sequence normal data pattern mode 0111 = one/zero word toggle 1000 = user test mode 1111 = ramp output 0x0E BIST Open Open Open Open Open Initialize Open BIST enable 0x00 enable BIST sequence (global) 0x10 Customer Offset adjust in LSBs from +127 to −128 0x00 offset (twos complement format) adjust (local) 0x14 Output Output port logic type Output Output port Open Output Output format 0x00 Configures mode (global) Interleave disable (local) invert the (global) 00 = offset binary enable (local) outputs 00 = CMOS, 1.8 V 01 = twos complement and the (global) 10 = LVDS, ANSI 10 = Gray code format of 11 = LVDS, reduced the data range 0x15 Output Open Open CMOS 1.8 V DCO drive Open Open CMOS 1.8 V data 0x00 Determines adjust strength drive strength CMOS 00 = 1× 00 = 1× output 01 = 2× 01 = 2× drive 10 = 3× 10 = 3× strength 11 = 4× 11 = 4× properties 0x16 Clock Invert Open Open Open Open Input clock divider phase adjust 0x00 Allows phase DCO selection of relative to the encode clock control clock clock 000 = no delay delays into 0 = not (global) 001 = one input clock cycle the input inverted 010 = two input clock cycles clock 1 = 011 = three input clock cycles divider inverted 100 = four input clock cycles 101 = five input clock cycles 110 = six input clock cycles 111 = seven input clock cycles 0x17 Output DCO Open Data delay Open Open Delay selection 0x00 This sets delay clock the fine 0 = 000 = 0.56 ns (global) delay output disabled 001 = 1.12 ns delay of 0 = 1 = 010 = 1.68 ns the output disabled enabled 011 = 2.24 ns clock but 1 = 100 = 2.80 ns does not enabled 101 = 3.36 ns change 110 = 3.92 ns internal 111 = 4.48 ns timing Rev. 0 | Page 37 of 44 AD9648 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x18 VREF Open Open Open Open Open Internal V digital adjustment 0x04 Select and/ REF select or adjust 000 = 1.0 V p-p V (global) REF 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p 0x19 User B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Pattern 1 defined LSB Pattern 1 (global) LSB 0x1A User B15 B14 B13 B12 B11 B10 B9 B8 0x00 User- Pattern 1 defined MSB Pattern, 1 (global) MSB 0x1B User B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Pattern 2 defined LSB Pattern 2 (global) LSB 0x1C User B15 B14 B13 B12 B11 B10 B9 B8 0x00 User- Pattern 2 defined Pattern, 2 MSB MSB 0x24 MISR LSB MISR LSB[7:0] 0xFF Read only 0x25 MISR MSB MISR MSB[15:8] 0xFF Read only 0x2A Overrange Open Open Open Open Open Open Open Overrange 0x01 Overrange control output control settings (global) 0 = disabled 1 = enabled 0x2E Output Open Open Open Open Open Open Open 0 = ADC A ADC A = Assign an assign 1 = ADC B 0x00 ADC to an (local) (local) output ADC B = channel 0x01 0x3A Sync Open Open Open Open Open Sync Sync Open 0x00 Sets the control next only enable global sync (global) options 0x100 Sample Open Sample rate Resolution Sample rate 0x00 rate override 010 = 14 bits 011 = 80 MSPS override enable 100 = 12 bits 100 = 105 MSPS 110 = 10 bits 101 = 125 MSPS 0x101 User I/O Output Open Open Open Open Open Open Disable 0x00 OEB and Control enable SDIO pull- SDIO pin Register 2 bar (OEB) down controls pin enable 0x102 User I/O Open Open Open Open VCM power- Open 0x00 Control down Register 3 Rev. 0 | Page 38 of 44 AD9648 interleaving feature. Channel A is sent on least significant bits MEMORY MAP REGISTER DESCRIPTIONS (LSBs), and Channel B is sent on most significant bits (MSBs). For additional information about functions controlled in The even bits are sent coincident with a high DCO clock, and Register 0x00 to Register 0xFF, see the AN-877 Application Note, the odd bits are sent coincident with a low DCO clock. Interfacing to High Speed ADCs via SPI. For CMOS outputs, setting Bit 5 enables interleaving in CMOS Power Modes (Register 0x08) DDR mode. On ADC Output Port A, Channel A is sent coincident Bits[7:6]—Open with a low DCO clock, and Channel B is coincident with a high DCO clock. On ADC Output Port B, Channel B is sent coincident Bit 5—External Power-Down Pin Function with a low DCO clock, and Channel A is coincident with a high If set, the external PDWN pin initiates power-down mode. DCO clock. Clearing Bit 5 disables the interleaving feature, and If clear, the external PDWN pin initiates standby mode. data is output in CMOS SDR mode. Channel A is sent to Port A, Bits[4:2]—Open and Channel B is sent to Port B. Bits[1:0]—Internal Power-Down Mode Bit 4—Output Port Disable In normal operation (Bits[1:0] = 00), both ADC channels are Setting Bit 4 high disables the output port for the channels active. selected in Bits[1:0] of the device index register (Register 0x05). In power-down mode (Bits[1:0] = 01), the digital data path clocks Bit 3—Open are disabled while the digital data path is reset. Outputs are Bit 2—Output Invert disabled. Setting Bit 2 high inverts the output port data for the channels In standby mode (Bits[1:0] = 10), the digital data path clocks selected in Bits[1:0] of the device index register (Register 0x05). and the outputs are disabled. Bits[1:0]—Output Format During a digital reset (Bits[1:0] = 11), the digital data path clocks 00 = offset binary are disabled while the digital data path is held in reset. The outputs 01 = twos complement are enabled in this state. For optimum performance, it is recom- 10 = Gray code mended that both ADC channels be reset simultaneously. This is accomplished by ensuring that both channels are selected via Sync Control (Register 0x3A) Register 0x05 prior to issuing the digital reset instruction. Bits[7:3]—Open Enhancement Control (Register 0x0C) Bit 2—Clock Divider Next Sync Only Bits[7:3]—Open If the clock divider sync enable bit (Address 0x3A, Bit 1) is high, Bit 2—Chop Mode Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit For applications that are sensitive to offset voltages and other resets after it syncs. low frequency noise, such as homodyne or direct-conversion receivers, chopping in the first stage of the AD9628 is a feature Bit 1—Clock Divider Sync Enable that can be enabled by setting Bit 2. In the frequency domain, Bit 1 gates the sync pulse to the clock divider. The sync signal is chopping translates offsets and other low frequency noise to enabled when Bit 1 is high. This is continuous sync mode. f /2 where it can be filtered. CLK Bit 0—Open Bits[1:0]—Open Transfer (Register 0xFF) Output Mode (Register 0x14) All registers except Register 0x100 are updated the moment they Bits[7:6]—Output Port Logic Type are written. Setting Bit 0 of this transfer register high initializes 00 = CMOS, 1.8 V the settings in the ADC sample rate override register (Address 10 = LVDS, ANSI 0x100). 11 = LVDS, reduced range Sample Rate Override (Register 0x100) Bit 5—Output Interleave Enable This register is designed to allow the user to downgrade the device. For LVDS outputs, setting Bit 5 enables interleaving. Channel A Any attempt to upgrade the default speed grade results in a chip is sent coincident with a high DCO clock, and Channel B is power-down. Settings in this register are not initialized until Bit 0 coincident with a low DCO clock. Clearing Bit 5 disables the of the transfer register (Register 0xFF) is written high. Rev. 0 | Page 39 of 44 AD9648 User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) Bit 7—OEB Pin Enable Bits[7:4]—Open If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. Bit 3—VCM Power-Down If Bit 7 is clear, the OEB pin is disabled (default). Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external Bits[6:1]—Open reference. Bit 0—SDIO Pull-Down Bits[2:0]—Open Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Rev. 0 | Page 40 of 44 AD9648 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting design and layout of the AD9648 as a system, the bottom of the PCB. These vias should be filled or plugged to it is recommended that the designer become familiar with these prevent solder wicking through the vias, which can compromise guidelines, which discuss the special circuit connections and the connection. layout requirements that are needed for certain pins. To maximize the coverage and adhesion between the ADC and Power and Ground Recommendations the PCB, a silkscreen should be overlaid to partition the continuous When connecting power to the AD9648, it is recommended that plane on the PCB into several uniform sections. This provides two separate 1.8 V supplies be used. Use one supply for analog several tie points between the ADC and the PCB during the reflow (AVDD); use a separate supply for the digital outputs (DRVDD). process. Using one continuous plane with no partitions guarantees For both AVDD and DRVDD several different decoupling capa- only one tie point between the ADC and the PCB. For detailed citors should be used to cover both high and low frequencies. information about packaging and PCB layout of chip scale Place these capacitors close to the point of entry at the PCB level packages, see the AN-772 Application Note, A Design and and close to the pins of the part, with minimal trace length. Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. A single PCB ground plane should be sufficient when using the AD9648. With proper decoupling and smart partitioning of the VCM PCB analog, digital, and clock sections, optimum performance The VCM pin should be decoupled to ground with a 0.1 μF is easily achieved. capacitor. LVDS Operation Reference Decoupling The AD9648 defaults to CMOS output mode on power-up. The VREF pin should be externally decoupled to ground with If LVDS operation is desired, this mode must be programmed, a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF using the SPI configuration registers after power-up. When the ceramic capacitor. AD9648 powers up in CMOS mode with LVDS termination SPI Port resistors (100 Ω) on the outputs, the DRVDD current can be The SPI port should not be active during periods when the full higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage dynamic performance of the converter is required. Because the to the AD9648, but it should be taken into account when consid- SCLK, CSB, and SDIO signals are typically asynchronous to the ering the maximum DRVDD current for the part. ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, To avoid this additional DRVDD current, the AD9648 outputs it may be necessary to provide buffers between this bus and the can be disabled at power-up by taking the PDWN pin high. AD9648 to keep these signals from transitioning at the converter After the part is placed into LVDS mode via the SPI port, the inputs during critical sampling periods. PDWN pin can be taken low to enable the outputs. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9648 exposed paddle, Pin 0. Rev. 0 | Page 41 of 44 AD9648 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 BSC TOP VIEW EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 63. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9648BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9648BCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9648BCPZRL7-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9648BCPZRL7-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9648-125EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 42 of 44 091707-C AD9648 NOTES Rev. 0 | Page 43 of 44 AD9648 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09975-0-7/11(0) Rev. 0 | Page 44 of 44