ANALOG DEVICES AD9642

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9642 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 71.0 dBFS at 185 MHz A and 250 MSPS IN SFDR = 83 dBc at 185 MHz A and 250 MSPS IN VIN+ PIPELINE D0±/D1± 14 −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A , 250 MSPS IN 14-BIT VIN– ADC Total power consumption: 390 mW at 250 MSPS PARALLEL VCM AD9642 1.8 V supply voltages DDR LVDS AND LVDS (ANSI-644 levels) outputs D12±/D13± DRIVERS Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS DCO± REFERENCE IF sampling frequencies of up to 350 MHz Internal ADC voltage reference 1-TO-8 Flexible analog input range SERIAL PORT CLOCK DIVIDER 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer Serial port control SCLK SDIO CSB CLK+ CLK– Energy saving power-down modes Figure 1. User-configurable, built-in self-test (BIST) capability APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9642 is a 14-bit analog-to-digital converter (ADC) with Programming for setup and control is accomplished using a sampling speeds of up to 250 MSPS. The AD9642 is designed to 3-wire SPI-compatible serial interface. support communications applications, where low cost, small The AD9642 is available in a 32-lead LFCSP and is specified size, wide bandwidth, and versatility are desired. over the industrial temperature range of −40°C to +85°C. This The ADC core features a multistage, differential pipelined product is protected by a U.S. patent. architecture with integrated output error correction logic. The PRODUCT HIGHLIGHTS ADC features wide bandwidth inputs that can support a variety 1. Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. of user-selectable input ranges. An integrated voltage reference 2. Operation from a single 1.8 V supply and a separate digital eases design considerations. A duty cycle stabilizer (DCS) is output driver supply accommodating LVDS outputs. provided to compensate for variations in the ADC clock duty 3. Proprietary differential input maintains excellent SNR cycle, allowing the converter to maintain excellent performance. performance for input frequencies of up to 350 MHz. The ADC output data is routed directly to the external 4. 3-pin, 1.8 V SPI port for register programming and readback. 14-bit LVDS output port. 5. Pin compatibility with the AD9634, allowing a simple migra- Flexible power-down options allow significant power savings, tion from 14 bits to 12 bits, and with the AD6672. when desired. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09995-001 AD9642 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 17  Applications....................................................................................... 1  ADC Architecture ...................................................................... 17  Functional Block Diagram .............................................................. 1  Analog Input Considerations ................................................... 17  General Description ......................................................................... 1  Voltage Reference ....................................................................... 19  Product Highlights ........................................................................... 1  Clock Input Considerations...................................................... 19  Revision History ............................................................................... 2  Power Dissipation and Standby Mode .................................... 20  Specifications..................................................................................... 3  Digital Outputs ........................................................................... 20  ADC DC Specifications............................................................... 3  Serial Port Interface (SPI).............................................................. 22  ADC AC Specifications ............................................................... 4  Configuration Using the SPI..................................................... 22  Digital Specifications ................................................................... 5  Hardware Interface..................................................................... 22  Switching Specifications .............................................................. 6  SPI Accessible Features.............................................................. 23  Timing Specifications .................................................................. 7  Memory Map .................................................................................. 24  Absolute Maximum Ratings............................................................ 8  Reading the Memory Map Register Table............................... 24  Thermal Characteristics .............................................................. 8  Memory Map Register Table..................................................... 25  ESD Caution.................................................................................. 8  Applications Information .............................................................. 27  Pin Configurations and Function Descriptions ........................... 9  Design Guidelines ...................................................................... 27  Typical Performance Characteristics ........................................... 10  Outline Dimensions....................................................................... 28  Equivalent Circuits ......................................................................... 16  Ordering Guide .......................................................................... 28  REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9642 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 1. AD9642-170 AD9642-210 AD9642-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±11 ±11 ±10 mV Gain Error Full +2/−11 +3.5/−8 +3/−7 %FSR Differential Nonlinearity (DNL) Full ±0.5 ±0.55 ±0.6 LSB 25°C ±0.3 ±0.3 ±0.32 LSB 1 Integral Nonlinearity (INL) Full ±1.3 ±2.0 ±2.5 LSB 25°C ±0.6 ±0.75 ±1.0 LSB TEMPERATURE DRIFT Offset Error Full ±7 ±7 ±7 ppm/°C Gain Error Full ±52 ±105 ±75 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.83 0.85 0.85 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p 2 Input Capacitance Full 2.5 2.5 2.5 pF 3 Input Resistance Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 I Full 123 136 129 139 136 146 mA AVDD 1 IDRVDD Full 50 64 56 67 64 69 mA POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 311 360 333 371 360 387 mW 4 Standby Power Full 50 50 50 mW Power-Down Power Full 5 5 5 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. 0 | Page 3 of 28 AD9642 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. AD9642-170 AD9642-210 AD9642-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 30 MHz 25°C 72.5 72.4 72.2 dBFS IN fIN = 90 MHz 25°C 72.2 72.2 72.0 dBFS Full 70.7 70.0 dBFS fIN = 140 MHz 25°C 71.8 71.6 71.8 dBFS f = 185 MHz 25°C 71.2 71.5 71.4 dBFS IN Full 68.6 dBFS fIN = 220 MHz 25°C 70.7 71.0 70.9 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 30 MHz 25°C 71.5 71.5 71.2 dBFS IN fIN = 90 MHz 25°C 71.3 71.3 71.0 dBFS Full 69.6 68.7 dBFS fIN = 140 MHz 25°C 70.8 70.6 70.9 dBFS fIN = 185 MHz 25°C 70.3 70.5 70.4 dBFS Full 67.5 dBFS fIN = 220 MHz 25°C 69.7 70.1 70.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) f = 30 MHz 25°C 11.6 11.6 11.5 Bits IN f = 90 MHz 25°C 11.6 11.6 11.5 Bits IN fIN = 140 MHz 25°C 11.5 11.4 11.5 Bits f = 185 MHz 25°C 11.4 11.4 11.4 Bits IN fIN = 220 MHz 25°C 11.3 11.3 11.3 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −96 −96 −90 dBc f = 90 MHz 25°C −95 −92 −89 dBc IN Full −82 −79 dBc f = 140 MHz 25°C −97 −94 −90 dBc IN f = 185 MHz 25°C −86 −95 −86 dBc IN Full −80 dBc f = 220 MHz 25°C −84 −84 −86 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 96 96 90 dBc f = 90 MHz 25°C 95 92 89 dBc IN Full 82 79 dBc fIN = 140 MHz 25°C 97 94 90 dBc f = 185 MHz 25°C 86 95 86 dBc IN Full 80 dBc f = 220 MHz 25°C 84 84 86 dBc IN WORST OTHER (HARMONIC OR SPUR) f = 30 MHz 25°C −99 −98 −95 dBc IN fIN = 90 MHz 25°C −95 −97 −98 dBc Full −87 −81 dBc fIN = 140 MHz 25°C −98 −96 −97 dBc fIN = 185 MHz 25°C −96 −97 −96 dBc Full −81 dBc fIN = 220 MHz 25°C −97 −94 −95 dBc TWO-TONE SFDR f = 184.1 MHz, 187.1 MHz (−7 dBFS) 25°C 87 88 88 dBc IN Rev. 0 | Page 4 of 28 AD9642 AD9642-170 AD9642-210 AD9642-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit 2 FULL POWER BANDWIDTH 25°C 350 350 350 MHz 3 NOISE BANDWIDTH 25°C 1000 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved. 3 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full 10 22 μA Low Level Input Current Full −22 −10 μA Input Capacitance Full 4 pF Input Resistance Full 12 15 18 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 50 71 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUTS (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR Outputs (OR+, OR−) Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (V), ANSI Mode Full 1.15 1.25 1.35 V OS Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull-up. 2 Pull-down. Rev. 0 | Page 5 of 28 AD9642 SWITCHING SPECIFICATIONS Table 4. AD9642-170 AD9642-210 AD9642-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 40 170 40 210 40 250 MSPS CLK Period—Divide-by-1 Mode (t) Full 5.8 4.8 4 ns CLK CLK Pulse Width High (t) CH Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Full 0.8 0.8 0.8 ns Divide-by-8 Mode Aperture Delay (t) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J DATA OUTPUT PARAMETERS Data Propagation Delay (t) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns PD DCO Propagation Delay (t) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns DCO DCO-to-Data Skew (tSKEW) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power-Down) Full 100 100 100 μs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider. Timing Diagram t A N – 1 N + 4 N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO– DCO+ t SKEW t PD D0±/D1± D0 D1 D0 D1 D0 D1 D0 D1 D0 EVEN/ODD (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 D12±/D13± D12 D13 D12 D13 D12 D13 D12 D12 D12 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 Figure 2. LVDS Data Output Timing Rev. 0 | Page 6 of 28 09995-002 AD9642 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI TIMING REQUIREMENTS See Figure 58 for SPI timing diagram t Setup time between the data and the rising edge of SCLK 2 ns DS tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns t Hold time between CSB and SCLK 2 ns H t Minimum period that SCLK should be in a logic high state 10 ns HIGH t Minimum period that SCLK should be in a logic low state 10 ns LOW tEN_SDIO Time required for the SDIO pin to switch from an input to an output 10 ns relative to the SCLK falling edge (not shown in Figure 58) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input 10 ns relative to the SCLK rising edge (not shown in Figure 58) Rev. 0 | Page 7 of 28 AD9642 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating The exposed paddle must be soldered to the ground plane for the Electrical LFCSP package. Soldering the exposed paddle to the customer AVDD to AGND −0.3 V to +2.0 V board increases the reliability of the solder joints, maximizing DRVDD to AGND −0.3 V to +2.0 V the thermal capability of the package. VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance VCM to AGND −0.3 V to AVDD + 0.2 V Airflow CSB to AGND −0.3 V to DRVDD + 0.3 V Velocity SCLK to AGND −0.3 V to DRVDD + 0.3 V 1, 2 1, 3 1, 4 Package Type (m/sec) θ θ θ Unit JA JC JB SDIO to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 °C/W D0−/D1−, D0+/D1+ Through −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 °C/W D12−/D13−, D12+/D13+ to AGND (CP-32-12) 2.0 29.1 °C/W DCO+, DCO− to AGND −0.3 V to DRVDD + 0.3 V 1 Environmental Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Operating Temperature Range −40°C to +85°C 3 Per MIL-Std 883, Method 1012.1. (Ambient) 4 Per JEDEC JESD51-8 (still air). Maximum Junction Temperature 150°C Under Bias Typical θJA is specified for a 4-layer PCB with a solid ground Storage Temperature Range −65°C to +125°C plane. As shown in Table 7, airflow increases heat dissipation, (Ambient) which reduces θJA. In addition, metal in direct contact with the package leads from metal traces—through holes, ground, and Stresses above those listed under Absolute Maximum Ratings power planes—reduces the θ . JA may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any ESD CAUTION other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 28 AD9642 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CLK+ 1 24 CSB CLK– 2 23 SCLK AVDD 3 AD9642 22 SDIO D0–/D1– (LSB) 4 INTERLEAVED 21 DCO+ LVDS D0+/D1+ (LSB) 5 20 DCO– TOP VIEW 6 19 D2–/D3– D12+/D13+ (MSB) (Not to Scale) D2+/D3+ 7 18 D12–/D13– (MSB) DRVDD 8 17 DRVDD NOTES 1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. LFCSP Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Supplies 8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of the package provides Exposed Paddle the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 25 DNC Do Not Connect. Do not connect to this pin. ADC Analog 30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Outputs 5 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/1—True. 4 D0−/D1− (LSB) Output DDR LVDS Output Data 0/1—Complement. 7 D2+/D3+ Output DDR LVDS Output Data 2/3—True. 6 D2−/D3− Output DDR LVDS Output Data 2/3—Complement. 10 D4+/D5+ Output DDR LVDS Output Data 4/5—True. 9 D4−/D5− Output DDR LVDS Output Data 4/5—Complement. 12 D6+/D7+ Output DDR LVDS Output Data 6/7—True. 11 D6−/D7− Output DDR LVDS Output Data 6/7—Complement. 14 D8+/D9+ Output DDR LVDS Output Data 8/9—True. 13 D8−/D9− Output DDR LVDS Output Data 8/9—Complement. 16 D10+/D11+ Output DDR LVDS Output Data 10/11—True. 15 D10−/D11− Output DDR LVDS Output Data 10/11—Complement. 19 D12+/D13+ (MSB) Output DDR LVDS Output Data 12/13—True. 18 D12−/D13− (MSB) Output DDR LVDS Output Data 12/13—Complement. 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement. SPI Control 23 SCLK Input SPI Serial Clock. 22 SDIO Input/output SPI Serial Data I/O. 24 CSB Input SPI Chip Select (Active Low). Rev. 0 | Page 9 of 28 D4–/D5– 9 32 AVDD D4+/D5+ 10 31 AVDD D6–/D7– 11 30 VIN+ D6+/D7+ 12 29 VIN– D8–/D9– 13 28 AVDD D8+/D9+ 14 27 AVDD 15 26 D10–/D11– VCM D10+/D11+ 16 25 DNC 09995-003 AD9642 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted. 0 0 170MSPS 170MSPS 90.1MHz @ –1dBFS 305.1MHz @ –1dBFS –20 –20 SNR = 71.82dB (72.2dBFS) SNR = 68.0dB (69.0dBFS) SFDR = 93dBc SFDR = 86dBc –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9642-170 Single-Tone FFT with fIN = 90.1 MHz Figure 7. AD9642-170 Single-Tone FFT with fIN = 305.1 MHz 120 0 170MSPS SFDR (dBFS) 185.1MHz @ –1dBFS –20 SNR = 70.2dB (71.2dBFS) 100 SFDR = 86dBc –40 80 SNR (dBFS) –60 60 THIRD HARMONIC SFDR (dBc) –80 SECOND HARMONIC 40 –100 SNR (dBc) 20 –120 –140 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60 70 80 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 5. AD9642-170 Single-Tone FFT with fIN = 185.1 MHz Figure 8. AD9642-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 90.1 MHz, fS = 170 MSPS 0 100 170MSPS 220.1MHz @ –1dBFS 95 –20 SFDR (dBc) SNR = 69.7dB (70.7dBFS) SFDR = 84dBc 90 –40 85 –60 THIRD HARMONIC 80 –80 SNR (dBFS) SECOND HARMONIC 75 –100 70 –120 65 –140 60 60 90 120 150 180 210 240 270 300 330 0 10 20 30 40 50 60 70 80 75 105 135 165 195 225 255 285 315 345 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9642-170 Single-Tone FFT with f = 220.1 MHz ), IN Figure 9. AD9642-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN f = 170 MSPS S Rev. 0 | Page 10 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09995-006 09995-005 09995-004 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) SUPPLY CURRENT (A) 09995-058 09995-007 09995-106 AD9642 0 0 170MSPS 184.12MHz @ –7dBFS –20 187.12MHz @ –7dBFS –20 SFDR = 87dBc (94dBFS) SFDR (dBc) –40 –40 –60 IMD3 (dBc) –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 0 10 20 30 40 50 60 70 80 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 10. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 13. AD9642-170 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS 100 0 SFDR (dBFS) 95 –20 SFDR (dBc) –40 90 IMD3 (dBc) –60 85 –80 80 SFDR (dBFS) –100 75 SNR (dBc) IMD3 (dBFS) –120 70 40 50 60 70 80 90 100 110 120 130 140 150 160 170 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 14. AD9642-170 Single-Tone SNR/SFDR vs. Sample Rate (f ) Figure 11. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) S with f = 90 MHz with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS IN 6000 0 170MSPS 0.830 LSB rms 89.12MHz @ –7dBFS 16,384 TOTAL HITS –20 92.12MHz @ –7dBFS 5000 SFDR = 88dBc (95dBFS) –40 4000 –60 3000 –80 2000 –100 1000 –120 –140 0 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) OUTPUT CODE Figure 12. AD9642-170 Two-Tone FFT with f = 89.12 MHz, f = 92.12 MHz IN1 IN2 Figure 15. AD9642-170 Grounded Input Histogram, fS = 170 MSPS Rev. 0 | Page 11 of 28 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) 09995-011 09995-010 09995-009 SNR/SFDR (dBc and dBFS) NUMBER OF HITS AMPLITUDE (dBFS) N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 09995-014 09995-012 09995-013 AD9642 0 0 210MSPS 210MSPS 90.1MHz @ –1dBFS 305.1MHz @ –1dBFS –20 –20 SNR = 71.2dB (72.2dBFS) SNR = 68.7dB (69.7dBFS) SFDR = 92dBc SFDR = 83dBc –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC –80 –80 SECOND HARMONIC –100 –100 –120 –120 –140 –140 0 15 30 45 60 75 90 105 01 15 30 45 60 75 9005 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. AD9642-210 Single-Tone FFT with fIN = 90.1 MHz Figure 19. AD9642-210 Single-Tone FFT with fIN = 305.1 MHz 0 120 210MSPS SFDR (dBFS) 185.1MHz @ –1dBFS –20 SNR = 70.5dB (71.5dBFS) 100 SFDR = 93dBc –40 80 SNR (dBFS) –60 60 SECOND HARMONIC SFDR (dBc) –80 THIRD HARMONIC 40 –100 SNR (dBc) 20 –120 –140 0 0 15 30 45 60 75 90 105 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 17. AD9642-210 Single-Tone FFT with fIN = 185.1 MHz Figure 20. AD9642-210 Single-Tone SNR/SFDR vs. Input Amplitude (A ) IN with f = 90.1 MHz, f = 210 MSPS IN S 0 100 210MSPS 220.1MHz @ –1dBFS 95 –20 SNR = 70dB (71dBFS) SFDR (dBc) SFDR = 84dBc 90 –40 85 SECOND HARMONIC –60 THIRD HARMONIC 80 –80 75 SNR (dBFS) –100 70 –120 65 –140 60 0 15 30 45 60 75 90 105 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9642-210 Single-Tone FFT with f = 220.1 MHz Figure 21. AD9642-210 Single-Tone SNR/SFDR vs. Input Frequency (f ), IN IN f = 210 MSPS S Rev. 0 | Page 12 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09995-017 09995-016 09995-015 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc and dBFS) 60 75 90 105 120 135 150 165 180 195 210 225 240 255 270 285 300 315 330 345 09995-019 09995-018 09995-117 AD9642 0 0 210MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS –20 –20 SFDR = 88dBc (95dBFS) SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 0 153045 6075 90 105 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 22. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Figure 25. AD9642-210 Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 210 MSPS 0 100 SFDR (dBc) 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 SFDR (dBFS) 75 –100 SNR (dBFS) IMD3 (dBFS) 70 –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 23. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 26. AD9642-210 Single-Tone SNR/SFDR vs. Sample Rate (f ) IN S with f = 184.12 MHz, f = 187.12 MHz, f = 210 MSPS with f = 90 MHz IN1 IN2 S IN 0 6000 210MSPS 0.852 LSB rms 89.12MHz @ –7dBFS 16,384 TOTAL HITS –20 92.12MHz @ –7dBFS 5000 SFDR = 89dBc (96dBFS) –40 4000 –60 3000 –80 2000 –100 1000 –120 –140 0 0 15 30 45 60 75 90 105 FREQUENCY (MHz) OUTPUT CODE Figure 24. AD9642-210 Two-Tone FFT with f = 89.12 MHz, f = 92.12 MHz Figure 27. AD9642-210 Grounded Input Histogram, f = 210 MSPS IN1 IN2 S Rev. 0 | Page 13 of 28 AMPLITUDE (dBFS) SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) 09995-021 09995-022 09995-020 SNR/SFDR (dBc and dBFS) AMPLITUDE (dBFS) NUMBER OF HITS 40 N – 5 50 60 N – 4 70 N – 3 80 N – 2 90 100 N – 1 110 N 120 130 N + 1 140 N + 2 150 160 N + 3 170 N + 4 180 N + 5 190 200 N + 6 210 09995-025 09995-023 09995-024 AD9642 0 0 250MSPS 250MSPS 90.1MHz @ –1dBFS 305.1MHz @ –1dBFS –20 –20 SNR = 71dB (72dBFS) SNR = 68.5dB (69.5dBFS) SFDR = 89dBc SFDR = 82dBc –40 –40 THIRD HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 25 50 75 100 125 0 25 50 75 100 125 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. AD9642-250 Single-Tone FFT with fIN = 90.1 MHz Figure 31. AD9642-250 Single-Tone FFT with fIN = 305.1 MHz 0 120 250MSPS SFDR (dBFS) 185.1MHz @ –1dBFS –20 100 SNR = 70.4dB (71.4dBFS) SFDR = 86dBc –40 80 SNR (dBFS) THIRD HARMONIC –60 60 SECOND HARMONIC SFDR (dBc) –80 40 –100 SNR (dBc) 20 –120 –140 0 0 25 50 75 100 125 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 29. AD9642-250 Single-Tone FFT with f = 185.1 MHz Figure 32. AD9642-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) IN with fIN = 90.1 MHz, fS = 250 MSPS 0 100 250MSPS 220.1MHz @ 1.0dBFS 95 SNR = 69.9dB (70.9dBFS) –20 SFDR (dBFS) SFDR = 91dBc 90 –40 85 –60 80 THIRD HARMONIC –80 SECOND HARMONIC 75 –100 70 SNR (dBc) –120 65 –140 60 0 25 50 75 100 125 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. AD9642-250 Single-Tone FFT with f = 220.1 MHz Figure 33. AD9642-250 Single-Tone SNR/SFDR vs. Input Frequency (f ), IN IN f = 250 MSPS S Rev. 0 | Page 14 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09995-059 09995-027 09995-026 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc and dBFS) 60 75 90 105 120 135 150 165 180 195 210 225 240 255 270 285 300 315 330 345 09995-030 09995-029 09995-128 AD9642 0 0 250MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS –20 SFDR = 87dBc (94dBFS) –20 SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –120 0 255075 100 125 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 34. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Figure 37. AD9642-250 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS 0 100 95 –20 SFDR (dBc) –40 90 SFDR IMD3 (dBc) 85 –60 –80 80 SFDR (dBFS) –100 75 SNR IMD3 (dBFS) –120 70 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 35. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Figure 38. AD9642-250 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS with fIN = 90 MHz 0 5000 0.847LSB rms 250MSPS 16,384 TOTAL HITS 4500 89.12MHz @ –7.0dBFS –20 92.12MHz @ –7.0dBFS SFDR = 88dBc (95dBFS) 4000 –40 3500 3000 –60 2500 –80 2000 1500 –100 1000 –120 500 –140 0 0 25 50 75 100 125 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 FREQUENCY (MHz) OUTPUT CODE Figure 36. AD9642-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 39. AD9642-250 Grounded Input Histogram, fS = 250 MSPS Rev. 0 | Page 15 of 28 AMPLITUDE (dBFS) SFDR/IMD3 (dBc and dBFS) SFDR/IMD3 (dBc and dBFS) 09995-033 09995-032 09995-031 AMPLITUDE (dBFS) NUMBER OF HITS SNR/SFDR (dBFS/dBc) 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 09995-035 09995-036 09995-034 AD9642 EQUIVALENT CIRCUITS DRVDD AVDD VIN 350Ω SDIO 26kΩ Figure 43. Equivalent SDIO Circuit Figure 40. Equivalent Analog Input Circuit AVDD AVDD AVDD 0.9V 350Ω SCLK 15kΩ 15kΩ CLK+ CLK– 26kΩ Figure 41. Equivalent Clock Input Circuit Figure 44. Equivalent SCLK Input Circuit DRVDD AVDD 26kΩ 350Ω V+ V– CSB DATAOUT– DATAOUT+ V– V+ Figure 45. Equivalent CSB Input Circuit Figure 42. Equivalent LVDS Output Circuit Rev. 0 | Page 16 of 28 09995-037 09995-039 09995-038 09995-042 09995-040 09995-041 AD9642 THEORY OF OPERATION The AD9642 can sample any fS/2 frequency segment from dc to “Transformer-Coupled Front-End for Wideband A/D Converters,” 250 MHz using appropriate low-pass or band-pass filtering at for more information on this subject. the ADC inputs with little loss in ADC performance. BIAS Programming and control of the AD9642 are accomplished S S C using a 3-pin, SPI-compatible serial interface. C S FB VIN+ ADC ARCHITECTURE C C PAR1 PAR2 The AD9642 architecture consists of a front-end sample-and- H S S hold circuit, followed by a pipelined switched-capacitor ADC. C The quantized outputs from each stage are combined into a S VIN– final 14-bit result in the digital correction logic. The pipelined C C C FB PAR1 PAR2 S architecture permits the first stage to operate on a new input S BIAS sample and the remaining stages to operate on the preceding Figure 46. Switched-Capacitor Input samples. Sampling occurs on the rising edge of the clock. For best dynamic performance, match the source impedances Each stage of the pipeline, excluding the last, consists of a low driving VIN+ and VIN− and differentially balance the inputs. resolution flash ADC connected to a switched-capacitor digital- to-analog converter (DAC) and an interstage residue amplifier Input Common Mode (MDAC). The MDAC magnifies the difference between the The analog inputs of the AD9642 are not internally dc biased. reconstructed DAC output and the flash input for the next stage In ac-coupled applications, the user must provide this bias in the pipeline. One bit of redundancy is used in each stage to externally. Setting the device so that V = 0.5 × AVDD (or CM facilitate digital correction of flash errors. The last stage simply 0.9 V) is recommended for optimum performance. An on- consists of a flash ADC. board common-mode voltage reference is included in the The input stage of the AD9642 contains a differential sampling design and is available from the VCM pin. Using the VCM circuit that can be ac- or dc-coupled in differential or single- output to set the input common mode is recommended. ended modes. The output staging block aligns the data, corrects Optimum performance is achieved when the common-mode errors, and passes the data to the output buffers. The output voltage of the analog input is set by the VCM pin voltage buffers are powered from a separate supply, allowing digital (typically 0.5 × AVDD). The VCM pin must be decoupled to output noise to be separated from the analog core. During ground by a 0.1 μF capacitor, as described in the Applications power-down, the output buffers go into a high impedance state. Information section. Place this decoupling capacitor close to the pin to minimize the series resistance and inductance between ANALOG INPUT CONSIDERATIONS the part and this capacitor. The analog input to the AD9642 is a differential switched- Differential Input Configurations capacitor circuit that has been designed to attain optimum performance when processing a differential input signal. Optimum performance can be achieved when driving the AD9642 in a differential input configuration. For baseband applications, The clock signal alternatively switches the input between the AD8138, ADA4937-1, and ADA4930-1 differential drivers sample mode and hold mode (see the configuration shown in provide excellent performance and a flexible interface to the ADC. Figure 46). When the input is switched into sample mode, the signal source must be capable of charging the sampling The output common-mode voltage of the ADA4930-1 is easily capacitors and settling within 1/2 clock cycle. set with the VCM pin of the AD9642 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to A small resistor in series with each input can help reduce the provide band-limiting of the input signal. peak transient current required from the output stage of the 15pF driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive 200Ω 33Ω 15Ω network creates a low-pass filter at the ADC input; therefore, 90Ω VIN– AVDD VIN 76.8Ω the precise values are dependent on the application. 5pF ADC ADA4930-1 In intermediate frequency (IF) undersampling applications, the 0.1µF 33Ω 15Ω shunt capacitors should be reduced. In combination with the VCM VIN+ 120Ω driving source impedance, the shunt capacitors limit the input 15pF 200Ω bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 0.1µF Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, Figure 47. Differential Input Configuration Using the ADA4930-1 Rev. 0 | Page 17 of 28 09995-043 09995-044 AD9642 For baseband applications where SNR is a key parameter, adjusted or some components may need to be removed. Table 9 differential transformer coupling is the recommended input displays recommended values to set the RC network for different configuration. An example is shown in Figure 48. To bias the input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as a analog input, connect the VCM voltage to the center tap of the secondary winding of the transformer. starting guide. Note that the values given in Table 9 are for each R1, R2, C2, and R3 component shown in Figure 48 and Figure 50. C2 R3 R2 Table 9. Example RC Network VIN+ R1 Frequency R1 C1 R2 C2 R3 2V p-p 49.9Ω Range Series Differential Series Shunt Shunt C1 ADC (MHz) (Ω) (pF) (Ω) (pF) (Ω) R2 R1 VCM VIN– 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 0.1µF R3 0.1µF C2 An alternative to using a transformer-coupled input at Figure 48. Differential Transformer-Coupled Configuration frequencies in the second Nyquist zone is to use an amplifier with variable gain. The AD8375 digital variable gain amplifier The signal characteristics must be considered when selecting (DVGA) provides good performance for driving the AD9642. a transformer. Most RF transformers saturate at frequencies below a few megahertz. Excessive signal power can also cause Figure 49 shows an example of the AD8375 driving the AD9642 core saturation, which leads to distortion. through a band-pass antialiasing filter. 1000pF 180nH 220nH At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve 1µH 165Ω 15pF the true SNR performance of the AD9642. For applications where VPOS AD9642 AD8375 SNR is a key parameter, differential double balun coupling is 5.1pF 3.9pF VCM 2.5kΩ║2pF the recommended input configuration (see Figure 50). In this 1nF 1µH 301Ω 165Ω 1nF 68nH configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω resistor. This resistor 180nH 220nH 1000pF NOTES compensates for losses in the input baluns to provide a 50 Ω ® 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS). impedance to the driver. 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. In the double balun and transformer configurations, the value Figure 49. Differential Input Configuration Using the AD8375 of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters, the value of the input resistors and capacitors may need to be C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– R3 0.1µF C2 Figure 50. Differential Double Balun Input Configuration Rev. 0 | Page 18 of 28 09995-045 09995-047 09995-046 AD9642 VOLTAGE REFERENCE 25Ω A stable and accurate voltage reference is built into the AD9642. ADC 390pF 390pF CLOCK The full-scale input range can be adjusted by varying the reference CLK+ INPUT voltage via SPI. The input span of the ADC tracks reference voltage 390pF changes linearly. 1nF CLK– SCHOTTKY 25Ω CLOCK INPUT CONSIDERATIONS DIODES: HSMS2822 For optimum performance, the AD9642 sample clock inputs, Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ and CLK−, should be clocked with a differential signal. If a low jitter clock source is not available, another option is to The signal is typically ac-coupled into the CLK+ and CLK− pins ac-couple a differential PECL signal to the sample clock input via a transformer or via capacitors. These pins are biased internally pins as shown in Figure 54. The AD9510, AD9511, AD9512, (see Figure 51) and require no external bias. If the inputs are AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, floated, the CLK− pin is pulled low to prevent spurious clocking. AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ AVDD ADCLK925 clock drivers offer excellent jitter performance. 0.9V 0.1µF 0.1µF CLOCK CLK+ CLK+ CLK– INPUT AD95xx, ADC 100Ω ADCLK9xx AD9642 4pF 4pF 0.1µF PECL DRIVER 0.1µF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 51. Simplified Equivalent Clock Input Circuit Figure 54. Differential PECL Sample Clock (Up to 625 MHz) Clock Input Options A third option is to ac-couple a differential LVDS signal to the The AD9642 has a very flexible clock input structure. Clock input sample clock input pins, as shown in Figure 55. The AD9510, can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, of the type of signal being used, clock source jitter is of the most AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers concern, as described in the Jitter Considerations section. offer excellent jitter performance. Figure 52 and Figure 53 show two preferable methods for clocking the AD9642 (at clock rates of up to 625 MHz). A low 0.1µF 0.1µF CLOCK CLK+ jitter clock source is converted from a single-ended signal to a INPUT ADC AD95xx differential signal using an RF balun or RF transformer. 100Ω LVDS DRIVER AD9642 0.1µF 0.1µF CLOCK The RF balun configuration is recommended for clock CLK– INPUT 50kΩ 50kΩ frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from Figure 55. Differential LVDS Sample Clock (Up to 625 MHz) 10 MHz to 200 MHz. The back-to-back Schottky diodes across the secondary winding of the transformer limit clock excursions Input Clock Divider into the AD9642 to approximately 0.8 V p-p differential. This The AD9642 contains an input clock divider with the ability to limit helps prevent the large voltage swings of the clock from divide the input clock by integer values between 1 and 8. The feeding through to other portions of the AD9642 while duty cycle stabilizer (DCS) is enabled by default on power-up. preserving the fast rise and fall times of the signal, which are Clock Duty Cycle critical for low jitter performance. Typical high speed ADCs use both clock edges to generate a ® Mini-Circuits variety of internal timing signals and, as a result, may be ADT1-1WT, 1:1Z ADC sensitive to clock duty cycle. Commonly, a ±5% tolerance is 390pF 390pF XFMR CLOCK CLK+ required on the clock duty cycle to maintain dynamic INPUT 100Ω 50Ω performance characteristics. 390pF CLK– The AD9642 contains a DCS that retimes the nonsampling (falling) SCHOTTKY DIODES: edge, providing an internal clock signal with a nominal 50% duty HSMS2822 cycle. This allows the user to provide a wide range of clock input Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz) duty cycles without affecting the performance of the AD9642. Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. The duty Rev. 0 | Page 19 of 28 09995-048 09995-056 09995-057 09995-052 09995-051 AD9642 cycle control loop does not function for clock rates less than using the same operating conditions as those used for the 40 MHz nominally. The loop has a time constant associated Typical Performance Characteristics section. with it that must be considered when the clock rate may change 0.4 0.25 dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS 0.20 loop is relocked to the input signal. During the time that the loop 0.3 TOTAL POWER is not locked, the DCS loop is bypassed, and internal device timing 0.15 is dependent on the duty cycle of the input clock signal. In such IAVDD applications, it may be appropriate to disable the duty cycle 0.2 stabilizer. In all other applications, enabling the DCS circuit is 0.10 recommended to maximize ac performance. 0.1 IDRVDD Jitter Considerations 0.05 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input 0 0 40 55 70 85 100 115 130 145 160 175 190 205 220 235 250 frequency (f ) due to jitter (t ) can be calculated by IN J ENCODE FREQUENCY (MSPS) (−SNR /10) 2 LF Figure 57. AD9642-250 Power and Current vs. Sample Rate SNR = −10 log[(2π × f × t ) + 10 ] HF IN JRMS By setting the internal power-down mode bits (Bits[1:0]) in the In the equation, the rms aperture jitter represents the root- power modes register (Address 0x08) to 01, the AD9642 is mean-square of all jitter sources, which include the clock input, placed in power-down mode. In this state, the ADC typically the analog input signal, and the ADC aperture jitter specification. dissipates 2.5 mW. During power-down, the output drivers are IF undersampling applications are particularly sensitive to jitter, placed in a high impedance state. as shown in Figure 56. 80 Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, 75 and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning 70 to normal operation. As a result, the wake-up time is related to the time spent in power-down mode, and shorter power-down 65 cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC 60 in power-down mode or standby mode. Standby mode allows 0.05ps 0.2ps the user to keep the internal reference circuitry powered when 55 0.5ps 1ps faster wake-up times are required. To put the part into standby 1.5ps MEASURED mode, set the internal power-down mode bits (Bits[1:0]) in the 50 1 10 100 1000 power modes register (Address 0x08) to 10. See the Memory INPUT FREQUENCY (MHz) Map section and the AN-877 Application Note, Interfacing to Figure 56. AD9642-250 SNR vs. Input Frequency and Jitter High Speed ADCs via SPI, for additional details. In cases where aperture jitter may affect the dynamic range of the DIGITAL OUTPUTS AD9642, treat the clock input as an analog signal. In addition, The AD9642 output drivers can be configured for either ANSI use separate power supplies for the clock drivers and the ADC LVDS or reduced swing LVDS using a 1.8 V DRVDD supply. output driver to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators provide the best As detailed in the AN-877 Application Note, Interfacing to High clock sources. If the clock is generated from another type of source Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. (by gating, dividing, or another method), it should be retimed by the original clock during the last step. Digital Output Enable Function (OEB) Refer to the AN-501 Application Note, Aperture Uncertainty and The AD9642 has a flexible three-state ability for the digital ADC System Performance, and the AN-756 Application Note, output pins. The three-state mode is enabled using the SPI Sampled Systems and the Effects of Clock Phase Noise and Jitter, for interface. The data outputs can be three-stated by using the more information about jitter performance as it relates to ADCs. output enable bar bit (Bit 4) in Register 0x14. This OEB function is not intended for rapid access to the data bus. POWER DISSIPATION AND STANDBY MODE As shown in Figure 57, the power dissipated by the AD9642 is proportional to its sample rate. The data in Figure 57 was taken Rev. 0 | Page 20 of 28 SNR (dBFS) 09995-061 TOTAL POWER (W) SNR/SFDR (dBc and dBFS) 09995-060 AD9642 Timing The lowest typical conversion rate of the AD9642 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may The AD9642 provides latched data with a pipeline delay of degrade. 10 input sample clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Data Clock Output (DCO) Minimize the length of the output data lines as well as the loads The AD9642 also provides the data clock output (DCO) intended placed on these lines to reduce transients within the AD9642. for capturing the data in an external register. Figure 2 shows a These transients may degrade converter dynamic performance. timing diagram of the AD9642 output modes. Table 10. Output Data Format VIN+ − VIN−, Input (V) Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) VIN+ − VIN− <–0.875 00 0000 0000 0000 10 0000 0000 0000 VIN+ − VIN− −0.875 00 0000 0000 0000 10 0000 0000 0000 VIN+ − VIN− 0 10 0000 0000 0000 00 0000 0000 0000 VIN+ − VIN− +0.875 11 1111 1111 1111 01 1111 1111 1111 VIN+ − VIN− >+0.875 11 1111 1111 1111 01 1111 1111 1111 Rev. 0 | Page 21 of 28 AD9642 SERIAL PORT INTERFACE (SPI) The AD9642 serial port interface (SPI) allows the user to All data is composed of 8-bit words. The first bit of each configure the converter for specific functions or operations individual byte of serial data indicates whether a read or write through a structured register space provided inside the ADC. command is issued. This allows the serial data input/output The SPI offers added flexibility and customization, depending (SDIO) pin to change direction from an input to an output. on the application. Addresses are accessed via the serial port In addition to word length, the instruction phase determines and can be written to or read from via the port. Memory is whether the serial frame is a read or write operation, allowing organized into bytes that can be further divided into fields. the serial port to be used both to program the chip and to read the These fields are documented in the Memory Map section. For contents of the on-chip memory. If the instruction is a readback detailed operational information, see the AN-877 Application operation, performing a readback causes the serial data input/ Note, Interfacing to High Speed ADCs via SPI. output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, Data can be sent in MSB first mode or in LSB first mode. MSB first mode is the default on power-up and can be changed via the SPI and the CSB pin (see Table 11). The SCLK (serial clock) pin is port configuration register. For more information about this and used to synchronize the read and write data presented from and other features, see the AN-877 Application Note, Interfacing to to the ADC. The SDIO (serial data input/output) pin is a dual- High Speed ADCs via SPI. purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an HARDWARE INTERFACE active low control that enables or disables the read and write cycles. The pins described in Table 11 comprise the physical interface Table 11. Serial Port Interface Pins between the user programming device and the serial port of the Pin Function AD9642. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. functioning as an input during write phases and as an output SDIO Serial data input/output. A dual-purpose pin that during readback. typically serves as an input or an output, depending on The SPI interface is flexible enough to be controlled by either the instruction being sent and the relative position in the FPGAs or microcontrollers. One method for SPI configuration timing frame. is described in detail in the AN-812 Application Note, Micro- CSB Chip select bar. An active low control that gates the read and write cycles. controller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full The falling edge of CSB, in conjunction with the rising edge of dynamic performance of the converter is required. Because the SCLK, determines the start of the framing. An example of the SCLK signal, the CSB signal, and the SDIO signal are typically serial timing and its definitions can be found in Figure 58 and asynchronous to the ADC clock, noise from these signals can Table 5. degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between Other modes involving the CSB are available. The CSB can be this bus and the AD9642 to prevent these signals from transi- held low indefinitely, which permanently enables the device; tioning at the converter inputs during critical sampling periods. this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Rev. 0 | Page 22 of 28 AD9642 SPI ACCESSIBLE FEATURES Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 12. Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power-down mode or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Digital Processing Allows the user to enable the synchronization features t HIGH t DS t t CLK H t t S DH t LOW CSB DON’T DON’T SCLK CARE CARE DON’T DON’T R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SDIO CARE CARE Figure 58. Serial Port Interface Timing Diagram Rev. 0 | Page 23 of 28 09995-055 AD9642 MEMORY MAP Address 0x18). If the entire address location is open (for example, READING THE MEMORY MAP REGISTER TABLE Address 0x13), this address location should not be written. Each row in the memory map register table has eight bit locations. Default Values The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the After the AD9642 is reset, critical registers are loaded with default values. The default values for the registers are given in transfer register (Address 0xFF); and the ADC functions registers, the memory map register table (Table 13). including setup, control, and test (Address 0x08 to Address 0x25). The memory map register table (Table 13) documents the Logic Levels default hexadecimal value for each hexadecimal address shown. An explanation of logic level terminology follows: The Bit 7 (MSB) column is the start of the default hexadecimal • “Bit is set” is synonymous with “bit is set to Logic 1” or value given. For example, Address 0x14, the output mode register, “writing Logic 1 for the bit.” has a hexadecimal default value of 0x01. This means that Bit 0 = 1 • “Clear a bit” is synonymous with “bit is set to Logic 0” or and the remaining bits are 0s. This setting is the default output “writing Logic 0 for the bit.” format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Transfer Register Map Interfacing to High Speed ADCs via SPI. This document details Address 0x08 to Address 0x20 are shadowed. Writes to these the functions controlled by Register 0x00 to Register 0x25. addresses do not affect part operation until a transfer command Open Locations is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and All address and bit locations that are not included in Table 13 are simultaneously when the transfer bit is set. The internal update not currently supported for this device. Write 0s to unused bits takes place when the transfer bit is set, and then the bit autoclears. of a valid address location. Writing to these locations is required only when part of an address location is open (for example, Rev. 0 | Page 24 of 28 AD9642 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles configuration are mirrored so that LSB first mode or MSB first mode is set correctly, regardless of shift mode. 0x01 Chip ID 8-bit chip ID[7:0] 0x86 Read only. (AD9642 = 0x86) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade ID 00 = 250 MSPS used to 01 = 210 MSPS differentiate 11 = 170 MSPS devices; read only. Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchro- nously transfers data from the master shift register to the slave. ADC Functions Registers 0x08 Power modes Open Open Open Open Open Open Internal power-down mode 0x00 Determines various 00 = normal operation generic 01 = full power-down modes 10 = standby of chip 11 = reserved operation. 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (default) 0x0B Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide Clock divide 000 = no delay 000 = divide by 1 values 001 = 1 input clock cycle 001 = divide by 2 other than 010 = 2 input clock cycles 010 = divide by 3 000 auto- 011 = 3 input clock cycles 011 = divide by 4 matically 100 = 4 input clock cycles 100 = divide by 5 cause the 101 = 5 input clock cycles 101 = divide by 6 duty cycle 110 = 6 input clock cycles 110 = divide by 7 stabilizer to 111 = 7 input clock cycles 111 = divide by 8 become active. 0x0D Test mode User test Open Reset PN Reset PN Output test mode 0x00 When this mode long gen short gen register is 0000 = off (default) control set, the test 0001 = midscale short data is 0 = con- 0010 = positive FS placed on tinuous/ 0011 = negative FS the output repeat 0100 = alternating checkerboard pins in place pattern 0101 = PN long sequence of normal 1 = single 0110 = PN short sequence data. pattern, 0111 = one/zero word toggle then 0s 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output Rev. 0 | Page 25 of 28 AD9642 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (twos complement format) 0x14 Output mode Open Open Open Output Open Output Output format 0x01 Configures enable bar invert the outputs 00 = offset binary and the 0 = normal 01 = twos complement format of 0 = on (default) (default) the data. (default) 1 = inverted 10 = gray code 1 = off 11 = reserved 0x15 Output adjust Open Open Open Open LVDS output drive current adjust 0x01 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved 0x16 Clock phase Invert Open Open Open Open Open Open Open 0x00 control DCO clock 0x17 DCO output Enable Open Open DCO clock delay 0x00 delay DCO [delay = (3100 ps × register value/31 + 100)] clock 00000 = 100 ps delay 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps 0x18 Input span Open Open Open Full-scale input voltage selection 0x00 Full-scale select input 01111 = 2.087 V p-p adjustment … in 0.022 V 00001 = 1.772 V p-p steps. 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1[7:0] 0x00 Pattern 1 LSB 0x1A User Test User Test Pattern 1[15:8] 0x00 Pattern 1 MSB 0x1B User Test Pattern 2[7:0] 0x00 User Test Pattern 2 LSB 0x1C User Test User Test Pattern 2[15:8] 0x00 Pattern 2 MSB 0x1D User Test User Test Pattern 3[7:0] 0x00 Pattern 3 LSB 0x1E User Test User Test Pattern 3[15:8] 0x00 Pattern 3 MSB 0x1F User Test User Test Pattern 4[7:0] 0x00 Pattern 4 LSB 0x20 User Test User Test Pattern 4[15:8] 0x00 Pattern 4 MSB 0x24 BIST signature BIST signature[7:0] 0x00 Read only. LSB 0x25 BIST signature BIST signature[15:8] 0x00 Read only. MSB Rev. 0 | Page 26 of 28 AD9642 APPLICATIONS INFORMATION VCM DESIGN GUIDELINES Decouple the VCM pin to ground with a 0.1 μF capacitor, as Before starting system level design and layout of the AD9642, shown in Figure 48. it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and SPI Port layout requirements for certain pins. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the Power and Ground Recommendations SCLK, CSB, and SDIO signals are typically asynchronous to the When connecting power to the AD9642, it is recommended that ADC clock, noise from these signals can degrade converter two separate 1.8 V supplies be used: use one supply for analog performance. If the on-board SPI bus is used for other devices, (AVDD) and a separate supply for the digital outputs (DRVDD). it may be necessary to provide buffers between this bus and the The designer can employ several different decoupling capacitors AD9642 to keep these signals from transitioning at the to cover both high and low frequencies. Locate these capacitors converter input pins during critical sampling periods. close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD9642. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance can be easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9642 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, overlay a silkscreen to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about the packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Rev. 0 | Page 27 of 28 AD9642 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC * 3.75 EXPOSED PAD 3.60 SQ 3.55 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9642BCPZ-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642BCPZ-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642BCPZ-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642BCPZRL7-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642BCPZRL7-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642BCPZRL7-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9642-170EBZ −40°C to +85°C Evaluation Board with AD9642 and Software AD9642-210EBZ −40°C to +85°C Evaluation Board with AD9642 and Software AD9642-250EBZ −40°C to +85°C Evaluation Board with AD9642 and Software 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09995-0-7/11(0) Rev. 0 | Page 28 of 28 PIN 1 IND AT IC OR 08-16-2010-B