ANALOG DEVICES AD9641

14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC) Data Sheet AD9641 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD SDIO SCLK CSB DRVDD JESD204A coded serial digital outputs SNR = 73.7 dBFS at 70 MHz/80 MSPS SPI AD9641 SNR = 72.8 dBFS at 70 MHz and 155 MSPS SFDR = 94 dBc at 70 MHz and 80 MSPS PROGRAMMING DATA SFDR = 90 dBc at 70 MHz and 155 MSPS DOUT+ Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS VIN+ DOUT– 1.8 V supply operation ADC DSYNC+ VIN– Integer 1-to-8 input clock divider DSYNC– VCM IF sampling frequencies to 250 MHz REFERENCE DATA RATE −148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS MULTIPLIER −148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS DUTY CYCLE Programmable internal ADC voltage reference STABILIZER Flexible analog input range: 1.4 V p-p to 2.1 V p-p DIVIDE-BY-1 CLK+ MULTICHIP ADC clock duty cycle stabilizer (DCS) TO SYNC DIVIDE-BY-8 CLK– Serial port control User-configurable, built-in self-test (BIST) capability AGND SYNC PDWN DRGND Energy-saving power-down modes Figure 1. APPLICATIONS The ADC output data is routed directly to the JESD204A serial Communications output port. This output is at CML voltage levels. A CMOS or Diversity radio systems LVDS synchronization input (DSYNC) is provided. Multimode digital receivers (3G and 4G) The flexible power-down options allow significant power savings, GSM, EDGE, W-CDMA, LTE, when desired. CDMA2000, WiMAX, TD-SCDMA Programming for setup and control is accomplished using a 3-wire Smart antenna systems SPI-compatible serial interface. General-purpose software radios Broadband data applications The AD9641 is available in a 32-lead LFCSP and is specified over Ultrasound equipment the industrial temperature range of −40°C to +85°C. GENERAL DESCRIPTION This product is protected by a U.S. patent. The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital PRODUCT HIGHLIGHTS converter (ADC) with a high speed serial output interface. The 1. An on-chip PLL allows users to provide a single ADC AD9641 is designed to support communications applications sampling clock. The PLL multiplies the ADC sampling clock where high performance, combined with low cost, small size, and to produce the corresponding JESD204A data rate clock. versatility, is desired. The JESD204A high speed serial interface 2. The configurable JESD204A output block coded data rate reduces board routing requirements and lowers pin count supports up to 1.6 Gbps. requirements for the receiving device. 3. A proprietary differential input maintains excellent SNR The ADC core features a multistage, differential pipelined performance for input frequencies of up to 250 MHz. architecture with integrated output error correction logic. The 4. Operation is from a single 1.8 V power supply. ADC features wide bandwidth, differential sample-and-hold, 5. The standard serial port interface (SPI) supports various analog input amplifiers that support a variety of user-selectable product features and functions, such as data formatting input ranges. An integrated voltage reference eases the design (offset binary, twos complement, or Gray coding), control- considerations. A duty cycle stabilizer (DCS) is provided to ling the clock DCS, power-down, test modes, voltage compensate for variations in the ADC clock duty cycle, reference mode, and serial output configuration. allowing the converter to maintain excellent performance. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DATA SERIALIZER, ENCODER, AND CML DRIVERS 09210-001 AD9641 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 19 General Description ......................................................................... 1 Chip Synchronization ................................................................ 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 21 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 21 Revision History ............................................................................... 2 Built-In Self-Test (BIST) and Output Test .................................. 25 Specifications ..................................................................................... 3 Built-In Self-Test (BIST) ............................................................ 25 ADC DC Specifications ............................................................... 3 Output Test Modes ..................................................................... 25 ADC AC Specifications ............................................................... 4 Serial Port Interface (SPI) .............................................................. 27 Digital Specifications ................................................................... 5 Configuration Using the SPI ..................................................... 27 Switching Specifications .............................................................. 6 Hardware Interface ..................................................................... 28 Timing Specifications .................................................................. 7 SPI Accessible Features .............................................................. 28 Absolute Maximum Ratings ............................................................ 8 Memory Map .................................................................................. 29 Thermal Characteristics .............................................................. 8 Reading the Memory Map Register Table ............................... 29 ESD Caution .................................................................................. 8 Memory Map Register Table ..................................................... 29 Pin Configuration and Function Descriptions ............................. 9 Memory Map Register Descriptions ........................................ 32 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 35 Equivalent Circuits ......................................................................... 16 Design Guidelines ...................................................................... 35 Theory of Operation ...................................................................... 17 Outline Dimensions ....................................................................... 36 ADC Architecture ...................................................................... 17 Ordering Guide .......................................................................... 36 Analog Input Considerations .................................................... 17 REVISION HISTORY 1/12—Rev. A to Rev. B Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13 Change to General Description Section ........................................ 1 Changes to Clock Input Considerations Section ....................... 19 Changes to Table 2 ............................................................................ 4 Changes to Digital Outputs and Timing Section ....................... 23 Moved Figure 65 and Figure 66 .................................................... 23 8/11—Rev. 0 to Rev. A Added Figure 68 ............................................................................. 24 Added Model -155 ......................................................... Throughout Changes to Output Test Modes Section ...................................... 25 Changes to Features .......................................................................... 1 Changes to SPI Accessible Features Section ............................... 28 Changes to Table 1 ............................................................................ 3 Changes to Addr (Hex) 0x02, Table 17 ........................................ 29 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide .......................................................... 36 Changes to Table 4 ............................................................................ 6 Changes to Figure 11 to Figure 14 Captions ............................... 11 7/10—Revision 0: Initial Version Rev. B | Page 2 of 36 Data Sheet AD9641 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted. Table 1. AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±2 ±10 ±2 ±11 mV Gain Error Full −7 −2.5 +1 −7.5 −2.5 +1 % FSR 1 Differential Nonlinearity (DNL) Full ±0.55 ±0.55 LSB 25°C ±0.3 ±0.3 LSB 1 Integral Nonlinearity (INL) Full ±1.1 ±1.2 LSB 25°C ±0.5 ±0.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±35 ±35 ppm/°C INPUT REFERRED NOISE 25°C 0.7 0.7 LSB rms ANALOG INPUT Input Span Full 1.383 1.75 2.087 1.383 1.75 2.087 V p-p 2 Input Capacitance Full 6 5 pF Input Resistance Full 20 20 kΩ VCM OUTPUT LEVEL Full 0.88 0.9 0.92 0.87 0.9 0.92 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 IAVDD Full 96 100 121 132 mA 1 IDRVDD Full 36 40 51 54 mA POWER CONSUMPTION 1 Sine Wave Input Full 238 252 310 335 mW 3 Standby Power Full 56 56 mW Power-Down Power Full 7 18 7 18 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). Rev. B | Page 3 of 36 AD9641 Data Sheet ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted. Table 2. AD9641-80 AD9641-155 1 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) f = 10 MHz 25°C 73.8 72.0 dBFS IN f = 70 MHz 25°C 73.7 71.7 dBFS IN 25°C 72.6 71.3 dBFS f = 180 MHz IN Full 71.8 69.8 dBFS fIN = 220 MHz 25°C 71.3 71.2 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 73.7 71.0 dBFS fIN = 70 MHz 25°C 73.6 70.6 dBFS f = 180 MHz 25°C 72.5 70.2 dBFS IN Full 71.4 68.7 dBFS f = 220 MHz 25°C 71.2 70.1 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) f = 10 MHz 25°C 12.0 11.5 Bits IN f = 70 MHz 25°C 11.9 11.4 Bits IN fIN = 180 MHz 25°C 11.8 11.4 Bits fIN = 220 MHz 25°C 11.5 11.4 Bits WORST SECOND OR THIRD HARMONIC fIN = 10 MHz 25°C −94 −91 dBc fIN = 70 MHz 25°C −94 −91 dBc −90 fIN = 180 MHz 25°C −91 dBc Full −80 −80 dBc f = 220 MHz 25°C −90 −89 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 10 MHz 25°C 94 91 dBc IN f = 70 MHz 25°C 94 91 dBc IN fIN = 180 MHz 25°C 91 90 dBc Full 80 80 dBc fIN = 220 MHz 25°C 90 89 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 10 MHz 25°C −98 −96 dBc fIN = 70 MHz 25°C −98 −98 dBc f = 180 MHz 25°C −96 −94 dBc IN Full −90 −87 dBc f = 220 MHz 25°C −90 −90 dBc IN TWO-TONE SFDR f = 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS ) 25°C 93 89 dBc IN fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 89 89 dBc 2 ANALOG INPUT BANDWIDTH 25°C 780 780 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz. Rev. B | Page 4 of 36 Data Sheet AD9641 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ DSYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ 1 LOGIC INPUT (CSB) Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF Rev. B | Page 5 of 36 AD9641 Data Sheet Parameter Temperature Min Typ Max Unit 1 LOGIC INPUT/OUTPUT (SDIO) Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS Logic Compliance Full CML Differential Output Voltage (VOD) Full 0.6 0.8 1.1 V Output Offset Voltage (V) Full 0.75 DRVDD/2 1.05 V OS 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted. Table 4. AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 640 640 MHz 1 Conversion Rate Full 40 80 40 155 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 6.45 ns CLK Pulse Width High (t) CH Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 1.935 3.225 4.515 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 3.065 3.225 3.385 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay (tA) Full 0.78 0.78 ns Aperture Uncertainty (Jitter, tJ) Full 0.125 0.125 ps rms DATA OUTPUT PARAMETERS Data Output Period or UI (Unit Interval) Full 1/(20 × fCLK) 1/(20 × fCLK) sec Data Output Duty Cycle 25°C 50 50 % Data Valid Time 25°C 0.8 0.75 UI PLL Lock Time (t) 25°C 4 4 μs LOCK Wake Up Time (Standby) 25°C 5 5 μs 2 Wake Up Time (Power-Down) 25°C 2.5 2.5 ms Pipeline Delay (Latency) Full 23 24 23 24 CLK cycles Data Rate (NRZ) 25°C 1.6 3.1 Gbps Deterministic Jitter 25°C 40 40 ps Random Jitter at 1.6 Gbps 25°C 9.5 ps rms Random Jitter at 3.1 Gbps 25°C 5.2 ps rms Output Rise/Fall Time 25°C 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25°C 100 100 Ω OUT-OF-RANGE RECOVERY TIME 25°C 2 2 CLK cycles 1 Conversion rate is the clock rate after the divider. 2 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 6 of 36 Data Sheet AD9641 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.30 ns typ t SYNC to rising edge of CLK+ hold time 0.30 ns typ HSYNC SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min t Time required for the SDIO pin to switch from an input to an output relative to the SCLK 10 ns min EN_SDIO falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK 10 ns min rising edge Timing Diagrams SAMPLE N N – 23 ANALOG N – 22 N + 1 INPUT SIGNAL N – 21 N – 1 N – 20 CLK– CLK+ CLK– CLK+ DOUT+ DOUT– SAMPLE N – 23 SAMPLE N – 22 SAMPLE N – 21 ENCODED INTO 2 ENCODED INTO 2 ENCODED INTO 2 8b/10b SYMBOLS 8b/10b SYMBOLS 8b/10b SYMBOLS Figure 2. Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Input Timing Requirements Rev. B | Page 7 of 36 09210-003 09210-002 AD9641 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the PCB ELECTRICAL increases the reliability of the solder joints and maximizes the AVDD to AGND −0.3 V to +2.0 V thermal capability of the package. DRVDD to AGND −0.3 V to +2.0V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Airflow SYNC to AGND −0.3 V to AVDD + 0.2 V Velocity VCM to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 Package Type (m/sec) θ θ θ Unit JA JC JB CSB to AGND −0.3 V to DRVDD + 0.2 V 32-Lead LFCSP 0 36 3 20 °C/W SCLK to AGND −0.3 V to DRVDD + 0.2 V 5 mm × 5 mm 1.0 32 °C/W SDIO to AGND −0.3 V to DRVDD + 0.2 V (CP-32-12) 2.5 28 °C/W PDWN to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. DOUT+, DOUT− to AGND −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 DSYNC+, DSYNC− to AGND −0.3 V to DRVDD + 0.2 V Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). ENVIRONMENTAL Operating Temperature Range −40°C to +85°C Typical θJA is specified for a 4-layer PCB with a solid ground (Ambient) plane. As shown in Table 7, airflow improves heat dissipation, 150°C Maximum Junction Temperature which reduces θ . In addition, metal in direct contact with the JA Under Bias package leads from metal traces, through holes, ground, and Storage Temperature Range −65°C to +150°C power planes, reduces θ . JA (Ambient) Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 36 Data Sheet AD9641 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD 1 24 PDWN PIN 1 DNC 2 23 DNC INDICATOR AVDD 3 22 CSB CLK+ 4 21 SCLK AD9641 CLK– 5 20 SDIO TOP VIEW AVDD 6 19 DRVDD (Not to Scale) SYNC 7 18 DRVDD AVDD 8 17 DRGND NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. LFCSP Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Supplies 12, 16, 18, 19 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 1, 3, 6, 8, 26, 27, 30, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 2, 23 DNC Do Not Connect. 11, 13, 17 DRGND Driver ground Digital Driver Supply Ground. 0 AGND, Exposed pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 29 VIN+ Input Differential Analog Input Pin (+). 28 VIN− Input Differential Analog Input Pin (−). 25 VCM Output Common-Mode Level Bias Output. 4 CLK+ Input ADC Clock Input—True. 5 CLK− Input ADC Clock Input—Complement. Digital Inputs 7 SYNC Input Input Clock Divider Synchronization Pin. 10 DSYNC+ Input Active Low JESD204A LVDS Sync Input—True/Active Low JESD204A CMOS Sync Input. 9 DSYNC− Input Active Low JESD204A LVDS Sync Input—Complement. Digital Outputs 15 DOUT+ Output CML Output Data—True. 14 DOUT− Output CML Output Data—Complement. SPI Control 21 SCLK Input SPI Serial Clock. 20 SDIO Input/output SPI Serial Data I/O. 22 CSB Input SPI Chip Select (Active Low). ADC Configuration 24 PDWN Input Power-Down Input. Using the SPI interface, this input can be configured as power-down or standby. Rev. B | Page 9 of 36 DSYNC– AVDD DSYNC+ AVDD DRGND AVDD DRVDD VIN+ DRGND VIN– DOUT– AVDD DOUT+ AVDD DRVDD VCM 09210-004 9 32 10 31 11 30 12 29 13 28 14 27 15 6 2 16 25 AD9641 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted. 0 0 80MSPS 80MSPS 10.1MHz @ –1dBFS 140.3MHz @ –1dBFS –20 –20 SNR = 73.0dB (74.0dBFS) SNR = 72.2dB (73.2dBFS) SFDR = 95dBc SFDR = 94.0dBc –40 –40 –60 –60 –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10203040 0 10203040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9641-80 Single-Tone FFT with f = 10.1 MHz Figure 8. AD9641-80 Single-Tone FFT with f = 140.1 MHz IN IN 0 0 80MSPS 80MSPS 30.1MHz @ –1dBFS 180.1MHz @ –1dBFS –20 –20 SNR = 72.7dB (73.7dBFS) SNR = 71.6dB (72.6dBFS) SFDR = 94dBc SFDR = 93dBc –40 –40 –60 –60 SECOND HARMONIC SECOND HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10203040 0 10203040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9641-80 Single-Tone FFT with f = 30.1 MHz Figure 9. AD9641-80 Single-Tone FFT with f = 180.1 MHz IN IN 0 0 80MSPS 80MSPS 220.1MHz @ –1dBFS 70.1MHz @ –1dBFS –20 –20 SNR = 71.1dB (72.1dBFS) SNR = 72.5dB (73.5dBFS) SFDR = 92dBc SFDR = 94.0dBc –40 –40 –60 –60 THIRD HARMONIC SECOND HARMONIC –80 –80 SECOND HARMONIC THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10203040 0 10203040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. AD9641-80 Single-Tone FFT with f = 220.1 MHz Figure 7. AD9641-80 Single-Tone FFT with f = 70.1 MHz IN IN Rev. B | Page 10 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09210-007 09210-006 09210-005 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09210-010 09210-009 09210-008 Data Sheet AD9641 100 120 95 100 90 80 SNR @ –40°C 85 SFDR @ –40°C SFDR (dBFS) SNR @ +25°C 60 SFDR (dBc) SFDR @ +25°C SNR (dBFS) 80 SNR @ +85°C SNR (dBc) SFDR @ +85°C 40 75 20 70 0 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 11. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and with fIN = 10.1 MHz, fS = 80 MSPS Temperature with 2.0 V p-p Full Scale, fS = 80 MSPS 120 0 100 –20 80 –40 SFDR (dBFS) 60 –60 SFDR (dBc) SFDR (dBc) IMD3 (dBc) SNR (dBFS) SNR (dBc) SFDR (dBFS) –80 40 IMD3 (dBFS) –100 20 –120 0 –90 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 12. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A ) Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN IN with f = 180 MHz, f = 80 MSPS with f = 29.9 MHz, f = 32.9 MHz, f = 80 MSPS IN S IN1 IN2 S 0 100 95 –20 90 –40 SNR @ –40°C 85 SFDR @ –40°C SNR @ +25°C –60 SFDR (dBc) SFDR @ +25°C IMD3 (dBc) 80 SNR @ +85°C SFDR (dBFS) SFDR @ +85°C –80 IMD3 (dBFS) 75 –100 70 65 –120 0 50 100 150 200 250 –90 –78 –66 –54 –42 –30 –18 –6 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 13. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f ) and Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) IN Temperature with 1.75 V p-p Full Scale, f = 80 MSPS with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 80 MSPS S Rev. B | Page 11 of 36 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBc/dBFS) SNR/SFDR (dBc/dBFS) –100 –100 –95 –95 –90 –90 –85 –85 –80 –80 –75 –75 –70 –70 –65 –65 –60 –60 –55 –55 –50 –50 –45 –45 –40 –40 –35 –35 –30 –30 –25 –25 –20 –20 –15 –15 –10 –10 –5 –5 0 0 09210-013 09210-012 09210-011 SNR/SFDR (dBFS/dBc) SFDR/IMD3 (dBc/dBFS) SFDR/IMD3 (dBc/dBFS) 09210-016 09210-015 09210-014 AD9641 Data Sheet 0 14,000 80MSPS 29.9MHz @ –7dBFS –20 12,000 32.9MHz @ –7dBFS SFDR = 94.4dBc (101.4dBFS) –40 10,000 –60 8000 –80 6000 4000 –100 2000 –120 –140 0 0 10203040 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 FREQUENCY (MHz) OUTPUT CODE Figure 17. AD9641-80 Two-Tone FFT with fIN1 = 29.9 MHz and fIN2 = 32.9 MHz Figure 20. AD9641-80 Grounded Input Histogram 1.0 0 80MSPS 0.8 169.1MHz @ –7dBFS –20 172.1MHz @ –7dBFS 0.6 SFDR = 91.9dBc (98.9dBFS) –40 0.4 0.2 –60 0 –80 –0.2 –0.4 –100 –0.6 –120 –0.8 –140 –1.0 0 10203040 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz) OUTPUT CODE Figure 18. AD9641-80 Two-Tone FFT with f = 169.1 MHz and Figure 21. AD9641-80 INL with f = 30.3 MHz IN1 IN f = 172.1 MHz IN2 0.50 100 SFDR 95 0.25 90 85 0 80 –0.25 75 SNR 70 –0.50 45 50 55 60 65 70 75 80 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 OUTPUT CODE SAMPLE RATE (MSPS) Figure 19. AD9641-80 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 22. AD9641-80 DNL with fIN = 30.3 MHz with fIN = 70.1 MHz Rev. B | Page 12 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBFS/dBc) 09210-019 09210-018 09210-017 NUMBER OF HITS DNL ERROR (LSB) INL ERROR (LSB) 09210-021 09210-022 09210-020 Data Sheet AD9641 0 0 155MSPS 155MSPS 10.1MHz @ –1dBFS 140.1MHz @ –1dBFS –20 –20 SNR = 71.0dB (72.0dBFS) SNR = 70.7dB (71.7dBFS) SFDR = 95dBc SFDR = 93dBc –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. AD9641-155 Single-Tone FFT with fIN = 10.1 MHz Figure 26. AD9641-155 Single-Tone FFT with fIN = 140.1 MHz 0 0 155MSPS 155MSPS 30.1MHz @ –1dBFS 180.1MHz @ –1dBFS –20 –20 SNR = 70.9dB (71.9dBFS) SNR = 70.3dB (71.3dBFS) SFDR = 95dBc SFDR = 92dBc –40 –40 –60 –60 THIRD HARMONIC THIRD HARMONIC SECOND HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD9641-155 Single-Tone FFT with f = 30.1 MHz Figure 27. AD9641-155 Single-Tone FFT with f = 180.1 MHz IN IN 0 0 155MSPS 155MSPS 70.1MHz @ –1dBFS 220.1MHz @ –1dBFS –20 –20 SNR = 70.7dB (71.7dBFS) SNR = 70.2dB (71.2dBFS) SFDR = 93dBc SFDR = 89dBc –40 –40 THIRD HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC –80 –80 SECOND HARMONIC –100 –100 –120 –120 –140 –140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. AD9641-155 Single-Tone FFT with fIN = 70.1 MHz Figure 28. AD9641-155 Single-Tone FFT with fIN = 220.1 MHz Rev. B | Page 13 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09210-124 09210-123 09210-122 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09210-127 09210-126 09210-125 AD9641 Data Sheet 120 100 SFDR (dBFS) 95 100 90 80 SNR (dBFS) SNR @ –40°C SFDR @ –40°C 85 SNR @ +25°C 60 SFDR @ +25°C SFDR (dBc) SNR @ +85°C 80 SFDR @ +85°C 40 75 SNR (dBc) 20 70 0 65 0 50 100 150 200 250 300 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 29. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (A ) Figure 32. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f ) and IN IN with f = 10.1 MHz, f = 155 MSPS Temperature with 2.0 V p-p Full Scale, f = 155 MSPS IN S S 120 0 SFDR (dBFS) 100 –20 80 –40 SNR (dBFS) SFDR (dBc) 60 –60 SFDR (dBc) IMD3 (dBc) 40 –80 SNR (dBc) 20 –100 SFDR (dBFS) IMD3 (dBFS) 0 –120 –90 –78 –66 –54 –42 –30 –18 –6 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 33. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 30. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) IN with f = 29.9 MHz, f = 32.9 MHz, f = 155 MSPS with fIN = 180 MHz, fS = 155 MSPS IN1 IN2 S 0 100 95 –20 90 –40 SNR @ –40°C SFDR (dBc) SFDR @ –40°C 85 SNR @ +25°C –60 SFDR @ +25°C SNR @ +85°C 80 IMD3 (dBc) SFDR @ +85°C –80 75 SFDR (dBFS) –100 70 IMD3 (dBFS) 65 –120 0 50 100 150 200 250 300 –90 –78 –66 –54 –42 –30 –18 –6 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 31. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Figure 34. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Temperature with 1.75 V p-p Full Scale, fS = 155 MSPS with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 155 MSPS Rev. B | Page 14 of 36 SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09210-129 09210-128 09210-130 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS AND dBc) 09210-132 09210-131 09210-133 Data Sheet AD9641 0 6000 155MSPS 29.9MHz @ –7dBFS –20 32.9MHz @ –7dBFS 5000 SFDR = 88.7dBc (95.7dBFS) –40 4000 –60 3000 –80 2000 –100 1000 –120 –140 0 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 FREQUENCY (MHz) OUTPUT CODE Figure 35. AD9641-155 Two-Tone FFT with f = 29.9 MHz and f = 32.9 MHz IN1 IN2 Figure 38. AD9641-155 Grounded Input Histogram 0 1.0 155MSPS 169.1MHz @ –7dBFS 0.8 –20 172.1MHz @ –7dBFS SFDR = 89.8dBc (96.8dBFS) 0.6 –40 0.4 0.2 –60 0 –80 –0.2 –100 –0.4 –0.6 –120 –0.8 –140 –1.0 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 FREQUENCY (MHz) OUTPUT CODE Figure 36. AD9641-155 Two-Tone FFT with fIN1 = 169.1 MHz and Figure 39. AD9641-155 INL with fIN = 30.3 MHz fIN2 = 172.1 MHz 105 0.50 SFDR 100 0.25 95 90 0 85 80 –0.25 75 SNR 70 –0.50 50 65 80 95 110 125 140 155 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 SAMPLE RATE (MSPS) OUTPUT CODE Figure 37. AD9641-155 Single-Tone SNR/SFDR vs. Sample Rate (f ) S Figure 40. AD9641-155 DNL with fIN = 30.3 MHz with f = 70.1 MHz IN Rev. B | Page 15 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBFS AND dBc) 09210-136 09210-134 09210-135 DNL ERROR (LSB) INL ERROR (LSB) NUMBER OF HITS 09210-137 09210-139 09210-138 AD9641 Data Sheet EQUIVALENT CIRCUITS AVDD 350Ω SCLK VIN OR 30kΩ PDWN Figure 41. Equivalent Analog Input Circuit Figure 45. Equivalent SCLK or PDWN Input Circuit AVDD AVDD AVDD AVDD 30kΩ 0.9V 350Ω CSB 15kΩ 15kΩ CLK+ CLK– Figure 42. Equivalent Clock Input Circuit Figure 46. Equivalent CSB Input Circuit DRVDD AVDD AVDD 4mA R 4mA TERM DOUT+ V DOUT– DSYNC± CM 0.9V OR SYNC 16kΩ 4mA 4mA 0.9V Figure 43. Digital CML Output Figure 47. Equivalent SYNC and DSYNC Input Circuit DRVDD 350Ω SDIO 30kΩ Figure 44. Equivalent SDIO Circuit Rev. B | Page 16 of 36 09210-023 09210-026 09210-025 09210-024 09210-028 09210-027 09210-029 Data Sheet AD9641 THEORY OF OPERATION In intermediate frequency (IF) undersampling applications, any The AD9641 can sample any fS/2 frequency segment from dc to shunt capacitors should be reduced because the input sample 250 MHz, using appropriate low-pass or band-pass filtering at capacitor is unbuffered. In combination with the driving source the ADC inputs with little loss in ADC performance. impedance, the shunt capacitors limit the input bandwidth. Synchronization capability is provided to allow synchronized Refer to the AN-742 Application Note, Frequency Domain timing between multiple devices. Response of Switched-Capacitor ADCs; the AN-827 Application Programming and control of the AD9641 are accomplished Note, A Resonant Approach to Interfacing Amplifiers to Switched- using a 3-wire, SPI-compatible serial interface. Capacitor ADCs; and the Analog Dialogue article, “Transformer- Coupled Front-End for Wideband A/D Converters,” for more ADC ARCHITECTURE information on this subject (refer to www.analog.com). The AD9641 architecture consists of a front-end sample-and- BIAS hold circuit, followed by a pipelined, switched-capacitor ADC. S S The quantized outputs from each stage are combined into a final C C S FB 14-bit result in the digital correction logic. The pipelined architec- VIN+ ture permits the first stage to operate on a new input sample C C PAR1 PAR2 and the remaining stages to operate on the preceding samples. H S S Sampling occurs on the rising edge of the clock. C Each stage of the pipeline, excluding the last, consists of a low S VIN– resolution, flash ADC connected to a switched-capacitor digital- C C C FB PAR1 PAR2 S to-analog converter (DAC) and an interstage residue amplifier S BIAS (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage Figure 48. Switched-Capacitor Input in the pipeline. One bit of redundancy is used in each stage to For best dynamic performance, the source impedances driving facilitate digital correction of flash errors. The last stage consists VIN+ and VIN− should be matched, and the inputs should be of a flash ADC. differentially balanced. The input stage contains a differential sampling circuit that can Input Common Mode be ac- or dc-coupled in differential or single-ended modes. The The analog inputs of the AD9641 are not internally dc biased. output staging block aligns the data, corrects errors, and passes the In ac-coupled applications, the user must provide this bias data to the output buffers. The output buffers are powered from externally. Setting the device so that VCM = 0.5 × AVDD (or a separate supply, allowing digital output noise to be separated 0.9 V) is recommended for optimum performance. An on-board, from the analog core. During power-down, the output buffers go common-mode voltage reference is included in the design and into a high impedance state. is available from the VCM pin. Using the VCM output to set the ANALOG INPUT CONSIDERATIONS input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input The analog input to the AD9641 is a differential switched- is set by the VCM pin voltage (typically, 0.5 × AVDD). The VCM capacitor circuit that has been designed for optimum performance pin must be decoupled to ground by a 0.1 μF capacitor. This while processing a differential input signal. decoupling capacitor should be placed close to the pin to minimize The clock signal switches the input alternatively between sample the series resistance and inductance between the part and this mode and hold mode (see Figure 48). When the input is switched capacitor. into sample mode, the signal source must be capable of charging Differential Input Configurations the sample capacitors and settling within 1/2 of a clock cycle. Optimum performance is achieved while driving the AD9641 in a A small resistor in series with each input can help reduce the differential input configuration. For baseband applications, the peak transient current required from the output stage of the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide driving source. A shunt capacitor can be placed across the excellent performance and a flexible interface to the ADC. inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. Rev. B | Page 17 of 36 09210-030 AD9641 Data Sheet The signal characteristics must be considered when selecting The output common-mode voltage of the ADA4938-2 is easily a transformer. Most RF transformers saturate at frequencies set with the VCM pin of the AD9641 (see Figure 49), and the below a few megahertz (MHz). Excessive signal power can also driver can be configured in a Sallen-Key filter topology to provide cause core saturation, which leads to distortion. band limiting of the input signal. 15pF At input frequencies in the second Nyquist zone and above, the 200Ω noise performance of most amplifiers is not adequate to achieve 33Ω 15Ω the true SNR performance of the AD9641. For applications where 90Ω VIN– AVDD 76.8Ω VIN 5pF SNR is a key parameter, differential double balun coupling is the ADC ADA4938-2 recommended input configuration (see Figure 51). In this configu- 0.1µF 33Ω 15Ω VCM ration, the input is ac-coupled, and the common-mode voltage VIN+ 120Ω 15pF (VCM) is provided to each input through a 33 Ω resistor. These 200Ω resistors compensate for losses in the input baluns to provide Figure 49. Differential Input Configuration Using the ADA4938-2 a 50 Ω impedance to the driver. For baseband applications in which SNR is a key parameter, In the double balun and transformer configurations, the value differential transformer coupling is the recommended input of the input capacitors and resistors is dependent on the input configuration. An example is shown in Figure 50. To bias the frequency and source impedance. Based on these parameters, analog input, the voltage of VCM can be connected to the the value of the input resistors and capacitors may need to be center tap of the secondary winding of the transformer. adjusted, or some components may need to be removed. Table 9 displays recommended values to set the RC network for different C2 R3 input frequency ranges. However, these values are dependent on R2 VIN+ the input signal and bandwidth and should be used only as R1 a starting guide. 2V p-p 49.9Ω C1 ADC R2 An alternative to using a transformer-coupled input at frequencies R1 VCM VIN– in the second Nyquist zone is to use the AD8376 variable gain 0.1µF R3 amplifier. An example drive circuit including a band-pass filter C2 is shown in Figure 52. See the AD8376 data sheet for more information. Figure 50. Differential Transformer-Coupled Configuration C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– R3 C2 Figure 51. Differential Double Balun Input Configuration Table 9. Example RC Network Frequency Range (MHz) R1 Series (Ω Each) C1 Differential (pF) R2 Series (Ω Each) C2 Shunt (pF Each) R3 Shunt (Ω Each) 0 to 100 33 8.2 0 8.2 49.9 100 to 250 15 3.9 0 Open Open 1000pF 180nH 220nH 1µH 165Ω VPOS 15pF AD8376 5.1pF 3.9pF 301Ω VCM 165Ω 1nF 1µH 1nF 68nH AD9641 180nH 220nH 1000pF NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 52. Differential Input Configuration Using the AD8376 Rev. B | Page 18 of 36 09210-032 09210-031 09210-034 09210-033 Data Sheet AD9641 The RF balun configuration is recommended for clock frequencies VOLTAGE REFERENCE between 125 MHz and 640 MHz, and the RF transformer is A stable and accurate voltage reference is built into the AD9641. recommended for clock frequencies from 40 MHz to 200 MHz. The input full-scale range can be adjusted through the SPI port by The back-to-back Schottky diodes across the transformer/balun adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be secondary limit clock excursions into the AD9641 to approxi- used to change the full-scale value between 1.383 V p-p and mately 0.8 V p-p differential. 2.087 V p-p in 0.022 V steps, as shown in Table 17. This limit helps prevent the large voltage swings of the clock CLOCK INPUT CONSIDERATIONS from feeding through to other portions of the AD9641 while For optimum performance, the AD9641 sample clock inputs, preserving the fast rise and fall times of the signal that are CLK+ and CLK−, should be clocked with a differential signal. critical to a low jitter performance. The signal is typically ac-coupled into the CLK+ and CLK− pins If a low jitter clock source is not available, another option is to by means of a transformer or a passive component configuration. ac couple a differential PECL signal to the sample clock input These pins are biased internally (see Figure 53) and require no pins, as shown in Figure 56. The AD9510/AD9511/AD9512/ external bias. If the inputs are floated, the CLK− pin is pulled low AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/ to prevent spurious clocking. AD9520/AD9522 clock drivers offer excellent jitter performance. AVDD 0.1µF 0.1µF 0.9V CLOCK CLK+ INPUT CLK+ CLK– ADC AD95xx 100Ω PECL DRIVER 0.1µF 0.1µF CLOCK 4pF 4pF CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 56. Differential PECL Sample Clock (Up to 640 MHz) Figure 53. Equivalent Clock Input Circuit A third option is to ac-couple a differential LVDS signal to the Clock Input Options sample clock input pins, as shown in Figure 57. The AD9510/ The AD9641 has a very flexible clock input structure. Clock input AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of AD9518/AD9520/AD9522 clock drivers offer excellent jitter the type of signal being used, clock source jitter is of the most performance. concern, as described in the Jitter Considerations section. The minimum conversion rate of the AD9641 is 40 MSPS. At clock 0.1µF 0.1µF rates below 40 MSPS, dynamic performance of the AD9641 can CLOCK CLK+ INPUT degrade. ADC AD95xx 100Ω LVDS DRIVER Figure 54 and Figure 55 show two preferred methods for clocking 0.1µF 0.1µF CLOCK CLK– the AD9641 (at clock rates up to 640 MHz). A low jitter clock INPUT 50kΩ 50kΩ source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. Figure 57. Differential LVDS Sample Clock (Up to 640 MHz) ® In some applications, it may be acceptable to drive the sample Mini-Circuits ADC ADT1-1WT, 1:1Z clock inputs with a single-ended CMOS signal. In such applica- 0.1µF 0.1µF XFMR CLOCK CLK+ tions, the CLK+ pin should be driven directly from a CMOS gate, INPUT 100Ω 50Ω and the CLK− pin should be bypassed to ground with a 0.1 μF 0.1µF CLK– capacitor (see Figure 58). SCHOTTKY 0.1µF DIODES: HSMS2822 V CC OPTIONAL Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz) 0.1µF 0.1µF 1kΩ 100Ω AD95xx CLOCK CLK+ CMOS DRIVER INPUT 1kΩ ADC 50Ω* ADC 1nF 0.1µF CLK– CLOCK CLK+ 0.1µF INPUT 50Ω 0.1µF *50Ω RESISTOR IS OPTIONAL. 1nF CLK– Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) SCHOTTKY DIODES: HSMS2822 Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz) Rev. B | Page 19 of 36 09210-035 09210-037 09210-036 09210-040 09210-039 09210-038 AD9641 Data Sheet Input Clock Divider In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly The AD9641 contains an input clock divider with the ability sensitive to jitter, as illustrated in Figure 59. The measured curve to divide the input clock by integer values between 1 and 8. in Figure 59 was taken using an ADC clock source with approxi- For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) mately 65 fS of jitter, which combines with the 125 fS of jitter is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the inherent in the AD9641 to produce the result shown. DCS must be enabled for proper part operation. 75 The AD9641 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock 70 divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchro- 0.05ps 65 0.2ps nization feature allows multiple parts to have their clock dividers 0.5ps 1ps aligned to guarantee simultaneous input sampling. 1.5ps 60 MEASURED Clock Duty Cycle Typical high speed ADCs use both clock edges to generate 55 a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. The AD9641 requires a tight 50 tolerance on the clock duty cycle to maintain dynamic 1 10 100 1000 performance characteristics. INPUT FREQUENCY (MHz) Figure 59. SNR vs. Input Frequency and Jitter The AD9641 contains a DCS that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal The clock input should be treated as an analog signal in cases in 50% duty cycle. This allows the user to provide a wide range of which aperture jitter may affect the dynamic range of the AD9641. clock input duty cycles without affecting the performance of the Power supplies for clock drivers should be separated from the AD9641. Noise and distortion performance are nearly flat for a ADC output driver supplies to avoid modulating the clock signal wide range of duty cycles with the DCS enabled. with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type Jitter in the rising edge of the input is still of paramount concern of source (by gating, dividing, or another method), it should be and is not easily reduced by the internal stabilization circuit. retimed by the original clock at the last step. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant Refer to the AN-501 Application Note and the AN-756 Application associated with it that must be considered in applications in Note for more information about jitter performance as it relates which the clock rate can change dynamically. A wait time of to ADCs. 1.5 μs to 5 μs is required after a dynamic clock frequency CHIP SYNCHRONIZATION increase or decrease before the DCS loop is relocked to the The AD9641 has a SYNC input that offers the user flexible input signal. During the time when the loop is not locked, the synchronization options for synchronizing the clock divider. DCS loop is bypassed, and internal device timing is dependent The clock divider sync feature is useful for guaranteeing synchro- on the duty cycle of the input clock signal. In such applications, nized sample clocks across multiple ADCs. The input clock it may be appropriate to disable the DCS. In all other applications, divider can be enabled to synchronize on a single occurrence of enabling the DCS circuit is recommended to maximize ac the SYNC signal or on every occurrence. performance. The SYNC input is internally synchronized to the sample clock; Jitter Considerations however, to ensure that there is no timing uncertainty between High speed, high resolution ADCs are sensitive to the quality multiple parts, the SYNC input signal should be externally syn- of the clock input. For inputs near full scale, the degradation in chronized to the input clock signal, meeting the setup and hold SNR from the low frequency SNR (SNR ) at a given input LF times shown in Table 5. The SYNC input should be driven using frequency (f ) due to jitter (t ) can be calculated by INPUT JRMS a single-ended CMOS-type signal. (SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS Rev. B | Page 20 of 36 SNR (dBFS) 09210-041 Data Sheet AD9641 POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204A Transmit Top Level Description As shown in Figure 60, the power dissipated by the AD9641 varies with its sample rate. The data in Figure 60 was taken The AD9641 digital output complies with the JEDEC Standard in JESD204A serial output mode, using the same operating No. 204A (JESD204A), which describes a serial interface for conditions as those used for the Typical Performance data converters. JESD204A uses 8b/10b encoding, as well as Characteristics. optional scrambling. K28.5 and K28.7 comma symbols are used 0.30 0.15 for frame synchronization, and the K28.3 control symbol is used for lane synchronization. The receiver is required to lock onto TOTAL POWER the serial data stream and recover the clock with the use of a PLL. For details on the output interface, users are encouraged to refer 0.20 0.10 to the JESD204A standard. The JESD204A link is described according to the following I AVDD nomenclature:  S = samples transmitted per single converter per 0.10 0.05 frame cycle  M = number of converters per converter device (link) I DRVDD  L = number of lanes per converter device (link) 0 0  N = converter resolution 40 50 60 70 80  N’ = total number of bits per sample ENCODE FREQUENCY (MSPS)  CF = number of control words per frame clock cycle per Figure 60. Power and Current vs. Encode Frequency converter device (link) The AD9641 is placed in power-down mode using Register 0x08,  CS = number of control bits per conversion sample Bits[1:0] or by asserting the PDWN pin high. In this state, the  K = number of frames per multiframe ADC typically dissipates 7 mW. During power-down, the output  HD = high density mode drivers are placed in a high impedance state. Pulling the PDWN  F = number of octets per frame pin low returns the AD9641 to its normal operating mode. Low  C = control bit (overrange, overflow, underflow) power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock.  T = tail bit Internal capacitors are discharged when entering power-down  SCR = scrambling enabled mode and then must be recharged when returning to normal  FCHK = checksum operation. The JESD204A block for the AD9641 is designed to support the When using the SPI port interface, the user can place the ADC configurations described in Table 10. in power-down mode or standby mode (Register 0x08, Bits[1:0]). Standby mode allows the user to keep the internal reference circuitry powered and the JESD204A outputs running when faster wake-up times are required. Table 10. AD9641 JESD204A Typical Configuration Configuration JESD204A Link Settings Comments M = 1; L = 1; S = 1; F = 2 Maximum sample rate = 80 or 155 MSPS One Converter N’ = 16; CF = 0 One JESD204A Link CS = 0, 1, 2; K = N/A One Lane Per Link SCR = 0, 1; HD = 0 Rev. B | Page 21 of 36 TOTAL POWER (W) SUPPLY CURRENT (A) 09210-042 AD9641 Data Sheet Figure 61 shows a simplified block diagram of the JESD204A link The two resulting octets are optionally scrambled and encoded for the AD9641. The 8b/10b encoding works by taking eight bits of into their corresponding 10-bit code. The scrambler function is data (an octet) and encoding them into a 10-bit symbol. By default controlled by the JESD204A scrambling and lane configuration in the AD9641, the 14-bit converter word is broken into two octets. register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit Bit 13 through Bit 6 are in the first octet. The second octet contains data is taken from the ADC, the tail bits are added, the two octets Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can are scrambled, and the octets are encoded into two 10-bit symbols. also be used to indicate an out-of-range condition. The tail bits Figure 63 illustrates the default data format. are configured using the JESD204A link control in JESD204A The scrambler uses a self-synchronizing, polynomial-based Link Control Register 1, Address 0x60, Bit 6. 14 15 algorithm defined by the following equation: 1 + x + x . The LINK descrambler in the receiver should be a self-synchronizing DSYNC AD9641 ADC version of the scrambler polynomial. Figure 64 shows the CONVERTER CONVERTER OUTPUT LANE corresponding receiver data path. INPUT SAMPLE JESD204 A LINK CONVERTER (M = 0, 1; L = 0, 1) Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for complete transport layer and data format details. See Section 5.2 Figure 61. AD9641 Transmit Link Simplified Block Diagram for a complete explanation of scrambling and descrambling. DATA FRAME OPTIONAL 8B/10B TO FROM ASSEMBLER SCRAMBLER ENCODER RECEIVER 14 15 ADC (ADD TAIL BITS) 1 + x + x Figure 62. ADC Output Data Path WORD 0[13:6] SYMBOL 0[9:0] FRAME 0 WORD 0[5:0], TAIL BITS[1:0] SYMBOL 1[9:0] TIME WORD 1[13:6] SYMBOL 2[9:0] FRAME 1 WORD 1[5:0], TAIL BITS[1:0] SYMBOL 3[9:0] Figure 63. 14-Bit Data Transmission with Tail Bits OPTIONAL FROM 8B/10B FRAME DATA DESCRAMBLER TRANSMITTER DECODER ALIGNMENT OUT 14 15 1 + x + x Figure 64. Required Receiver Data Path Rev. B | Page 22 of 36 09210-043 09210-044 09210-046 09210-045 Data Sheet AD9641 Initial Frame Synchronization A 100 Ω differential termination resistor should be placed at each receiver input to result in a nominal 400 mV peak-to-peak swing at The serial interface must synchronize to the frame boundaries the receiver (see Figure 65). Alternatively, single-ended 50 Ω before data can be properly decoded. The JESD204A standard termination can be used. When single-ended termination is has a synchronization routine to identify the frame boundary. used, the termination voltage should be DRVDD/2; otherwise, When the DSYNC pin is taken low for at least two clock cycles, ac coupling capacitors can be used to terminate to any single- the AD9641 enters the code group synchronization mode. The ended voltage. AD9641 transmits the K28.5 comma symbol until the receiver achieves synchronization. The receiver should then deassert the The AD9641 digital outputs can interface with custom ASICs and sync signal (take DSYNC high), and the AD9641 begins the initial FPGA receivers, providing superior switching performance in lane alignment sequence (when enabled through Address 0x60, noisy environments. Single point-to-point network topologies are Bits[3:2]) and, subsequently, begins transmitting sample data. The recommended with a single differential 100 Ω termination resistor first non-K28.5 symbol corresponds to the first octet in a frame. placed as close as possible to the receiver logic. The common mode of the digital output automatically biases itself to half the The DSYNC input can be driven either from a differential LVDS supply of the receiver (that is, the common-mode voltage is 0.9 V source or by using a single-ended CMOS driver circuit. The for a receiver supply of 1.8 V) if dc-coupled connecting is used DSYNC input default to LVDS mode but can be set to CMOS (see Figure 66). mode by setting Bit 4 in Address 0x61. If it is driven differen- 100Ω DRVDD tially from an LVDS source, an external 100 Ω termination DIFFERENTIAL TRACE PAIR resistor should be provided. If the DSYNC input is driven single DOUT + x endedly, the CMOS signal should be connected to the DSYNC+ 100Ω RECEIVER signal, and the DSYNC− signal should be left disconnected. DOUT – x Frame and Lane Alignment Monitoring and Correction Frame alignment monitoring and correction is part of the V = DRVDD/2 OUTPUT SWING = 400mV p-p CM JESD204A specification. The 14-bit word requires two octets to Figure 65. AC-Coupled Digital Output Termination Example transmit all the data. The two octets (MSB and LSB), where V RXCM F = 2, make up a frame. During normal operating conditions, frame alignment is monitored via alignment characters, which 100Ω DRVDD DIFFERENTIAL are inserted under certain conditions at the end of a frame. 0.1µF TRACE PAIR Table 11 summarizes the conditions for character insertion, DOUT+x along with the expected characters under the various operation 100Ω OR RECEIVER modes. If lane synchronization is enabled, the replacement DOUT–x 0.1µF character value depends on whether the octet is at the end of a frame or at the end of a multiframe. OUTPUT SWING = 400mV p-p V = Rx V CM CM Based on the operating mode, the receiver can ensure that it is Figure 66. DC-Coupled Digital Output Termination Example still synchronized to the frame boundary by correctly receiving For receiver logic that is not within the bounds of the DRVDD the replace characters. supply, an ac-coupled connection should be used. Place a 0.1 μF Digital Outputs and Timing capacitor on each output pin and derive a 100 Ω differential The AD9641 has differential digital outputs that power up termination close to the receiver side. by default. The driver current is derived on-chip and sets the If there is no far-end receiver termination or if there is poor output current at each output equal to a nominal 4 mA. Each differential trace routing, timing errors may result. To avoid output presents a 100 Ω dynamic internal termination to reduce such timing errors, it is recommended that the trace length be unwanted reflections. less than 8 inches and that the differential output traces be close together and at equal lengths. Table 11. AD9641 JESD204A Frame Alignment Monitoring and Correction Replacement Characters Lane Replacement Scrambling Synchronization Character to Be Replaced Last Octet in Multiframe Character Off On Last octet in frame repeated from previous frame No K28.7 (0xFC) Off On Last octet in frame repeated from previous frame Yes K28.3 (0x7C) Off Off Last octet in frame repeated from previous frame Not applicable K28.7 (0xFC) On On Last octet in frame equals D28.7 (0xFC) No K28.7 (0xFC) On On Last octet in frame equals D28.3 (0x7C) Yes K28.3 (0x7C) On Off Last octet in frame equals D28.7 (0x7C) Not applicable K28.7 (0xFC) Rev. B | Page 23 of 36 09210-047 09210-048 AD9641 Data Sheet Figure 67 shows an example of the digital output (default) data The lowest typical clock rate is 40 MSPS. For clock rates slower eye and a time interval error (TIE) jitter histogram. than 60 MSPS, Bit 3 should be set to 0 in the PLL control register (Address 0x21 in Table 17). This option sets the PLL loop band- Additional SPI options allow the user to further increase the output width to use clock rates between 40 MSPS and 60 MSPS. driver voltage swing of all four outputs to drive longer trace lengths (see Address 0x15 in Table 17). Even though this produces sharper Setting Bit 2 in the output mode register (Address 0x14) allows rise and fall times on the data edges and is less prone to bit errors, the user to invert the digital samples from their nominal state. the power dissipation of the DRVDD supply increases when this As shown in Figure 63, the MSB is transmitted first in the data option is used. See the Memory Map section for more details. output serial stream. The format of the output data is twos complement, by default. Table 12 provides an example of this output coding format. To change the output data format to offset binary or Gray code, see the Memory Map section (Address 0x14 in Table 17). HEIGHT1: EYE DIAGRAM PERIOD1: HISTOGRAM WIDTH@BER1: BATHTUB 0 10 1 4 3 25,000 – + + –2 10 400 20,000 –4 10 200 –6 10 15,000 0 –8 10 10,000 –200 –10 10 5000 0.781 –400 –12 10 EYE: TRANSITION BITS OFFSET: –0.004 UIS: 8000; 639999, TOTAL: 8000; 639999 –14 0 10 –600 –400 –200 0 200 400 600 610 615 620 625 630 635 –0.5 0 0.5 TIME (ps) TIME (ps) ULS Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations HEIGHT1: EYE DIAGRAM PERIOD1: HISTOGRAM WIDTH@BER1: BATHTUB 0 600 10 1 4 3 – 400k – – –2 10 400 350k –4 10 300k 200 –6 10 250k 0 200k –8 10 150k –200 –10 10 100k 0.75 –400 –12 10 EYE: TRANSITION BITS 50k OFFSET: –0.002 UIS: 8000; 1239996, TOTAL: 48000; 7439996 –14 10 –600 0 –300 –200 –100 100 200 300 305 310 315 320 325 330 335 –0.5 0 0.5 0 TIME (ps) TIME (ps) ULS Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations Table 12. Digital Output Coding Code (VIN+) − (VIN−), Input Span = 1.75 V p-p (V) Digital Output Twos Complement ([D13:D0]) 8191 +0.875 01 1111 1111 1111 0 0.00 00 0000 0000 0000 −1 −0.000107 11 1111 1111 1111 −8192 −0.875 10 0000 0000 0000 Rev. B | Page 24 of 36 VOLTAGE (mV) VOLTAGE (mV) HITS HITS BER BER 09210-068 09210-050 Data Sheet AD9641 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9641 includes built-in test features designed to enable OUTPUT TEST MODES verification of the integrity of the channel as well as facilitate Digital test patterns can be inserted at various points along the board level debugging. A BIST (built-in self-test) feature is included signal path within the AD9641 as shown in Figure 69. The ability that verifies the integrity of the digital datapath of the AD9641. to inject these signals at several locations facilitates debugging Various output test options are also provided to place predictable of the JESD204A serial communication link. values on the outputs of the AD9641. Register 0x0D allows test signals generated at the output of the BUILT-IN SELF-TEST (BIST) ADC core to be fed directly into the input of the serial link. The The BIST is a thorough test of the digital portion of the selected output test options available from Register 0x0D are shown in AD9641 signal path. When enabled, the test runs from an internal Table 14. When an output test mode is enabled, the analog pseudorandom noise (PN) source through the digital datapath section of the ADC is disconnected from the digital back end starting at the ADC block output. The BIST sequence runs blocks and the test pattern is run through the output formatting for 512 cycles and stops. The BIST signature value is placed in block. Some of the test patterns are subject to output formatting, Register 0x24 and Register 0x25. The outputs are not disconnected and some are not. The seed value for the PN sequence tests can be during this test; therefore, the PN sequence can be observed as forced if the PN reset bits are used to hold the generator in reset it runs. The PN sequence can be continued from its last value or mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can reset from the beginning, based on the value programmed in be performed with or without an analog signal (if present, the Register 0x0E, Bit 2. The BIST signature result varies based on analog signal is ignored), but they do require an encode clock. the channel configuration. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. JESD204A TEST PATTERNS 10-BIT ADC TEST PATTERNS JESD204A TEST PATTERNS SPI REGISTER 0x62 BITS [5:4] = 14-BIT 16-BIT 01 AND BITS [2:0] ≠ 000 SPI REGISTER 0x0D SPI REGISTER 0x62 BITS [5:4] = BITS [3:0] ≠ 0000 00 AND BITS [2:0] ≠ 000 SERIALIZER OUTPUT FRAME SCRAMBLER 8-BIT/10-BIT JESD204A CONSTRUCTION (OPTIONAL) ENCODER SAMPLE CONSTRUCTION ADC CORE FRAMER TAIL BITS Figure 69. Block Diagram Showing Digital Test Modes Rev. B | Page 25 of 36 09210-051 AD9641 Data Sheet There are nine digital output test pattern options available that A description of the PN sequence long and how it is generated can be initiated through the SPI (see Table 14 for the output bit can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. sequencing options). This feature is useful when validating The only differences are that the starting value must be a specific receiver capture and timing. Some test patterns have two serial value instead of all 1s (see Table 13 for the initial values) and sequential words and can be alternated in various ways, depending that the AD9641 inverts the bit stream with relation to the ITU-T on the test pattern selected. Note that some patterns do not standard. adhere to the data format select option. In addition, custom Table 13. PN Sequence user-defined test patterns can be assigned in the user pattern Initial First Three Output Samples registers (Address 0x19 and Address 0x20). Sequence Value (MSB First) The PN sequence short pattern produces a pseudorandom bit PN Sequence Short 0x0092 0x125B, 0x3C9A, 0x2660 9 sequence that repeats itself every 2 − 1 (511) bits. A description PN Sequence Long 0x3AFF 0x3FD7, 0x0002, 0x36E0 of the PN sequence short and how it is generated can be found Register 0x62 allows patterns that are similar to those described in Section 5.1 of the ITU-T O.150 (05/96) recommendation. in Table 14 to be input at different points along the datapath. The only difference is that the starting value must be a specific This allows the user to provide predictable output data on the value instead of all 1s (see Table 13 for the initial values). serial link without it having been manipulated by the internal The PN sequence long pattern produces a pseudorandom bit formatting logic. Refer to Table 17 for additional information 23 sequence that repeats itself every 2 − 1 (8,388,607) bits. on the test modes available in Register 0x62. Table 14. Flexible Output Test Modes from SPI Register 0x0D Output Test Mode Digital Output Word 1 (Default Digital Output Word 2 (Default Subject to Data Bit Sequence Pattern Name Twos Complement Format) Twos Complement Format) Format Select 0000 Off (default) Not applicable Not applicable Yes 0001 Midscale short 00 0000 0000 0000 Same Yes 0010 +Full-scale short 01 1111 1111 1111 Same Yes 0011 −Full-scale short 10 0000 0000 0000 Same Yes 0100 Checkerboard 10 1010 1010 1010 01 0101 0101 0101 No 0101 PN sequence long Not applicable Not applicable Yes 0110 PN sequence short Not applicable Not applicable Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User test mode User data from Register 0x19 to User data from Register 0x19 to Yes Register 0x20 Register 0x20 1001 to 1110 Not used Not applicable Not applicable 1111 Ramp output N N + 1 No Rev. B | Page 26 of 36 Data Sheet AD9641 SERIAL PORT INTERFACE (SPI) The AD9641 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 70 gives the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. High Speed ADCs via SPI. During an instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: the SCLK pin, the SDIO by the W0 and W1 bits. pin, and the CSB pin (see Table 15). The SCLK (a serial clock) is In addition to word length, the instruction phase determines used to synchronize the read and write data presented from and whether the serial frame is a read or write operation, allowing to the ADC. The SDIO (serial data input/output) is a dual-purpose the serial port to be used both to program the chip and to read pin that allows data to be sent to and read from the internal ADC the contents of the on-chip memory. The first bit of the first byte in memory map registers. The CSB (chip select bar) is an active- a multibyte serial data transfer frame indicates whether a read low control that enables or disables the read and write cycles. command or a write command is issued. If the instruction is Table 15. Serial Port Interface Pins a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input Pin Function to an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB- SDIO Serial data input/output. A dual-purpose pin that first mode or in LSB-first mode. MSB first is the default on typically serves as an input or an output, depending on power-up and can be changed via the SPI port configuration the instruction being sent and the relative position in the timing frame. register. For more information about this and other features, CSB Chip select bar. An active-low control that gates the read see the AN-877 Application Note, Interfacing to High Speed and write cycles. ADCs via SPI. t HIGH t t DS CLK t H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 Figure 70. Serial Port Interface Timing Diagram Rev. B | Page 27 of 36 09210-049 AD9641 Data Sheet HARDWARE INTERFACE SPI ACCESSIBLE FEATURES The pins described in Table 15 comprise the physical interface Table 16 provides a brief description of the general features that between the user programming device and the serial port of are accessible via the SPI. These features are described in detail the AD9641. The SCLK pin and the CSB pin function as inputs in the AN-877 Application Note, Interfacing to High Speed ADCs when using the SPI interface. The SDIO pin is bidirectional, via SPI. The AD9641 part-specific features are described in detail in functioning as an input during write phases and as an output the Reading the Memory Map Register Table section. during readback. Table 16. Features Accessible Using the SPI The SPI interface is flexible enough to be controlled by either Feature Name Description FPGAs or microcontrollers. One method for SPI configuration Mode Allows the user to set either power-down mode is described in detail in the AN-812 Application Note, Micro- or standby mode controller-Based Serial Port Interface (SPI) Boot Circuit. Clock Allows the user to access the DCS, set the clock divider, set the clock divider phase, and The SPI port should not be active during periods when the full enable the sync dynamic performance of the converter is required. Because the Offset Allows the user to digitally adjust the SCLK signal, the CSB signal, and the SDIO signal are typically converter offset asynchronous to the ADC clock, noise from these signals can Test I/O Allows the user to set test modes to have degrade converter performance. If the on-board SPI bus is used known data on output bits for other devices, it may be necessary to provide buffers between Full Scale Allows the user to set the input full-scale this bus and the AD9641 to prevent these signals from transi- voltage tioning at the converter inputs during critical sampling periods. JESD204A Allows user to configure the JESD204A output Rev. B | Page 28 of 36 Data Sheet AD9641 MEMORY MAP Default Values READING THE MEMORY MAP REGISTER TABLE After the AD9641 is reset, critical registers are loaded with Each row in the memory map register table has eight bit locations. default values. The default values for the registers are given in The memory map is roughly divided into four sections: the chip the memory map register table, Table 17. configuration registers (Address 0x00 to Address 0x02); the transfer Logic Levels register (Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x3A); and the An explanation of logic level terminology follows: JESD204A configuration registers (Address 0x60 to Address 0x78).  “Bit is set” is synonymous with “bit is set to Logic 1” or The memory map register table (see Table 17) lists the default “writing Logic 1 for the bit.” hexadecimal value for each hexadecimal address shown. The  “Clear a bit” is synonymous with “bit is set to Logic 0” or column with the heading Bit 7 (MSB) is the start of the default “writing Logic 0 for the bit.” hexadecimal value given. For example, Address 0x18, the input Transfer Register Map span select register, has a hexadecimal default value of 0x00. This means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s. Address 0x08 through Address 0x78 are shadowed. Writes to the This setting is the default reference selection setting. The default addresses do not affect part operation until a transfer command is value uses a 1.75 V p-p reference. For more information on this issued by writing 0x01 to Address 0xFF, setting the transfer bit. function and others, see the AN-877 Application Note, Interfacing This allows these registers to be updated internally and simulta- to High Speed ADCs via SPI. This application note details the neously when the transfer bit is set. The internal update takes functions controlled by Register 0x00 to Register 0xFF. place when the transfer bit is set, and the bit autoclears. Open Locations All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are configuration mirrored so LSB- or MSB- first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID[7:0] 0x80 Read only (AD9641 = 0x80) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade ID used to 00 = 80 MSPS differentiate 10 = 155 MSPS devices; read only Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronous transfer of data from the master shift register to the slave Rev. B | Page 29 of 36 AD9641 Data Sheet Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments ADC Functions 0x08 Power Open Open External Open Open Open Internal power-down mode 0x00 Determines modes power- various 00 = normal operation down pin generic 01 = full power-down function modes of 10 = standby chip 0 = PDWN 11 = reserved operation. 1 = STNDBY 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (default) 0x0A PLL status PLL locked Open Open Open Open Open Open Open 0x00 Read only. 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide values other 000 = no delay 000 = divide-by-1 than 000 001 = 1 input clock cycle 001 = divide-by-2 cause the 010 = 2 input clock cycles 010 = divide-by-3 duty cycle 011 = 3 input clock cycles 011 = divide-by-4 stabilizer to 100 = 4 input clock cycles 100 = divide-by-5 become 101 = 5 input clock cycles 101 = divide-by-6 active. 110 = 6 input clock cycles 110 = divide-by-7 111 = 7 input clock cycles 111 = divide-by-8 0x0D Test mode User test Open Reset PN Reset PN Output test mode 0x00 When this mode long gen short gen register is 0000 = off (default) control set, the 0001 = midscale short test data is 0 = 0010 = positive FS placed on continuous/ 0011 = negative FS the output repeat 0100 = alternating checkerboard pins in place pattern 0101 = PN long sequence of normal 1 = single 0110 = PN short sequence data. pattern 0111 = one-/zero- word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (twos complement format) 0x14 Output Open Open Open Output Open Output Output format 0x01 Configures mode disable invert the outputs 00 = offset binary and the 01 = twos complement format of (default) the data. 01 = Gray code 11 = offset binary 0x15 Output Open Open Open Open Open Open Output drive level adjust 0x00 adjust 11 = 320 mV 00 = 400 mV 10 = 440 mV 01 = 500 mV 0x18 Open Open Open Full scale input voltage selection 0x00 Input span Full-scale select input 01111 = 2.087 V p-p adjustment … in 0.022 V 00001 = 1.772 V p-p steps. 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1, Bits[7:0] 0x00 Pattern 1 LSB 0x1A User Test User Test Pattern 1, Bits[15:8] 0x00 Pattern 1 MSB 0x1B User Test User Test Pattern 2, Bits[7:0] 0x00 Pattern 2 LSB 0x1C User Test User Test Pattern 2, Bits[15:8] 0x00 Pattern 2 MSB 0x1D User Test User Test Pattern 3, Bits[7:0] 0x00 Pattern 3 LSB Rev. B | Page 30 of 36 Data Sheet AD9641 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x1E User Test User Test Pattern 3, Bits[15:8] 0x00 Pattern 3 MSB 0x1F User Test User Test Pattern 4, Bits[7:0] 0x00 Pattern 4 LSB 0x20 User Test User Test Pattern 4, Bits[15:8] 0x00 Pattern 4 MSB 0x21 PLL control Open Open Open Open PLL low Open Open Open 0x00 Bit 3 must encode be enabled rate enable if the ADC clock rate is <60 MHz. 0x24 BIST BIST signature, Bits[7:0] 0x00 Read only. signature LSB 0x25 BIST BIST signature, Bits[15:8] 0x00 Read only. signature MSB 0x3A Sync control Open Open Open Open Open Clock Clock Master sync 0x00 divider divider buffer next sync sync enable only enable JESD204A Configuration Registers 0x60 JESD204A Open Serial tail Serial test Serial lane Serial lane alignment Frame Serial 0x00 Link Control bit enable sample synchroni- sequence mode alignment transmit link Register 1 enable zation character power- down 00 = disabled enable insertion 01 = enabled disable 10 = reserved 11 = always on test mode 0x61 JESD204A Local DSYNC mode DSYNC CMOS Open Bypass Invert Mirror serial 0x00 Link Control pin input DSYNC 8b/10b transmit output bits 00 = individual mode Register 2 inverted input encoding bits 01 = global mode 0 = LVDS 10 = DSYNC active mode 1 = CMOS 11 = DSYNC pin disabled 0x62 JESD204A Disable Open Link test generation Open Link test generation mode 0x00 Link Control CHKSUM input selection 000 = normal operation Register 3 00 = 16-bit data injected 001 = alternating checkerboard at sample input to the 010 = 1/0 word toggle link 011 = PN sequence, long 01 = 10-bit data injected 100 = PN sequence, short at output of 8b/10b 101 = user test pattern data continuous encoder 110 = user test pattern data single 10 = reserved 111 = ramp output 11 = reserved 0x63 JESD204A Initial lane assignment sequence repeat count 0x00 Link Control Register 4 0x64 JESD204A JESD204A serial device identification (DID) number 0x00 device identification number (DID) 0x65 JESD204A Open Open Open Open JESD204A serial bank identification (BID) number 0x00 bank identification number (BID) 0x66 JESD204A Open Open Open JESD204A serial lane identification (LID) number 0x00 lane identification number (LID) 0x6E JESD204A Enable Open Open Open Open Open Open Serial lane 0x80 scrambler serial control (SCR) and scrambler 0 = one lane lane (L) mode (SCR) per link configuration (L = 1) 1 = reserved Rev. B | Page 31 of 36 AD9641 Data Sheet Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x6F JESD204A JESD204A number of octets per frame (F) 0x01 Read only. number of (bits are calculated based on the equation F = (M × 2)/L) octets per frame (F) 0x70 JESD204A Open Open Open JESD204A number of frames per multiframe (K) 0x0F number of frames per multiframe (K) 0x71 JESD204A Open Open Open Open Open Open Open Number of 0x00 Read only. number of converters converters per link per link per per device converter 0 = link device (link) connected to (M) one ADC (M = 1) 1 = reserved 0x72 JESD 204A Number of control bits per Open Converter resolution (N) (read only) 0x4D converter sample (CS) resolution (N) 00 = no control bits and control (CS = 0) bits per 01 = one control bit sample (CS) (CS = 1) 10 = two control bits (CS = 2) 11 = unused 0x73 JESD204A Open Open Open Total number of bits per sample (N’) (read only) 0x0F Read only. total bits per sample (N’) 0x74 JESD204A Open Open Open Samples per converter per frame cycle (S) (read only) 0x00 Read only. samples per (always 1 for the AD9641) converter (S) per frame cycle 0x75 JESD204A Enable HD Open Open Number of control words per frame clock cycle per link (CF) 0x00 HD and CF (high (always 0 for the AD9641 (read only)) configuration density) format 0x76 JESD204A Serial Reserved Field 1 (RES1) 0x00 Serial (these registers are available for customer use) Reserved Field 1 (RES1) 0x77 JESD204A Serial Reserved Field 2 (RES2) 0x00 Serial (these registers are available for customer use) Reserved Field 2 (RES2) 0x78 JESD204A Serial checksum value for lane (FCHK) 0x00 Read only checksum value for lane (FCHK) receives and to ignore the rest. The clock divider sync enable bit MEMORY MAP REGISTER DESCRIPTIONS (Address 0x3A, Bit 1) resets after it syncs. For additional information about functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application Note, Bit 1—Clock Divider Sync Enable Interfacing to High Speed ADCs via SPI. Bit 1 gates the sync pulse to the clock divider. The sync signal Sync Control (Address 0x3A) is enabled when Bit 1 and Bit 0 are high. This is in continuous sync mode. Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 0—Master Sync Buffer Enable Bit 0 must be high to enable any of the sync functions. If the If the master sync buffer enable bit (Address 0x3A, Bit 0) and sync capability is not used, this bit should remain low to the clock divider sync enable bit (Address 0x3A, Bit 1) are high, conserve power. Bit 2 allows the clock divider to sync to the first sync pulse it Rev. B | Page 32 of 36 Data Sheet AD9641 JESD204A Link Control Register 1 (Address 0x60) Bit 2—Bypass 8b/10b Encoding Bit 7—Open If this bit is set, the 8b/10b encoding is bypassed and the most significant bits are set to 0. Bit 6—Serial Tail Bit Enable Bit 1—Invert Transmit Bits If this bit is set, unused tail bits are padded with a pseudo random number sequence from a 31-bit LFSR (see JESD204A 5.1.4). Setting this bit inverts the 10 serial output bits. This effectively inverts the output signals. Bit 5—Serial Test Sample Enable Bit 0—Mirror Serial Output Bits If set, JESD204A test samples are enabled, and the transport layer test sample sequence (as specified in JESD204A section Setting this bit reverses the order of the 10b outputs. 5.1.6.2) sent on all link lanes. JESD204A Link Control Register 3 (Address 0x62) Bit 4—Serial Lane Synchronization Enable Bit 7—Disable CHKSUM If this bit is set, lane synchronization is enabled. Both sides Setting this bit high disables the CHKSUM configuration perform lane sync; frame alignment character insertion uses parameter. (For testing purposes only.) either /K28.3/ or /K28.7/ control characters (see JESD204A Bit 6—Open 5.3.3.4). Bits[5:4]—Link Test Generation Input Selection Bits[3:2]—Serial Lane Alignment Sequence Mode 00: 16-bit test generation data injected at sample input to the link. 00: initial lane alignment sequence disabled. 01: 10-bit test generation data injected at output of 8b/10b 01: initial lane alignment sequence enabled. encoder (at input to PHY). 10: reserved. 10: reserved. 11: initial lane alignment sequence always on test mode; JESD204A 11: reserved. data link layer test mode where repeated lane alignment sequence is sent on all lanes. Bit 3—Open Bit 1—Frame Alignment Character Insertion Disable Bits[2:0]—Link Test Generation Mode If Bit 1 is set, the frame alignment character insertion is 000: normal operation (test mode disabled). disabled per JESD204A section 5.3.3.4. 001: alternating checkerboard. 010: 1/0 word toggle. Bit 0—Serial Transmit Link Power-Down 011: PN sequence, long. If Bit 0 is set high, the serial transmit link is held in reset with its 100: PN sequence, short. clock gated off. The JESD204A transmitter should be powered 101: continuous/repeat user test mode. The most significant bits down when changing any of the link configuration bits. from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeated. (Output User Pattern 1, 2, 3, 4, JESD204A Link Control Register 2 (Address 0x61) 1, 2, 3, 4, 1, 2, 3, 4….) Bits[7:6]—Local DSYNC Mode 110: single user test mode. The most significant bits from the user 00: individual/separate mode. Each link is controlled by a pattern (1, 2, 3, 4) are placed on the output for one clock cycle, separate DSYNC pin that independently controls code group and then all zeros are output. (Output User Pattern 1, 2, 3, 4; synchronization. then output all zeros.) 01: global mode. Any DSYNC signal causes the link to begin 111: ramp output. code group synchronization. JESD204A Link Control Register 4 (Address 0x63) 10: DSYNC active mode. The DSYNC signal is active; force Bits[7:0]—Initial Lane Alignment Sequence Repeat Count code group synchronization. Bits[7:0] specify the number of times the initial lane alignment 11: DSYNC pin disabled. sequence (ILAS) is repeated. If 0 is programmed, the ILAS does Bit 5—DSYNC Pin Input Inverted not repeat. If 1 is programmed, the ILAS repeats one time, and so on. See Register 0x60, Bits[3:2] to enable the ILAS and for If this bit is set, the DSYNC pin of the link is inverted (active a test mode to continuously enable the initial lane alignment high). sequence. Bit 4—CMOS DSYNC Input JESD204A Device Identification (DID) Number 0: LVDS differential pair DSYNC input (default). (Address 0x64) 1: CMOS single-ended DSYNC input. Bits[7:0]—Serial Device Identification (DID) Number Bit 3—Open Rev. B | Page 33 of 36 AD9641 Data Sheet Bit 5—Open JESD204A Bank Identification (BID) Number (Address 0x65) Bits [4:0]—Converter Resolution (N). Bits[7:4]—Open Read only bits showing the converter resolution (reads back 13 Bits[3:0]—Serial Bank Identification (BID) Number (0xD) for 14-bit resolution). JESD204A Lane Identification (LID) Number (Address 0x66) JESD204A Total Number of Bits per Sample (N’) Bits[7:5]—Open (Address 0x73) Bits[4:0]—Serial Lane Identification (LID) Number for Bits[7:5]—Reserved Lane Bits[4:0]—Total Number of Bits per Sample (N’) JESD204A Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) Read only bits showing the total number of bits per sample, minus 1 (reads back 15 (0xF) for 16 bits per sample). Bit 7—Enable Serial Scrambler Mode (SCR) JESD204A Samples per Converter per Frame Cycle (S) Setting this bit high enables the scrambler (SCR = 1). (Address 0x74) Bits[6:1]—Open. Bits[7:5]—Open Bit 0—Serial Lane Control. Bits[4:0]—Samples per Converter per Frame Cycle (S) 0: one lane per link (L = 1). Read only bits showing the number of samples per converter 1: 11111 = reserved. frame cycle, minus 1 (reads back 0 (0x0) for one sample per JESD204A Number of Octets per Frame (Address 0x6F, converter frame). Read Only) JESD204A HD and CF Configuration (Address 0x75) Bits[7:0]—Number of Octets per Frame (F) Bit 7—High Density Format Enabled (Read Only) The readback from this register is calculated from the following Read only bit. Always 0 in the AD9641. equation: F = (M × 2)/L. Bits[6:5]—Open Valid values for F for the AD9641 are Bits[4:0]—Number of Control Words per Frame Clock F = 2, with M = 1 and L = 1 Cycle per Converter Device (Link) (CF) JESD204A Number of Frames per Multiframe (K) Read only bits. Reads back 0x0 for the AD9641. (Address 0x70) JESD204A Serial Reserved Field 1 (Address 0x76) Bits[7:5]—Open Bits[7:0]—Serial Reserved Field 1 (RES1) Bits[4:0]—Number of Frames per Multiframe (K) This read/write register is available for customer use. JESD204A Number of Converters per Converter Device (Link) (M) (Address 0x71) JESD204A Serial Reserved Field 2 (Address 0x77) Bits[7:1]—Open Bits[7:0]—Serial Reserved Field 2 (RES2) Bit 0—Number of Converters per Converter Device (Link) This read/write register is available for customer use. (M) JESD204A Serial Checksum Value for Lane (Address 0x78) 0: link connected to one ADC. Only primary input used (M = 1). Bits[7:0]—Checksum Value for Lane 1: reserved. This read only register is automatically calculated for the lane. JESD204A Converter Resolution (N) and Control Bits per Sum (all link configuration parameters for the lane) MOD 256. Sample (CS) (Address 0x72) Bits[7:6]—Number of Control Bits per Sample (CS) 00: no control bits sent per sample (CS = 0). 01: one control bit sent per sample—overrange bit enabled (CS = 1). 10: two control bits sent per sample—overflow/underflow bits enabled (CS = 2). 11: unused. Rev. B | Page 34 of 36 Data Sheet AD9641 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting design and layout of the AD9641 as a system, the bottom of the PCB. These vias should be filled or plugged to it is recommended that the designer become familiar with these prevent solder wicking through the vias, which can compromise guidelines, which discuss the special circuit connections and the connection. layout requirements that are needed for certain pins. To maximize the coverage and adhesion between the ADC and Power and Ground Recommendations the PCB, a silkscreen should be overlaid to partition the continuous When connecting power to the AD9641, it is recommended plane on the PCB into several uniform sections. This provides that two separate 1.8 V supplies be used. Use one supply for several tie points between the ADC and the PCB during the reflow analog (AVDD), and use a separate supply for the digital outputs process. Using one continuous plane with no partitions guarantees (DRVDD). For both AVDD and DRVDD, several different only one tie point between the ADC and the PCB. For detailed decoupling capacitors should be used to cover both high and information about packaging and PCB layout of chip scale low frequencies. Place these capacitors close to the point of entry packages, see the AN-772 Application Note, A Design and at the PCB level and close to the pins of the part, with minimal Manufacturing Guide for the Lead Frame Chip Scale Package trace length. (LFCSP), at www.analog.com. A single PCB ground plane should be sufficient when using the VCM AD9641. With proper decoupling and smart partitioning of the The VCM pin should be decoupled to ground with a 0.1 μF PCB analog, digital, and clock sections, optimum performance capacitor, as shown in Figure 50. is easily achieved. SPI Port Exposed Paddle Thermal Heat Slug Recommendations The SPI port should not be active during periods when the full It is mandatory that the exposed paddle on the underside of the dynamic performance of the converter is required. Because the ADC be connected to analog ground (AGND) to achieve the SCLK, CSB, and SDIO signals are typically asynchronous to the best electrical and thermal performance. A continuous, exposed ADC clock, noise from these signals can degrade converter (no solder mask) copper plane on the PCB should mate to the performance. If the on-board SPI bus is used for other devices, AD9641 exposed paddle, Pin 0. it may be necessary to provide buffers between this bus and the AD9641 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. B | Page 35 of 36 AD9641 Data Sheet OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC * 3.75 EXPOSED PAD 3.60 SQ 3.55 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9641BCPZ-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZRL7-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZ-155 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZRL7-155 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641-80KITZ Evaluation Board Kit AD9641-155KITZ Evaluation Board Kit 1 Z = RoHS Compliant Part. ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09210-0-1/12(B) Rev. B | Page 36 of 36 PIN 1 INDICATOR 08-16-2010-B