ANALOG DEVICES AD9640

14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FEATURES FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS AVDD FD(0:3)A DCS DFS CSB DRVDD DVDD SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS FD BITS/THRESHOLD SPI DETECT SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS D13A SFDR = 84 dBc to 70 MHz @ 150 MSPS PROGRAMMING DATA D0A VIN+A Low power: 820 mW @ 150 MSPS SHA ADC 1.8 V analog supply operation VIN–A SIGNAL CLK+ 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS MONITOR VREF CLK– output supply SENSE DIVIDE DCOA Integer 1 to 8 input clock divider 1TO 8 DCO GENERATION CML REF IF sampling frequencies to 450 MHz DCOB SELECT DUTY CYCLE Internal ADC voltage reference RBIAS D13B STABILIZER Integrated ADC sample-and-hold inputs D0B VIN–B Flexible analog input range: 1 V p-p to 2 V p-p SHA ADC Differential analog inputs with 650 MHz bandwidth VIN+B SIGNAL MONITOR DATA ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR Serial port control SYNC DETECT INTERFACE User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes AGND SYNC FD(0:3)B SMI SMI SMI DRGND SDFS SCLK/ SDO/ Integrated receive features PDWN OEB Fast detect/threshold bits Figure 1. Composite signal monitor PRODUCT HIGHLIGHTS APPLICATIONS 1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC. Communications 2. Fast overrange detect and signal monitor with serial output. Diversity radio systems 3. Signal monitor block with dedicated serial output mode. Multimode digital receivers 4. Proprietary differential input that maintains excellent SNR GSM, EDGE, WCDMA, LTE, performance for input frequencies up to 450 MHz. CDMA2000, WiMAX, TD-SCDMA 5. Operation from a single 1.8 V supply and a separate digital I/Q demodulation systems output driver supply to accommodate 1.8 V to 3.3 V logic Smart antenna systems families. General-purpose software radios 6. A standard serial port interface that supports various Broadband data applications product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. 7. Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 06547-001 AD9640 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 28 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 30 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 31 Product Highlights ........................................................................... 1 Timing ......................................................................................... 31 Revision History ............................................................................... 3 ADC Overrange and Gain Control .............................................. 32 General Description ......................................................................... 4 Fast Detect Overview ................................................................. 32 Specif ica t ions ..................................................................................... 5 ADC Fast Magnitude ................................................................. 32 ADC DC Specifications—AD9640ABCPZ-80, ADC Overrange (OR) ................................................................ 33 AD9640BCPZ-80, AD9640ABCPZ-105, and Gain Switching ............................................................................ 33 AD9640BCPZ-105 ......................................................................... 5 Signal Monitor ................................................................................ 35 ADC DC Specifications—AD9640ABCPZ-125, Peak Detector Mode................................................................... 35 AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ......................................................................... 6 RMS/MS Magnitude Mode ......................................................... 35 ADC AC Specifications—AD9640ABCPZ-80, Threshold Crossing Mode ......................................................... 36 AD9640BCPZ-80, AD9640ABCPZ-105, and Additional Control Bits ............................................................. 36 AD9640BCPZ-105 ......................................................................... 7 DC Correction ............................................................................ 36 ADC AC Specifications—AD9640ABCPZ-125, Signal Monitor SPORT Output ................................................ 37 AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ 150 ......................................................................... 8 Built-In Self-Test (BIST) and Output Test .................................. 38 Digital Specifications ................................................................... 9 Built-In Self-Test (BIST) ............................................................ 38 Switching Specifications—AD9640ABCPZ-80, Output Test Modes ..................................................................... 38 AD9640BCPZ-80, AD9640ABCPZ-105, and Channel/Chip Synchronization .................................................... 39 AD9640BCPZ-105 ..................................................................... 10 Serial Port Interface (SPI) .............................................................. 40 Switching Specifications—AD9640ABCPZ-125, Configuration Using the SPI ..................................................... 40 AD9640BCPZ-125, AD9640ABCPZ-150, and Hardware Interface ..................................................................... 40 AD9640BCPZ-150 ..................................................................... 11 Configuration Without the SPI ................................................ 41 Timing Specifications ................................................................ 12 Absolute Maximum Ratings .......................................................... 14 SPI Accessible Features .............................................................. 41 Thermal Characteristics ............................................................ 14 Memory Map .................................................................................. 42 ESD Caution ................................................................................ 14 Reading the Memory Map Table .............................................. 42 Pin Configurations and Function Descriptions ......................... 15 External Memory Map .............................................................. 43 Memory Map Register Description ......................................... 46 Equivalent Circuits ......................................................................... 19 Applications Information .............................................................. 49 Typical Performance Characteristics ........................................... 20 Design Guidelines ...................................................................... 49 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Outline Dimensions ....................................................................... 50 Analog Input Considerations .................................................... 25 Ordering Guide .......................................................................... 51 Voltage Reference ....................................................................... 27 Rev. B | Page 2 of 52 AD9640 REVISION HISTORY Changes to Figure 11, Figure 12, Figure 14 ................................. 18 12/09—Rev. A to Rev. B Change to Table 15 .......................................................................... 30 Added CP-64-6 Package .................................................... Universal Changes to ADC Overrange and Gain Control Section ............ 31 Changes to Ordering Guide ........................................................... 51 Changes to Signal Monitor Section .............................................. 34 6/09—Rev. 0 to Rev. A Changes to Table 25 ........................................................................ 42 Changes to Applications Section and Product Changes to Signal Monitor Period (Register 0x113 to Highlights Section ............................................................................. 1 Register 0x115) Section .................................................................. 47 Changes to General Description Section ....................................... 3 Added LVDS Operation Section ................................................... 48 Changes to Specifications Section ................................................... 4 Added Exposed Pad Notation to Outline Dimensions .............. 49 Changes to Figure 2 ......................................................................... 11 6/07—Revision 0: Initial Version Changes to Figure 3 ......................................................................... 12 Changes to Pin Configurations and Functional Descriptions Section ....................................................................... 12 Rev. B | Page 3 of 52 AD9640 GENERAL DESCRIPTION The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to- In addition, the programmable threshold detector allows moni- digital converter (ADC). The AD9640 is designed to support toring of the incoming signal power using the four fast detect communications applications where low cost, small size, and bits of the ADC with very low latency. If the input signal level versatility are desired. exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four The dual ADC core features a multistage, differential pipelined MSBs, the user can quickly turn down the system gain to avoid an architecture with integrated output error correction logic. Each overrange condition. ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable The second AGC-related function is the signal monitor. This input ranges. An integrated voltage reference eases design block allows the user to monitor the composite magnitude of considerations. A duty cycle stabilizer is provided to compen- the incoming signal, which aids in setting the gain to optimize sate for variations in the ADC clock duty cycle, allowing the the dynamic range of the overall system. converters to maintain excellent performance. The ADC output data can be routed directly to the two external The AD9640 has several functions that simplify the automatic 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V gain control (AGC) function in the system receiver. The fast detect CMOS or 1.8 V LVDS. feature allows fast overrange detection by outputting four bits of Flexible power-down options allow significant power savings, input level information with very short latency. when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. B | Page 4 of 52 AD9640 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. AD9640ABCPZ- AD9640ABCPZ- 80/AD9640BCPZ-80 105/AD9640BCPZ-105 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.3 ±0.6 % FSR Gain Error Full ±0.2 ±3.0 ±0.2 ±3.0 % FSR 1 Differential Nonlinearity (DNL) Full ±0.9 ±0.9 LSB 25°C ±0.4 ±0.4 LSB 1 Full ±5.0 ±5.0 LSB Integral Nonlinearity (INL) 25°C ±2.0 ±2.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.3 ±0.6 ±0.4 ±0.7 % FSR Gain Error Full ±0.1 ±0.5 ±0.1 ±0.5 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±2 ±15 ±2 ±15 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.3 1.3 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p 2 Input Capacitance Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1, 3 I Full 233 310 mA AVDD 277 371 1, 3 I Full 26 34 mA DVDD 1 I (3.3 V CMOS) Full 27 35 mA DRVDD 1 Full 12 18 mA IDRVDD (1.8 V CMOS) 1 Full 54 55 mA IDRVDD (1.8 V LVDS) POWER CONSUMPTION DC Input Full 452 492 603 657 mW 1 Full 487 645 mW Sine Wave Input (DRVDD = 1.8 V) 1 Full 550 730 mW Sine Wave Input (DRVDD = 3.3 V) 4 Standby Power Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). Rev. B | Page 5 of 52 AD9640 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2. AD9640ABCPZ-125/ AD9640ABCPZ-150/ AD9640BCPZ-125 AD9640BCPZ-150 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.3 ±0.6 % FSR Gain Error Full ±0.2 ±3.0 ±0.2 ±3.0 % FSR 1 Differential Nonlinearity (DNL) Full ±0.9 −0.95/+1.5 LSB 25°C ±0.4 −0.4/+0.6 LSB 1 Integral Nonlinearity (INL) Full ±5.0 ±5.0 LSB 25°C ±2 ±2 LSB MATCHING CHARACTERISTIC Offset Error 25°C ±0.4 ±0.7 ±0.4 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.6 ±0.2 ±0.6 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±2 ±15 ±3 ±15 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.3 1.3 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p 2 Input Capacitance Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1, 3 Full 385 419 mA IAVDD 470 517 1, 3 Full 42 50 mA IDVDD 1 IDRVDD (3.3 V CMOS) Full 44 53 mA 1 I (1.8 V CMOS) Full 22 27 mA DRVDD 1 I (1.8 V LVDS) 56 57 DRVDD POWER CONSUMPTION DC Input Full 750 846 820 938 mW 1 Sine Wave Input (DRVDD = 1.8 V) Full 810 895 mW 1 Sine Wave Input (DRVDD = 3.3 V) Full 910 1000 mW 4 Standby Power Full 77 77 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). Rev. B | Page 6 of 52 AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. AD9640ABCPZ-80/ AD9640ABCPZ-105/ AD9640BCPZ-80 AD9640BCPZ-105 1 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.3 MHz 25°C 72.5 72.3 dB IN fIN = 70 MHz 25°C 72.1 71.9 dB Full 70.5 70.2 dB f = 140 MHz 25°C 71.6 71.3 dB IN fIN = 200 MHz 25°C 71.0 70.3 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 72.2 72.0 dB f = 70 MHz 25°C 71.6 71.6 dB IN Full 69 69.5 dB f = 140 MHz 25°C 71.1 70.9 dB IN fIN = 200 MHz 25°C 70.4 70.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.9 11.8 Bits f = 70 MHz 25°C 11.8 11.8 Bits IN fIN = 140 MHz 25°C 11.7 11.7 Bits fIN = 200 MHz 25°C 11.6 11.5 Bits WORST SECOND OR THIRD HARMONIC f = 2.3 MHz 25°C −87 −87 dBc IN fIN = 70 MHz 25°C −85 −85 dBc Full −75 −74 dBc f = 140 MHz 25°C −84 −84 dBc IN fIN = 200 MHz 25°C −83 −83 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.3 MHz 25°C 87 87 dBc IN f = 70 MHz 25°C 85 85 dBc IN Full 75 74 dBc f = 140 MHz 25°C 84 84 dBc IN fIN = 200 MHz 25°C 83 83 dBc WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −93 −93 dBc f = 70 MHz 25°C −89 −89 dBc IN Full −82 −81 dBc f = 140 MHz 25°C −89 −89 dBc IN f = 200 MHz 25°C −89 −89 dBc IN TWO TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) 25°C 85 85 dBc f = 169.1 MHz, 172.1 MHz (−7 dBFS) 25°C 82 82 dBc IN 2 CROSSTALK Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. Rev. B | Page 7 of 52 AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. AD9640ABCPZ-125 AD9640ABCPZ-150/ AD9640BCPZ-125 AD9640BCPZ-150 1 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.3 MHz 25°C 72.1 71.9 dB IN fIN = 70 MHz 25°C 71.8 71.6 dB Full 70.2 69.5 dB f = 140 MHz 25°C 71.4 70.9 dB IN fIN = 200 MHz 25°C 70.8 70.0 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 71.8 71.6 dB f = 70 MHz 25°C 71.4 71.0 dB IN Full 69.5 67.5 dB f = 140 MHz 25°C 71.0 70.5 dB IN fIN = 200 MHz 25°C 70.3 69.9 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.8 11.8 Bits f = 70 MHz 25°C 11.7 11.8 Bits IN fIN = 140 MHz 25°C 11.7 11.6 Bits fIN = 200 MHz 25°C 11.6 11.5 Bits WORST SECOND OR THIRD HARMONIC f = 2.3 MHz 25°C −86.5 −86.5 dBc IN fIN = 70 MHz 25°C −85 −84 dBc Full −74 −73 dBc f = 140 MHz 25°C −84 −83.5 dBc IN fIN = 200 MHz 25°C −83 −77 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.3 MHz 25°C 86.5 86.5 dBc IN f = 70 MHz 25°C 85 84 dBc IN Full 74 73 dBc f = 140 MHz 25°C 84 83.5 dBc IN fIN = 200 MHz 25°C 83 77 dBc WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 dBc f = 70 MHz 25°C −89 −90 dBc IN Full −80 −80 dBc f = 140 MHz 25°C −89 −90 dBc IN f = 200 MHz 25°C −89 −90 dBc IN TWO TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) 25°C 85 85 dBc f = 169.1 MHz, 172.1 MHz (−7 dBFS) 25°C 82 82 dBc IN 2 CROSSTALK Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. Rev. B | Page 8 of 52 AD9640 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS) High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 2 LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN) High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF Rev. B | Page 9 of 52 AD9640 Parameter Temperature Min Typ Max Unit DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage (I = 50 μA) Full 3.29 V OH High Level Output Voltage (I = 0.5 mA) Full 3.25 V OH Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (I = 50 μA) Full 0.05 V OL CMOS Mode—DRVDD = 1.8 V High Level Output Voltage (IOH = 50 μA) Full 1.79 V High Level Output Voltage (I = 0.5 mA) Full 1.75 V OH Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (I = 50 μA) Full 0.05 V OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (V ), ANSI Mode Full 1.15 1.25 1.35 V OS Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.25 1.35 V OS 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. AD9640ABCPZ-80 AD9640ABCPZ-105/ AD9640BCPZ-80 AD9640BCPZ-105 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate 1 DCS Enabled Full 20 80 20 105 MSPS 1 DCS Disabled Full 10 80 10 105 MSPS CLK Period—Divide by 1 Mode (t) Full 12.5 9.5 ns CLK CLK Pulse Width High Divide by 1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns Divide by 1 Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns Divide by 2 Mode, DCS Enabled Full 1.6 1.6 ns Divide by 3 Through 8, DCS Enabled Full 0.8 0.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V 2 Data Propagation Delay (tPD) Full 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (t) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns DCO Setup Time (tS) Full 6.25 5.25 ns Hold Time (t) Full 5.75 4.25 ns H CMOS Mode—DRVDD = 1.8 V 2 Data Propagation Delay (tPD) Full 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns LVDS Mode—DRVDD = 1.8 V 2 Data Propagation Delay (t ) Full 3.0 3.7 4.4 3.0 3.7 4.4 ns PD DCO Propagation Delay (t) Full 5.4 7.0 8.4 5.2 6.4 7.6 ns DCO Rev. B | Page 10 of 52 AD9640 AD9640ABCPZ-80 AD9640ABCPZ-105/ AD9640BCPZ-80 AD9640BCPZ-105 Parameter Temp Min Typ Max Min Typ Max Unit CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency) 12/12.5 12/12.5 Cycles Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, t) Full 0.1 0.1 ps rms J 3 Wake-Up Time Full 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 7. AD9640ABCPZ-125/ AD9640ABCPZ-150/ AD9640BCPZ-125 AD9640BCPZ-150 Parameter Temperature Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate 1 DCS Enabled Full 20 125 20 150 MSPS 1 DCS Disabled Full 10 125 10 150 MSPS CLK Period—Divide by 1 Mode (t) Full 8 6.66 ns CLK CLK Pulse Width High Divide by 1 Mode, DCS Enabled Full 2.4 4 5.6 2.0 3.33 4.66 ns Divide by 1 Mode, DCS Disabled Full 3.6 4 4.4 3.0 3.33 3.66 ns Divide by 2 Mode, DCS Enabled Full 1.6 1.6 ns Divide by 3 Through 8, DCS Enabled Full 0.8 0.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V 2 Data Propagation Delay (tPD) Full 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (t) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns DCO Setup Time (tS) Full 4.5 3.83 ns Hold Time (t) Full 3.5 2.83 ns H CMOS Mode—DRVDD = 1.8 V 2 Data Propagation Delay (tPD) Full 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns LVDS Mode—DRVDD = 1.8 V 2 Data Propagation Delay (t ) Full 3.0 3.8 4.5 3.0 3.8 4.5 ns PD DCO Propagation Delay (t) Full 5.0 6.2 7.4 4.8 5.9 7.3 ns DCO CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency) 12/12.5 12/12.5 Cycles Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, t) Full 0.1 0.1 ps rms J 3 Wake-Up Time Full 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Rev. B | Page 11 of 52 AD9640 TIMING SPECIFICATIONS Table 8. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge SPORT TIMING REQUIREMENTS tCSSCLK Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns tSSCLKSDO Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 +0.4 ns tSSCLKSDFS Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 +0.4 ns Timing Diagrams N+ 2 N+ 1 N+ 3 N N+ 4 N+ 8 t A N+ 5 N+ 7 N+ 6 t CLK CLK+ CLK– t PD CH A/B DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 CH A/B FAST N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 DETECT t S t t t H DCO CLK DCOA/DCOB Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0) Rev. B | Page 12 of 52 06547-021 AD9640 N + 2 N + 1 N + 3 N N + 4 N + 8 t A N + 5 N + 7 N + 6 t CLK CLK+ CLK– t PD CH A/CH B DATA ABABAB ABABAB ABABA B A N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 CH A/CH B FAST ABABAB ABABAB ABABA B A DETECT N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 t t DCO CLK DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5) CLK+ t t SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements CLK+ CLK– t CSSCLK SMI SCLK t t SSCLKSDFS SSCLKSDO SMI SDFS SMI SDO DATA DATA Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode) Rev. B | Page 13 of 52 06547-072 06547-089 06547-082 AD9640 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 9. The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the customer ELECTRICAL board increases the reliability of the solder joints and maximizes AVDD, DVDD to AGND −0.3 V to +2.0 V the thermal capability of the package. DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V Table 10. Thermal Resistance AVDD to DRVDD −3.9 V to +2.0 V Airflow VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Package Velocity 1, 2 1, 3 1, 4 Type (m/s) θ θ θ Unit CLK+, CLK− to AGND −0.3 V to +3.9 V JA JC JB SYNC to AGND −0.3 V to +3.9 V 64-lead LFCSP 0 18.8 0.6 6.0 °C/W 9 mm × 9 mm VREF to AGND −0.3 V to AVDD + 0.2 V 1.0 16.5 °C/W SENSE to AGND −0.3 V to AVDD + 0.2 V 2.0 15.8 °C/W CML to AGND −0.3 V to AVDD + 0.2 V 1 JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). RBIAS to AGND −0.3 V to AVDD + 0.2 V 3 Per MIL-Std 883, Method 1012.1. CSB to AGND −0.3 V to +3.9 V 4 Per JEDEC JESD51-8 (still air). SCLK/DFS to DRGND −0.3 V to +3.9 V Typical θJA is specified for a 4-layer PCB with a solid ground SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V plane. As shown, airflow improves heat dissipation, which SMI SDO/OEB −0.3 V to DRVDD + 0.3 V reduces θJA. In addition, metal in direct contact with the SMI SCLK/PDWN −0.3 V to DRVDD + 0.3 V package leads from metal traces, through holes, ground, and SMI SDFS −0.3 V to DRVDD + 0.3 V power planes, reduces the θ . JA D0A/D0B through D13A/D13B to −0.3 V to DRVDD + 0.3 V DRGND ESD CAUTION FD0A/FD0B through FD3A/FD3B to −0.3 V to DRVDD + 0.3 V DRGND DCOA/DCOB to DRGND −0.3 V to DRVDD + 0.3 V ENVIRONMENTAL Operating Temperature Range −40°C to +85°C (Ambient) Maximum Junction Temperature 150°C Under Bias Storage Temperature Range −65°C to +150°C (Ambient) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 14 of 52 AD9640 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 DRVDD 1 INDICATOR 48 SCLK/DFS D6B 2 47 SDIO/DCS D7B 3 46 AVDD D8B 4 45 AVDD EXPOSED PADDLE, PIN 0 D9B 5 44 VIN+B (BOTTOM OF PACKAGE) D10B 6 43 VIN–B D11B 7 42 RBIAS D12B 8 41 CML AD9640 D13B (MSB) 9 40 SENSE PARALLEL CMOS DCOB 10 39 VREF DCOA 11 TOP VIEW 38 VIN–A D0A (LSB) 12 (Not to Scale) 37 VIN+A D1A 13 36 AVDD D2A 14 35 SMI SDFS D3A 15 34 SMI SCLK/PDWN D4A 16 33 SMI SDO/OEB NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View) Table 11. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground Exposed Pad for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. Rev. B | Page 15 of 52 D5A 17 64 DRGND D6A 18 63 D5B D7A 19 62 D4B DRGND 20 61 D3B DRVDD 21 60 D2B D8A 22 59 D1B D9A 23 58 D0B (LSB) DVDD 24 57 DVDD D10A 25 56 FD3B D11A 26 55 FD2B D12A 27 54 FD1B D13A (MSB) 28 53 FD0B FD0A 29 52 SYNC FD1A 30 51 CSB FD2A 31 50 CLK– FD3A 32 49 CLK+ 06547-002 AD9640 Pin No. Mnemonic Type Description ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator. See Table 18 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Table 18 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Table 18 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Table 18 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Table 18 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 18 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 18 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 18 for details. Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 12 D0A (LSB) Output Channel A CMOS Output Data. 13 D1A Output Channel A CMOS Output Data. 14 D2A Output Channel A CMOS Output Data. 15 D3A Output Channel A CMOS Output Data. 16 D4A Output Channel A CMOS Output Data. 17 D5A Output Channel A CMOS Output Data. 18 D6A Output Channel A CMOS Output Data. 19 D7A Output Channel A CMOS Output Data. 22 D8A Output Channel A CMOS Output Data. 23 D9A Output Channel A CMOS Output Data. 25 D10A Output Channel A CMOS Output Data. 26 D11A Output Channel A CMOS Output Data. 27 D12A Output Channel A CMOS Output Data. 28 D13A (MSB) Output Channel A CMOS Output Data. 58 D0B (LSB) Output Channel B CMOS Output Data. 59 D1B Output Channel B CMOS Output Data. 60 D2B Output Channel B CMOS Output Data. 61 D3B Output Channel B CMOS Output Data. 62 D4B Output Channel B CMOS Output Data. 63 D5B Output Channel B CMOS Output Data. 2 D6B Output Channel B CMOS Output Data. 3 D7B Output Channel B CMOS Output Data. 4 D8B Output Channel B CMOS Output Data. 5 D9B Output Channel B CMOS Output Data. 6 D10B Output Channel B CMOS Output Data. 7 D11B Output Channel B CMOS Output Data. 8 D12B Output Channel B CMOS Output Data. 9 D13B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Serial Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B | Page 16 of 52 AD9640 PIN 1 DRVDD 1 INDICATOR 48 SCLK/DFS D1– 2 47 SDIO/DCS D1+ 3 46 AVDD D2– 4 45 AVDD EXPOSED PADDLE, PIN 0 D2+ 5 44 VIN+B (BOTTOM OF PACKAGE) D3– 6 43 VIN–B D3+ 7 42 RBIAS D4– 8 41 CML AD9640 D4+ 9 40 SENSE PARALLEL LVDS DCO– 10 39 VREF DCO+ 11 TOP VIEW 38 VIN–A D5– 12 (Not to Scale) 37 VIN+A D5+ 13 36 AVDD D6– 14 35 SMI SDFS D6+ 15 34 SMI SCLK/PDWN D7– 16 33 SMI SDO/OEB NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Pin Configuration, LFCSP LVDS (Top View) Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Function ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground for the Exposed Pad part. This exposed pad must be connected to ground for proper operation. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 18 for details. 53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 18 for details. 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 18 for details. 55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 18 for details. 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 18 for details. 58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 18 for details. 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details. 60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details. Rev. B | Page 17 of 52 D7+ 17 64 DRGND D8– 18 63 D0+ (LSB) D8+ 19 62 D0– (LSB) DRGND 20 61 FD3+ DRVDD 21 60 FD3– D9– 22 59 FD2+ D9+ 23 58 FD2– DVDD 24 57 DVDD D10– 25 56 FD1+ D10+ 55 FD1– 26 FD0+ D11– 27 54 D11+ 28 53 FD0– D12– 29 52 SYNC D12+ 30 51 CSB D13– (MSB) 31 50 CLK– D13+ (MSB) 32 49 CLK+ 06547-003 AD9640 Pin No. Mnemonic Type Function Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 63 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 62 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 3 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 2 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 5 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 4 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 7 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 6 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 9 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 8 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 13 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 12 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 15 D6+ Output Channel A/Channel B LVDS Output Data 6 —True. 14 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 17 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 16 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 19 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 18 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 23 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 22 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 26 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 25 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 28 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 27 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 30 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 29 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 32 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True. 31 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Ports 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B | Page 18 of 52 AD9640 EQUIVALENT CIRCUITS DVDD 1kΩ SCLK/DFS VIN 26kΩ Figure 8. Equivalent Analog Input Circuit Figure 12. Equivalent SCLK/DFS Input Circuit AVDD 1kΩ 1.2V SENSE 10kΩ 10kΩ CLK+ CLK– Figure 13. Equivalent SENSE Circuit Figure 9. Equivalent Clock Input Circuit DRVDD DVDD DVDD 26kΩ 1kΩ CSB DRGND Figure 10. Digital Output Figure 14. Equivalent CSB Input Circuit DRVDD DVDD AVDD 26kΩ DVDD 1kΩ VREF SDIO/DCS 6kΩ DRVDD Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit Figure 15. Equivalent VREF Circuit Rev. B | Page 19 of 52 06547-081 06547-004 06547-007 06547-005 06547-096 06547-010 06547-009 06547-011 AD9640 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input; VIN = −1.0 dBFS; and 64k sample; TA = 25°C, unless otherwise noted. 0 0 150MSPS 150MSPS 2.3MHz @ –1dBFS 140.3MHz @ –1dBFS SNR = 71.9dBc (72.9dBFS) SNR = 70.9dBc (71.9dBFS) –20 –20 ENOB = 11.8 BITS ENOB = 11.6 BITS SFDR = 86dBc SFDR = 85.1dBc –40 –40 –60 –60 SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. AD9640-150 Single-Tone FFT with f = 2.3 MHz Figure 19. AD9640-150 Single-Tone FFT with f = 140.3 MHz IN IN 0 0 150MSPS 150MSPS 30.3MHz @ –1dBFS 200.3MHz @ –1dBFS SNR = 71.7dBc (72.7dBFS) SNR = 70dBc (71dBFS) –20 –20 ENOB = 11.8 BITS ENOB = 11.5 BITS SFDR = 89.9dBc SFDR = 80dBc –40 –40 SECOND HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. AD9640-150 Single-Tone FFT with fIN = 30.3 MHz Figure 20. AD9640-150 Single-Tone FFT with fIN = 200.3 MHz 0 0 150MSPS 150MSPS 70MHz @ –1dBFS 337MHz @ –1dBFS SNR = 71.5dBc (72.5dBFS) SNR = 68dBc (69dBFS) –20 –20 ENOB = 11.7 BITS ENOB = 11 BITS SFDR = 84dBc SFDR = 72.4dB –40 –40 THIRD HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9640-150 Single-Tone FFT with fIN = 70 MHz Figure 21. AD9640-150 Single-Tone FFT with fIN = 337 MHz Rev. B | Page 20 of 52 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06547-052 06547-051 06547-050 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06547-085 06547-054 06547-053 AD9640 0 0 150MSPS 125MSPS 440MHz @ –1dBFS 70MHz @ –1dBFS SNR = 65dBc (66dBFS) SNR = 71.8dBc (72.8dBFS) –20 –20 ENOB = 10.4 BITS ENOB = 11.7 BITS SFDR = 70.0dB SFDR = 85dBc –40 –40 SECOND HARMONIC –60 –60 THIRD HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. AD9640-150 Single-Tone FFT with f = 440 MHz Figure 25. AD9640-125 Single-Tone FFT with f = 70 MHz IN IN 0 0 125 MSPS 125 MSPS 2.3MHz @ –1dBFS 140MHz @ –1dBFS SNR = 72.3dBc (73.3dBFS) SNR = 71.4dBc (72.4dBFS) –20 –20 ENOB = 11.8 BITS ENOB = 11.7 BITS SFDR = 88.4dBc SFDR = 87.1dBc –40 –40 SECOND HARMONIC –60 –60 THIRD HARMONIC SECOND HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. AD9640-125 Single-Tone FFT with fIN = 2.3 MHz Figure 26. AD9640-125 Single-Tone FFT with f = 140 MHz IN 0 0 125 MSPS 125 MSPS 30.3MHz @ –1dBFS 200MHz @ –1dBFS SNR = 72.1dBc (73.1dBFS) SNR = 70.8dBc (71.8dBFS) –20 –20 ENOB = 11.8 BITS ENOB = 11.6 BITS SFDR = 89.1dBc SFDR = 80.5dBc –40 –40 THIRD HARMONIC THIRD HARMONIC –60 –60 SECOND HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD9640-125 Single-Tone FFT with f = 30.3 MHz Figure 27. AD9640-125 Single-Tone FFT with f = 200 MHz IN IN Rev. B | Page 21 of 52 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06547-058 06547-057 06547-086 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06547-060 06547-059 06547-093 AD9640 120 95 SFDR (dBFS) 90 SFDR = +25°C 100 85 80 SNR (dBFS) 80 SFDR = –40°C 60 75 SFDR = +85°C 40 SFDR (dBc) SNR = –40°C SNR (dBc) 70 20 85dB REFERENCE LINE 65 SNR = +25°C SNR = +85°C 0 60 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 250 300 350 400 450 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 28. AD9640-150 Single-Tone SNR/SFDR vs. Input Amplitude (A ) Figure 31. AD9640-150 Single-Tone SNR/SFDR vs. IN with f = 2.3 MHz Input Frequency (f ) and Temperature with 1 V p-p Full Scale IN IN 120 0.8 SFDR (dBFS) 0.6 100 0.4 OFFSET 80 0.2 SNR (dBFS) 0 60 –0.2 40 SFDR (dBc) –0.4 SNR (dBc) –0.6 GAIN 20 85dB REFERENCE LINE –0.8 0 –1.0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –40 –20 0 2040 6080 INPUT AMPLITUDE (dBFS) TEMPERATURE (°C) Figure 29. AD9640-150 Single-Tone SFDR vs. Input Amplitude with Figure 32. AD9640 Gain and Offset vs. Temperature f = 98.12 MHz IN 95 0 90 –20 SFDR = +25°C SFDR (dBc) 85 –40 SFDR = –40°C 80 IMD3 (dBc) –60 SFDR = +85°C SNR = –40°C 75 –80 70 SFDR (dBFS) SNR = +25°C –100 65 SNR = +85°C IMD3 (dBFS) 60 –120 0 50 100 150 200 250 300 350 400 450 –90 –78 –66 –54 –42 –30 –18 –6 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 30. AD9640-150 Single-Tone SNR/SFDR vs. Figure 33. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN Input Frequency (f ) and Temperature with 2 V p-p Full Scale with f = 29.1 MHz, f = 32.1 MHz, f = 150 MSPS IN IN1 IN2 S Rev. B | Page 22 of 52 SNR/SFDR (dBc) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 06547-087 06547-062 06547-061 SNR/SFDR (dBc AND dBFS) GAIN/OFFSET ERROR (%FSR) SNR/SFDR (dBc) 06547-063 06547-098 06547-088 AD9640 0 0 150 MSPS 169.1MHz @–7dBFS 172.1MHz @–7dBFS –20 –20 SFDR = 83.8dBc (90.8dBFS) SFDR (dBc) –40 –40 –60 –60 IMD3 (dBc) IMD3 (dBFS) –80 –80 SFDR (dBFS) –100 –100 –120 –120 –90 –78 –66 –54 –42 –30 –18 –6 0 10 20 30 40 50 60 70 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 37. AD9640-150 Two-Tone FFT with f = 169.1 MHz and IN IN1 with f = 169.1 MHz, f = 172.1 MHz, f = 150 MSPS f = 172.1 MHz IN1 IN2 S IN2 0 0 NPR = 64.7dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 15.36 30.72 46.08 61.44 0 15.625 31.25 46.875 62.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 35. AD9640-125, Two 64 k WCDMA Carriers Figure 38. AD9640 Noise Power Ratio (NPR) with f = 170 MHz, f = 122.88 MSPS IN S 0 100 150 MSPS 29.1MHz @–7dBFS 32.1MHz @–7dBFS –20 95 SFDR = 86.1dBc (93dBFS) SFDR—SIDE A –40 90 –60 85 SFDR—SIDE B –80 80 SNR—SIDE B SNR—SIDE A –100 75 –120 70 0 10 20 30 40 50 60 70 0 25 50 75 100 125 150 FREQUENCY (MHz) CLOCK FREQUENCY (Msps) Figure 36. AD9640-150 Two-Tone FFT with f = 29.1 MHz and f = 32.1 MHz Figure 39. AD9640-125 Single-Tone SNR/SFDR vs. Clock Frequency (f ) IN1 IN2 S with f = 2.3 MHz IN Rev. B | Page 23 of 52 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 06547-065 06547-102 06547-064 SNR/SFDR (dBc) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06547-067 06547-100 06547-066 AD9640 10 100 1.3 LSB rms SFDR DCS ON 95 8 90 85 SFDR DCS OFF 6 80 SNR DCS ON 4 75 70 2 SNR DCS OFF 65 0 60 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 20 40 60 80 OUTPUT CODE DUTY CYCLE (%) Figure 40. AD9640 Grounded Input Histogram Figure 43. AD9640 SNR/SFDR vs. Duty Cycle with f = 10.3 MHz IN 2.0 90 SFDR 1.5 1.0 85 0.5 0 80 –0.5 –1.0 75 –1.5 SNR –2.0 70 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0.5 1.3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 OUTPUT CODE INPUT COMMON-MODE VOLTAGE (V) Figure 41. AD9640 INL with f = 10.3 MHz IN Figure 44. AD9640 SNR/SFDR vs. Input Common Mode Voltage (VCM) with fIN = 30 MHz 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4. –0.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE Figure 42. AD9640 DNL with f = 10.3 MHz IN Rev. B | Page 24 of 52 DNL ERROR (LSB) INL ERROR (LSB) NUMBER OF HITS (1M) 06547-069 06547-068 06547-079 SNR/SFDR (dBc) SNR/SFDR (dBc) 06547-091 06547-090 AD9640 THEORY OF OPERATION A small resistor in series with each input can help reduce the The AD9640 dual ADC design can be used for diversity reception peak transient current required from the output stage of the of signals, where the ADCs are operating identically on the same driving source. A shunt capacitor can be placed across the carrier but from two separate antennae. The ADCs can also be inputs to provide dynamic charging currents. This passive operated with independent analog inputs. The user can sample network creates a low-pass filter at the ADC input; therefore, any f /2 frequency segment from dc to 200 MHz using appropriate S the precise values are dependent on the application. low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is In intermediate frequency (IF) undersampling applications, permitted but occurs at the expense of increased ADC distortion. any shunt capacitors should be reduced. In combination with the driving source impedance, they limit the input bandwidth. In nondiversity applications, the AD9640 can be used as a base- See the AN-742 Application Note, Frequency Domain Response band receiver, where one ADC is used for I input data and the of Switched-Capacitor ADCs; the AN-827 Application Note, A other is used for Q input data. Resonant Approach to Interfacing Amplifiers to Switched-Capacitor Synchronizaton capability is provided to allow synchronized ADCs; and the Analog Dialogue article, “Transformer-Coupled timing between multiple channels or multiple devices. Front-End for Wideband A/D Converters” for more information Programming and control of the AD9640 are accomplished on this subject. using a 3-bit SPI-compatible serial interface. S ADC ARCHITECTURE C H The AD9640 architecture consists of a dual front-end sample- S C S and-hold amplifier (SHA), followed by a pipelined, switched VIN+ capacitor ADC. The quantized outputs from each stage are C PIN, PAR S H C combined into a final 14-bit result in the digital correction S VIN– logic. The pipelined architecture permits the first stage to C C H PIN, PAR operate on a new input sample, and the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. S Each stage of the pipeline, excluding the last, consists of a low Figure 45. Switched-Capacitor SHA Input resolution flash ADC connected to a switched capacitor digital- For best dynamic performance, the source impedances driving to-analog converter (DAC) and an interstage residue amplifier VIN+ and VIN− should be matched. (MDAC). The residue amplifier magnifies the difference between An internal differential reference buffer creates positive and the reconstructed DAC output and the flash input for the next negative reference voltages that define the input span of the ADC stage in the pipeline. One bit of redundancy is used in each stage core. The span of the ADC core is set by the buffer to 2 × VREF. to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Input Common Mode The input stage of each channel contains a differential SHA that The analog inputs of the AD9640 are not internally dc biased. can be ac- or dc-coupled in differential or single-ended modes. In ac-coupled applications, the user must provide this bias The output staging block aligns the data, carries out error correc- externally. Setting the device so that V = 0.55 × AVDD CM tion, and passes the data to the output buffers. The output buffers is recommended for optimum performance, but the device are powered from a separate supply, allowing adjustment of the functions over a wider range with reasonable performance output voltage swing. During power-down, the output buffers go (see Figure 44). An on-board common-mode voltage reference into a high impedance state. is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode ANALOG INPUT CONSIDERATIONS voltage of the analog input is set by the CML pin voltage The analog input to the AD9640 is a differential switched (typically 0.55 × AVDD). The CML pin must be decoupled to capacitor SHA that has been designed for optimum performance ground by a 0.1 μF capacitor, as described in the Applications while processing a differential input signal. Information section. The clock signal alternatively switches the SHA between sample Differential Input Configurations mode and hold mode (see Figure 45). When the SHA is switched Optimum performance is achieved while driving the AD9640 into sample mode, the signal source must be capable of charging in a differential input configuration. For baseband applications, the sample capacitors and settling within ½ of a clock cycle. the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. Rev. B | Page 25 of 52 06547-024 AD9640 The output common-mode voltage of the AD8138 is easily set An alternative to using a transformer coupled input at frequencies with the CML pin of the AD9640 (see Figure 46), and the driver in the second Nyquist zone is to use the AD8352 differential can be configured in a Sallen-Key filter topology to provide driver. An example is shown in Figure 50. See the AD8352 data sheet for more information. band limiting of the input signal. 499Ω In any configuration, the value of Shunt Capacitor C is dependent R 1V p-p 49.9Ω VIN+ AVDD on the input frequency and source impedance and may need to 499Ω be reduced or removed. Table 13 displays recommended values to C AD9640 AD8138 set the RC network. However, these values are dependent on the 0.1µF 523Ω R CML VIN– input signal and should be used only as a starting guide. 499Ω Table 13. Example RC Network Figure 46. Differential Input Configuration Using the AD8138 R Series For baseband applications where SNR is a key parameter, Frequency Range (MHz) (Ω Each) C Differential (pF) 0 to 70 33 15 differential transformer coupling is the recommended input 70 to 200 33 5 configuration. An example is shown in Figure 47. To bias the analog input, the CML voltage can be connected to the center 200 to 300 15 5 tap of the transformer’s secondary winding. >300 15 Open R VIN+ Single-Ended Input Configuration 49.9Ω C 2V p-p AD9640 A single-ended input can provide adequate performance in cost R CML VIN– sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. 0.1µF If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 details a typical Figure 47. Differential Transformer-Coupled Configuration single-ended input configuration. The signal characteristics must be considered when selecting AVDD 10µF a transformer. Most RF transformers saturate at frequencies 1kΩ below a few MHz, and excessive signal power can also cause R VIN+ core saturation, which leads to distortion. 0.1µF 49.9Ω 1kΩ 1V p-p AVDD AD9640 C At input frequencies in the second Nyquist zone and above, the 1kΩ noise performance of most amplifiers is not adequate to achieve R VIN– the true SNR performance of the AD9640. For applications where 10µF 1kΩ 0.1µF SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49 for an example). Figure 48. Single-Ended Input Configuration 0.1µF 0.1µF R VIN+ 2V p-p 25Ω P S S P C AD9640 A 0.1µF 25Ω 0.1µF R CML VIN– Figure 49. Differential Double Balun Input Configuration V CC 0.1µF 0.1µF 0Ω 16 8, 13 ANALOG INPUT 0.1µF R 1 11 VIN+ 2 200Ω R R AD8352 C AD9640 C D G D 3 200Ω 0.1µF 10 R 4 CML VIN– 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 50. Differential Input Configuration Using the AD8352 Rev. B | Page 26 of 52 06547-026 06547-025 06547-070 06547-028 06547-071 AD9640 VOLTAGE REFERENCE VIN+A/VIN+B VIN–A/VIN–B A stable and accurate voltage reference is built into the AD9640. The input range can be adjusted by varying the reference voltage ADC applied to the AD9640, using either the internal reference or an CORE externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference VREF modes are summarized in the next few sections. The Reference 1.0µF 0.1µF R2 Decoupling section describes the best practices PCB layout of SELECT LOGIC the reference. SENSE Internal Reference Connection 0.5V R1 A comparator within the AD9640 detects the potential at the SENSE pin and configures the reference into four possible AD9640 modes, which are summarized in Table 14. If SENSE is grounded, Figure 52. Programmable Reference Configuration the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1 V. Connecting If the internal reference of the AD9640 is used to drive multiple the SENSE pin to VREF switches the reference amplifier output converters to improve gain matching, the loading of the reference to the SENSE pin, completing the loop and providing a 0.5 V by the other converters must be considered. Figure 53 shows reference output. If a resistor divider is connected external to how the internal reference voltage is affected by loading. the chip, as shown in Figure 52, the switch again sets to the 0 SENSE pin. This puts the reference amplifier in a noninverting VREF = 0.5V mode with the VREF output defined as –0.25 R2 ⎛ ⎞ VREF = 1V VREF =0 .5× 1+ ⎜ ⎟ R1 ⎝ ⎠ –0.50 The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. –0.75 VIN+A/VIN+B VIN–A/VIN–B –1.00 ADC CORE –1.25 02 0.5 1.0 1.5.0 LOAD CURRENT (mA) VREF Figure 53. VREF Accuracy vs. Load 1.0µF 0.1µF SELECT External Reference Operation LOGIC SENSE The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- 0.5V teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1 V mode. AD9640 Figure 51. Internal Reference Configuration Table 14. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 2 × VREF ⎛ R2 ⎞ (see Figure 52) 0.5 × ⎜1+ ⎟ R1 ⎝ ⎠ Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. B | Page 27 of 52 06547-030 REFERENCE VOLTAGE ERROR (%) 06547-031 06547-080 AD9640 2.5 This helps prevent the large voltage swings of the clock from 2.0 feeding through to other portions of the AD9640, while preserving the fast rise and fall times of the signal that are critical to a low 1.5 jitter performance. 1.0 0 MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF 0.1µF –0.5 XFMR CLOCK CLK+ INPUT 100Ω –1.0 ADC 50Ω 0.1µF AD9640 CLK– –1.5 SCHOTTKY 0.1µF DIODES: –2.0 HSMS2822 –2.5 Figure 56. Transformer Coupled Differential Clock (Up to 200 MHz) –40 –20 0 2040 6080 TEMPERATURE (°C) Figure 54. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is 1nF 0.1µF CLOCK disabled, allowing the use of an external reference. An internal CLK+ INPUT ADC 50Ω reference buffer loads the external reference with an equivalent 0.1µF AD9640 1nF 6 kΩ load (see Figure 15). The internal buffer generates the CLK– SCHOTTKY positive and negative full-scale references for the ADC core. DIODES: HSMS2822 Therefore, the external reference must be limited to a maximum Figure 57. Balun Coupled Differential Clock (Up to 625 MHz) of 1 V. If a low jitter clock source is not available, another option is to CLOCK INPUT CONSIDERATIONS ac couple a differential PECL signal to the sample clock input For optimum performance, the AD9640 sample clock inputs pins, as shown in Figure 58. The AD9510/AD9511/AD9512/ CLK+, and CLK− should be clocked with a differential signal. AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent The signal is typically ac-coupled into the CLK+ and CLK− pins jitter performance. via a transformer or capacitors. These pins are biased internally (see Figure 55) and require no external bias. AVDD 0.1µF 0.1µF CLOCK CLK+ INPUT ADC AD951x 100Ω 1.2V AD9640 PECL DRIVER 0.1µF 0.1µF CLOCK CLK– CLK+ CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ 2pF 2pF Figure 58. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 59. The AD9510/ Figure 55. Equivalent Clock Input Circuit AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock Clock Input Options drivers offer excellent jitter performance. The AD9640 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of 0.1µF 0.1µF the type of signal being used, the jitter of the clock source is of the CLOCK CLK+ INPUT most concern, as described in the Jitter Considerations section. ADC AD951x 100Ω AD9640 LVDS DRIVER 0.1µF 0.1µF Figure 56 and Figure 57 show two preferred methods for clocking CLOCK CLK– INPUT the AD9640 (at clock rates to 625 MHz). A low jitter clock source 50kΩ 50kΩ is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun Figure 59. Differential LVDS Sample Clock (Up to 625 MHz) configuration is recommended for clock frequencies between In some applications, it may be acceptable to drive the sample 125 MHz and 625 MHz, and the RF transformer is recommended clock inputs with a single-ended CMOS signal. In such applica- for clock frequencies from 10 MHz to 200MHz. The back-to-back tions, CLK+ should be directly driven from a CMOS gate, and Schottky diodes across the transformer/balun secondary limit the CLK− pin should be bypassed to ground with a 0.1 μF clock excursions into the AD9640 to approximately 0.8 V p-p capacitor in parallel with a 39 kΩ resistor (see Figure 60). differential. Rev. B | Page 28 of 52 REFERENCE VOLTAGE ERROR (mV) 06547-034 06547-099 06547-101 06547-035 06547-037 06547-036 AD9640 CLK+ can be directly driven from a CMOS gate. Although the Jitter in the rising edge of the input is still of paramount concern CLK+ input circuit supply is AVDD (1.8 V), this input is designed and is not easily reduced by the internal stabilization circuit. to withstand input voltages up to 3.6 V, making the selection of The duty cycle control loop does not function for clock rates the drive logic voltage very flexible. less than 20 MHz nominally. The loop has a time constant associated with it that needs to be considered where the clock V CC rate can change dynamically. This requires a wait time of 1.5 μs OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω to 5 μs after a dynamic clock frequency increase or decrease before CLOCK CLK+ CMOS DRIVER INPUT the DCS loop is relocked to the input signal. During the time 1 1kΩ 50Ω ADC AD9640 period the loop is not locked, the DCS loop is bypassed, and CLK– internal device timing is dependent on the duty cycle of the input 0.1µF 39kΩ clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS 1 50Ω RESISTOR IS OPTIONAL circuit is recommended to maximize ac performance. Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS) Jitter Considerations High speed, high resolution ADCs are sensitive to the quality V CC of the clock input. The degradation in SNR from the low OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK frequency SNR (SNRLF) at a given input frequency (fINPUT) due CLK+ CMOS DRIVER INPUT 1 50Ω 1kΩ to jitter (tJRMS) can be calculated by ADC AD9640 0.1µF (−SNR /10) 2 LF SNRHF = −10 log[(2π × fINPUT × tJRMS) + 10 ] CLK– In the equation, the rms aperture jitter represents the clock input 1 50Ω RESISTOR IS OPTIONAL jitter specification. IF undersampling applications are particularly Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) sensitive to jitter, as illustrated in Figure 62. Input Clock Divider 75 The AD9640 contains an input clock divider with the ability to 0.05ps 70 divide the input clock by integer values between 1 and 8. If a MEASURED divide ratio other than 1 is selected, the duty cycle stabilizer is PERFORMANCE 65 0.20ps automatically enabled. 60 The AD9640 clock divider can be synchronized using the external 0.5ps SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock 55 divider to be resynchronized on every SYNC signal or only on 1.0ps the first SYNC signal after the register is written. A valid SYNC 50 1.50ps causes the clock divider to reset to its initial state. This synchro- 2.00ps 45 nization feature allows multiple parts to have their clock dividers 2.50ps aligned to guarantee simultaneous input sampling. 3.00ps 40 1 10 100 1000 Clock Duty Cycle INPUT FREQUENCY (MHz) Typical high speed ADCs use both clock edges to generate Figure 62. SNR vs. Input Frequency and Jitter a variety of internal timing signals and, as a result, may be The clock input should be treated as an analog signal in cases sensitive to clock duty cycle. Commonly, a ±5% tolerance is where aperture jitter may affect the dynamic range of the AD9640. required on the clock duty cycle to maintain dynamic Power supplies for clock drivers should be separated from the performance characteristics. ADC output driver supplies to avoid modulating the clock The AD9640 contains a duty cycle stabilizer (DCS) that retimes signal with digital noise. Low jitter, crystal-controlled oscillators the nonsampling (falling) edge, providing an internal clock make the best clock sources. If the clock is generated from signal with a nominal 50% duty cycle. This allows the user to another type of source (by gating, dividing, or other methods), provide a wide range of clock input duty cycles without affecting it should be retimed by the original clock at the last step. the performance of the AD9640. Noise and distortion performance See the AN-501 Application Note and AN-756 Application are nearly flat for a wide range of duty cycles with the DCS on, Note for more information about jitter performance as it as shown in Figure 43. relates to ADCs. Rev. B | Page 29 of 52 06547-039 06547-038 SNR (dBc) 06547-041 AD9640 1 0.4 POWER DISSIPATION AND STANDBY MODE As shown in Figure 63, the power dissipated by the AD9640 I AVDD is proportional to its sample rate. In CMOS output mode, 0.3 0.75 the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. TOTAL POWER 0.2 The maximum DRVDD current (I ) can be calculated as 0.5 DRVDD I = V × C × f × N DRVDD DRVDD LOAD CLK where N is the number of output bits (30 in the case of the AD9640 0.1 0.25 I DRVDD with the FD bits disabled). This maximum current occurs when I DVDD every output bit switches on every clock cycle, that is, a full- scale square wave at the Nyquist frequency of fCLK/2. In practice, 0 0 25 50 75 100 0 the DRVDD current is established by the average number of ENCODE FREQUENCY (MHz) output bits switching, which is determined by the sample rate Figure 65. AD9640-105 Power and Current vs. Clock Frequency and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can 0.75 0.3 minimize digital power consumption. The data in Figure 63 was taken with the same operating conditions as the Typical Performance Characteristics, with a 5 pF load on each output I AVDD driver. 0.5 0.2 1.25 0.5 TOTAL POWER I AVDD 1.0 0.4 0.25 0.1 0.75 0.3 TOTAL POWER I DRVDD I DVDD 0.5 0.2 0 0 20 40 60 080 ENCODE FREQUENCY (MHz) I 0.25 DRVDD 0.1 Figure 66. AD9640-80 Power and Current vs. Clock Frequency I DVDD By asserting PDWN (either through the SPI port or by asserting 0 0 25 50 75 100 0 125 150 the PDWN pin high), the AD9640 is placed in power-down ENCODE FREQUENCY (MHz) mode. In this state, the ADC typically dissipates 2.5 mW. Figure 63. AD9640-150 Power and Current vs. Clock Frequency During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9640 to its normal operational mode. Note that PDWN is 1.25 0.5 referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. 1.0 0.4 I AVDD Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, 0.75 0.3 and clock. Internal capacitors are discharged when entering power- TOTAL POWER down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent 0.5 0.2 in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. 0.25 I 0.1 DRVDD I DVDD When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows 0 0 25 50 75 100 0 125 the user to keep the internal reference circuitry powered when ENCODE FREQUENCY (MHz) faster wake-up times are required. See the Memory Map Register Figure 64. AD9640-125 Power and Current vs. Clock Frequency Description section for more details. Rev. B | Page 30 of 52 TOTAL POWER (W) TOTAL POWER (W) SUPPLY CURRENT (A) SUPPLY CURRENT (A) 06547-075 06547-076 TOTAL POWER (W) TOTAL POWER (W) SUPPLY CURRENT (A) SUPPLY CURRENT (A) 06547-073 06547-074 AD9640 Digital Output Enable Function (OEB) DIGITAL OUTPUTS The AD9640 has a flexible three-state ability for the digital output The AD9640 output drivers can be configured to interface with pins. The three-state mode is enabled using the SMI SDO/OEB 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the pin or through the SPI interface. If the SMI SDO/OEB pin is low, digital supply of the interfaced logic. The AD9640 can also be the output data drivers are enabled. If the SMI SDO/OEB pin is configured for LVDS outputs using a DRVDD supply voltage high, the output data drivers are placed in a high impedance state. of 1.8 V. This OEB function is not intended for rapid access to the data In CMOS output mode, the output drivers are sized to provide bus. Note that OEB is referenced to the digital supplies (DRVDD) sufficient output current to drive a wide variety of logic families. and should not exceed that supply voltage. However, large drive currents tend to cause current glitches on When using the SPI interface, the data and fast detect outputs the supplies that may affect converter performance. of each channel can be independently three-stated by using the Applications requiring the ADC to drive large capacitive loads output enable bar bit in Register 0x14. or large fan-outs may require external buffers or latches. TIMING The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating The AD9640 provides latched data with a pipeline delay of in the external pin mode (see Table 15). twelve clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. As detailed in the AN-877 Application Note, Interfacing to High The length of the output data lines and loads placed on them Speed ADCs via SPI, the data format can be selected for offset should be minimized to reduce transients within the AD9640. binary, twos complement, or gray code when using the SPI control. These transients can degrade converter dynamic performance. Table 15. SCLK/DFS Mode Selection (External Pin Mode) The lowest typical conversion rate of the AD9640 is 10 MSPS. Voltage at Pin SCLK/DFS SDIO/DCS At clock rates below 10 MSPS, dynamic performance can degrade. AGND Offset binary (default) DCS disabled Data Clock Output (DCO) AVDD Twos complement DCS enabled (default) The AD9640 provides two data clock output (DCO) signals intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 16. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OVR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1 Rev. B | Page 31 of 52 AD9640 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to Table 17. Fast Detect Mode Select Bits Settings reliably determine when the converter is about to be clipped. Information Presented on Fast Detect The standard overflow indicator provides after-the-fact infor- 1, 2 Fast Detect (FD) Pins of Each ADC Mode Select Bits mation on the state of the analog input that is of limited usefulness. (Register 0x104[3:1]) FD3 FD2 FD1 FD0 Therefore, it is helpful to have a programmable threshold below 000 ADC fast magnitude full scale that allows time to reduce the gain before the clip (see Table 18) actually occurs. In addition, because input signals can have 001 ADC fast magnitude OR significant slew rates, latency of this function is of major concern. (see Table 19) Highly pipelined converters can have significant latency. A good 010 ADC fast magnitude OR F_LT (see Table 20) compromise is to use the output bits from the first stage of the ADC for this function. Latency for these output bits is very low, 011 ADC fast magnitude C_UT F_LT (see Table 20) and overall resolution is not highly significant. Peak input signals 100 OR C_UT F_UT F_LT are typically between full scale and 6 dB to 10 dB below full 101 OR F_UT IG DG scale. A 3-bit or 4-bit output provides adequate range and resolution for this function. 1 The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode configuration and FD0+/FD0− to FD3+/FD3− for the LVDS mode configuration. Using the SPI port, the user can provide a threshold above which 2 See the ADC Overrange (OR) and Gain Switching sections for more an overrange output is active. As long as the signal is below that information about OR, C_UT, F_UT, F_LT, IG, and DG. threshold, the output should remain low. The fast detect outputs ADC FAST MAGNITUDE can also be programmed via the SPI port so that one of the pins When the fast detect output pins are configured to output the ADC functions as a traditional overrange pin for customers who fast magnitude (that is, when the fast detect mode select bits are currently use this feature. In this mode, all 14 bits of the converter set to 0b000), the information presented is the ADC level from are examined in the traditional manner, and the output is high for an early converter stage with a latency of only two clock cycles the condition normally defined as overflow. In either mode, the (when in CMOS output mode). Using the fast detect output pins magnitude of the data is considered in the calculation of the in this configuration provides the earliest possible level indication condition (but the sign of the data is not considered). The threshold information. Because this information is provided early in the detection responds identically to positive and negative signals datapath, there is significant uncertainty in the level indicated. outside the desired range (magnitude). The nominal levels, along with the uncertainty indicated by the FAST DETECT OVERVIEW ADC fast magnitude, are shown in Table 18. The AD9640 contains circuitry to facilitate fast overrange detec- Table 18. ADC Fast Magnitude Nominal Levels with Fast Detect tion, allowing very flexible external gain control implementations. Mode Select Bits = 000 Each ADC has four fast detect (FD) output pins that are used Nominal Input ADC Fast Nominal Input to output information about the current state of the ADC input Magnitude Magnitude on Magnitude level. The function of these pins is programmable via the fast detect FD[3:0] Pins Below FS (dB) Uncertainty (dB) mode select bits and the fast detect enable bit in Register 0x104, 0000 <−24 Minimum to −18.07 allowing range information to be output from several points in 0001 −24 to −14.5 −30.14 to −12.04 the internal datapath. These output pins can also be set up to 0010 −14.5 to −10 −18.07 to −8.52 indicate the presence of overrange or underrange conditions, 0011 −10 to −7 −12.04 to −6.02 according to programmable threshold levels. Table 17 shows the 0100 −7 to −5 −8.52 to −4.08 six configurations available for the fast detect pins. 0101 −5 to −3.25 −6.02 to −2.5 0110 −3.25 to −1.8 −4.08 to −1.16 0111 −1.8 to −0.56 −2.5 to FS 1000 −0.56 to 0 −1.16 to 0 Rev. B | Page 32 of 52 AD9640 When the fast detect mode select bits are set to 0b001, 0b010, or Coarse Upper Threshold (C_UT) 0b011, a subset of the fast detect output pins is available. In these The coarse upper threshold indicator is asserted if the ADC fast modes, the fast detect output pins have a latency of six clock cycles. magnitude input level is greater than the level programmed in Table 19 shows the corresponding ADC input levels when the the coarse upper threshold register (Address 0x105[2:0]). The fast detect mode select bits are set to 0b001 (that is, when ADC fast coarse upper threshold output is output two clock cycles after the magnitude is presented on the FD[3:1] pins). level is exceeded at the input and, therefore, provides a fast indi- cation of the input signal level. The coarse upper threshold levels Table 19. ADC Fast Magnitude Nominal Levels with are listed in Table 21. This indicator remains asserted for a Fast Detect Mode Select Bits = 001 minimum of two ADC clock cycles or until the signal drops Nominal Input Nominal Input below the threshold level. ADC Fast Magnitude Magnitude Magnitude on FD[3:1] Pins Below FS (dB) Uncertainty (dB) Table 21. Coarse Upper Threshold Levels 000 <−24 Minimum to −18.07 C_UT Is Active When Signal 001 −24 to −14.5 −30.14 to −12.04 Coarse Upper Threshold Magnitude Below FS 010 −14.5 to −10 −18.07 to −8.52 Register 0x105[2:0] Is Greater Than (dB) 011 −10 to −7 −12.04 to −6.02 000 <−24 100 −7 to −5 −8.52 to −4.08 001 −24 101 −5 to −3.25 −6.02 to −2.5 010 −14.5 110 −3.25 to −1.8 −4.08 to −1.16 011 −10 111 −1.8 to 0 −2.5 to 0 100 −7 101 −5 When the fast detect mode select bits are set to 0b010 or 0b011 110 −3.25 (that is, when ADC fast magnitude is presented on the FD[3:2] 111 −1.8 pins), the LSB is not provided. The input ranges for this mode are shown in Table 20. Fine Upper Threshold (F_UT) Table 20. ADC Fast Magnitude Nominal Levels with The fine upper threshold indicator is asserted if the input Fast Detect Mode Select Bits = 010 or 011 magnitude exceeds the value programmed in the fine upper ADC Fast Nominal Input Nominal Input threshold register located in Register 0x106 and Register 0x107. Magnitude on Magnitude Magnitude The 13-bit threshold register is compared with the signal magni- FD[2:1] Pins Below FS (dB) Uncertainty (dB) tude at the output of the ADC. This comparison is subject to the 00 <−14.5 Minimum to −12.04 ADC clock latency but is accurate in terms of the converter 01 −14.5 to −7 −18.07 to −6.02 resolution. The fine upper threshold magnitude is defined by 10 −7 to −3.25 −8.52 to −2.5 the following equation: 11 −3.25 to 0 −4.08 to 0 13 dBFS = 20 log(Threshold Magnitude/2 ) ADC OVERRANGE (OR) Fine Lower Threshold (F_LT) The ADC overrange indicator is asserted when an overrange is The fine lower threshold indicator is asserted if the input detected on the input of the ADC. The overrange condition is magnitude is less than the value programmed in the fine lower determined at the output of the ADC pipeline and, therefore, is threshold register located at Register 0x108 and Register 0x109. subject to a latency of 12 ADC clock cycles. An overrange at the The fine lower threshold register is a 13-bit register that is input is indicated by this bit 12 clock cycles after it occurs. compared with the signal magnitude at the output of the ADC. This comparison is subject to ADC clock latency but is accurate GAIN SWITCHING in terms of the converter resolution. The fine lower threshold The AD9640 includes circuitry that is useful in applications either magnitude is defined by the following equation: where large dynamic ranges exist or where gain ranging converters 13 dBFS = 20 log(Threshold Magnitude/2 ) are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be The operation of the fine upper threshold indicators and fine programmed. Fast detect mode select bit = 010 through fast lower threshold indicators is shown in Figure 67. detect mode select bit = 101 support various combinations of the Increment Gain (IG) and Decrement Gain (DG) gain switching options. The increment gain and decrement gain indicators are intended One such use is to detect when an ADC is about to reach full to be used together to provide information to enable external scale with a particular input condition. The result is to provide gain control. The decrement gain indicator works in conjunction an indicator that can be used to quickly insert an attenuator that with the coarse upper threshold bits, asserting when the input prevents ADC overdrive. magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105). The increment gain indicator, Rev. B | Page 33 of 52 AD9640 13 similarly, corresponds to the fine lower threshold bits, except dBFS = 20 log(Threshold Magnitude/2 ) that it is asserted only if the input magnitude is less than the The decrement gain output works from the ADC fast detect value programmed in the fine lower threshold register after the output pins, providing a fast indication of potential overrange dwell time elapses. The dwell time is set by the 16-bit dwell time conditions. The increment gain uses the comparison at the value located at Address 0x10A and Address 0x10B and is set in output of the ADC, requiring the input magnitude to remain units of ADC input clock cycles ranging from 1 to 65,535. The below an accurate, programmable level for a predefined period fine lower threshold register is a 13-bit register that is compared before signaling external circuitry to increase the gain. with the magnitude at the output of the ADC. This comparison The operation of the increment gain output and the decrement is subject to the ADC clock latency but allows a finer, more gain output is shown in Figure 67. accurate comparison. The fine upper threshold magnitude is defined by the following equation: FINE UPPER THRESHOLD FINE LOWER THRESHOLD F_UT F_LT Figure 67. Threshold Settings for F_UT and F_LT Rev. B | Page 34 of 52 06547-097 AD9640 SIGNAL MONITOR The signal monitor block provides additional information When the monitor period timer reaches a count of 1, the 13-bit about the signal being digitized by the ADC. The signal monitor peak level value is transferred to the signal monitor holding register computes the rms input magnitude, the peak magnitude, (not accessible to the user), which can be read through the SPI port and/or the number of samples by which the magnitude exceeds or output through the SPORT serial interface. The monitor period a particular threshold. Together, these functions can be used to timer is reloaded with the value in the SMPR, and the countdown is gain insight into the signal characteristics and to estimate the restarted. In addition, the magnitude of the first input sample is peak/average ratio or even the shape of the complementary cumu- updated in the peak level holding register, and the comparison and lative distribution function (CCDF) curve of the input signal. This update procedure, as explained previously, continues. information can be used to drive an AGC loop to optimize the Figure 68 is a block diagram of the peak detector logic. The SMR range of the ADC in the presence of real-world signals. register contains the absolute magnitude of the peak detected by The signal monitor result values can be obtained from the part by the peak detector logic. reading back internal registers at Address 0x116 to Address 0x11B, FROM MEMORY using the SPI port or the signal monitor SPORT output. The output MAP SIGNAL MONITOR DOWN IS COUNT = 1? contents of the SPI-accessible signal monitor registers are set via PERIOD REGISTER COUNTER the two signal monitor mode bits of the signal monitor control LOAD register. Both ADC channels must be configured for the same FROM TO CLEAR MEMORY INPUT signal monitor mode (Address 0x112). Separate SPI-accessible, MAGNITUDE SIGNAL MONITOR MAP/SPORT PORTS STORAGE HOLDING 20-bit signal monitor result (SMR) registers are provided for each REGISTER REGISTER (SMR) LOAD LOAD ADC channel. Any combination of the signal monitor functions can also be output to the user via the serial SPORT interface. These outputs are enabled using the peak detector output enable COMPARE A>B bit, the rms/ms magnitude output enable bit, and the threshold Figure 68. ADC Input Peak Detector Block Diagram crossing output enable bit in the signal monitor SPORT control register. RMS/MS MAGNITUDE MODE For each signal monitor measurement, a programmable signal In this mode, the root-mean-square (rms) or mean-square (ms) monitor period register (SMPR) controls the duration of the magnitude of the input port signal is integrated (by adding an measurement. This period of time is programmed as the number accumulator) over a programmable period of time (determined by of input clock cycles in a 24-bit signal monitor period register the SMPR) to give the rms or ms magnitude of the input signal. located at Address 0x113, Address 0x114, and Address 0x115. This mode is set by programming Logic 0 in the signal monitor This register can be programmed with a period from 128 samples mode bits of the signal monitor control register or by setting the 24 ) million samples. to 16.78 (2 rms/ms magnitude output enable bit in the signal monitor SPORT Because the dc offset of the ADC can be significantly larger control register. The 24-bit SMPR, representing the period over than the signal of interest (affecting the results from the signal which integration is performed, must be programmed before acti- monitor), a dc correction circuit is included as part of the signal vating this mode. monitor block to null the dc offset before measuring the power. After enabling the rms/ms magnitude mode, the value in the SMPR PEAK DETECTOR MODE is loaded into a monitor period timer, and the countdown is started immediately. Each input sample is converted to floating-point The magnitude of the input port signal is monitored over a format and squared. It is then converted to 11-bit, fixed-point programmable time period (determined by the SMPR) to give format and added to the contents of the 24-bit accumulator. the peak value detected. This function is enabled by programming The integration continues until the monitor period timer reaches a Logic 1 in the signal monitor mode bits of the signal monitor a count of 1. control register or by setting the peak detector output enable bit in the signal monitor SPORT control register. The 24-bit SMPR When the monitor period timer reaches a count of 1, the square must be programmed before activating this mode. root of the value in the accumulator is taken and transferred, after some formatting, to the signal monitor holding register, which After enabling this mode, the value in the SMPR is loaded into can be read through the SPI port or output through the SPORT a monitor period timer, and the countdown is started. The magni- serial port. The monitor period timer is reloaded with the value tude of the input signal is compared with the value in the internal in the SMPR, and the countdown is restarted. In addition, the peak level holding register (not accessible to the user), and the first input sample signal power is updated in the accumulator, greater of the two is updated as the current peak level. The initial and the accumulation continues with the subsequent input value of the peak level holding register is set to the current ADC samples. input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. Rev. B | Page 35 of 52 06547-044 AD9640 Figure 69 illustrates the rms magnitude monitoring logic. When the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor FROM MEMORY holding register, which can be read through the SPI port or output MAP SIGNAL MONITOR DOWN through the SPORT serial port. IS COUNT = 1? PERIOD REGISTER COUNTER LOAD The monitor period timer is reloaded with the value in the SMPR TO FROM register, and the countdown is restarted. The internal count CLEAR LOAD MEMORY INPUT SIGNAL MONITOR register is also cleared to a value of 0. Figure 70 illustrates the MAP/SPORT PORTS ACCUMULATOR HOLDING threshold crossing logic. The value in the SMR register is the REGISTER (SMR) number of samples that have a magnitude greater than the Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram threshold register. FROM For rms magnitude mode, the value in the signal monitor result MEMORY (SMR) register is a 20-bit fixed-point number. The following MAP SIGNAL MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER equation can be used to determine the rms magnitude in dBFS LOAD from the MAG value in the register. Note that if the signal monitor FROM TO CLEAR LOAD period (SMP) is a power of 2, the second term in the equation INPUT MEMORY SIGNAL MONITOR A MAP/SPORT PORTS COMPARE COMPARE becomes 0. HOLDING A>B A>B REGISTER (SMR) FROM MAG SMP B ⎛ ⎞ ⎡ ⎤ MEMORY RMS Magnitude = 20 log − 10 log MAP UPPER ⎜ ⎟ 20 ceil[] log (SMP) ⎢ ⎥ 2 2 2 THRESHOLD ⎝ ⎠ ⎣ ⎦ REGISTER For ms magnitude mode, the value in the SMR is a 20-bit fixed- Figure 70. ADC Input Threshold Crossing Block Diagram point number. The following equation can be used to determine ADDITIONAL CONTROL BITS the ms magnitude in dBFS from the MAG value in the register. Note that if the SMP is a power of 2, the second term in the For additional flexibility in the signal monitoring process, two equation becomes 0. control bits are provided in the signal monitor control register. They are the signal monitor enable bit and the complex power MAG SMP ⎛ ⎞ ⎡ ⎤ MS Magnitude = 10 log − 10 log ⎜ ⎟ 20 ceil[] log (SMP) calculation mode enable bit. ⎢ 2 ⎥ 2 2 ⎝ ⎠ ⎣ ⎦ Signal Monitor Enable Bit THRESHOLD CROSSING MODE The signal monitor enable bit, Bit 0 of Register 0x112, enables In the threshold crossing mode of operation, the magnitude of operation of the signal monitor block. If the signal monitor the input port signal is monitored over a programmable time function is not needed in a particular application, this bit should period (given by the SMPR) to count the number of times it be cleared (default) to conserve power. crosses a certain programmable threshold value. This mode is set Complex Power Calculation Mode Enable Bit by programming Logic 1x (where x is a don’t care bit) in the signal monitor mode bits of the signal monitor control register When this bit is set, the part assumes that Channel A is digitizing or by setting the threshold crossing output enable bit in the the I data and Channel B is digitizing the Q data for a complex signal monitor SPORT control register. Before activating this input signal (or vice versa). In this mode, the power reported is mode, the user needs to program the 24-bit SMPR and the equal to the following: 13-bit upper threshold register for each individual input port. 2 2 I + Q The same upper threshold register is used for both signal moni- toring and gain control (see the ADC Overrange and Gain This result is presented in the Signal Monitor DC Value Channel A Control section). register if the signal monitor mode bits are set to 00. The Signal After entering this mode, the value in the SMPR is loaded into Monitor DC Value Channel B register continues to compute the a monitor period timer, and the countdown is started. The magni- Channel B value. tude of the input signal is compared with the upper threshold DC CORRECTION register (programmed previously) on each input clock cycle. Because the dc offset of the ADC may be significantly larger If the input signal has a magnitude greater than the upper than the signal being measured, a dc correction circuit is included threshold register, the internal count register is incremented by 1. to null the dc offset before measuring the power. The dc correction The initial value of the internal count register is set to 0. This circuit can also be switched into the main signal path, but this comparison and incrementing of the internal count register may not be appropriate if the ADC is digitizing a time-varying continues until the monitor period timer reaches a count of 1. signal with significant dc content, such as GSM. Rev. B | Page 36 of 52 06547-092 06547-046 AD9640 DC Correction Bandwidth SIGNAL MONITOR SPORT OUTPUT The dc correction circuit is a high-pass filter with a programmable The SPORT is a serial interface with three output pins: bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and The bandwidth is controlled by writing Bits[5:2] of the signal SMI SDO (SPORT data output). The SPORT is the master and monitor dc correction control register, located at Address 0x10C. drives all three SPORT output pins on the chip. The following equation can be used to compute the bandwidth SMI SCLK value for the dc correction circuit: The data output and frame sync are driven on the positive edge of f −k −14 CLK DC _Corr _ BW = 2 × the SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 2× π 1/4, or 1/8 the ADC clock rate, based on the SPORT controls. The where: SMI SCLK can also be gated off when not sending any data, based k is the 4 bit value programmed in Register 0x10C, Bits[5:2] on the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI (values between 0 and 13 are valid for k; programming 14 or SCLK when it is not needed can reduce any coupling errors back 15 provides the same result as programming 13). into the signal path, if these prove to be a problem in the system. fCLK is the ADC sample rate in hertz (Hz). Doing so, however, has the disadvantage of spreading the frequency content of the clock. If desired, the SMI SCLK can be left running DC Correction Readback to ease frequency planning. The current dc correction value can be read back in Register 0x10D SMI SDFS and Register 0x10E for Channel A and in Register 0x10F and Register 0x110 for Channel B. The dc correction value is a 14-bit The SMI SDFS is the serial data frame sync, and it defines the value that can span the entire input range of the ADC. start of a frame. One SPORT frame includes data from both datapaths. The data from Datapath A is sent just after the frame DC Correction Freeze sync, followed by data from Datapath B. Setting Bit 6 of Register 0x10C freezes the dc correction at its current state and continues to use the last updated value as the SMI SDO dc correction value. Clearing this bit restarts dc correction and The SMI SDO is the serial data output of the block. The data adds the currently calculated value to the data. is sent MSB first on the next positive edge after the SMI SDFS. Each data output block includes one or more rms/ms magnitude, DC Correction Enable Bits peak level, and threshold crossing values from each datapath in Setting Bit 0 of Register 0x10C enables dc correction for use in the stated order. If enabled, the data is sent, rms first, followed by the signal monitor calculations. The calculated dc correction peak and threshold, as shown in Figure 71. value can be added to the output data signal path by setting Bit 1 of Register 0x10C. GATED, BASED ON CONTROL SMI SCLK SMI SDFS RMS/MS CH B LSB SMI SDO MSB RMS/MS CH A LSB PK CH A THR CH A MSB PK CH B THR CH B RMS/MS CH A 20 CYCLES 16 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES 16 CYCLES Figure 71. Signal Monitor SPORT Output Timing (RMS/MS, Peak, and Threshold Enabled) GATED, BASED ON CONTROL SMI SCLK SMI SDFS SMI SDO MSB RMS/MS CH A LSB THR CH A MSB RMS/MS CH B LSB THR CH B RMS/MS CH A 20 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES Figure 72. Signal Monitor SPORT Output Timing (RMS/MS and Threshold Enabled) Rev. B | Page 37 of 52 06547-095 06547-094 AD9640 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9640 includes built-in test features to enable verification The outputs are not disconnected during this test, so the PN of the integrity of each channel as well as to facilitate board level sequence can be observed as it runs. The PN sequence can be debugging. A built-in self-test (BIST) feature is included that continued from its last value or started from the beginning, verifies the integrity of the digital data path of the AD9640. based on the value programmed in Register 0x00E, Bit 2. The Various output test options are also provided to place predictable BIST signature result varies based on the channel configuration. values on the outputs of the AD9640. OUTPUT TEST MODES BUILT-IN SELF-TEST (BIST) The output test options are shown in Table 25. When an output The BIST is a thorough test of the digital portion of the selected test mode is enabled, the analog section of the ADC is discon- AD9640 signal path. When enabled, the test runs from an internal nected from the digital backend blocks and the test pattern is run PN source through the digital data path starting at the ADC through the output formatting block. Some of the test patterns are block output. The BIST sequence runs for 512 cycles and stops. subject to output formatting and some are not. The seed value for The BIST signature value for Channel A or Channel B is placed the PN sequence tests can be forced if the PN reset bits are used in Register 0x024 and Register 0x025. If one channel is chosen, to hold the generator in reset mode by setting Bit 4 or Bit 5 of its BIST signature is written to the two registers. If both channels Register 0x0D. These tests can be performed with or without are chosen, the results from the A channel are placed in the an analog signal (if present, the analog signal is ignored), but BIST signature register. they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. B | Page 38 of 52 AD9640 CHANNEL/CHIP SYNCHRONIZATION The AD9640 has a SYNC input that allows the user flexible The SYNC input is internally synchronized to the sample clock; synchronization options for synchronizing the internal blocks. however, to ensure there is no timing uncertainty between multiple The clock divider sync feature is useful to guarantee synchronized parts, the SYNC input signal should be externally synchronized to sample clocks across multiple ADCs. The signal monitor block the input clock signal, meeting the setup and hold times shown can also be synchronized using the SYNC input allowing properties in Table 8. The SYNC input should be driven using a single- of the input signal to be measured during a specific time period. ended CMOS-type signal. The input clock divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. The signal monitor block is synchronized on every SYNC input signal. Rev. B | Page 39 of 52 AD9640 SERIAL PORT INTERFACE (SPI) The AD9640 serial port interface (SPI) allows the user to In addition to word length, the instruction phase determines if configure the converter for specific functions or operations the serial frame is a read or write operation, allowing the serial through a structured register space provided inside the ADC. port to be used to both program the chip as well as read the This gives the user added flexibility and customization contents of the on-chip memory. If the instruction is a readback depending on the application. Addresses are accessed via the operation, performing a readback causes the serial data input/ serial port and can be written to or read from via the port. output (SDIO) pin to change direction from an input to an output Memory is organized into bytes that can be further divided into at the appropriate point in the serial frame. fields, which are documented in the Memory Map section. For Data can be sent in MSB first mode or LSB first mode. MSB detailed operational information, see the AN-877 Application first is the default on power-up and can be changed via the Note, Interfacing to High Speed ADCs via SPI. configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to CONFIGURATION USING THE SPI High Speed ADCs via SPI. There are three pins that define the SPI of this ADC. They are the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see HARDWARE INTERFACE Table 22). The SCLK/DFS (a serial clock) is used to synchronize The pins described in Table 22 comprise the physical interface the read and write data presented from and to the ADC. The between the user’s programming device and the serial port of SDIO/DCS (serial data input/output) is a dual-purpose pin that the AD9640. The SCLK pin and the CSB pin function as inputs allows data to be sent and read from the internal ADC memory when using the SPI interface. The SDIO pin is bidirectional, map registers. The CSB (chip select bar) is an active-low control functioning as an input during write phases and as an output that enables or disables the read and write cycles. during readback. Table 22. Serial Port Interface Pins The SPI interface is flexible enough to be controlled by either Pin Function FPGAs or microcontrollers. One method for SPI configuration SCLK Serial Clock. The serial shift clock input. SCLK is used to is described in detail in the AN-812 Application Note, synchronize serial interface reads and writes. Microcontroller-Based Serial Port Interface Boot Circuit. SDIO Serial Data Input/Output. A dual-purpose pin. The typical The SPI port should not be active during periods when the full role for this pin is an input and output depending on the dynamic performance of the converter is required. Because the instruction being sent and the relative position in the timing frame. SCLK signal, the CSB signal, and the SDIO signal are typically CSB Chip Select Bar. An active-low control that gates the read asynchronous to the ADC clock, noise from these signals can and write cycles. degrade converter performance. If the on-board SPI bus is utilized The falling edge of the CSB, in conjunction with the rising edge for other devices, it may be necessary to provide buffers between of the SCLK, determines the start of the framing. An example of this bus and the AD9640 to keep these signals from transitioning the serial timing and its definitions can be found in Figure 73 at the converter inputs during critical sampling periods. and Table 8. Some pins serve a dual function when the SPI interface is not Other modes involving the CSB are available. The CSB can be being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific held low indefinitely, which permanently enables the device; this is called streaming. The CSB may stall high between bytes function. The Digital Outputs section describes the strappable to allow for additional external timing. When CSB is tied high, functions supported on the AD9640. SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. Rev. B | Page 40 of 52 AD9640 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, A brief description of general features accessible via the SPI the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, follows. These features are described in detail in the AN-877 and the SMI SCLK/PDWN pin serve as standalone, CMOS- Application Note, Interfacing to High Speed ADCs via SPI. The compatible control pins. When the device is powered up, it is AD9640 part-specific features are described in detail following assumed that the user intends to use the pins as static control Table 25, the external memory map register table. lines for the duty cycle stabilizer, output data format, output Table 24. Features Accessible Using the SPI enable, and power-down feature control. In this mode, the CSB Feature Name Description chip select should be connected to AVDD, which disables the Modes Allows user to set either power-down mode or serial port interface. standby mode. Clock Allows user to access the DCS via the SPI. Table 23. Mode Selection Offset Allows user to digitally adjust the converter External offset. Pin Voltage Configuration Test I/O Allows user to set test modes to have known SDIO/DCS AVDD (default) Duty cycle stabilizer enabled. data on output bits. AGND Duty cycle stabilizer disabled. Output Mode Allows user to set up outputs. SCLK/DFS AVDD Twos complement enabled. Output Phase Allows user to set the output clock polarity. AGND (default) Offset binary enabled. Output Delay Allows user to vary the DCO delay. SMI SDO/OEB AVDD Outputs in high impedance. VREF Allows user to set the reference voltage. AGND (default) Outputs enabled. SMI SCLK/PDWN AVDD Chip in power-down or standby. AGND (default) Normal operation. t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 73. Serial Port Interface Timing Diagram Rev. B | Page 41 of 52 06547-049 AD9640 MEMORY MAP Logic Levels READING THE MEMORY MAP TABLE An explanation of logic level terminology follows: Each row in the memory map table has eight bit locations. The memory map is roughly divided into four sections: chip configura- • “Bit is set” is synonymous with “Bit is set to Logic 1” or tion and ID register map (Address 0x00 to Address 0x02); ADC “Writing Logic 1 for the bit.” setup, control, and test (Address 0x08 to Address 0x25); the • “Clear a bit” is synonymous with “Bit is set to Logic 0” or channel index and transfer register map (Address 0x05 to “Writing Logic 0 for the bit.” Address 0xFF); and digital feature control (Address 0x100 to Transfer Register Map Address 0x11B). Address 0x08 to Address 0x18 are shadowed. Writes to these Starting from the right hand column, the memory map register addresses do not affect part operation until a transfer command in Table 25 documents the default hex value for each hex address is issued by writing 0x01 to Address 0xFF, setting the transfer bit. shown. The column with the heading Bit 7 (MSB) is the start This allows these registers to be updated internally and simulta- of the default hex value given. For example, Address 0x18, VREF neously when the transfer bit is set. The internal update takes select, has a hex default value of 0xC0. This means Bit 7 = 1, place when the transfer bit is set, and the bit autoclears. Bit 6 = 1, and the remaining bits are 0s. This setting is the default Channel-Specific Registers reference selection setting. The default value uses a 2.0 V peak- to-peak reference. For more information on this function and Some channel setup functions, such as the signal monitor others, see the AN-877 Application Note, Interfacing to High Speed thresholds, can be programmed differently for each channel. ADCs via SPI. This document details the functions controlled by In these cases, channel address locations are internally duplicated Register 0x00 to Register 0xFF. The remaining registers, from for each channel. These registers are designated in the parameter Register 0x100 to Register 0x11B, are documented in the Memory name column of Table 25 as local registers. These local registers Map Register Description section. can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write Open Locations affects the registers of both channels. In a read cycle, only All address and bit locations that are not included in Table 25 Channel A or Channel B should be set to read one of the two are currently not supported for this device. Unused bits of a registers. If both bits are set during an SPI read cycle, the part valid address location should be written with 0s. Writing to these returns the value for Channel A. Registers designated as global locations is required only when part of an address location is in the parameter name column of Table 25 affect the entire part open (for example, Address 0x18). If the entire address location or the channel features where independent settings are not is open (for example, Address 0x13), this address location should allowed between the channels. The settings in Register 0x05 not be written. do not affect the global registers. Default Values Coming out of reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 25. Rev. B | Page 42 of 52 AD9640 EXTERNAL MEMORY MAP Table 25. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI Port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles Configuration are mirrored so that (Global) LSB-first mode or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit Chip ID[7:0] 0x11 Read only (AD9640 = 0x11) (Global) Read (default) only 0x02 Chip Grade Open Open Speed grade ID Open Open Open Open Read Speed grade only ID used to (Global) 00 = 150 MSPS differentiate 01 = 125 MSPS devices 10 = 105 MSPS 11 = 80 MSPS Channel Index and Transfer Registers 0x05 Channel Index Open Open Open Open Open Open 0x03 Data Data Bits are set Channel B Channel A to determine which device (default) (default) on the chip receives the next write command; applies to local registers 0xFF Device Update Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Functions 0x08 Power Modes Open Open External Open Open Open Internal power-down 0x00 Determines power- mode (local) various generic down pin modes of chip 00 = normal operation function operation 01 = full power-down (global) 10 = standby 0 = pdwn 11 = normal operation 1 = stndby 0x09 Global Clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (Global) (default) 0x0B Clock Divide Open Open Open Open Open Clock divide ratio 0x00 Clock divide values other (Global) 000 = divide by 1 than 000 001 = divide by 2 automatically 010 = divide by 3 cause the duty 011 = divide by 4 cycle stabilizer 100 = divide by 5 to become 101 = divide by 6 active 110 = divide by 7 111 = divide by 8 0x0D Open Open Open Output test mode 0x00 Test Mode Reset PN Reset When set, (Local) long gen PNshort the test data 000 = off (default) gen is placed on 001 = midscale short the output 010 = positive FS pins in place of 011 = negative FS normal data 100 = alternating checker board 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle Rev. B | Page 43 of 52 AD9640 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST Enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 sequence (Local) 0x10 Offset Adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (twos complement format) (Local) 0x14 Output Mode Drive Output type Open Output Open Output 00 = offset binary 0x00 Configures the strength enable bar invert outputs and 0 = CMOS 01 = twos complement (local) (local) the format of 0 V to 3.3 V 1 = LVDS 01 = gray code the data CMOS or (global) 11 = offset binary ANSI (local) LVDS: 1 V to 1.8 V CMOS or reduced: LVDS (global) 0x16 Clock Phase Invert DCO Open Open Open Open Input clock divider phase adjust 0x00 Allows Control clock selection of 000 = no delay clock delays (Global) 001 = 1 input clock cycle into the input 010 = 2 input clock cycles clock divider 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 0x17 DCO Output Open Open Open DCO clock delay 0x00 Delay (Global) (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps … 11110 = 2419 ps 11111 = 2500 ps 0x18 VREF Select Reference voltage selection Open Open Open Open Open Open 0xC0 (Global) 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) 0x24 BIST Signature BIST signature[7:0] 0x00 Read only LSB (Local) 0x25 BIST Signature BIST signature[15:8] 0x00 Read only MSB (Local) Digital Feature Control 0x100 Sync Control SM sync Open Open Open Open Clock Clock Master 0x00 enable divider next divider sync (Global) sync only sync enable enable 0x104 Fast Detect Open Open Open Open Fast Detect Mode Select[2:0] Fast detect 0x00 Control (Local) enable 0x106 Fine Upper Fine Upper Threshold[7:0] 0x00 Threshold Register 0 (Local) 0x107 Fine Upper Open Open Open Fine Upper Threshold[12:8] 0x00 Threshold Register 1 (Local) 0x108 Fine Lower Fine Lower Threshold[7:0] 0x00 Threshold Register 0 (Local) 0x109 Fine Lower Open Open Open Fine Lower Threshold[12:8] 0x00 Threshold Register 1 (Local) Rev. B | Page 44 of 52 AD9640 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x10C Signal Monitor Open DC DC Correction Bandwidth[3:0] DC DC 0x00 DC Correction correction correction correction Control freeze for signal for SM (Global) path enable enable 0x10D Signal Monitor DC Value Channel A[7:0] Read only DC Value Channel A Register 0 (Global) 0x10E Signal Monitor Open Open DC Value Channel A[13:8] Read only DC Value Channel A Register 1 (Global) 0x10F Signal Monitor DC Value Channel B[7:0] Read only DC Value Channel B Register 0 (Global) 0x110 Open Open DC Value Channel B[13:8] Read only Signal Monitor DC Value Channel B Register 1 (Global) 0x111 Signal Monitor Open RMS/MS Peak Threshold SPORT SMI SPORT Signal 0x04 SPORT Control magnitude power crossing CLK divide SMI SCLK monitor (Global) output output output sleep SPORT 00 = undefined enable enable enable output 01 = divide by 2 enable 10 = divide by 4 11 = divide by 8 0x112 Signal Monitor Complex Open Open Open MS Signal monitor mode Signal 0x00 Control power mode monitor 00 = RMS/MS Magnitude (Global) calculation enable 0 = 01 = peak power mode rms 1x = threshold count enable 1 = ms 0x113 Signal Monitor Signal Monitor Period[7:0] 0x40 In ADC clock Period cycles Register 0 (Global) 0x114 Signal Monitor Signal Monitor Period[15:8] 0x00 In ADC clock Period cycles Register 1 (Global) 0x115 Signal Monitor Signal Monitor Period[23:16] 0x00 In ADC clock Period cycles Register 2 (Global) 0x116 Signal Monitor Signal Monitor Result Channel A[7:0] Read only Result Channel A Register 0 (Global) 0x117 Signal Monitor Signal Monitor Result Channel A[15:8] Read only Result Channel A Register 1 (Global) 0x118 Signal Monitor Open Open Open Open Signal Monitor Value Channel A[19:16] Read only Result Channel A Register 2 (Global) 0x119 Signal Monitor Signal Monitor Result Channel B[7:0] Read only Result Channel B Register 0 (Global) Rev. B | Page 45 of 52 AD9640 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x11A Signal Monitor Signal Monitor Result Channel B[15:8] Read only Result Channel B Register 1 (Global) 0x11B Signal Monitor Open Open Open Open Signal Monitor Result Channel B[19:16] Read only Result Channel B Register 2 (Global) Fine Upper Threshold (Register 0x106 and Register 0x107) MEMORY MAP REGISTER DESCRIPTION Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Register 0x107, Bits[7:5]—Reserved Interfacing to High Speed ADCs via SPI. Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8] Sync Control (Register 0x100) These registers provide the fine upper limit threshold. This 13-bit Bit 7—Signal Monitor Sync Enable value is compared to the 13-bit magnitude from the ADC block and, if the ADC magnitude exceeds this threshold value, the Bit 7 enables the sync pulse from the external SYNC input to F_UT flag is set. the signal monitor block. The sync signal is passed when Bit 7 is high and Bit 0 is high. This is continuous sync mode. Fine Lower Threshold (Register 0x108 and Register 0x109) Bits[6:3]—Reserved Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0] Register 0x109, Bits[7:5]—Reserved Bit 2—Clock Divider Next Sync Only Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8] If the sync enable bit (Address 0x100[0]) is high and the clock These registers provide a fine lower limit threshold. This 13-bit divider sync enable (Address 0x100[1]) is high, Bit 2 allows the value is compared to the 13-bit magnitude from the ADC block clock divider to sync to the first sync pulse it receives and ignore and, if the ADC magnitude is less than this threshold value, the the rest. Address 0x100[1] resets after it syncs. F_LT flag is set. Bit 1—Clock Divider Sync Enable Signal Monitor DC Correction Control (Register 0x10C) Bit 1 gates the sync pulse to the clock divider. The sync signal is Bit 7—Reserved passed when Bit 1 is high and Bit 0 is high. This is continuous Bit 6—DC Correction Freeze sync mode. When Bit 6 is set high, the dc correction is no longer updated Bit 0—Master Sync Enable to the signal monitoring block. It holds the last dc value it Bit 0 must be high to enable any of the sync functions. calculated. Fast Detect Control (Register 0x104) Bits[5:2]—DC Correction Bandwidth Bits[7:4]—Reserved These bits set the averaging time of the signal monitor dc correc- Bits[3:1]—Fast Detect Mode Select tion function. It is a 4-bit word that sets the bandwidth of the These bits set the mode of the fast detect output bits according correction block (see Table 26). to Table 17. Bit 0—Fast Detect Enable Bit 0 is used to enable the fast detect bits. When the fast detect outputs are disabled, the outputs go into a high impedance state. In LVDS mode, when the outputs are interleaved, the outputs go high-Z only if both channels are turned off (power-down/standby/ output disabled). If only one channel is turned off (power-down/ standby/output disabled), the fast detect outputs repeat the data of the active channel. Rev. B | Page 46 of 52 AD9640 Bit 5—Peak Power Output Enable Table 26. DC Correction Bandwidth DC Correction Control Register 0x10C[5:2] Bandwidth (Hz) Bit 5 enables the 13-bit peak measurement as output on the SPORT. 0000 1218.56 0001 609.28 Bit 4—Threshold Crossing Output Enable 0010 304.64 Bit 4 enables the 13-bit threshold measurement as output on 0011 152.32 the SPORT. 0100 76.16 0101 38.08 Bits[3:2]—SPORT SMI SCLK Divide 0110 19.04 The values of these bits set the SPORT SMI SCLK divide ratio 0111 9.52 from the input clock. A value of 0x01 sets divide by 2 (default), 1000 4.76 a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8. 1001 2.38 Bit 1— SPORT SMI SCLK Sleep 1010 1.19 1011 0.60 Setting Bit 1 high causes the SMI SCLK to remain low when the 1100 0.30 signal monitor block has no data to transfer. 1101 0.15 Bit 0—Signal Monitor SPORT Output Enable 1110 0.15 When set, Bit 0 enables the SPORT output of the signal monitor 1111 0.15 to begin shifting out the result data from the signal monitor block. Bit 1—DC Correction for Signal Path Enable Signal Monitor Control (Register 0x112) Setting Bit 1 high causes the output of the dc measurement Bit 7—Complex Power Calculation Mode Enable block to be summed with the data in the signal path to remove This mode assumes I data is present on one channel and Q data the dc offset from the signal path. is present on the opposite channel. The result reported is the Bit 0—DC Correction for SM Enable complex power, measured as Bit 0 enables the dc correction function in the signal monitoring 2 2 I + Q block. The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. Bits[6:4]—Reserved Removing this dc from the measurement allows a more accurate Bit 3—Signal Monitor RMS/MS Select reading. Setting Bit 3 low selects rms power measurement mode. Setting Signal Monitor DC Value Channel A (Register 0x10D and Bit 3 high selects ms power measurement mode. Register 0x10E) Bits[2:1]—Signal Monitor Mode Register 0x10D, Bits[7:0]—Channel A DC Value[7:0] Bit 2 and Bit 1 set the mode of the signal monitor for data output Register 0x10E, Bits[7:0]—Channel A DC Value[13:8] to Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1 to These read-only registers hold the latest dc offset value computed 0x00 selects rms/ms power output; setting these bits to 0x01 by the signal monitor for Channel A. selects peak power output; and setting 0x10 or 0x11 selects Signal Monitor DC Value Channel B (Register 0x10F and threshold crossing output. Register 0x110) Bit 0—Signal Monitor Enable Register 0x10F Bits[7:0]—Channel B DC Value[7:0] Setting Bit 0 high enables the signal monitor block. Register 0x110 Bits[7:0]—Channel B DC Value[13:8] Signal Monitor Period (Register 0x113 to Register 0x115) These read-only registers hold the latest dc offset value computed Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] by the signal monitor for Channel B. Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Signal Monitor SPORT Control (Register 0x111) Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] Bit 7—Reserved This 24-bit value sets the number of clock cycles over which the Bit 6—RMS/MS Magnitude Output Enable signal monitor performs its operation. Although this register These bits enable the 20-bit rms or ms magnitude measurement defaults to 64 (0x40), the minimum value for this register is 128 as output on the SPORT. (0x80) cycles – writing values less than 128 can cause inaccurate results. Rev. B | Page 47 of 52 AD9640 Signal Monitor Result Channel A (Register 0x116 to Signal Monitor Result Channel B (Register 0x119 to Register 0x118) Register 0x11B) Register 0x116, Bits[7:0]—Signal Monitor Result Register 0x119, Bits[7:0]— Signal Monitor Result Channel A[7:0] Channel B[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Register 0x11A, Bits[7:0]—Signal Monitor Result Channel A[15:8] Channel B[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x11B, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Register 0x11B, Bits[3:0]—Signal Monitor Result Channel A[19:16] Channel B[19:16] This 20-bit value contains the result calculated by the signal This 20-bit value contains the result calculated by the signal monitoring block for Channel A. The content is dependent on the monitoring block for Channel B. The content is dependent on settings in Register 0x112[2:1]. the settings in Register 0x112[2:1]. Rev. B | Page 48 of 52 AD9640 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow Before starting design and layout of the AD9640 as a system, through the bottom of the PCB. These vias should be filled or it is recommended that the designer become familiar with these plugged with nonconductive epoxy. guidelines, which discuss the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements needed for certain pins. PCB, a silkscreen should be overlaid to partition the continuous Power and Ground Recommendations plane on the PCB into several uniform sections. This provides When connecting power to the AD9640, it is recommended several tie points between the two during the reflow process. that two separate 1.8 V supplies be used: one supply should be Using one continuous plane with no partitions guarantees only used for analog (AVDD) and digital (DVDD), and a separate one tie point between the ADC and PCB. See the evaluation supply should be used for the digital outputs (DRVDD). The board for a PCB layout example. For detailed information about AVDD and DVDD supplies, while derived from the same packaging and PCB layout of chip scale packages, see the AN-772 source, should be isolated with a ferrite bead or filter choke Application Note, A Design and Manufacturing Guide for the and separate decoupling capacitors. The user can employ Lead Frame Chip Scale Package (LFCSP). several different decoupling capacitors to cover both high CML and low frequencies. These should be located close to the The CML pin should be decoupled to ground with a 0.1 μF point of entry at the PC board level and close to the part’s capacitor, as shown in Figure 47. pins with minimal trace length. RBIAS A single PCB ground plane should be sufficient when using the The AD9640 requires that a 10 kΩ resistor be placed between AD9640. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance the RBIAS pin and ground. This resistor sets the master current is easily achieved. reference of the ADC core and should have at least a 1% tolerance. LVDS Operation Reference Decoupling The AD9640 defaults to CMOS output mode on power-up. The VREF pin should be externally decoupled to ground with a low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic, low If LVDS operation is desired, this mode must be programmed ESR capacitor. using the SPI configuration registers after power-up. When the AD9640 powers up in CMOS mode with LVDS termination SPI Port resistors (100 Ω) on the outputs, the DRVDD current may be The SPI port should not be active during periods when the full higher than the typical value until the part is placed in LVDS dynamic performance of the converter is required. Because the mode. This additional DRVDD current does not cause damage SCLK, CSB, and SDIO signals are typically asynchronous to the to the AD9640, but it should be taken into account when consid- ADC clock, noise from these signals can degrade converter ering the maximum DRVDD current for the part. performance. If the on-board SPI bus is used for other devices, To avoid this additional DRVDD current, the AD9640 outputs it may be necessary to provide buffers between this bus and the can be disabled at power-up by taking the OEB pin high. After AD9640 to keep these signals from transitioning at the converter the part is placed into LVDS mode via the SPI port, the OEB inputs during critical sampling periods. pin can be taken low to enable the outputs. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask), copper plane on the PCB should mate to the AD9640 exposed paddle, Pin 0. Rev. B | Page 49 of 52 AD9640 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 7.25 8.75 BSC TOP VIEW EXPOSED PAD 7.10 SQ BSC SQ (BOTTOM VIEW) 6.95 0.50 16 33 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 74. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters 9.00 0.60 MAX BSC SQ 0.60 PIN 1 MAX INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 7.65 8.75 TOP VIEW BSC EXPOSED PAD 7.50 SQ BSC SQ (BOTTOM VIEW) 7.35 0.50 16 33 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 75. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters Rev. B | Page 50 of 52 041509-A 080108-C AD9640 ORDERING GUIDE Model Temperature Range Package Description Package Option 1, 2 AD9640ABCPZ-150 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1, 2 AD9640ABCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1, 2 AD9640ABCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1, 2 AD9640ABCPZ-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1, 2 AD9640ABCPZRL7-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9640BCPZ-150 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 1 AD9640BCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 1 AD9640BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 1 AD9640BCPZ-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 1 AD9640-150EBZ Evaluation Board 1 AD9640-125EBZ Evaluation Board 1 AD9640-105EBZ Evaluation Board 1 AD9640-80EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 Recommended for use in new designs; reference PCN 09_0156. Rev. B | Page 51 of 52 AD9640 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06547-0-12/09(B) Rev. B | Page 52 of 52