ANALOG DEVICES AD9637

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9637 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD Low power: 60 mW per channel at 80 MSPS with scalable power options AD9637 12 D+ A VIN+ A SERIAL ADC D– A SNR = 71.5 dBFS (to Nyquist) VIN– A LVDS SFDR = 92 dBc (to Nyquist) 12 D+ B VIN+ B SERIAL DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) ADC D– B LVDS VIN– B Serial LVDS (ANSI-644, default) 12 D+ C VIN+ C Low power, reduced signal option (similar to IEEE 1596.3) SERIAL ADC D– C LVDS VIN– C Data and frame clock outputs 12 D+ D 650 MHz full power analog bandwidth VIN+ D SERIAL ADC D– D LVDS VIN– D 2 V p-p differential input voltage range 12 D+ E 1.8 V supply operation VIN+ E SERIAL ADC D– E LVDS VIN– E Serial port control Full chip and individual channel power-down modes 12 D+ F VIN+ F SERIAL ADC D– F Flexible bit orientation LVDS VIN– F Built-in and custom digital test pattern generation 12 D+ G VIN+ G SERIAL ADC D– G Programmable clock and data alignment LVDS VIN– G Programmable output resolution 12 D+ H VIN+ H SERIAL Standby mode ADC D– H LVDS VIN– H APPLICATIONS VREF SENSE FCO+ 1.0V Medical imaging and nondestructive ultrasound DATA FCO– VCM REF SERIAL PORT RATE Portable ultrasound and digital beam-forming systems DCO+ MULTIPLIER SELECT INTERFACE DCO– Quadrature radio receivers SYNC Diversity radio receivers RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK– Optical networking DFS DTP Test equipment Figure 1. GENERAL DESCRIPTION clock and data alignment and programmable digital test pattern The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital generation. The available digital test patterns include built-in converter (ADC) with an on-chip sample-and-hold circuit deterministic and pseudorandom patterns, along with custom user- designed for low cost, low power, small size, and ease of use. defined test patterns entered via the serial port interface (SPI). The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance PRODUCT HIGHLIGHTS operation. No external reference or driver components are 1. Small Footprint. Eight ADCs are contained in a small, required for many applications. space-saving package. The ADC automatically multiplies the sample rate clock for the 2. Low Power of 60 mW/Channel at 80 MSPS with Scalable appropriate LVDS serial data rate. A data clock output (DCO) for Power Options. capturing data on the output and a frame clock output (FCO) for 3. Ease of Use. A data clock output (DCO) is provided that signaling a new output byte are provided. Individual channel operates at frequencies of up to 480 MHz and supports power-down is supported and typically consumes less than 2 mW double data rate (DDR) operation. when all channels are disabled. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. The ADC contains several features designed to maximize 5. Pin Compatible with the AD9257 (14-Bit Octal ADC). flexibility and minimize system cost, such as programmable Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 10215-001 AD9637 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Clock Input Considerations...................................................... 20  Applications....................................................................................... 1  Power Dissipation and Power-Down Mode ........................... 22  General Description ......................................................................... 1  Digital Outputs and Timing ..................................................... 23  Functional Block Diagram .............................................................. 1  Built-In Output Test Modes .......................................................... 27  Product Highlights ........................................................................... 1  Output Test Modes..................................................................... 27  Table of Contents.............................................................................. 2  Serial Port Interface (SPI).............................................................. 28  Revision History ............................................................................... 2  Configuration Using the SPI..................................................... 28  Specifications..................................................................................... 3  Hardware Interface..................................................................... 29  DC Specifications ......................................................................... 3  Configuration Without the SPI ................................................ 29  AC Specifications.......................................................................... 4  SPI Accessible Features.............................................................. 29  Digital Specifications ................................................................... 5  Memory Map .................................................................................. 30  Switching Specifications .............................................................. 6  Reading the Memory Map Register Table............................... 30  Timing Specifications .................................................................. 6  Memory Map Register Table..................................................... 31  Absolute Maximum Ratings............................................................ 8  Memory Map Register Descriptions........................................ 34  Thermal Characteristics .............................................................. 8  Applications Information .............................................................. 36  ESD Caution.................................................................................. 8  Design Guidelines ...................................................................... 36  Pin Configuration and Function Descriptions............................. 9  Power and Ground Recommendations ................................... 36  Typical Performance Characteristics ........................................... 11  Exposed Pad Thermal Heat Slug Recommendations............ 36  AD9637-80 .................................................................................. 11  VCM............................................................................................. 36  AD9637-40 .................................................................................. 14  Reference Decoupling................................................................ 36  Equivalent Circuits ......................................................................... 17  SPI Port........................................................................................ 36  Theory of Operation ...................................................................... 18  Outline Dimensions....................................................................... 37  Analog Input Considerations.................................................... 18  Ordering Guide .......................................................................... 37  Voltage Reference ....................................................................... 19  REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 40 Data Sheet AD9637 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. AD9637-40 AD9637-80 1 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.6 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full 0.0 0.2 0.6 0.0 0.2 0.6 % FSR Gain Error Full −8.0 −2.1 +2.0 −7.0 −3.2 +1.0 % FSR Gain Matching Full −1.0 +1.7 +5.0 −1.0 +2.3 +6.0 % FSR Differential Nonlinearity (DNL) Full −0.8 ±0.3 +0.8 −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL) Full −1.0 ±0.4 +1.0 −1.2 ±0.5 +1.2 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 0.99 1.01 0.98 0.99 1.01 V Load Regulation at 1.0 mA (VREF = 1 V) Full 2 2 mV Input Resistance Full 7.5 7.5 kΩ INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.36 0.49 LSB rms ANALOG INPUTS Differential Input Voltage (V = 1 V) Full 2 2 V p-p REF Common-Mode Voltage Full 0.9 0.9 V Differential Input Resistance 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V I (Eight Channels) Full 142 151 221 234 mA AVDD I (Eight Channels, ANSI-644 Mode) Full 51 79 58 85 mA DRVDD IDRVDD (Eight Channels, Reduced Range Mode) 25°C 36 43 mA TOTAL POWER CONSUMPTION Total Power Dissipation (Eight Channels, ANSI-644 Mode) Full 347 414 502 574 mW Total Power Dissipation (Eight Channels, Reduced Range Mode) 25°C 320 475 mW Power-Down Dissipation 25°C 1 1 mW 2 Standby Dissipation 25°C 72 98 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. Rev. 0 | Page 3 of 40 AD9637 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. AD9637-40 AD9637-80 1 Parameter Temp Unit Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 72.0 71.5 dBFS IN fIN = 19.7 MHz Full 70.0 72.0 71.0 71.5 dBFS fIN = 30.5 MHz 25°C 72.0 71.5 dBFS fIN = 63.5 MHz 25°C 71.5 dBFS f = 69.5 MHz 25°C 71.5 dBFS IN f = 123.5 MHz 25°C 70.5 dBFS IN SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f = 9.7 MHz 25°C 71.0 70.5 dBFS IN f = 19.7 MHz Full 69.0 71.0 70.0 70.5 dBFS IN fIN = 30.5 MHz 25°C 71.0 70.5 dBFS fIN = 63.5 MHz 25°C 70.5 dBFS fIN = 69.5 MHz 25°C 70.5 dBFS f = 123.5 MHz 25°C 69.5 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.5 11.4 Bits f = 19.7 MHz Full 11.2 11.5 11.3 11.4 Bits IN f = 30.5 MHz 25°C 11.5 11.4 Bits IN fIN = 63.5 MHz 25°C 11.4 Bits fIN = 69.5 MHz 25°C 11.4 Bits fIN = 123.5 MHz 25°C 11.3 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 96 93 dBc fIN = 19.7 MHz Full 78 95 78 92 dBc f = 30.5 MHz 25°C 96 92 dBc IN f = 63.5 MHz 25°C 93 dBc IN f = 69.5 MHz 25°C 89 dBc IN fIN = 123.5 MHz 25°C 88 dBc WORST HARMONIC (SECOND OR THIRD) f = 9.7 MHz 25°C −99 −96 dBc IN fIN = 19.7 MHz Full −96 −78 −92 −78 dBc fIN = 30.5 MHz 25°C −98 −92 dBc fIN = 63.5 MHz 25°C −95 dBc f = 69.5 MHz 25°C −89 dBc IN f = 123.5 MHz 25°C −89 dBc IN WORST OTHER (EXCLUDING SECOND OR THIRD) f = 9.7 MHz 25°C −98 −97 dBFS IN f = 19.7 MHz Full −98 −86 −97 −86 dBFS IN fIN = 30.5 MHz 25°C −98 −97 dBFS fIN = 63.5 MHz 25°C −97 dBFS fIN = 69.5 MHz 25°C −97 dBFS f = 123.5 MHz 25°C −92 dBFS IN TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS f = 8 MHz, f = 10 MHz 25°C 93 dBc IN1 IN2 f = 30 MHz, f = 32 MHz 25°C 85 dBc IN1 IN2 Rev. 0 | Page 4 of 40 Data Sheet AD9637 AD9637-40 AD9637-80 CROSSTALK 25°C −98 −96 dB 2 Crosstalk (Overrange Condition) 25°C −89 −89 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Overrange condition is specified with 3 dB of the full-scale input range. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. 1 Parameter Temp Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF 3 LOGIC OUTPUT (SDIO) Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (I = 50 μA) Full 0.05 V OL DIGITAL OUTPUTS (D± x), ANSI-644 Logic Compliance LVDS Differential Output Voltage (V) Full 247 350 454 mV OD Output Offset Voltage (V) Full 1.13 1.21 1.38 V OS Output Coding (Default) Twos complement DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 200 250 mV Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V Output Coding (Default) Twos complement 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO/DFS pins sharing the same connection. Rev. 0 | Page 5 of 40 AD9637 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. 1 , 2 Parameter Temp Min Typ Max Unit 3 CLOCK Input Clock Rate Full 10 640 MHz Conversion Rate Full 10 40/80 MSPS Clock Pulse Width High (tEH) Full 12.5/6.25 ns Clock Pulse Width Low (t) Full 12.5/6.25 ns EL 3 OUTPUT PARAMETERS Propagation Delay (t ) Full 2.3 ns PD Rise Time (t ) (20% to 80%) Full 300 ps R Fall Time (t ) (20% to 80%) Full 300 ps F FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns 4 DCO Propagation Delay (tCPD) Full tFCO + (tSAMPLE/24) ns 4 DCO to Data Delay (tDATA) Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps 4 DCO to FCO Delay (t ) Full (t /24) − 300 (t/24) (t /24) + 300 ps FRAME SAMPLE SAMPLE SAMPLE Data to Data Skew Full ±50 ±200 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 35 μs 5 Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (t ) 25°C 1 ns A Aperture Uncertainty (Jitter) 25°C 0.1 ps rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. tSAMPLE = 1/fS. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS See Figure 61 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S t Hold time between CSB and SCLK 2 ns min H tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to 10 ns min the SCLK falling edge (not shown in Figure 61) t Time required for the SDIO pin to switch from an output to an input relative to 10 ns min DIS_SDIO the SCLK rising edge (not shown in Figure 61) Rev. 0 | Page 6 of 40 Data Sheet AD9637 Timing Diagrams N – 1 t A VIN± x N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D– x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 D+ x Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default) N – 1 VIN± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D– x MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 D+ x Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode CLK+ t t SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev. 0 | Page 7 of 40 10215-004 05967-002 10215-003 AD9637 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the printed Electrical circuit board (PCB) increases the reliability of the solder joints AVDD to AGND −0.3 V to +2.0 V and maximizes the thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V Table 7. Thermal Resistance Digital Outputs −0.3 V to +2.0 V (D± x, DCO+, DCO−, FCO+, FCO−) to Airflow AGND Package Velocity 1, 2 1, 3 1, 4 1, 2 Type (m/sec) θJA θJC θJB JT Unit CLK+, CLK− to AGND −0.3 V to +2.0 V 64-Lead 0 22.3 1.4 N/A 0.1 °C/W VIN+ x, VIN− x to AGND −0.3 V to +2.0 V LFCSP 1.0 19.5 N/A 11.8 0.2 °C/W SCLK/DTP, SDIO/DFS, CSB to AGND −0.3 V to +2.0 V 9 mm × 9 mm 2.5 17.5 N/A 0.2 °C/W SYNC, PDWN to AGND −0.3 V to +2.0 V (CP-64-4) N/A RBIAS to AGND −0.3 V to +2.0 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 VREF, SENSE to AGND −0.3 V to +2.0 V Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. Environmental 4 Per JEDEC JESD51-8 (still air). Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Typical θJA is specified for a 4-layer PCB with a solid ground Lead Temperature (Soldering, 10 sec) 300°C plane. As shown Table 7, airflow improves heat dissipation, Storage Temperature Range (Ambient) −65°C to +150°C which reduces θ . In addition, metal in direct contact with the JA package leads from metal traces, through holes, ground, and Stresses above those listed under Absolute Maximum Ratings power planes reduces θ . JA may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational ESD CAUTION section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 40 Data Sheet AD9637 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AVDD 1 48 AVDD VIN+ G 2 47 VIN+ B VIN– G 3 46 VIN– B AVDD 4 45 AVDD VIN– H 5 44 VIN– A VIN+ H 6 43 VIN+ A AVDD 7 42 AVDD AD9637 AVDD 8 41 PDWN TOP VIEW CLK– 9 40 CSB (Not to Scale) CLK+ 10 39 SDIO/DFS AVDD 11 38 SCLK/DTP 37 AVDD 12 AVDD DNC 13 36 DNC DRVDD 14 35 DRVDD 34 D– H 15 D+ A D+ H 16 33 D– A NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND. Figure 5. Pin Configuration, Top View Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0, EP AGND, Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the Exposed Pad analog ground for the part. This exposed pad must be connected to analog ground for proper operation. AVDD 1.8 V Analog Supply. 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 13, 36 DNC Do Not Connect. Do not connect to this pin. 14, 35 DRVDD 1.8 V Digital Output Driver Supply. 2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement. 5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True. 9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True. 15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True. 17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True. 19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True. 21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True. 23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True. 25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True. 27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True. 29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True. 31, 32 D− B, D+ B ADC B Digital Output Complement, ADC B Digital Output True. 33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True. 38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP). 39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS). 40 CSB Chip Select Bar. 41 PDWN Power-Down. 43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement. 46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True. 49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement. Rev. 0 | Page 9 of 40 D– G 17 64 VIN+ F D+ G 18 63 VIN– F D– F 19 62 AVDD D+ F 20 61 VIN– E D– E 21 60 VIN+ E D+ E 22 59 AVDD DCO– 23 58 SYNC DCO+ 24 57 VCM FCO– 25 56 VREF FCO+ 26 55 SENSE D– D 27 54 RBIAS D+ D 28 53 VIN+ D D– C 29 52 VIN– D D+ C 30 51 AVDD D– B 31 50 VIN– C D+ B 32 49 VIN+ C 10215-005 AD9637 Data Sheet Pin No. Mnemonic Description 52, 53 VIN− D, VIN+ D ADC D Analog Input Complement, ADC D Analog Input True. 54 RBIAS Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 55 SENSE Reference Mode Selection. 56 VREF Voltage Reference Input/Output. 57 VCM Analog Output Voltage at Midsupply. Sets common mode of the analog inputs. 58 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 60, 61 VIN+ E, VIN− E ADC E Analog Input True, ADC E Analog Input Complement. 63, 64 VIN− F, VIN+ F ADC F Analog Input Complement, ADC F Analog Input True. Rev. 0 | Page 10 of 40 Data Sheet AD9637 TYPICAL PERFORMANCE CHARACTERISTICS AD9637-80 0 0 80MSPS 80MSPS 9.7MHz AT –1dBFS 19.7MHz AT –1dBFS –15 –15 SNR = 70.8dB (71.8dBFS) SNR = 70.7dB (71.7dBFS) SFDR = 92.7dBc SFDR = 90.1dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 80 MSPS Figure 9. Single-Tone 16k FFT with fIN = 19.7 MHz, fSAMPLE = 80 MSPS 0 0 80MSPS 80MSPS –15 63.5MHz AT –1dBFS –15 30.5MHz AT –1dBFS SNR = 70.5dB (71.5dBFS) SNR = 70.7dB (71.7dBFS) SFDR = 93.2dBc SFDR = 90.7dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Single-Tone 16k FFT with f = 30.5 MHz, f = 80 MSPS Figure 7. Single-Tone 16k FFT with fIN = 63.5 MHz, fSAMPLE = 80 MSPS IN SAMPLE 0 0 80MSPS –15 –15 123.5MHz AT –1dBFS SNR = 69.6dB (70.6dBFS) SFDR = 90.3dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 F1 + F2 + F2–F1 2F1 + F2 2F2 – F1 2F1 – F2 2F2 + F1 –105 –105 –120 –120 –135 –135 4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Two-Tone 16k FFT with fIN1 = 30 MHz and fIN2 = 32 MHz, Figure 11. Single-Tone 16k FFT with fIN = 123.5 MHz, fSAMPLE = 80 MSPS fSAMPLE = 80 MSPS Rev. 0 | Page 11 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10215-008 10215-007 10215-006 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10215-109 10215-010 10215-009 AD9637 Data Sheet 0 105 100 SFDR (dBc) –20 SFDR (dBc) 95 –40 IMD3 (dBc) 90 –60 85 –80 SFDR (dBFS) 80 –100 75 SNR (dBFS) IMD3 (dBFS) –120 70 –90 –78 –66 –54 –42 –30 –18 –6 –40 –15 10 35 60 85 INPUT AMPLITUDE (dBFS) TEMPERATURE (°C) Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 15. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 80 MSPS fIN1 = 30 MHz and fIN2 = 32 MHz, fSAMPLE = 80 MSPS 120 110 100 SFDR (dBc) 100 90 SFDRFS 80 SNR (dBFS) 80 SNRFS 70 60 60 50 SFDR 40 40 SNR 30 20 20 10 0 0 –70 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 13. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 80 MSPS Figure 16. SNR/SFDR vs. fIN, fSAMPLE = 80 MSPS 105 105 100 SFDR 100 SFDR 95 95 90 90 85 85 80 80 75 SNRFS 75 70 SNRFS 70 65 20 30 40 50 60 70 80 20 30 40 50 60 70 80 SAMPLE FREQUENCY (MSPS) SAMPLE FREQUENCY (MSPS) Figure 14. SNR/SFDR vs. Encode, f = 19.7 MHz Figure 17. SNR/SFDR vs. Encode, f = 30.5 MHz IN IN Rev. 0 | Page 12 of 40 SFDR/IMD3 (dBc/dBFS) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10215-013 10215-012 10215-011 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10215-016 10215-015 10215-014 Data Sheet AD9637 700,000 1.0 0.491 LSB RMS 0.8 600,000 0.6 500,000 0.4 0.2 400,000 0 300,000 –0.2 –0.4 200,000 –0.6 100,000 –0.8 0 –1.0 OUTPUT CODE OUTPUT CODE Figure 18. Input Referred Noise Histogram, f = 80 MSPS Figure 20. DNL, f = 9.7 MHz, f = 80 MSPS SAMPLE IN SAMPLE 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 OUTPUT CODE Figure 19. INL, f = 9.7 MHz, f = 80 MSPS IN SAMPLE Rev. 0 | Page 13 of 40 NUMBER OF HITS INL (LSB) 0 N – 10 N – 9 400 N – 8 N – 7 800 N – 6 N – 5 1200 N – 4 N – 3 1600 N – 2 N – 1 2000 N N + 1 2400 N + 2 N + 3 2800 N + 4 N + 5 3200 N + 6 N + 7 3600 N + 8 N + 9 4000 N + 10 10215-018 10215-017 DNL (LSB) 0 500 1000 1500 2000 2500 3000 3500 4000 10215-019 AD9637 Data Sheet AD9637-40 0 0 40MSPS 40MSPS –15 –15 19.7MHz AT –1dBFS 9.7MHz AT –1dBFS SNR = 70.9dB (71.9dBFS) SNR = 71.0dB (72.0dBFS) SFDR = 91.0dBc SFDR = 96.9dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18 FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. Single-Tone 16k FFT with f = 9.7 MHz, f = 40 MSPS IN SAMPLE Figure 24. Single-Tone 16k FFT with fIN = 19.7 MHz, fSAMPLE = 40 MSPS 0 0 40MSPS 40MSPS –15 30.5MHz AT –1dBFS –15 69.5MHz AT –1dBFS SNR = 70.9dB (7.19dBFS) SNR = 70.5dB (71.5dBFS) SFDR = 95.87dBc –30 –30 SFDR = 88.6dBc –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 40 MSPS Figure 25. Single-Tone 16k FFT with fIN = 69.5 MHz, fSAMPLE = 40 MSPS 0 0 –15 –20 SFDR (dBc) –30 –40 –45 IMD3 (dBc) –60 –60 –75 –90 –80 2F1 + F2 SFDR (dBFS) + 2F2 – F1 F2 – F1 2F2 + F1 F1 + F2 2F1 – F2 –105 –100 –120 IMD3 (dBFS) –135 –120 2 4 6 8 10 12 14 16 18 –90 –78 –66 –54 –42 –30 –18 –6 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 23. Two-Tone 16k FFT with fIN1 = 8 MHz and fIN2 = 10 MHz, Figure 26. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fSAMPLE = 40 MSPS f = 30 MHz and f = 32 MHz, f = 40 MSPS IN1 IN2 SAMPLE Rev. 0 | Page 14 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10215-022 10215-020 10215-021 SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10215-024 10215-023 10215-025 Data Sheet AD9637 110 120 100 SFDR (dBc) 100 90 SFDRFS 80 SNR (dBFS) 80 SNRFS 70 60 60 50 SFDR 40 40 SNR 30 20 20 10 0 0 –70 –60 –50 –40 –30 –20 –10 0 0 20 40 60 80 100 120 140 160 180 200 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 27. SNR/SFDR vs. Analog Input Level, f = 9.7 MHz, f = 40 MSPS Figure 30. SNR/SFDR vs. f , f = 40 MSPS IN SAMPLE IN SAMPLE 105 105 100 100 SFDR SFDR 95 95 90 90 85 85 80 80 75 75 SNRFS SNRFS 70 70 65 65 20 25 30 35 40 20 25 30 35 40 SAMPLE FREQUENCY (MSPS) SAMPLE FREQUENCY (MSPS) Figure 28. SNR/SFDR vs. Encode, f = 19.7 MHz Figure 31. SNR/SFDR vs. Encode, fIN = 30.5 MHz IN 105 1,000,000 0.356 LSB RMS 900,000 SFDR (dBc) 100 800,000 95 700,000 600,000 90 500,000 85 400,000 300,000 80 200,000 75 SNR (dBFS) 100,000 70 0 –40 –15 103560 85 TEMPERATURE (°C) OUTPUT CODE Figure 29. SNR/SFDR vs. Temperature, f = 9.7 MHz, f = 40 MSPS Figure 32. Input-Referred Noise Histogram, fSAMPLE = 40 MSPS IN SAMPLE Rev. 0 | Page 15 of 40 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10215-027 10215-026 10215-028 NUMBER OF HITS SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 10215-030 10215-029 10215-031 AD9637 Data Sheet 2.0 1.0 1.6 0.8 1.2 0.6 0.8 0.4 0.4 0.2 0 0 –0.4 –0.2 –0.8 –0.4 –1.2 –0.6 –1.6 –0.8 –2.0 –1.0 OUTPUT CODE OUTPUT CODE Figure 33. INL, fIN = 9.7 MHz, fSAMPLE = 40 MSPS Figure 34. DNL, f = 9.7 MHz, f = 40 MSPS IN SAMPLE Rev. 0 | Page 16 of 40 INL (LSB) 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 10215-032 DNL (LSB) 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 10215-033 Data Sheet AD9637 EQUIVALENT CIRCUITS AVDD AVDD 350Ω SCLK/DTP, SYNC, VIN± x AND PDWN 30kΩ Figure 39. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit Figure 35. Equivalent Analog Input Circuit AVDD 5Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 375Ω RBIAS AND VCM 5Ω CLK– Figure 36. Equivalent Clock Input Circuit Figure 40. Equivalent RBIAS, VCM Circuit AVDD AVDD 30kΩ 350Ω SDIO/DFS 30kΩ 350Ω 30kΩ CSB Figure 37. Equivalent SDIO/DFS Input Circuit Figure 41. Equivalent CSB Input Circuit DRVDD AVDD V V D– x D+ x V V 375Ω VREF 7.5kΩ DRGND Figure 38. Equivalent Digital Output Circuit Figure 42. Equivalent VREF Circuit Rev. 0 | Page 17 of 40 10215-037 10215-034 10215-035 10215-036 10215-040 10215-039 10215-041 10215-038 AD9637 Data Sheet THEORY OF OPERATION input can help reduce the peak transient current injected from The AD9637 is a multistage, pipelined ADC. Each stage the output stage of the driving source. In addition, low Q inductors provides sufficient overlap to correct for flash errors in the or ferrite beads can be placed on each leg of the input to reduce preceding stage. The quantized outputs from each stage are high differential capacitance at the analog inputs and, therefore, combined into a final 12-bit result in the digital correction achieve the maximum bandwidth of the ADC. Such use of low logic. The serializer transmits this converted data in a 12-bit Q inductors or ferrite beads is required when driving the converter output. The pipelined architecture permits the first stage to front end at high IF frequencies. Either a differential capacitor or operate with a new input sample, while the remaining stages two single-ended capacitors can be placed on the inputs to provide operate with preceding samples. Sampling occurs on the rising a matching passive network. This ultimately creates a low-pass edge of the clock. filter at the input to limit unwanted broadband noise. See the Each stage of the pipeline, excluding the last, consists of a low AN-742 Application Note, the AN-827 Application Note, and the resolution flash ADC connected to a switched-capacitor DAC Analog Dialogue article “Transformer-Coupled Front-End for and an interstage residue amplifier (for example, a multiplying Wideband A/D Converters” (Volume 39, April 2005) for more digital-to-analog converter (MDAC)). The residue amplifier information. In general, the precise values depend on the magnifies the difference between the reconstructed DAC output application. and the flash input for the next stage in the pipeline. One bit of Input Common Mode redundancy is used in each stage to facilitate digital correction The analog inputs of the AD9637 are not internally dc-biased. of flash errors. The last stage simply consists of a flash ADC. Therefore, in ac-coupled applications, the user must provide The output staging block aligns the data, corrects errors, and this bias externally. Setting the device so that V = AVDD/2 is CM passes the data to the output buffers. The data is then serialized recommended for optimum performance, but the device can and aligned to the frame and data clocks. function over a wider range with reasonable performance, as ANALOG INPUT CONSIDERATIONS shown in Figure 44. 100 The analog input to the AD9637 is a differential, switched SFDR capacitor circuit designed for processing differential input 90 signals. This circuit can support a wide common-mode range 80 while maintaining excellent performance. By using an input SNRFS common-mode voltage of midsupply, users can minimize 70 signal-dependent errors and achieve optimum performance. 60 50 H 40 C PAR H VIN+ x 30 C SAMPLE SS 20 0.5 0.7 0.9 1.1 1.3 SS C V (V) CM SAMPLE VIN– x H Figure 44. SNR/SFDR vs. Common-Mode Voltage, C PAR fIN = 9.7 MHz, fSAMPLE = 80 MSPS H An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin Figure 43. Switched-Capacitor Input Circuit must be decoupled to ground by a 0.1 μF capacitor, as described The clock signal alternately switches the input circuit between in the Applications Information section. sample mode and hold mode (see Figure 43). When the input Maximum SNR performance is achieved by setting the ADC to circuit is switched to sample mode, the signal source must be the largest span in a differential configuration. In the case of the capable of charging the sample capacitors and settling within AD9637, the largest input span available is 2 V p-p. one-half of a clock cycle. A small resistor in series with each Rev. 0 | Page 18 of 40 10215-042 SNR/SFDR (dBFS/dBc) 10215-043 Data Sheet AD9637 Differential Input Configurations Internal Reference Connection There are several ways to drive the AD9637 either actively or A comparator within the AD9637 detects the potential at the passively. However, optimum performance is achieved by driving SENSE pin and configures the reference into two possible modes, the analog input differentially. Using a differential double balun which are summarized in Table 9. If SENSE is grounded, the configuration to drive the AD9637 provides excellent performance reference amplifier switch is connected to the internal resistor and a flexible interface to the ADC (see Figure 46) for baseband divider (see Figure 45), setting VREF to 1.0 V. applications. Table 9. Reference Configuration Summary For applications where SNR is a key parameter, differential trans- Resulting former coupling is the recommended input configuration (see SENSE Resulting Differential Selected Mode Voltage (V) VREF (V) Span (V p-p) Figure 47), because the noise performance of most amplifiers is Fixed Internal AGND to 0.2 1.0 internal 2.0 not adequate to achieve the true performance of the AD9637. Reference Regardless of the configuration, the value of the shunt capacitor, Fixed External AVDD 1.0 applied 2.0 C, is dependent on the input frequency and may need to be Reference to external reduced or removed. VREF pin It is not recommended to drive the AD9637 input single-ended. VIN+ x VOLTAGE REFERENCE VIN– x A stable and accurate 1.0 V voltage reference is built into the AD9637. VREF can be configured using either the internal 1.0 V ADC reference or an externally applied 1.0 V reference voltage. The CORE various reference modes are summarized in the sections that follow. The VREF pin should be externally decoupled to ground VREF with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 1.0µF 0.1µF SELECT 0.1 μF ceramic capacitor. LOGIC SENSE 0.5V ADC Figure 45. Internal Reference Configuration 0.1µF 0.1µF R *C1 VIN+ x 33Ω 33Ω C 2V p-p C 5pF ADC 33Ω 0.1µF R VCM VIN– x 33Ω ET1-1-I3 *C1 C R 200Ω 0.1µF C 0.1µF *C1 IS OPTIONAL Figure 46. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO *C1 R VIN+ x 33Ω 2Vp-p 49.9Ω ADC C 5pF R VIN– x VCM 33Ω *C1 200Ω 0.1µF 0.1μF *C1 IS OPTIONAL Figure 47. Differential Transformer-Coupled Configuration for Baseband Applications Rev. 0 | Page 19 of 40 10215-046 10215-045 10215-044 AD9637 Data Sheet If the internal reference of the AD9637 is used to drive multiple CLOCK INPUT CONSIDERATIONS converters to improve gain matching, the loading of the reference For optimum performance, clock the AD9637 sample clock inputs, by the other converters must be considered. Figure 48 shows CLK+ and CLK−, with a differential signal. The signal is typically how the internal reference voltage is affected by loading. ac-coupled into the CLK+ and CLK− pins via a transformer or 0 capacitors. These pins are biased internally (see Figure 36) and –0.5 require no external bias. –1.0 Clock Input Options INTERNAL V = 1V REF –1.5 The AD9637 has a very flexible clock input structure. The clock –2.0 input can be a CMOS, LVDS, LVPECL, or sine wave signal. –2.5 Regardless of the type of signal being used, clock source jitter is of the utmost concern, as described in the Jitter Considerations –3.0 section. –3.5 Figure 50 and Figure 51 show two preferred methods for clocking –4.0 the AD9637 (at clock rates of up to 640 MHz prior to the internal –4.5 CLK divider). A low jitter clock source is converted from a single- –5.0 0 0.5 1.0 1.5 2.0 2.53.0 ended signal to a differential signal using either an RF transformer LOAD CURRENT (mA) or an RF balun. Figure 48. V Error vs. Load Current REF The RF balun configuration is recommended for clock frequencies External Reference Operation between 80 MHz and 640 MHz, and the RF transformer is recom- mended for clock frequencies from 10 MHz to 200 MHz. The The use of an external reference may be necessary to enhance back-to-back Schottky diodes across the transformer/balun the gain accuracy of the ADC or improve thermal drift charac- secondary winding limit clock excursions into the AD9637 to teristics. Figure 49 shows the typical drift characteristics of the approximately 0.8 V p-p differential. internal reference in 1.0 V mode. 4 This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9637 while 2 preserving the fast rise and fall times of the signal that are critical to a low jitter performance. However, the diode capacitance comes 0 into play at frequencies above 500 MHz. Care must be taken in choosing the appropriate signal limiting diode. –2 ® Mini-Circuits ADT1-1WT, 1:1 Z –4 0.1µF 0.1µF XFMR CLOCK CLK+ INPUT 100Ω –6 50Ω ADC 0.1µF CLK– SCHOTTKY –8 0.1µF DIODES: –40 –15 10 35 60 85 HSMS2822 TEMPERATURE (°C) Figure 50. Transformer Coupled Differential Clock (Up to 200 MHz) Figure 49. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 0.1µF 0.1µF 7.5 kΩ load (see Figure 42). The internal buffer generates the CLOCK CLK+ positive and negative full-scale references for the ADC core. INPUT 50Ω ADC 0.1µF Therefore, the external reference must be limited to a maximum 0.1µF CLK– of 1.0 V. It is not recommended to leave the SENSE pin floating. SCHOTTKY DIODES: HSMS2822 Figure 51. Balun Coupled Differential Clock (80 MHz to 640 MHz) Rev. 0 | Page 20 of 40 V ERROR (mV) REF V ERROR (%) REF 10215-047 10215-048 10215-050 10215-049 Data Sheet AD9637 If a low jitter clock source is not available, another option is to causes the clock divider to reset to its initial state. This ac couple a differential PECL signal to the sample clock input synchronization feature allows multiple parts to have their clock pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ dividers aligned to guarantee simultaneous input sampling. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer Clock Duty Cycle excellent jitter performance. Typical high speed ADCs use both clock edges to generate a variety A third option is to ac couple a differential LVDS signal to the of internal timing signals and, as a result, may be sensitive to sample clock input pins, as shown in Figure 53. The AD9510/ clock duty cycle. Commonly, a ±5% tolerance is required on the AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock duty cycle to maintain dynamic performance characteristics. clock drivers offer excellent jitter performance. The AD9637 contains a duty cycle stabilizer (DCS) that retimes In some applications, it may be acceptable to drive the sample the nonsampling (falling) edge, providing an internal clock signal clock inputs with a single-ended 1.8 V CMOS signal. In such with a nominal 50% duty cycle. This allows the user to provide applications, drive the CLK+ pin directly from a CMOS gate, and a wide range of clock input duty cycles without affecting the bypass the CLK− pin to ground with a 0.1 μF capacitor (see performance of the AD9637. Noise and distortion performance Figure 54). are nearly flat for a wide range of duty cycles with the DCS turned on. Input Clock Divider The AD9637 contains an input clock divider with the ability Jitter in the rising edge of the input is still of concern and is not to divide the input clock by integer values between 1 and 8. easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than The AD9637 clock divider can be synchronized using the external 20 MHz, nominally. The loop has a time constant associated SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock with it that must be considered in applications in which the divider to be resynchronized on every SYNC signal or only on clock rate can change dynamically. A wait time of 1.5 μs to 5 μs the first SYNC signal after the register is written. A valid SYNC is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x 100Ω ADC PECL DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 52. Differential PECL Sample Clock (Up to 640 MHz) 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x 100Ω ADC LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 50kΩ 50kΩ Figure 53. Differential LVDS Sample Clock (Up to 640 MHz) V CC OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER INPUT 1 1kΩ 50Ω ADC CLK– 0.1µF 1 50Ω RESISTOR IS OPTIONAL. Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. 0 | Page 21 of 40 10215-053 10215-052 10215-051 AD9637 Data Sheet Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 56, the power dissipated by the AD9637 is clock input. The degradation in SNR at a given input frequency proportional to its sample rate. The digital power dissipation (fA) due only to aperture jitter (tJ) can be calculated by does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ⎛ ⎞ 1 SNR Degradation = 20 log10 ⎜ ⎟ 400 ⎜ ⎟ 2π× f ×t ⎝ A J⎠ In this equation, the rms aperture jitter represents the root mean 350 square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling 80MSPS 300 applications are particularly sensitive to jitter (see Figure 55). 65MSPS The clock input should be treated as an analog signal in cases 250 where aperture jitter may affect the dynamic range of the AD9637. 50MSPS Power supplies for clock drivers should be separated from the 40MSPS ADC output driver supplies to avoid modulating the clock signal 200 with digital noise. Low jitter, crystal-controlled oscillators make 20MSPS the best clock sources. If the clock is generated from another 150 type of source (by gating, dividing, or other methods), it should 10 20 30 40 50 60 70 80 be retimed by the original clock at the last step. SAMPLE RATE (MSPS) Figure 56. Analog Core Power vs. f for f = 9.7 MHz SAMPLE IN Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter The AD9637 is placed in power-down mode either by the SPI performance as it relates to ADCs. port or by asserting the PDWN pin high. In this state, the ADC 130 typically dissipates 1 mW. During power-down, the output drivers RMS CLOCK JITTER REQUIREMENT are placed in a high impedance state. Asserting the PDWN pin 120 low returns the AD9637 to its normal operating mode. Note 110 that PDWN is referenced to the digital output driver supply 16 BITS 100 (DRVDD) and should not exceed that supply voltage. 90 14 BITS Low power dissipation in power-down mode is achieved by 80 12 BITS shutting down the reference, reference buffer, biasing networks, 70 and clock. Internal capacitors are discharged when entering 10 BITS 60 power-down mode and then must be recharged when returning 0.125ps 8 BITS to normal operation. As a result, wake-up time is related to the 50 0.25ps 0.5ps time spent in power-down mode, and shorter power-down 1.0ps 40 2.0ps cycles result in proportionally shorter wake-up times. When 30 1 10 100 1000 using the SPI port interface, the user can place the ADC in ANALOG INPUT FREQUENCY (MHz) power-down mode or standby mode. Standby mode allows the Figure 55. Ideal SNR vs. Input Frequency and Jitter user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details on using these features. Rev. 0 | Page 22 of 40 SNR (dB) 10215-054 ANALOG POWER (mW) 10215-055 Data Sheet AD9637 DIGITAL OUTPUTS AND TIMING The AD9637 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. When operating in reduced range mode, the output current is reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p differential) across a 100 Ω termination at the receiver. FCO 500mV/DIV 5ns/DIV DCO 500mV/DIV DATA 500mV/DIV The AD9637 LVDS outputs facilitate interfacing with LVDS Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default) receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 57. An example of LVDS output timing in reduced range mode is shown in Figure 58. FCO 500mV/DIV 5ns/DIV DCO 500mV/DIV DATA 500mV/DIV Figure 58. LVDS Output Timing Example in Reduced Range Mode Rev. 0 | Page 23 of 40 10215-057 10215-056 AD9637 Data Sheet Figure 59 shows an example of the LVDS output using the to drive longer trace lengths, which can be achieved by program- ANSI-644 standard (default) data eye and a time interval error ming Register 0x15. Even though this option produces sharper (TIE) jitter histogram with trace lengths of less than 24 inches rise and fall times on the data edges and is less prone to bit errors, on standard FR-4 material. it also increases the power dissipation of the DRVDD supply. 300 300 EYE: ALL BITS ULS: 8000:448000 EYE: ALL BITS ULS: 7000:448000 200 200 100 100 0 0 –100 –100 –200 –200 –300 –300 3.0k 3.0k 2.5k 2.5k 2.0k 2.0k 1.5k 1.5k 1.0k 1.0k 0.5k 0.5k 0 0 Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4, External 100 Ω Far-End Greater Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only Termination Only The default format of the output data is twos complement. Table 10 Figure 60 shows an example of trace lengths exceeding 24 inches shows an example of the output coding format. To change the on standard FR-4 material. Note that the TIE jitter histogram output data format to offset binary, see the Memory Map section. reflects the decrease of the data eye opening as the edge deviates Data from each ADC is serialized and provided on a separate from the ideal position. channel in DDR mode. The data rate for each serial stream is equal It is the responsibility of the user to determine if the waveforms to 12 bits times the sample clock rate, quantity divided by 2, meet the timing budget of the design when the trace lengths exceed with a maximum of 480 Mbps (12 bits × 80 MSPS)/2 = 480 Mbps. 24 inches. Additional SPI options allow the user to further increase The lowest typical conversion rate is 10 MSPS. See the Memory the internal termination (increasing the current) of all eight outputs Map section for details on enabling this feature. Table 10. Digital Output Coding Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000 VIN+ − VIN− = −VREF 0000 0000 0000 1000 0000 0000 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111 Rev. 0 | Page 24 of 40 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) –0.8ns –60ps –0.6ns –40ps –0.4ns –20ps –0.2ns 0ps 0ns 20ps 0.2ns 40ps 0.4ns 60ps 0.6ns 80ps 0.8ns 10215-058 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) –0.8ns –60ps –0.6ns –40ps –0.4ns –20ps –0.2ns 0ps 0ns 20ps 0.2ns 40ps 0.4ns 0.6ns 60ps 0.8ns 80ps 10215-059 Data Sheet AD9637 Two output clocks are provided to assist in capturing data from resolution systems. When changing the resolution to a 10-bit the AD9637. The DCO is used to clock the output data and is equal serial stream, the data stream is shortened. See Figure 3 for the to 6× the sample clock (CLK) rate for the default mode of opera- 10-bit example. tion. Data is clocked out of the AD9637 and must be captured In default mode, as shown in Figure 2, the MSB is first in the data on the rising and falling edges of the DCO that supports double output serial stream. This can be inverted so that the LSB is first data rate (DDR) capturing. The FCO is used to signal the start of in the data output serial stream by using the SPI. a new output byte and is equal to the sample clock rate (see the There are 12 digital output test pattern options available that can Timing Diagrams section). be initiated through the SPI. This is a useful feature when validating When the SPI is used, the DCO phase can be adjusted in 60° receiver capture and timing (see Table 11 for the output bit increments relative to the data edge. This enables the user to sequencing options that are available). Some test patterns have refine system timing margins, if required. The default DCO+ two serial sequential words and can be alternated in various ways, and DCO− timing, as shown in Figure 2, is 90° relative to the depending on the test pattern chosen. Note that some patterns output data edge. do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, A 10-bit serial stream can also be initiated from the SPI. This 0x1A, 0x1B, and 0x1C register addresses. allows the user to implement and test compatibility to lower Table 11. Flexible Output Test Modes Subject Output Test to Data Mode Bit Format Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Select Notes 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 (12-bit) N/A Yes Offset binary code shown 10 0000 0000 (10-bit) N/A Yes Offset binary code shown 0010 +Full-scale short 1111 1111 1111 (12-bit) N/A Yes Offset binary code shown 11 1111 1111 (10-bit) N/A Yes Offset binary code shown 0011 −Full-scale short 0000 0000 0000 (12-bit) N/A Yes Offset binary code shown 00 0000 0000 (10-bit) N/A Yes Offset binary code shown 0100 Checkerboard 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) No 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) No 1 0101 PN sequence long N/A N/A Yes PN23 ITU 0.150 23 18 X + X + 1 1 0110 PN sequence short N/A N/A Yes PN9 ITU O.150 9 5 X + X + 1 0111 One-/zero-word toggle 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) No 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) No 1000 User input Reg. 0x19 to Reg. 0x1A Reg. 0x1B to Reg. 0x1C No 1001 1-/0-bit toggle 1010 1010 1010 (12-bit) N/A No 10 1010 1010 (10-bit) N/A No 1010 1× sync 0000 0011 1111 (12-bit) N/A No 00 0001 1111 (10-bit) N/A No 1011 One bit high 1000 0000 0000 (12-bit) N/A No Pattern associated with the external pin 10 0000 0000 (10-bit) N/A No Pattern associated with the external pin 1100 Mixed frequency 1010 0011 0011 (12-bit) N/A No 10 0110 0011 (10-bit) N/A No 1 All test mode options except PN sequence short and PN sequence long can support 10-bit to 12-bit word lengths to verify data capture to the receiver. Rev. 0 | Page 25 of 40 AD9637 Data Sheet The PN sequence short pattern produces a pseudorandom bit SCLK/DTP Pin 9 sequence that repeats itself every 2 − 1 or 511 bits. A description The SCLK/DTP pin is for use in applications that do not require of the PN sequence and how it is generated can be found in SPI mode operation. This pin can enable a single digital test Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value pattern if it and the CSB pin are both held high during device is all 1s (see Table 12 for the initial values). The output is a parallel power-up. When SCLK/DTP is tied to AVDD, the ADC channel representation of the serial PN9 sequence in MSB first format. outputs shift out the following pattern: 1000 0000 0000. The The first output word is the first 12 bits of the PN9 sequence in FCO and DCO function normally while all channels shift out the MSB aligned format. repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output Table 12. PN Sequence data. This pin has an internal 30 kΩ resistor to GND. It can be Initial First Three Output Samples left unconnected for normal operation. Sequence Value (MSB First) Twos Complement PN Sequence Short 0x1FE0 0x1DF1, 0x3CC8, 0x294E Table 14. Digital Test Pattern Pin Settings PN Sequence Long 0x1FFF 0x1FE0, 0x2001, 0x1C00 Selected DTP DTP Voltage Resulting D± x The PN sequence long pattern produces a pseudorandom bit Normal Operation No connect Normal operation 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A DTP AVDD 1000 0000 0000 description of the PN sequence and how it is generated can be Additional and custom test patterns can also be observed when found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The commanded from the SPI port. Consult the Memory Map section seed value is all 1s (see Table 12 for the initial values) and the for information about the options available. AD9637 inverts the bit stream with relation to the ITU standard. CSB Pin The output is a parallel representation of the serial PN23 sequence in MSB first format. The first output word is the first 12 bits of the The CSB pin should be tied to AVDD for applications that do PN23 sequence in MSB aligned format. not require SPI mode operation. Tying CSB high causes all SCLK and SDIO information to be ignored. See the Memory Map section for information on how to change these additional digital output timing features through the SPI. RBIAS Pin SDIO/DFS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. For applications that do not require SPI mode operation, the CSB pin is tied to AVDD, and the SDIO/DFS pin controls the output data format select operation according to Table 13. Table 13. Output Data Format Select Pin Settings DFS Pin Voltage Output Mode AVDD Twos complement GND (Default) Offset binary Rev. 0 | Page 26 of 40 Data Sheet AD9637 BUILT-IN OUTPUT TEST MODES ADC is disconnected from the digital back-end blocks and the The AD9637 includes a built-in test feature designed to enable test pattern is run through the output formatting block. Some of verification of the integrity of each data output channel, as well the test patterns are subject to output formatting, and some are as to facilitate board level debugging. Various output test options not. The PN generators from the PN sequence tests can be reset are provided to place predictable values on the outputs of the by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be AD9637. performed with or without an analog signal (if present, the OUTPUT TEST MODES analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, The output test options are described in Table 17 at Address 0x0D. When an output test mode is enabled, the analog section of the Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 27 of 40 AD9637 Data Sheet SERIAL PORT INTERFACE (SPI) The falling edge of the CSB, in conjunction with the rising edge The AD9637 serial port interface (SPI) allows the user to configure of the SCLK, determines the start of the framing. An example of the converter for specific functions or operations through a the serial timing and its definitions can be found in Figure 61 structured register space provided inside the ADC. The SPI and Table 5. gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: the SCLK/DTP pin, the by the W0 and W1 bits. SDIO/DFS pin, and the CSB pin (see Table 15). The SCLK In addition to word length, the instruction phase determines (a serial clock) is used to synchronize the read and write data whether the serial frame is a read or write operation, allowing presented from and to the ADC. The SDIO (serial data input/ output) is a dual-purpose pin that allows data to be sent to and the serial port to be used both to program the chip and to read read from the internal ADC memory map registers. The CSB the contents of the on-chip memory. The first bit of the first byte in (chip select bar) is an active low control that enables or disables a multibyte serial data transfer frame indicates whether a read the read and write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial Table 15. Serial Port Interface Pins data input/output (SDIO) pin to change direction from an input to Pin Function an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to All data is composed of 8-bit words. Data can be sent in MSB synchronize serial interface reads and writes. first mode or in LSB first mode. MSB first is the default on SDIO Serial data input/output. A dual-purpose pin that power-up and can be changed via the SPI port configuration typically serves as an input or an output, depending on the instruction being sent and the relative position in the register. For more information about this and other features, timing frame. see the AN-877 Application Note, Interfacing to High Speed CSB Chip select bar. An active low control that gates the read ADCs via SPI. and write cycles. t HIGH t t CLK H t DS t t S LOW t DH CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 61. Serial Port Interface Timing Diagram Rev. 0 | Page 28 of 40 10215-060 Data Sheet AD9637 pins as static control lines for the output data format, output HARDWARE INTERFACE digital test pattern, and power-down feature control. In this The pins described in Table 15 comprise the physical interface mode, CSB should be connected to AVDD, which disables the between the user programming device and the serial port of the serial port interface. AD9637. The SCLK pin and the CSB pin function as inputs When the device is in SPI mode, the PDWN pin (if enabled) when using the SPI interface. The SDIO pin is bidirectional, remains active. For SPI control of power-down, the PDWN pin functioning as an input during write phases and as an output should be set to its default state. during readback. SPI ACCESSIBLE FEATURES The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration Table 16 provides a brief description of the general features that is described in detail in the AN-812 Application Note, Micro- are accessible via the SPI. These features are described in detail controller-Based Serial Port Interface (SPI) Boot Circuit. in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9637 part-specific features are described in detail The SPI port should not be active during periods when the full in the Memory Map Register Descriptions section following dynamic performance of the converter is required. Because the Table 17, the external memory map register table. SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can Table 16. Features Accessible Using the SPI degrade converter performance. If the on-board SPI bus is used for Feature Name Description other devices, it may be necessary to provide buffers between Mode Allows the user to set either power-down this bus and the AD9637 to prevent these signals from transi- mode or standby mode tioning at the converter inputs during critical sampling periods. Clock Allows the user to access the DCS, set the clock divider, set the clock divider phase, Some pins serve a dual function when the SPI interface is not and enable the sync being used. When the pins are strapped to DRVDD or ground Offset Allows the user to digitally adjust the during device power-on, they are associated with a specific converter offset function. Table 16 describes the strappable functions supported Test I/O Allows the user to set test modes to have on the AD9637. known data on output bits CONFIGURATION WITHOUT THE SPI Output Mode Allows the user to set the output mode Output Phase Allows the user to set the output clock polarity In applications that do not interface to the SPI control registers, ADC Resolution Scalable power consumption options based the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin and Speed Grade on resolution and speed grade selection serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the Rev. 0 | Page 29 of 40 AD9637 Data Sheet MEMORY MAP Default Values READING THE MEMORY MAP REGISTER TABLE After the AD9637 is reset, critical registers are loaded with Each row in the memory map register table has eight bit locations. default values. The default values for the registers are given in The memory map is roughly divided into three sections: the chip Table 17, the memory map register table. configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address Logic Levels 0xFF) and the global ADC functions registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x109). • “Bit is set” is synonymous with “bit is set to Logic 1” or The memory map register table (see Table 17) lists the default “writing Logic 1 for the bit.” hexadecimal value for each hexadecimal address shown. The • “Clear a bit” is synonymous with “bit is set to Logic 0” or column with the heading Bit 7 (MSB) is the start of the default “writing Logic 0 for the bit.” hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x3F. This Channel-Specific Registers means that in Address 0x05, Bits[7:6] = 0, and the remaining Some channel setup functions, such as the signal monitor Bits[5:0] = 1. This setting is the default channel index setting. thresholds, can be programmed differently for each channel. In The default value results in both ADC channels receiving the these cases, channel address locations are internally duplicated next write command. For more information on this function for each channel. These registers and bits are designated in and others, see the AN-877 Application Note, Interfacing to Table 17 as local. These local registers and bits can be accessed High Speed ADCs via SPI. This application note details the by setting the appropriate data channel bits (A, B, C, or D) and functions controlled by Register 0x00 to Register 0xFF. The the clock channel DCO/FCO bits (Bits[5:4]) in Register 0x05. If remaining registers are documented in the Memory Map all the bits are set, the subsequent write affects the registers of Register Descriptions section. all channels and the DCO/FCO clock channels. In a read cycle, Open Locations only one of the channels, A, B, C, or D, should be set to read one of the four registers. If all the bits are set during a SPI read All address and bit locations that are not included in Table 17 cycle, the part returns the value for Channel A. Registers and are not currently supported for this device. Unused bits of a bits designated as global in Table 17 affect the entire part or the valid address location should be written with 0s. Writing to these channel features for which independent settings are not allowed locations is required only when part of an address location is between channels. The settings in Register 0x05 do not affect open (for example, Address 0x05). If the entire address location the global registers and bits. is open or not listed in Table 17 (for example, Address 0x13) this address location should not be written. Rev. 0 | Page 30 of 40 Data Sheet AD9637 MEMORY MAP REGISTER TABLE The AD9637 uses a 3-wire interface and 16-bit addressing and, SPI enters a soft reset, where all of the user registers revert to therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 their default values and Bit 2 is automatically cleared. and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the Table 17. Memory Map Register Table Reg. Default Addr. Parameter Value (Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 = SDO LSB first Soft reset 1 = 1 = Soft reset LSB first 0 = SDO 0x18 The nibbles configuration active 16-bit 16-bit active are mirrored address address so that LSB or MSB first mode registers correctly. The default for the ADCs is 16-bit mode. 0x01 Chip ID (global) 8-bit chip ID, Bits[7:0] Read Unique chip ID only that is used to AD9637 0x93 = octal 12-bit 40 MSPS/80 MSPS serial LVDS differentiate 0x93 devices; read only. 0x02 Chip grade Open Speed grade ID, Bits[6:4] Open Open Open Open Read Unique speed (global) only grade ID that 001 = 40 MSPS is used to 100 = 80 MSPS differentiate graded devices; read only. Device Index and Transfer Registers 0x04 Device Index 2 Open Open Open Open Data Data Data Data 0xF Bits are set to Channel H Channel G Channel F Channel E determine which device on chip receives the next write command. The default is all devices on chip. 0x05 Device Index 1 Open Open Clock Clock Data Data Data Data 0x3F Bits are set Channel Channel Channel D Channel C Channel B Channel A to determine DCO FCO which device on chip receives the next write command. The default is all devices on chip. 0xFF Transfer Open Open Open Open Open Open Open 0x00 Initiate Set override resolution/ sample rate override. Global ADC Functions 0x08 Power modes Open Open External Open Open Open Internal power-down 0x00 Determines (global) power- mode various down generic 00 = chip run pin modes of chip 01 = full power-down function operation. 10 = standby 0 = full 11 = reset power- down 1 = standby 0x09 Clock (global) Open Open Open Open Open Open Open Duty cycle 0x01 Turns duty stabilizer cycle stabilizer on 0 = off or off. 1 = on Rev. 0 | Page 31 of 40 AD9637 Data Sheet Reg. Default Addr. Parameter Value (Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Comments 0x0B Clock divide Open Open Open Open Open Clock divide ratio, Bits[2:0] 0x00 The divide 000 = divide by 1 ratio is the (global) 001 = divide by 2 value plus 1. 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0C Enhancement Open Open Open Open Open Chop Open Open 0x00 Enables/ control mode disables chop 0 = off mode. 1 = on 0x0D Test mode (local User input test mode Reset PN Reset Output test mode, Bits[3:0] (local) 0x00 When set, except for PN long gen PN the test data 00 = single 0000 = off (default) sequence resets) short is placed on 01 = alternate 0001 = midscale short gen the output 10 = single once 0010 = positive FS pins in place 11 = alternate once 0011 = negative FS of normal (affects user input test 0100 = alternating checkerboard data. mode only, 0101 = PN 23 sequence Bits[3:0] = 1000) 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) 0x00 Device offset (local) Offset adjust in LSBs from +127 to −128 (twos complement format) trim. 0x14 Output mode Open LVDS-ANSI/ Open Open Open Output Open Output 0x01 Configures LVDS-IEEE invert format the outputs option 0 = offset and the (local) 0 = LVDS- binary format of the ANSI data. 1 = twos 1 = LVDS- comple- IEEE reduced ment range link (global) (global) (see Table 18) 0x15 Output adjust Open Open Output driver Open Open Open Output 0x00 Determines termination, Bits[1:0] drive LVDS or other 0 = 1× drive output 00 = none 1 = 2× drive properties. 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω 0x16 Output phase Open Input clock phase adjust, Bits[6:4] Output clock phase adjust, Bits[3:0] 0x03 On devices that use (value is number of input clock (setting = 0000 through 1011) global clock cycles of phase delay) (see Table 20) divide, (see Table 19) determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x18 V Open Open Open Open Open Internal V adjustment 0x04 Selects REF REF and/or digital scheme, Bits[2:0] adjusts the 000 = 1.0 V p-p VREF. 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p Rev. 0 | Page 32 of 40 Data Sheet AD9637 Reg. Default Addr. Parameter Value (Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Comments 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 1 LSB. 0x1A USER_PATT1_MSB15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined B (global) Pattern 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 2 LSB. 0x1C USER_PATT2_MSB15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined B (global) Pattern 2 MSB. 0x21 Serial control LVDS Word-wise DDR 1-lane, Bits[6:4] Open Open Serial output number 0x42 Serial stream (global) output LSB of bits control. 100 = DDR 1-lane first Default 10 = 12 bits causes MSB 11 = 10 bits first and the native bit stream. 0x22 Serial channel Open Open Open Open Open Open Channel Channel 0x00 Used to status (local) output power- power down reset down individual sections of a converter. 0x100 Open Resolution Open Sample rate 0x00 Resolution/ Resolution/ Resolution/ sample rate sample rate sample rate 10 = 12 bits 000 = 20 MSPS override override override 11 = 10 bits 001 = 40 MSPS enable (requires 010 = 50 MSPS transfer bit, 011 = 65 MSPS 0xFF). 100 = 80 MSPS 0x101 User I/O Control 2 Open Open Open Open Open Open Open SDIO 0x00 Disables SDIO pull-down pull-down. 0x102 User I/O Control 3 Open Open Open Open VCM Open Open Open 0x00 VCM control. power- down 0x109 Sync Open Open Open Open Open Open 0x00 Sync next Enable only sync Rev. 0 | Page 33 of 40 AD9637 Data Sheet Output Mode (Register 0x14) MEMORY MAP REGISTER DESCRIPTIONS Bit 7—Open For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Bit 6—LVDS-ANSI/LVDS-IEEE Option Interfacing to High Speed ADCs via SPI. Setting this bit chooses the LVDS-IEEE (reduced range) option. Device Index (Register 0x04 and Register 0x05) The default setting is LVDS-ANSI. As described in Table 18, There are certain features in the map that can be set independently when LVDS-ANSI or LVDS-IEEE reduced range link is selected, the user can select the driver termination. The driver current for each channel, whereas other features apply globally to all channels (depending on context), regardless of which are selected. is automatically selected to give the proper output swing. The first four bits in Register 0x04 and Register 0x05 can be Table 18. LVDS-ANSI/LVDS-IEEE Options used to select which individual data channels are affected. The Output output clock channels can be selected in Register 0x05, as well. Mode, Output Output Driver Output Driver A smaller subset of the independent feature list can be applied Bit[6] Mode Termination Current to those devices. 0 LVDS-ANSI User selectable Automatically selected to give Transfer (Register 0xFF) proper swing All registers except Register 0x100 are updated the moment 1 User selectable LVDS-IEEE Automatically they are written. Setting Bit 0 of this transfer register high reduced selected to give initializes the settings in the ADC sample rate override register range link proper swing (Address 0x100). Bits[5:3]—Open Power Modes (Register 0x08) Bit 2—Output Invert Bits[7:6]—Open Setting this bit inverts the output bit stream. Bit 5—External Power-Down Pin Function Bit 1—Open If set, the external PDWN pin initiates standby mode. If cleared, Bit 0—Output Format the external PDWN pin initiates power-down mode. By default, this bit is set to send the data output in twos Bits[4:2]—Open complement format. Resetting this bit changes the output mode Bits[1:0]—Internal Power-Down Mode to offset binary. In normal operation (Bits[1:0] = 00), all ADC channels are active. Output Adjust (Register 0x15) In power-down mode (Bits[1:0] = 01), the digital data path clocks Bits[7:6]—Open are disabled while the digital data path is reset. Outputs are Bits[5:4]—Output Driver Termination disabled. These bits allow the user to select the internal termination In standby mode (Bits[1:0] = 10), the digital data path clocks resistor. and the outputs are disabled. Bits[3:1]—Open During a digital reset (Bits[1:0] = 11), all the digital data path clocks and the outputs (where applicable) on the chip are reset, Bit 0—Output Drive except the SPI port. Note that the SPI is always left under Bit 0 of the output adjust register controls the drive strength on control of the user, that is, it is never automatically disabled or the LVDS driver of the FCO and DCO outputs only. The default in reset (except by power-on reset). values set the drive to 1×. The drive can be increased to 2× by setting the appropriate channel bit in Register 0x05 and then Enhancement Control (Register 0x0C) setting Bit 0. These features cannot be used with the output driver Bits[7:3]—Open termination select. The termination selection takes precedence Bit 2—Chop Mode over the 2× driver strength on FCO and DCO when both the For applications that are sensitive to offset voltages and other output driver termination and output drive are selected. low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9637 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2, where they can be filtered. Bits[1:0]—Open Rev. 0 | Page 34 of 40 Data Sheet AD9637 Output Phase (Register 0x16) Resolution/Sample Rate Override (Register 0x100) Bit 7—Open This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip Bits[6:4]—Input Clock Phase Adjust power-down. Settings in this register are not initialized until Bit 0 Table 19. Input Clock Phase Adjust Options of the transfer register (Register 0xFF) is written high. Input Clock Phase Number of Input Clock Cycles of User I/O Control 2 (Register 0x101) Adjust, Bits[6:4] Phase Delay Bits[7:1]—Open 000 (Default) 0 001 1 Bit 0—SDIO Pull-Down 010 2 Bit 0 can be set to disable the internal 30 kΩ pull-down on the 011 3 SDIO pin, which can be used to limit loading when many 100 4 devices are connected to the SPI bus. 101 5 User I/O Control 3 (Register 0x102) 110 6 Bits[7:4]—Open 111 7 Bit 3—VCM Power-Down Bits[3:0]—Output Clock Phase Adjust Bit 3 can be set high to power down the internal VCM generator. Table 20. Output Clock Phase Adjust Options This feature is used when applying an external reference. Output Clock (DCO), DCO Phase Adjustment Bits[2:0]—Open Phase Adjust, Bits[3:0] (Degrees Relative to D± x Edge) 0000 0 0001 60 0010 120 0011 (Default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 Rev. 0 | Page 35 of 40 AD9637 Data Sheet APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES PCB, partition the continuous copper plane by overlaying a silk- Before starting the design and layout of the AD9637 as a system, screen on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and PCB during the reflow guidelines, which describes the special circuit connections and process, whereas using one continuous plane with no partitions layout requirements that are needed for certain pins. guarantees only one tie point. For detailed information on packaging and the PCB layout of chip scale packages, see the POWER AND GROUND RECOMMENDATIONS AN-772 Application Note, A Design and Manufacturing Guide When connecting power to the AD9637, it is recommended for the Lead Frame Chip Scale Package (LFCSP), at that two separate 1.8 V supplies be used. Use one supply for www.analog.com. analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different VCM decoupling capacitors should be used to cover both high and The VCM pin should be decoupled to ground with a 0.1 μF low frequencies. Place these capacitors close to the point of capacitor. entry at the PCB level and close to the pins of the part, with REFERENCE DECOUPLING minimal trace length. The VREF pin should be externally decoupled to ground with A single PCB ground plane should be sufficient when using the a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF AD9637. With proper decoupling and smart partitioning of the ceramic capacitor. PCB analog, digital, and clock sections, optimum performance is easily achieved. SPI PORT EXPOSED PAD THERMAL HEAT SLUG The SPI port should not be active during periods when the full RECOMMENDATIONS dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the It is required that the exposed pad on the underside of the ADC clock, noise from these signals can degrade converter ADC be connected to analog ground (AGND) to achieve the performance. If the on-board SPI bus is used for other devices, best electrical and thermal performance of the AD9637. An it may be necessary to provide buffers between this bus and the exposed continuous copper plane on the PCB should mate to AD9637 to keep these signals from transitioning at the con- the AD9637 exposed pad, Pin 0. The copper plane should have verter inputs during critical sampling periods. several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. Rev. 0 | Page 36 of 40 Data Sheet AD9637 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 PIN 1 MAX INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 62. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9637BCPZ-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9637BCPZRL7-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9637BCPZ-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9637BCPZRL7-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9637-80EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 37 of 40 091707-C AD9637 Data Sheet NOTES Rev. 0 | Page 38 of 40 Data Sheet AD9637 NOTES Rev. 0 | Page 39 of 40 AD9637 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10215-0-10/11(0) Rev. 0 | Page 40 of 40