ANALOG DEVICES AD9634

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9634 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 69.7 dBFS at 185 MHz A and 250 MSPS IN SFDR = 87 dBc at 185 MHz A and 250 MSPS IN VIN+ −150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A and PIPELINE 12 IN D0±/D1± 12-BIT . 250 MSPS ADC VIN– . PARALLEL . DDR LVDS Total power consumption: 360 mW at 250 MSPS VCM AD9634 AND D10±/D11± DRIVERS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs REFERENCE DCO± Integer 1-to-8 input clock divider (625 MHz maximum input) OR± Sample rates of up to 250 MSPS 1-TO-8 SERIAL PORT IF sampling frequencies of up to 350 MHz CLOCK DIVIDER Internal ADC voltage reference Flexible analog input range SCLK SDIO CSB CLK+ CLK– 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) Figure 1. ADC clock duty cycle stabilizer Serial port control Energy-saving power-down modes User-configurable, built-in self test (BIST) capability APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9634 is a 12-bit, analog-to-digital converter (ADC) with Programming for setup and control is accomplished using a sampling speeds of up to 250 MSPS. The AD9634 is designed to 3-wire, SPI-compatible serial interface. support communications applications where low cost, small size, The AD9634 is available in a 32-lead LFCSP and is specified over wide bandwidth, and versatility are desired. the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The PRODUCT HIGHLIGHTS ADC features wide bandwidth inputs that can support a variety 1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. of user-selectable input ranges. An integrated voltage reference 2. Fast overrange and threshold detect. eases design considerations. A duty cycle stabilizer (DCS) is 3. Proprietary differential input maintains excellent SNR provided to compensate for variations in the ADC clock duty cycle, performance for input frequencies of up to 350 MHz. allowing the converter to maintain excellent performance. 4. 3-pin, 1.8 V SPI port for register programming and readback. The ADC output data are routed directly to the external 12-bit 5. Pin compatibility with the AD9642, allowing a simple LVDS output port. migration up to 14 bits, and with the AD6672. Flexible power-down options allow significant power savings, when desired. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09996-001 AD9634 TABLE OF CONTENTS Features .............................................................................................. 1  ADC Architecture ...................................................................... 19  Applications....................................................................................... 1  Analog Input Considerations ................................................... 19  Functional Block Diagram .............................................................. 1  Voltage Reference ....................................................................... 21  General Description ......................................................................... 1  Clock Input Considerations...................................................... 21  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 23  Revision History ............................................................................... 2  Digital Outputs ........................................................................... 23  Specifications..................................................................................... 3  ADC Overrange (OR)................................................................ 23  ADC DC Specifications................................................................. 3  Serial Port Interface (SPI).............................................................. 24  ADC AC Specifications ................................................................. 4  Configuration Using the SPI..................................................... 24  Digital Specifications ................................................................... 6  Hardware Interface..................................................................... 24  Switching Specifications ................................................................ 7  SPI Accessible Features.............................................................. 25  Timing Specifications .................................................................. 8  Memory Map .................................................................................. 26  Absolute Maximum Ratings............................................................ 9  Reading the Memory Map Register Table............................... 26  Thermal Characteristics .............................................................. 9  Memory Map Register Table..................................................... 27  ESD Caution.................................................................................. 9  Applications Information .............................................................. 29  Pin Configuration and Function Descriptions........................... 10  Design Guidelines ...................................................................... 29  Typical Performance Characteristics ........................................... 12  Outline Dimensions....................................................................... 30  Equivalent Circuits ......................................................................... 18  Ordering Guide .......................................................................... 30  Theory of Operation ...................................................................... 19  REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9634 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled, unless otherwise noted. Table 1. AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±11 ±11 ±11 mV Gain Error Full +2/−11 +1/−8 +3/−7 %FSR Differential Nonlinearity (DNL) Full ±0.4 ±0.4 ±0.4 LSB 25°C ±0.22 ±0.22 ±0.22 LSB 1 Integral Nonlinearity (INL) Full ±0.4 ±0.4 ±0.6 LSB 25°C ±0.2 ±0.2 ±0.27 LSB TEMPERATURE DRIFT Offset Error Full ±7 ±7 ±7 ppm/°C Gain Error Full ±55 ±58 ±75 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.531 0.391 0.407 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p 2 Input Capacitance Full 2.5 2.5 2.5 pF 3 Input Resistance Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 IAVDD Full 123 134 129 139 136 145 mA 1 IDRVDD Full 50 54 56 60 64 68 mA POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 311 340 333 360 360 385 mW 4 Standby Power Full 50 50 50 mW Power-Down Power Full 5 5 5 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. 0 | Page 3 of 32 AD9634 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. AD9634-170 AD9634-210 AD9634-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 30 MHz 25°C 70.3 70.2 70.1 dBFS IN f = 90 MHz 25°C 70.1 70.1 70.0 dBFS IN Full 69.1 68.8 dBFS fIN = 140 MHz 25°C 69.9 70.0 69.9 dBFS fIN = 185 MHz 25°C 69.5 69.6 69.7 dBFS Full 67.8 dBFS f = 220 MHz 25°C 69.2 69.2 69.3 dBFS IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 69.4 69.2 69.2 dBFS f = 90 MHz 25°C 69.2 69.1 69.0 dBFS IN Full 68.1 67.8 dBFS fIN = 140 MHz 25°C 68.9 69.1 69.0 dBFS fIN = 185 MHz 25°C 68.5 68.7 68.7 dBFS Full 66.7 dBFS f = 220 MHz 25°C 68.3 68.3 68.4 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 11.2 11.2 11.2 Bits f = 90 MHz 25°C 11.2 11.2 11.2 Bits IN f = 140 MHz 25°C 11.1 11.2 11.2 Bits IN f = 185 MHz 25°C 11.1 11.1 11.1 Bits IN fIN = 220 MHz 25°C 11.0 11.0 11.1 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −96 −96 −90 dBc fIN = 90 MHz 25°C −95 −92 −89 dBc Full −83 −80 dBc f = 140 MHz 25°C −97 −94 −91 dBc IN f = 185 MHz 25°C −86 −95 −87 dBc IN Full −80 dBc fIN = 220 MHz 25°C −84 −84 −93 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 30 MHz 25°C 96 96 90 dBc IN fIN = 90 MHz 25°C 95 92 89 dBc Full 83 80 dBc fIN = 140 MHz 25°C 97 94 91 dBc f = 185 MHz 25°C 86 95 87 dBc IN Full 80 dBc fIN = 220 MHz 25°C 84 84 93 dBc WORST OTHER (HARMONIC OR SPUR) f = 30 MHz 25°C −98 −96 −95 dBc IN fIN = 90 MHz 25°C −97 −95 −95 dBc Full −87 −83 dBc fIN = 140 MHz 25°C −98 −97 −96 dBc f = 185 MHz 25°C −95 −95 −94 dBc IN Full −81 dBc f = 220 MHz 25°C −96 −95 −94 dBc IN Rev. 0 | Page 4 of 32 AD9634 AD9634-170 AD9634-210 AD9634-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit TWO-TONE SFDR f = 184.1 MHz, 187.1 MHz (−7 dBFS) 25°C 87 89 88 dBc IN 2 FULL POWER BANDWIDTH 25°C 350 350 350 MHz 3 NOISE BANDWIDTH 25°C 1000 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved. 3 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally. Rev. 0 | Page 5 of 32 AD9634 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full 10 22 μA Low Level Input Current Full −22 −10 μA Input Capacitance Full 4 pF Input Resistance Full 12 15 18 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 50 71 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUTS (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR Outputs (OR+, OR−) Differential Output Voltage (V ), ANSI Mode Full 250 350 450 mV OD Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull-up. 2 Pull-down. Rev. 0 | Page 6 of 32 AD9634 SWITCHING SPECIFICATIONS Table 4. AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit 1 CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 2 Conversion Rate DCS Enabled Full 40 170 40 210 40 250 MSPS DCS Disabled Full 10 170 10 210 10 250 MSPS CLK Period, Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Full 0.8 0.8 0.8 ns Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms 1 DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns DCO Propagation Delay (tDCO) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns DCO to Data Skew (t ) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns SKEW Pipeline Delay (Latency) Full 10 10 10 Cycles Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power-Down) Full 100 100 100 μs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 See Figure 2. 2 Conversion rate is the clock rate after the divider. Timing Diagram N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO– DCO+ t SKEW t PD D0±/D1± D0 D1 D0 D1 D0 D1 D0 D1 D0 EVEN/ODD (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 D10±/D11± D10 D11 D10 D11 D10 D11 D10 D11 D10 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 Figure 2. Even/Odd LVDS Mode Data Output Timing Rev. 0 | Page 7 of 32 09996-002 AD9634 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns t Time required for the SDIO pin to switch from an input to an output 10 ns EN_SDIO relative to the SCLK falling edge (not shown in Figure 58) t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) Rev. 0 | Page 8 of 32 AD9634 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for the Parameter Rating LFCSP package. Soldering the exposed paddle to the customer Electrical board increases the reliability of the solder joints, maximizing AVDD to AGND −0.3 V to +2.0 V the thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance CLK+, CLK− to AGND −0.3 V to AVDD + 0.2V Airflow VCM to AGND −0.3 V to AVDD + 0.2 V Package Velocity CSB to AGND −0.3 V to DRVDD + 0.3 V 1, 2 1, 3 1, 4 Type (m/sec) θ θ θ Unit JA JC JB SCLK to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 °C/W SDIO to AGND −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 °C/W D0±/D1± through D10±/D11± −0.3 V to DRVDD + 0.3 V (CP-32-12) 2.0 29.1 °C/W to AGND 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Environmental Operating Temperature Range −40°C to +85°C Typical θJA is specified for a 4-layer PCB with solid ground plane. (Ambient) As shown in Table 7, airflow increases heat dissipation, which 150°C Maximum Junction Temperature reduces θJA. In addition, metal in direct contact with the package Under Bias leads from metal traces, through holes, ground, and power Storage Temperature Range −65°C to +125°C planes reduces the θ . JA (Ambient) Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 32 AD9634 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 24 CSB 2 23 CLK– SCLK AVDD 3 22 SDIO AD9634 OR– 4 21 DCO+ TOP VIEW OR+ 5 20 DCO– (Not to Scale) D0–/D1– (LSB) 6 19 D10+/D11+ (MSB) D0+/D1+ (LSB) 7 18 D10–/D11– (MSB) DRVDD 8 17 DRVDD NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Supplies 8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Exposed Ground Analog Ground. The exposed thermal paddle on the bottom of the Paddle package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 25 DNC Do No Connect. Do not connect to this pin. ADC Analog 30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Outputs 5 OR+ Output Overrange—True. 4 OR− Output Overrange—Complement. 7 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/Data 1—True (LSB). 6 D0−/D1− (LSB) Output DDR LVDS Output Data 0/Data 1—Complement (LSB). 10 D2+/D3+ Output DDR LVDS Output Data 2/Data 3—True. 9 D2−/D3− Output DDR LVDS Output Data 2/Data 3—Complement. 12 D4+/D5+ Output DDR LVDS Output Data 4/Data 5—True. 11 D4−/D5− Output DDR LVDS Output Data 4/Data 5—Complement. 14 D6+/D7+ Output DDR LVDS Output Data 6/Data 7—True. 13 D6−/D7− Output DDR LVDS Output Data 6/Data 7—Complement. 16 D8+/D9+ Output DDR LVDS Output Data 8/Data 9—True. 15 D8−/D9− Output DDR LVDS Output Data 8/Data 9—Complement. 19 D10+/D11+ (MSB) Output DDR LVDS Output Data 10/Data 11—True (MSB). 18 D10−/ D11− (MSB) Output DDR LVDS Output Data 10/Data 11—Complement (MSB). 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement. Rev. 0 | Page 10 of 32 D2–/D3– 9 32 AVDD 10 31 D2+/D3+ AVDD D4–/D5– 11 30 VIN+ D4+/D5+ 12 29 VIN– D6–/D7– 13 28 AVDD D6+/D7+ 14 27 AVDD D8–/D9– 15 26 VCM D8+/D9+ 16 25 DNC 09996-003 AD9634 Pin No. Mnemonic Type Description SPI Control 23 SCLK Input SPI Serial Clock. 22 SDIO Input/Output SPI Serial Data I/O. 24 CSB Input SPI Chip Select (Active Low). Rev. 0 | Page 11 of 32 AD9634 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted. 0 0 170MSPS 170MSPS 90.1MHz @ –1.0dBFS 305.1MHz @ –1.0dBFS SNR = 67.2dB (68.2dBFS) SNR = 69.1dB (70.1dBFS) –20 –20 SFDR = 86dBc SFDR = 93dBc –40 –40 –60 –60 SECOND THIRD THIRD SECOND HARMONIC HARMONIC HARMONIC HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 08 10 20 30 40 50 60 700 08 10 20 30 40 50 60 700 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9634-170 Single-Tone FFT with fIN = 90.1 MHz Figure 7. AD9634-170 Single-Tone FFT with fIN = 305.1 MHz 0 120 170MSPS 185.1MHz @ –1.0dBFS SFDR (dBFS) SNR = 68.5dB (69.5dBFS) –20 100 SFDR = 86dBc –40 80 SNR (dBFS) –60 THIRD SECOND 60 HARMONIC HARMONIC –80 SFDR (dBc) 40 –100 SNR (dBc) 20 –120 0 –140 08 10 20 30 40 50 60 700 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 8. AD9634-170 Single-Tone SNR/SFDR vs. Figure 5. AD9634-170 Single-Tone FFT with f = 185.1 MHz IN Input Amplitude (A ) with f = 90.1 MHz, f = 170 MSPS IN IN S 100 0 170MSPS 220.1MHz @ –1.0dBFS 95 SNR = 68.2dB (69.2dBFS) –20 SFDR = 84dBc SFDR (dBc) 90 –40 85 –60 THIRD SECOND 80 HARMONIC HARMONIC –80 75 –100 70 SNR (dBFS) –120 65 –140 60 60 90 120 150 180 210 240 270 300 330 08 10 20 30 40 50 60 700 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. AD9634-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN), Figure 6. AD9634-170 Single-Tone FFT with fIN = 220.1 MHz fS = 170 MSPS Rev. 0 | Page 12 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09996-006 09996-005 09996-004 SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) AMPLITUDE (dBFS) 09996-008 09996-107 09996-007 AD9634 0 0 170MSPS 184.12MHz @ –7.0dBFS 187.12MHz @ –7.0dBFS –20 –20 SFDR = 85dBc (92dBFS) SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 08 10 20 30 40 50 60 700 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 10. AD9634-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 13. AD9634-170 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS 0 100 SFDR 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 75 SFDR (dBFS) SNR –100 70 IMD3 (dBFS) –120 65 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 40 50 60 70 80 90 100 110 120 130 140 150 160 170 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 11. AD9634-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN Figure 14. AD9634-170 Single-Tone SNR/SFDR vs. Sample Rate (f ) S with f = 184.12 MHz, f = 187.12 MHz, f = 170 MSPS IN1 IN2 S with f = 90 MHz IN 0 14000 170MSPS 0.531 LSB rms 89.12MHz @ –7.0dBFS 16,384 TOTAL HITS 92.12MHz @ –7.0dBFS –20 12000 SFDR = 89dBc (96dBFS) –40 10000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 08 10 20 30 40 50 60 700 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 12. AD9634-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 15. AD9634-170 Grounded Input Histogram, fS = 170 MSPS Rev. 0 | Page 13 of 32 SFDR/IMD3 (dBc and dBFS) SFDR/IMD3 (dBc and dBFS) AMPLITUDE (dBFS) 09996-011 09996-010 09996-009 SNR/SFDR (dBFS and dBc) NUMBER OF HITS AMPLITUDE (dBFS) 09996-014 09996-012 09996-013 AD9634 0 0 210MSPS 210MSPS 90.1MHz @ –1.0dBFS 305.1MHz @ –1.0dBFS SNR = 69.1dB (70.1dBFS) SNR = 67.6dB (68.6dBFS) –20 –20 SFDR = 92dBc SFDR = 83dBc –40 –40 –60 –60 SECOND THIRD SECOND THIRD HARMONIC HARMONIC HARMONIC HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 15 30 45 60 75 90 105 0 15 30 45 60 75 90 105 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. AD9634-210 Single-Tone FFT with fIN = 90.1 MHz Figure 19. AD9634-210 Single-Tone FFT with fIN = 305.1 MHz 0 120 210MSPS 185.1MHz @ –1.0dBFS SFDR (dBFS) SNR = 68.6dB (69.6dBFS) –20 100 SFDR = 93dBc –40 80 SNR (dBFS) –60 SECOND THIRD 60 HARMONIC HARMONIC –80 SFDR (dBc) 40 –100 SNR (dBc) 20 –120 –140 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 15 30 45 60 75 90 105 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 17. AD9634-210 Single-Tone FFT with f = 185.1 MHz Figure 20. AD9634-210 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with IN fIN = 90.1 MHz, fS = 210 MSPS 100 0 210MSPS SFDR (dBc) 220.1MHz @ –1.0dBFS 95 SNR = 68.3dB (69.3dBFS) –20 SFDR = 84dBc 90 –40 SECOND HARMONIC 85 –60 THIRD 80 HARMONIC –80 75 –100 SNR (dBFS) 70 –120 65 60 –140 60 90 120 150 180 210 240 270 300 330 0 15 30 45 60 75 90 105 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. AD9634-210 Single-Tone SNR/SFDR vs. Input Frequency (f ), Figure 18. AD9634-210 Single-Tone FFT with fIN = 220.1 MHz IN f = 210 MSPS S Rev. 0 | Page 14 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09996-017 09996-016 09996-015 AMPLITUDE (dBFS) SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) 09996-019 09996-018 09996-100 AD9634 0 0 210MSPS 184.12MHz @ –7.0dBFS 187.12MHz @ –7.0dBFS –20 –20 SFDR = 89dBc (96dBFS) SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 01 15 30 45 60 75 9005 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 22. AD9634-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 25. AD9634-210 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 210 MSPS 0 100 SFDR 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 75 SFDR (dBFS) SNR –100 70 IMD3 (dBFS) –120 65 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 23. AD9634-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) with IN Figure 26. AD9634-210 Single-Tone SNR/SFDR vs. Sample Rate (fS) with f = 184.12 MHz, f = 187.12 MHz, f = 210 MSPS IN1 IN2 S fIN = 90 MHz 0 16000 210MSPS 0.391 LSB rms 89.12MHz @ –7.0dBFS 16,384 TOTAL HITS 92.12MHz @ –7.0dBFS 14000 –20 SFDR = 88dBc (95dBFS) 12000 –40 10000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 0 15 30 45 60 75 90 105 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 24. AD9634-210 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 27. AD9634-210 Grounded Input Histogram, f = 210 MSPS S Rev. 0 | Page 15 of 32 AMPLITUDE (dBFS) SFDR/IMD3 (dBc and dBFS) SFDR/IMD3 (dBc and dBFS) 09996-021 09996-020 09996-022 SNR/SFDR (dBFS and dBc) NUMBER OF HITS AMPLITUDE (dBFS) 09996-025 09996-023 09996-024 AD9634 0 0 250MSPS 250MSPS 90.1MHz @ –1.0dBFS 305.1MHz @ –1.0dBFS SNR = 69.0dB (70.0dBFS) SNR = 67.4dB (68.4dBFS) –20 –20 SFDR = 89dBc SFDR = 82dBc –40 –40 –60 –60 SECOND SECOND THIRD THIRD HARMONIC HARMONIC HARMONIC HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 25 50 75 100 125 0 25 50 75 100 125 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. AD9634-250 Single-Tone FFT with fIN = 90.1 MHz Figure 31. AD9634-250 Single-Tone FFT with fIN = 305.1 MHz 0 120 250MSPS 185.1MHz @ –1.0dBFS SFDR (dBFS) SNR = 68.7dB (69.7dBFS) –20 100 SFDR = 87dBc –40 80 SNR (dBFS) –60 THIRD SECOND 60 HARMONIC HARMONIC –80 SFDR (dBc) 40 –100 SNR (dBc) 20 –120 –140 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 01 25 50 75 10025 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 29. AD9634-250 Single-Tone FFT with f = 185.1 MHz Figure 32. AD9634-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with IN fIN = 90.1 MHz, fS = 250 MSPS 100 0 250MSPS 220.1MHz @ –1.0dBFS 95 SNR = 68.3dB (69.3dBFS) –20 SFDR (dBc) SFDR = 91dBc 90 –40 85 –60 SECOND THIRD 80 HARMONIC HARMONIC –80 75 –100 70 SNR (dBFS) –120 65 60 –140 60 90 120 150 180 210 240 270 300 330 0 25 50 75 100 125 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. AD9634-250 Single-Tone SNR/SFDR vs. Input Frequency (f ), Figure 30. AD9634-250 Single-Tone FFT with fIN = 220.1 MHz IN f = 250 MSPS S Rev. 0 | Page 16 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09996-028 09996-027 09996-026 AMPLITUDE (dBFS) SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) 09996-030 09996-029 09996-101 AD9634 0 0 250MSPS 184.12MHz @ –7.0dBFS 187.12MHz @ –7.0dBFS –20 –20 SFDR = 88dBc (95dBFS) SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 01 25 50 75 10025 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 34. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 37. AD9634-250 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS 0 100 SFDR 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 75 SFDR (dBFS) SNR –100 70 IMD3 (dBFS) –120 65 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 40 60 80 100 120 140 160 180 200 220 240 260 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 35. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN Figure 38. AD9634-250 Single-Tone SNR/SFDR vs. Sample Rate (f ) S with f = 184.12 MHz, f = 187.12 MHz, f = 250 MSPS IN1 IN2 S with f = 90 MHz IN 0 16000 250MSPS 0.407 LSB rms 89.12MHz @ –7.0dBFS 16,384 TOTAL HITS –20 92.12MHz @ –7.0dBFS 14000 SFDR = 88dBc (95dBFS) 12000 –40 10000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 0 25 50 75 100 125 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 36. AD9634-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 39. AD9634-250 Grounded Input Histogram, fS = 250 MSPS Rev. 0 | Page 17 of 32 AMPLITUDE (dBFS) SFDR/IMD3 (dBc and dBFS) SFDR/IMD3 (dBc and dBFS) 09996-032 09996-031 09996-033 SNR/SFDR (dBFS and dBc) NUMBER OF HITS AMPLITUDE (dBFS) 09996-036 09996-034 09996-035 AD9634 EQUIVALENT CIRCUITS DRVDD AVDD VIN 350Ω SDIO 26kΩ Figure 43. Equivalent SDIO Circuit Figure 40. Equivalent Analog Input Circuit AVDD AVDD AVDD 0.9V 350Ω SCLK 15kΩ 15kΩ CLK+ 26kΩ CLK– Figure 44. Equivalent SCLK Input Circuit Figure 41. Equivalent Clock lnput Circuit DRVDD AVDD 26kΩ 350Ω V+ V– CSB DATAOUT– DATAOUT+ V– V+ Figure 45. Equivalent CSB Input Circuit Figure 42. Equivalent LVDS Output Circuit Rev. 0 | Page 18 of 32 09996-037 09996-039 09996-038 09996-042 09996-040 09996-041 AD9634 THEORY OF OPERATION In intermediate frequency (IF) undersampling applications, reduce The AD9634 can sample any fS/2 frequency segment from dc to the shunt capacitors. In combination with the driving source 250 MHz using appropriate low-pass or band-pass filtering at impedance, the shunt capacitors limit the input bandwidth. the ADC inputs with little loss in ADC performance. Refer to the AN-742 Application Note, Frequency Domain Programming and control of the AD9634 are accomplished Response of Switched-Capacitor ADCs; the AN-827 Application using a 3-pin, SPI-compatible serial interface. Note, A Resonant Approach to Interfacing Amplifiers to Switched- Capacitor ADCs; and the Analog Dialogue article, “Transformer- ADC ARCHITECTURE Coupled Front-End for Wideband A/D Converters” for more The AD9634 architecture consists of a front-end sample-and- information on this subject. hold circuit, followed by a pipelined, switched-capacitor ADC. BIAS The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined S S C C architecture permits the first stage to operate on a new input S FB VIN+ sample and the remaining stages to operate on the preceding C C PAR1 PAR2 samples. Sampling occurs on the rising edge of the clock. H S S Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digital- C S to-analog converter (DAC) and an interstage residue amplifier VIN– C C PAR1 C FB PAR2 (MDAC). The MDAC magnifies the difference between the S S reconstructed DAC output and the flash input for the next stage BIAS in the pipeline. One bit of redundancy is used in each stage to Figure 46. Switched-Capacitor Input facilitate digital correction of flash errors. The last stage simply For best dynamic performance, match the source impedances consists of a flash ADC. driving VIN+ and VIN− and differentially balance the inputs. The input stage contains a differential sampling circuit that can Input Common Mode be ac- or dc-coupled in differential or single-ended modes. The The analog inputs of the AD9634 are not internally dc biased. In output staging block aligns the data, corrects errors, and passes the ac-coupled applications, the user must provide this bias externally. data to the output buffers. The output buffers are powered from a Setting the device so that V = 0.5 × AVDD (or 0.9 V) is separate supply, allowing digital output noise to be separated from CM the analog core. During power-down, the output buffers go into recommended for optimum performance. An on-board common- a high impedance state. mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input ANALOG INPUT CONSIDERATIONS common mode is recommended. Optimum performance is The analog input to the AD9634 is a differential switched-capacitor achieved when the common-mode voltage of the analog input circuit that has been designed to attain optimum performance is set by the VCM pin voltage (typically 0.5 × AVDD). The when processing a differential input signal. VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Place this The clock signal alternatively switches the input between sample decoupling capacitor close to the pin to minimize the series mode and hold mode (see the configuration shown in Figure 46). resistance and inductance between the part and this capacitor. When the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within ½ clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. Rev. 0 | Page 19 of 32 09996-043 AD9634 Differential Input Configurations C2 R3 Optimum performance can be achieved when driving the R2 VIN+ AD9634 in a differential input configuration. For baseband R1 2V p-p applications, the AD8138, ADA4937-1, and ADA4930-1 49.9Ω C1 ADC differential drivers provide excellent performance and a flexible R2 R1 VCM VIN– interface to the ADC. The output common-mode voltage of the ADA4930-1 is easily 0.1µF R3 0.1µF set with the VCM pin of the AD9634 (see Figure 47), and the C2 driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Figure 48. Differential Transformer-Coupled Configuration 15pF The signal characteristics must be considered when selecting 200Ω a transformer. Most RF transformers saturate at frequencies 33Ω 15Ω below a few megahertz. Excessive signal power can also cause 90Ω VIN– 76.8Ω AVDD VIN core saturation, which leads to distortion. 5pF ADC ADA4930-1 At input frequencies in the second Nyquist zone and above, the 0.1µF 33Ω 15Ω VCM noise performance of most amplifiers is not adequate to achieve VIN+ 120Ω 15pF the true SNR performance of the AD9634. For applications where 200Ω SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49). In this 0.1µF configuration, the input is ac-coupled and the VCM voltage is Figure 47. Differential Input Configuration Using the ADA4930-1 provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω For baseband applications where SNR is a key parameter, impedance to the driver. differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the In the double balun and transformer configurations, the value analog input, connect the VCM voltage to the center tap of the of the input capacitors and resistors is dependent on the input secondary winding of the transformer. frequency and source impedance. Based on these parameters the value of the input resistors and capacitors may need to be adjusted, or some components may need to be removed. Table 9 displays recommended values to set the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. Note that the values given in Table 9 are for the R1, R2, R3, C1, and C2 components shown in Figure 49. Table 9. Example RC Network Frequency Range (MHz) R1 Series (Ω) C1 Differential (pF) R2 Series (Ω) C2 Shunt (pF) R3 Shunt (Ω) 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– R3 0.1µF C2 Figure 49. Differential Double Balun Input Configuration Rev. 0 | Page 20 of 32 09996-044 09996-046 09996-045 AD9634 1000pF 180nH 220nH 1µH 165Ω VPOS 15pF AD8375 5.1pF 3.9pF 301Ω VCM 2.5kΩ║2pF 165Ω 1nF 1µH 1nF 68nH AD9634 180nH 220nH 1000pF NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 50. Differential Input Configuration Using the AD8375 An alternative to using a transformer-coupled input at The RF balun configuration is recommended for clock frequencies frequencies in the second Nyquist zone is to use an amplifier between 125 MHz and 625 MHz, and the RF transformer is with variable gain. The AD8375 digital variable gain amplifier recommended for clock frequencies from 10 MHz to 200 MHz. (DVGA) provides good performance for driving the AD9634. The back-to-back Schottky diodes across the secondary windings Figure 50 shows an example of the AD8375 driving the AD9634 of the transformer limit clock excursions into the AD9634 to through a band-pass antialiasing filter. approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other VOLTAGE REFERENCE portions of the AD9634, while preserving the fast rise and fall times A stable and accurate voltage reference is built into the AD9634. of the signal, which are critical for low jitter performance. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference ® Mini-Circuits ADT1-1WT, 1:1Z voltage changes linearly. ADC 390pF 390pF XFMR CLOCK CLK+ CLOCK INPUT CONSIDERATIONS INPUT 100Ω 50Ω 390pF For optimum performance, the AD9634 sample clock inputs, CLK– CLK+ and CLK−, should be clocked with a differential signal. SCHOTTKY DIODES: The signal is typically ac-coupled into the CLK+ and CLK− pins by HSMS2822 means of a transformer or a passive component configuration. Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz) These pins are biased internally (see Figure 51) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. 25Ω ADC 390pF 390pF AVDD CLOCK CLK+ INPUT 0.9V 390pF 1nF CLK– CLK+ CLK– SCHOTTKY 25Ω DIODES: HSMS2822 4pF 4pF Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz) If a low jitter clock source is not available, another option is to Figure 51. Equivalent Clock Input Circuit ac couple a differential PECL signal to the sample clock input pins as shown in Figure 54. The AD9510, AD9511,AD9512, AD9513, Clock Input Options AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, The AD9634 has a very flexible clock input structure. Clock input AD9523, AD9524, ADCLK905, ADCLK907, and ADCLK925 can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless clock drivers offer excellent jitter performance. of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. 0.1µF 0.1µF Figure 52 and Figure 53 show two preferable methods for clocking CLOCK CLK+ INPUT the AD9634 (at clock rates of up to 625 MHz). A low jitter clock AD95xx, 100Ω ADCLKxxx ADC source is converted from a single-ended signal to a differential 0.1µF PECL DRIVER 0.1µF CLOCK CLK– signal using an RF balun or RF transformer. INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 54. Differential PECL Sample Clock (Up to 625 MHz) Rev. 0 | Page 21 of 32 09996-048 09996-047 09996-057 09996-051 09996-056 AD9634 A third option is to ac couple a differential LVDS signal to the Jitter Considerations sample clock input pins, as shown in Figure 55. The AD9510, High speed, high resolution ADCs are sensitive to the quality AD9511,AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, of the clock input. The degradation in SNR at a given input AD9518, AD9520, AD9522, AD9523, AD9524 clock drivers offer frequency (fIN) due to jitter (tJ) can be calculated by excellent jitter performance. (−SNR /10) 2 LF SNRHF = −10 log[(2π × fIN × tJRMS) + 10 ] In the equation, the rms aperture jitter represents the root- 0.1µF 0.1µF CLOCK mean-square of all jitter sources, which include the clock input, CLK+ INPUT the analog input signal, and the ADC aperture jitter specification. AD95xx 100Ω ADC LVDS DRIVER 0.1µF IF undersampling applications are particularly sensitive to jitter, 0.1µF CLOCK CLK– as shown in Figure 56. INPUT 50kΩ 50kΩ 80 Figure 55. Differential LVDS Sample Clock (Up to 625 MHz) 75 Input Clock Divider The AD9634 contains an input clock divider with the ability to 70 divide the input clock by integer values between 1 and 8. For divide ratios other than 1, the DCS is enabled by default on 65 power-up. 60 Clock Duty Cycle 0.05ps 0.2ps Typical high speed ADCs use both clock edges to generate a 0.5ps 55 1ps variety of internal timing signals and, as a result, may be sensitive to 1.5ps MEASURED clock duty cycle. Commonly, a ±5% tolerance is required on the 50 1 10 100 1000 clock duty cycle to maintain dynamic performance characteristics. INPUT FREQUENCY (MHz) The AD9634 contains a DCS that retimes the nonsampling Figure 56. AD9634-250 SNR vs. Input Frequency and Jitter (falling) edge, providing an internal clock signal with a nominal In cases where aperture jitter may affect the dynamic range of the 50% duty cycle. This allows the user to provide a wide range of AD9634, treat the clock input as an analog signal. In addition, clock input duty cycles without affecting the performance of the use separate power supplies for the clock drivers and the ADC AD9634. output driver to avoid modulating the clock signal with digital Jitter on the rising edge of the input clock is still of paramount noise. Low jitter, crystal controlled oscillators provide the best clock concern and is not reduced by the duty cycle stabilizer. The duty sources. If the clock is generated from another type of source (by cycle control loop does not function for clock rates less than gating, dividing, or another method), it should be retimed by the 40 MHz nominally. The loop has a time constant associated original clock during the last step. with it that must be considered when the clock rate may change Refer to AN-501 Application Note, Aperture Uncertainty and ADC dynamically. A wait time of 1.5 μs to 5 μs is required after a System Performance, and AN-756 Application Note, Sampled dynamic clock frequency increase or decrease before the DCS loop Systems and the Effects of Clock Phase Noise and Jitter, for more is relocked to the input signal. During the time that the loop is information about jitter performance as it relates to ADCs. not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Rev. 0 | Page 22 of 32 09996-052 SNR (dBFS) 09996-054 AD9634 When using the SPI port interface, the user can place the ADC POWER DISSIPATION AND STANDBY MODE in power-down mode or standby mode. Standby mode allows As shown in Figure 57, the power dissipated by the AD9634 is the user to keep the internal reference circuitry powered when proportional to its sample rate. The data in Figure 57 was taken faster wake-up times are required. To put the part into standby using the same operating conditions as those used for the Typical mode, set the internal power-down mode bits (Bits[1:0]) in the Performance Characteristics section. power modes register (Address 0x08) to 10. See the Memory 0.4 0.25 Map section and AN-877 Application Note, Interfacing to High Speed ADCs via SPI for additional details. 0.20 0.3 DIGITAL OUTPUTS TOTAL POWER The AD9634 output drivers can be configured for either ANSI 0.15 LVDS or reduced swing LVDS using a 1.8 V DRVDD supply. 0.2 As detailed in the AN-877 Application Note, Interfacing to High I AVDD 0.10 Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI 0.1 0.05 control. I DRVDD Digital Output Enable Function (OEB) 0 0 The AD9634 has a flexible three-state ability for the digital output 40 55 70 85 100 115 130 145 160 175 190 205 220 235 250 ENCODE FREQUENCY (MSPS) pins. The three-state mode is enabled using the SPI interface. Figure 57. AD9634-250 Power and Current vs. Sample Rate The data outputs can be three-stated by using the output enable bar bit (Bit 4) in Register 0x14. This OEB function is not intended By setting the internal power-down mode bits (Bits[1:0]) in the for rapid access to the data bus. power modes register (Address 0x08) to 01, the AD9634 is placed in power-down mode. In this state, the ADC typically dissipates Timing 5 mW. During power-down, the output drivers are placed in a The AD9634 provides latched data with a pipeline delay of 10 input high impedance state. sample clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. Low power dissipation in power-down mode is achieved by PD shutting down the reference, reference buffer, biasing networks, Minimize the length of the output data lines as well as the loads and clock. Internal capacitors are discharged when entering power- placed on these lines to reduce transients within the AD9634. down mode and then must be recharged when returning to These transients may degrade converter dynamic performance. normal operation. As a result, wake-up time is related to the The lowest typical conversion rate of the AD9634 is 40 MSPS. At time spent in power-down mode, and shorter power-down clock rates below 40 MSPS, dynamic performance can degrade. cycles result in proportionally shorter wake-up times. Data Clock Output (DCO) The AD9634 also provides the data clock output (DCO) intended for capturing the data in an external register. Figure 2 shows timing diagram of the AD9634 output modes. ADC OVERRANGE (OR) The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange condition is determined at the output of the ADC pipeline and, therefore, is subject to a latency of 10 ADC clock cycles. An overrange at the input is indicated by this bit 10 clock cycles after it occurs. Table 10. Output Data Format Input (V) VIN+ − VIN−, Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR VIN+ − VIN− < −0.875 0000 0000 0000 1000 0000 0000 1 VIN+ − VIN− = −0.875 0000 0000 0000 1000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +0.875 1111 1111 1111 0111 1111 1111 0 VIN+ − VIN− > +0.875 1111 1111 1111 0111 1111 1111 1 Rev. 0 | Page 23 of 32 TOTAL POWER (W) SUPPLY CURRENT (A) 09996-053 AD9634 SERIAL PORT INTERFACE (SPI) The AD9634 serial port interface (SPI) allows the user to configure All data is composed of 8-bit words. The first bit of each individual the converter for specific functions or operations through a byte of serial data indicates whether a read or write command is structured register space provided inside the ADC. The SPI offers issued. This allows the serial data input/output (SDIO) pin to added flexibility and customization, depending on the application. change direction from an input to an output. Addresses are accessed via the serial port and can be written to In addition to word length, the instruction phase determines or read from via the port. Memory is organized into bytes that can whether the serial frame is a read or write operation, allowing be further divided into fields. These fields are documented in the the serial port to be used both to program the chip and to read Memory Map section. For detailed operational information, see the contents of the on-chip memory. If the instruction is a readback the AN-877 Application Note, Interfacing to High Speed ADCs operation, performing a readback causes the serial data input/ via SPI. output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO Data can be sent in MSB-first mode or in LSB-first mode. MSB- first mode is the default on power-up and can be changed via pin, and the CSB pin (see Table 11). The SCLK (serial clock) pin the SPI port configuration register. For more information about is used to synchronize the read and write data presented from this and other features, see the AN-877 Application Note, and to the ADC. The SDIO (serial data input/output) pin is a Interfacing to High Speed ADCs via SPI. dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) HARDWARE INTERFACE pin is an active-low control that enables or disables the read and The pins described in Table 11 comprise the physical interface write cycles. between the user programming device and the serial port of the Table 11. Serial Port Interface Pins AD9634. The SCLK pin and the CSB pin function as inputs when Pin Function using the SPI interface. The SDIO pin is bidirectional, functioning SCLK Serial clock. The serial shift clock input, which is used to as an input during write phases and as an output during readback. synchronize serial interface reads and writes. The SPI interface is flexible enough to be controlled by either SDIO Serial data input/output. A dual-purpose pin that FPGAs or microcontrollers. One method for SPI configuration typically serves as an input or an output, depending on is described in detail in the AN-812 Application Note, the instruction being sent and the relative position in the timing frame. Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. CSB Chip select bar. An active-low control that gates the read The SPI port should not be active during periods when the full and write cycles. dynamic performance of the converter is required. Because the The falling edge of CSB, in conjunction with the rising edge of SCLK signal, the CSB signal, and the SDIO signal are typically SCLK, determines the start of the framing. An example of the serial asynchronous to the ADC clock, noise from these signals can timing and its definitions can be found in Figure 58 and Table 5. degrade converter performance. If the on-board SPI bus is used for Other modes involving the CSB are available. The CSB can be other devices, it may be necessary to provide buffers between held low indefinitely, which permanently enables the device; this bus and the AD9634 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Rev. 0 | Page 24 of 32 AD9634 Table 12. Features Accessible Using the SPI SPI ACCESSIBLE FEATURES Feature Name Description Table 12 provides a brief description of the general features that Mode Allows the user to set either power-down mode are accessible via the SPI. These features are described in detail in or standby mode AN-877 Application Note, Interfacing to High Speed ADCs via Clock Allows the user to access the DCS via the SPI SPI. Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Digital Allows the user to enable the synchronization Processing features t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. 0 | Page 25 of 32 09996-055 AD9634 MEMORY MAP Default Values READING THE MEMORY MAP REGISTER TABLE After the AD9634 is reset, critical registers are loaded with Each row in the memory map register table has eight bit default values. The default values for the registers are given in locations. The memory map is roughly divided into three the memory map register table (see Table 13). sections: the chip configuration registers (Address 0x00 to Address 0x02), the transfer register (Address 0xFF), and the Logic Levels ADC functions registers (Address 0x08 to Address 0x25), An explanation of logic level terminology follows: including setup, control, and test. • “Bit is set” is synonymous with “bit is set to Logic 1” or The memory map register table (Table 13) documents the “writing Logic 1 for the bit.” default hexadecimal value for each hexadecimal address shown. • “Clear a bit” is synonymous with “bit is set to Logic 0” or The Bit 7 (MSB) column is the start of the default hexadecimal “writing Logic 0 for the bit.” value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1 Transfer Register Map and the remaining bits are 0s. This setting is the default output Address 0x08 to Address 0x20 are shadowed. Writes to these format value, which is twos complement. For more information addresses do not affect part operation until a transfer command is on this function and others, see the AN-877 Application Note, issued by writing 0x01 to Address 0xFF, setting the transfer bit. This Interfacing to High Speed ADCs via SPI. This document details allows these registers to be updated internally and simultaneously the functions controlled by Register 0x00 to Register 0x25. when the transfer bit is set. The internal update takes place Open Locations when the transfer bit is set, and then the bit autoclears. All address and bit locations that are not included in Table 13 are not currently supported for this device. Write 0s to unused bits of a valid address location. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), do not write to this address location. Rev. 0 | Page 26 of 32 AD9634 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are configuration mirrored so that LSB- first mode or MSB-first mode is set correctly, regardless of shift mode. 0x01 Chip ID 8-bit chip ID[7:0], AD9634 = 0x87 (default) 0x87 Read only. 0x02 Chip grade Open Open Speed grade ID; Open Open Open Open Speed grade ID 00 = 250 MSPS used to 01 = 210 MSPS differentiate 11 = 170 MSPS devices; read only. Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchro- nously transfers data from the master shift register to the slave. ADC Function Registers 0x08 Power modes Open Open Open Open Open Open Internal power-down mode 0x00 Determines various 00 = normal operation generic 01 = full power-down modes of 10 = standby chip 11 = reserved operation. 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (default) 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide values other 000 = no delay 000 = divide by 1 than 000 001 = 1 input clock cycle 001 = divide by 2 auto- 010 = 2 input clock cycles 010 = divide by 3 matically 011 = 3 input clock cycles 011 = divide by 4 cause the 100 = 4 input clock cycles 100 = divide by 5 duty cycle 101 = 5 input clock cycles 101 = divide by 6 stabilizer to 110 = 6 input clock cycles 110 = divide by 7 become 111 = 7 input clock cycles 111 = divide by 8 active. 0x0D Test mode Test mode Open Reset PN Reset PN Output test mode 0x00 When this long gen short gen register is 0 = contin- 0000 = off (default) set, the test uous/ 0001 = midscale short data is repeat 0010 = positive FS placed on pattern 0011 = negative FS the output 1 = single 0100 = alternating checkerboard pins in pattern 0101 = PN long sequence place of then zeros 0110 = PN short sequence normal 0111 = one/zero word toggle data. 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output Rev. 0 | Page 27 of 32 AD9634 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (twos complement format) 0x14 Output mode Open Open Open Output Open Output Output format 0x01 Configures enable bar invert 00 = offset binary the outputs 0 = on 0 = normal 01 = twos complement and the (default) (default) (default) format of 1 = off 1 = 10 = gray code the data. inverted 11 = reserved 0x15 Output adjust Open Open Open Open LVDS output drive current adjust 0x01 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved 0x16 Clock phase Invert Open Open Open Open Open Open Open 0x00 control DCO clock 0x17 DCO output Enable Open Open DCO clock delay 0x00 delay DCO [delay = (3100 ps × register value/31 + 100)] clock 00000 = 100 ps delay 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps 0x18 Input span Open Open Open Full-scale input voltage selection 0x00 Full-scale select input 01111 = 2.087 V p-p adjustment … in 0.022 V 00001 = 1.772 V p-p steps. 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1[7:0] 0x00 Pattern 1 LSB 0x1A User Test User Test Pattern 1[15:8] 0x00 Pattern 1 MSB 0x1B User Test User Test Pattern 2[7:0] 0x00 Pattern 2 LSB 0x1C User Test Pattern 2[15:8] User Test 0x00 Pattern 2 MSB 0x1D User Test User Test Pattern 3[7:0] 0x00 Pattern 3 LSB 0x1E User Test User Test Pattern 3[15:8] 0x00 Pattern 3 MSB 0x1F User Test User Test Pattern 4[7:0] 0x00 Pattern 4 LSB 0x20 User Test User Test Pattern 4[15:8] 0x00 Pattern 4 MSB 0x24 BIST signature BIST signature[7:0] 0x00 Read only. LSB 0x25 BIST signature BIST signature[15:8] 0x00 Read only. MSB Rev. 0 | Page 28 of 32 AD9634 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting system-level design and layout of the AD9634, it the bottom of the PCB. These vias should be filled or plugged with is recommended that the designer become familiar with these nonconductive epoxy. guidelines, which describe the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements needed for certain pins. the PCB, overlay a silkscreen to partition the continuous plane on Power and Ground Recommendations the PCB into several uniform sections. This provides several tie When connecting power to the AD9634, it is recommended that points between the ADC and the PCB during the reflow process. two separate 1.8 V supplies be used: use one supply for analog Using one continuous plane with no partitions guarantees only one (AVDD) and a separate supply for digital outputs (DRVDD). tie point between the ADC and the PCB. See the evaluation The designer can employ several different decoupling capacitors board for a PCB layout example. For detailed information about to cover both high and low frequencies. Locate these capacitors the packaging and PCB layout of chip scale packages, refer to close to the point of entry at the PC board level and close to the the AN-772 Application Note, A Design and Manufacturing pins of the part with minimal trace length. Guide for the Lead Frame Chip Scale Package (LFCSP). A single PCB ground plane should be sufficient when using the VCM AD9634. With proper decoupling and smart partitioning of the Decouple the VCM pin to ground with a 0.1 μF capacitor, as PCB analog, digital, and clock sections, optimum performance shown in Figure 48. can be easily achieved. SPI Port Exposed Paddle Thermal Heat Slug Recommendations The SPI port should not be active during periods when the full It is mandatory that the exposed paddle on the underside of the dynamic performance of the converter is required. Because the ADC be connected to analog ground (AGND) to achieve the SCLK, CSB, and SDIO signals are typically asynchronous to the best electrical and thermal performance. A continuous, exposed ADC clock, noise from these signals can degrade converter (no solder mask) copper plane on the PCB should be connected performance. If the on-board SPI bus is used for other devices, to the AD9634 exposed paddle, Pin 0. it may be necessary to provide buffers between this bus and the AD9634 to keep these signals from transitioning at the converter input pins during critical sampling periods. Rev. 0 | Page 29 of 32 AD9634 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 32 25 1 24 0.50 BSC * 3.75 EXPOSED PAD 3.60 SQ 3.55 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9634BCPZ-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634BCPZRL7-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634BCPZ-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634BCPZRL7-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634BCPZ-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634BCPZRL7-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9634-170EBZ Evaluation Board with AD9634 and Software AD9634-210EBZ Evaluation Board with AD9634 and Software AD9634-250EBZ Evaluation Board with AD9634 and Software 1 Z = RoHS Compliant Part. Rev. 0 | Page 30 of 32 PIN 1 INDICATOR 08-16-2010-B AD9634 NOTES Rev. 0 | Page 31 of 32 AD9634 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09996-0-7/11(0) Rev. 0 | Page 32 of 32