ANALOG DEVICES AD9633

Quad, 12-Bit, 80 MSPS/105 MSPS/ 125 MSPS, Serial LVDS 1.8 V ADC Data Sheet AD9633 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD 1.8 V supply operation 12 Low power: 100 mW per channel at 125 MSPS with scalable SERIAL D0+A VIN+A LVDS PIPELINE DIGITAL D0–A power options ADC SERIALIZER VIN–A D1+A SERIAL LVDS SNR = 71 dB (to Nyquist) 12 D1–A VIN+B PIPELINE DIGITAL SERIAL D0+B SFDR = 91 dBc (to Nyquist) VIN–B ADC SERIALIZER LVDS D0–B RBIAS DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical) SERIAL D1+B VREF LVDS D1–B Serial LVDS (ANSI-644, default) and low power, reduced SENSE FCO+ 1V AD9633 signal option (similar to IEEE 1596.3) REF FCO– SELECT D0+C 650 MHz full power analog bandwidth SERIAL AGND LVDS 12 D0–C 2 V p-p input voltage range VIN+C DIGITAL PIPELINE D1+C SERIAL SERIALIZER ADC VIN–C LVDS Serial port control D1–C 12 D0+D SERIAL Full chip and individual channel power-down modes VIN+D LVDS DIGITAL D0–D PIPELINE SERIALIZER Flexible bit orientation VIN–D ADC SERIAL D1+D LVDS D1–D Built-in and custom digital test pattern generation SERIAL PORT DCO+ CLOCK INTERFACE Multichip sync and clock divider VCM MANAGEMENT DCO– Programmable output clock and data alignment Programmable output resolution Standby mode APPLICATIONS Figure 1. Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers The ADC contains several features designed to maximize Test equipment flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern GENERAL DESCRIPTION generation. The available digital test patterns include built-in The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS deterministic and pseudorandom patterns, along with custom user- analog-to-digital converter (ADC) with an on-chip sample-and- defined test patterns entered via the serial port interface (SPI). hold circuit designed for low cost, low power, small size, and The AD9633 is available in a RoHS-compliant, 48-lead LFCSP. ease of use. The product operates at a conversion rate of up to It is specified over the industrial temperature range of −40°C to 125 MSPS and is optimized for outstanding dynamic performance +85°C. This product is protected by a U.S. patent. and low power in applications where a small package size is critical. PRODUCT HIGHLIGHTS 1. Small Footprint. Four ADCs are contained in a small, space- The ADC requires a single 1.8 V power supply and LVPECL-/ saving package. CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are 2. Low power of 100 mW/channel at 125 MSPS with scalable required for many applications. power options. 3. Pin compatible to the AD9253 14-bit quad ADC. The ADC automatically multiplies the sample rate clock for the 4. Ease of Use. A data clock output (DCO) operates at appropriate LVDS serial data rate. A data clock output (DCO) for frequencies of up to 375 MHz and supports double data capturing data on the output and a frame clock output (FCO) rate (DDR) operation. for signaling a new output byte are provided. Individual-channel 5. User Flexibility. The SPI control offers a wide range of flexible power-down is supported and typically consumes less than 2 mW features to meet specific system requirements. when all channels are disabled. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CSB SDIO/OLM SCLK/DTP SYNC CLK+ CLK– 10073-001 AD9633 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Clock Input Considerations...................................................... 24  Applications....................................................................................... 1  Power Dissipation and Power-Down Mode ........................... 26  General Description ......................................................................... 1  Digital Outputs and Timing ..................................................... 27  Functional Block Diagram .............................................................. 1  Output Test Modes..................................................................... 30  Product Highlights ........................................................................... 1  Serial Port Interface (SPI).............................................................. 31  Revision History ............................................................................... 2  Configuration Using the SPI..................................................... 31  Specifications..................................................................................... 3  Hardware Interface..................................................................... 32  DC Specifications ......................................................................... 3  Configuration Without the SPI ................................................ 32  AC Specifications.......................................................................... 4  SPI Accessible Features.............................................................. 32  Digital Specifications ................................................................... 5  Memory Map .................................................................................. 33  Switching Specifications .............................................................. 6  Reading the Memory Map Register Table............................... 33  Timing Specifications .................................................................. 7  Memory Map Register Table..................................................... 34  Absolute Maximum Ratings.......................................................... 11  Memory Map Register Descriptions........................................ 37  Thermal Resistance .................................................................... 11  Applications Information .............................................................. 39  ESD Caution................................................................................ 11  Design Guidelines ...................................................................... 39  Pin Configuration and Function Descriptions........................... 12  Power and Ground Recommendations ................................... 39  Typical Performance Characteristics ........................................... 14  Exposed Pad Thermal Heat Slug Recommendations............ 39  AD9633-80 .................................................................................. 14  VCM............................................................................................. 39  AD9633-105 ................................................................................ 16  Reference Decoupling................................................................ 39  AD9633-125 ................................................................................ 18  SPI Port........................................................................................ 39  Equivalent Circuits ......................................................................... 21  Crosstalk Performance .............................................................. 39  Theory of Operation ...................................................................... 22  Outline Dimensions....................................................................... 40  Analog Input Considerations.................................................... 22  Ordering Guide .......................................................................... 40  Voltage Reference ....................................................................... 23  REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 40 Data Sheet AD9633 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. AD9633-80 AD9633-105 AD9633-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 % FSR Gain Error Full −10 −5 0 −10 −5 0 −10 −5 0 % FSR Gain Matching Full 1 1.5 1 1.8 1 1.5 % FSR Differential Nonlinearity (DNL) Full −0.6 +0.6 −0.6 +0.6 −0.6 +0.6 LSB 25°C ±0.3 ±0.3 ±0.3 LSB Integral Nonlinearity (INL) Full −1.4 +1.6 −1.4 +1.6 −1.4 +1.6 LSB 25°C ±0.5 ±0.5 ±0.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.0 1.02 0.98 1.0 1.02 0.98 1.0 1.02 V Load Regulation at 1.0 mA (V = 1 V) Full 2 2 2 mV REF Input Resistance Full 7.5 7.5 7.5 kΩ INPUT-REFERRED NOISE V = 1.0 V 25°C 0.25 0.25 0.25 LSB rms REF ANALOG INPUTS Differential Input Voltage (V = 1 V) Full 2 2 2 V p-p REF Common-Mode Voltage Full 0.9 0.9 0.9 V Differential Input Resistance 5.2 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 2 IAVDD Full 125 136 151 166 173 191 mA 2 I (ANSI-644 Mode) Full 59 80 63 97 66 101 mA DRVDD 2 I (Reduced Range Mode) 25°C 40 43 46 mA DRVDD TOTAL POWER CONSUMPTION DC Input Full 313 360 400 mW Sine Wave Input (Four Channels Including Full 331 389 385 473 430 526 mW Output Drivers ANSI-644 Mode) Sine Wave Input (Four Channels Including 25°C 297 349 394 mW Output Drivers Reduced Range Mode) Power-Down Full 2 2 2 mW 3 Standby Full 174 202 226 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. Rev. 0 | Page 3 of 40 AD9633 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. AD9633-80 AD9633-105 AD9633-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 71.7 71.7 71.8 dBFS IN fIN = 30.5 MHz 25°C 71.7 71.6 71.4 dBFS fIN = 70 MHz Full 70.0 70.5 70.2 71.0 70.5 71.1 dBFS f = 140 MHz 25°C 70.3 70.2 70.0 dBFS IN fIN = 200 MHz 25°C 69.4 69.8 69.4 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz 25°C 71.6 71.6 71.1 dBFS f = 30.5 MHz 25°C 71.5 71.5 71.3 dBFS IN fIN = 70 MHz Full 69.0 70.4 68.5 70.9 69.5 71.0 dBFS f = 140 MHz 25°C 70.2 69.9 69.9 dBFS IN fIN = 200 MHz 25°C 68.4 68.7 67.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.6 11.6 11.5 Bits f = 30.5 MHz 25°C 11.6 11.6 11.5 Bits IN fIN = 70 MHz Full 11.5 11.6 11.5 Bits fIN = 140 MHz 25°C 11.4 11.3 11.3 Bits f = 200 MHz 25°C 11.2 11.2 10.9 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 96 94 94 dBc fIN = 30.5 MHz 25°C 90 89 91 dBc f = 70 MHz Full 76 96 75 87 75 91 dBc IN fIN = 140 MHz 25°C 87 91 86 dBc f = 200 MHz 25°C 86 88 86 dBc IN WORST HARMONIC (SECOND OR THIRD) f = 9.7 MHz 25°C −96 −94 −94 dBc IN fIN = 30.5 MHz 25°C −90 −89 −91 dBc f = 70 MHz Full −96 −76 −87 −75 −91 −75 dBc IN fIN = 140 MHz 25°C −87 −91 −86 dBc fIN = 200 MHz 25°C −86 −88 −86 dBc WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD) f = 9.7 MHz 25°C −98 −97 −95 dBFS IN fIN = 30.5 MHz 25°C −96 −94 −98 dBFS fIN = 70 MHz Full −97 −82 −95 −82 −97 −84 dBFS f = 140 MHz 25°C −98 −94 −93 dBFS IN fIN = 200 MHz 25°C −97 −94 −91 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS f = 70.5 MHz, f = 72.5 MHz 25°C 85 86 87 dBc IN1 IN2 2 CROSSTALK Full −95 −95 −95 dB 3 CROSSTALK (OVERRANGE CONDITION) 25°C −89 −89 −89 dB 1, 4 POWER SUPPLY REJECTION RATIO (PSRR) AVDD 25°C 52 52 52 dB DRVDD 25°C 75 75 75 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is specified with 3 dB of the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. Rev. 0 | Page 4 of 40 Data Sheet AD9633 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. 1 Parameter Temp Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 10 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF 3 LOGIC OUTPUT (SDIO) Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) Full 290 345 400 mV Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Twos complement DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (V) Full 160 200 230 mV OD Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Twos complement 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO/OLM pins sharing the same connection. Rev. 0 | Page 5 of 40 AD9633 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. 1, 2 Parameter Temp Min Typ Max Unit 3 CLOCK Input Clock Rate Full 10 1000 MHz Conversion Rate Full 10 80/105/125 MSPS Clock Pulse Width High (tEH) Full 6.25/4.76/4.00 ns Clock Pulse Width Low (t) Full 6.25/4.76/4.00 ns EL 3 OUTPUT PARAMETERS Propagation Delay (t ) Full 2.3 ns PD Rise Time (t ) (20% to 80%) Full 300 ps R Fall Time (t ) (20% to 80%) Full 300 ps F FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns 4 DCO Propagation Delay (tCPD) Full tFCO + (tSAMPLE/12) ns 4 DCO to Data Delay (tDATA) Full (tSAMPLE/12) − 300 (tSAMPLE/12) (tSAMPLE/12) + 300 ps 4 DCO to FCO Delay (t ) Full (t /12) − 300 (t /12) (t /12) + 300 ps FRAME SAMPLE SAMPLE SAMPLE Lane Delay (t ) 90 ps LD Data to Data Skew (t − t ) Full ±50 ±200 ps DATA-MAX DATA-MIN Wake-Up Time (Standby) 25°C 250 ns 5 Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, t) 25°C 135 fs rms J Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 tSAMPLE/12 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. 0 | Page 6 of 40 Data Sheet AD9633 TIMING SPECIFICATIONS Table 5. Unit Parameter Description Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS See Figure 73 tDS Setup time between the data and the rising edge of SCLK 2 ns min t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min t Time required for the SDIO pin to switch from an input to an output relative to the 10 ns min EN_SDIO SCLK falling edge (not shown in Figure 73) t 10 ns min DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 73) Timing Diagrams Refer to the Memory Map Register Descriptions section and Table 21 for SPI register settings. N – 1 VIN±x N + 1 t A N t t EH EL CLK– CLK+ t CPD DCO– DDR DCO+ DCO– SDR DCO+ t FRAME t FCO FCO– FCO+ t t DATA PD D0–A BITWISE D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 MODE D0+A t LD D1–A MSB D09 D07 D05 D03 D01 MSB D09 D07 D05 D03 D01 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1+A FCO– FCO+ D0–A BYTEWISE D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 MODE D0+A D1–A MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1+A Figure 2. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) Rev. 0 | Page 7 of 40 10073-004 AD9633 Data Sheet N – 1 VIN±x N t A N + 1 t t EH EL CLK– CLK+ t CPD DCO– DDR DCO+ DCO– SDR DCO+ t FRAME t FCO FCO– FCO+ t t DATA PD D0–A BITWISE D08 D06 D04 D02 LSB D08 D06 D04 D02 LSB D08 D06 D04 D02 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 MODE D0+A t LD D1–A MSB D07 D05 D03 D01 MSB D07 D05 D03 D01 MSB D07 D05 D03 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A FCO– FCO+ D0–A BYTEWISE D04 D03 D02 D01 LSB D0 D04 4 D03 D02 D01 LSB D04 D03 D02 D01 N – 17 N – 17 N – 17 N – 17 N – 17 N N – 16 – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 MODE D0+A D1–A MSB D08 D07 D06 D05 MSB D08 D07 D06 D05 MSB D08 D07 D06 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A Figure 3. 10-Bit DDR/SDR, Two-Lane, 1× Frame Mode N – 1 VIN±x N + 1 t A N t t EH EL CLK– CLK+ t CPD DCO– DDR DCO+ DCO– SDR DCO+ t FRAME t FCO FCO– FCO+ t t DATA PD D0–A BITWISE D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0+A t LD D1–A MSB D09 D07 D05 D03 D01 MSB D09 D07 D05 D03 D01 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1+A FCO– FCO+ D0–A BYTEWISE D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0+A D1–A MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1+A Figure 4. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode Rev. 0 | Page 8 of 40 10073-006 10073-085 Data Sheet AD9633 N – 1 VIN±x N t A N + 1 t t EH EL CLK– CLK+ t CPD DCO– DDR DCO+ DCO– SDR DCO+ t FRAME t FCO FCO– FCO+ t t PD DATA D0–A BITWISE D08 D06 D04 D02 LSB D08 D06 D04 D02 LSB D08 D06 D04 D02 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D0+A t LD D1–A MSB D07 D05 D03 D01 MSB D07 D05 D03 D01 MSB D07 D05 D03 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A FCO– FCO+ D0–A BYTEWISE D04 D03 D02 D01 LSB D0 D04 4 D03 D02 D01 LSB D04 D03 D02 D01 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N N – 16 – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D0+A D1–A MSB D08 D07 D06 D05 MSB D08 D07 D06 D05 MSB D08 D07 D06 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A Figure 5. 10-Bit DDR/SDR, Two-Lane, 2× Frame Mode N – 1 VIN±x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t t DATA PD D0–x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N–17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 D0+x Figure 6. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode Rev. 0 | Page 9 of 40 10073-082 10073-086 AD9633 Data Sheet N – 1 VIN±x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t t DATA PD D0–x MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5 N–9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 N – 8 N – 8 N – 8 D0+x Figure 7. Wordwise DDR, One-Lane, 1× Frame, 10-Bit Output Mode CLK+ t t SSYNC HSYNC SYNC Figure 8. SYNC Input Timing Requirements Rev. 0 | Page 10 of 40 10073-079 10073-084 Data Sheet AD9633 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating Table 7. Thermal Resistance Electrical Air Flow Velocity AVDD to AGND −0.3 V to +2.0 V 1 Package Type (m/sec) θJA θJB θJC Unit DRVDD to AGND −0.3 V to +2.0 V 48-Lead LFCSP 0.0 23.7 7.8 7.1 °C/W Digital Outputs (D0±x, D1±x, DCO+, −0.3 V to +2.0 V 7 mm × 7 mm 1.0 20.0 N/A N/A °C/W DCO−, FCO+, FCO−) to AGND CP-48-13 2.5 18.7 N/A N/A °C/W CLK+, CLK− to AGND −0.3 V to +2.0 V VIN+x, VIN−x to AGND −0.3 V to +2.0 V 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad SCLK/DTP, SDIO/OLM, CSB to AGND −0.3 V to +2.0 V soldered to PCB. SYNC, PDWN to AGND −0.3 V to +2.0 V RBIAS to AGND −0.3 V to +2.0 V ESD CAUTION VREF, SENSE to AGND −0.3 V to +2.0 V Environmental Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 11 of 40 AD9633 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN+D 1 36 VIN+A 2 35 VIN–A VIN–D AVDD 3 34 AVDD AVDD 4 33 PDWN CLK– 5 AD9633 32 CSB 6 CLK+ 31 SDIO/OLM TOP VIEW 7 SCLK/DTP AVDD 30 (Not to Scale) DRVDD 8 29 DRVDD D1–D 9 28 D0+A D1+D 10 27 D0–A D0–D 11 26 D1+A D0+D 12 25 D1–A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 9. 48-Lead LFCSP Pin Configuration, Top View Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND, Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides Exposed Pad the analog ground for the part. This exposed pad must be connected to ground for proper operation. 1 VIN+D ADC D Analog Input True. 2 VIN−D ADC D Analog Input Complement. 3, 4, 7, 34, 39, 45, 46 AVDD 1.8 V Analog Supply Pins. 5, 6 CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 8, 29 DRVDD Digital Output Driver Supply. 9, 10 D1−D, D1+D Channel D Digital Outputs. 11, 12 D0−D, D0+D Channel D Digital Outputs. 13, 14 D1−C, D1+C Channel C Digital Outputs. 15, 16 D0−C, D0+C Channel C Digital Outputs. 17, 18 DCO−, DCO+ Data Clock Outputs. 19, 20 FCO−, FCO+ Frame Clock Outputs. 21, 22 D1−B, D1+B Channel B Digital Outputs. 23, 24 D0−B, D0+B Channel B Digital Outputs. 25, 26 D1−A, D1+A Channel A Digital Outputs. 27, 28 D0−A, D0+A Channel A Digital Outputs. 30 SCLK/DTP SPI Clock Input/Digital Test Pattern. 31 SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. 32 CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up. 33 PDWN Digital Input, 30 kΩ Internal Pull-Down. PDWN high = power-down device. PDWN low = run device, normal operation. 35 VIN−A ADC A Analog Input Complement. 36 VIN+A ADC A Analog Input True. 37 VIN+B ADC B Analog Input True. 38 VIN−B ADC B Analog Input Complement. 40 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 41 SENSE Reference Mode Selection. 42 VREF Voltage Reference Input and Output. Rev. 0 | Page 12 of 40 10073-007 D1–C 13 48 VIN+C D1+C 14 47 VIN–C D0–C 15 46 AVDD D0+C 16 45 AVDD 17 DCO– 44 SYNC DCO+ 18 43 VCM FCO– 19 42 VREF FCO+ 20 41 SENSE D1–B 21 40 RBIAS 39 D1+B 22 AVDD D0–B 23 38 VIN–B D0+B 24 37 VIN+B Data Sheet AD9633 Pin No. Mnemonic Description 43 VCM Analog Input Common-Mode Voltage. 44 SYNC Digital Input. SYNC input to clock divider. 47 VIN−C ADC C Analog Input Complement. 48 VIN+C ADC C Analog Input True. Rev. 0 | Page 13 of 40 AD9633 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9633-80 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 71.7dB SNR = 69.3dB –20 –20 ENOB = 11.4 BITS ENOB = 11.3 BITS SFDR = 96.4dBc SFDR = 87.5dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 01 5 0 152025 30 35 40 0 5 10 152025 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Single-Tone 16k FFT with f = 140 MHz, f = 80 MSPS IN SAMPLE Figure 10. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 80 MSPS 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 69.7dB SNR = 70.6dB –20 –20 ENOB = 10.9 BITS ENOB = 11.4 BITS SFDR = 85.8dBc SFDR = 90dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 01 5 0 152025 30 35 40 01 5 0 152025 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Single-Tone 16k FFT with fIN = 200 MHz, fSAMPLE = 80 MSPS Figure 11. Single-Tone 16k FFT with f = 30.5 MHZ, f = 80 MSPS IN SAMPLE 120 0 AIN = –1dBFS SNR = 70.5dB SFDRFS 100 –20 ENOB = 11.4 BITS SFDR = 96.5dBc –40 80 SNRFS –60 SFDR 60 –80 40 SNR –100 20 –120 0 –140 –70 –60 –50 –40 –30 –20 –10 0 01 5 0 152025 30 35 40 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 80 MSPS Figure 12. Single-Tone 16k FFT with f = 70 MHz, f = 80 MSPS IN SAMPLE Rev. 0 | Page 14 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-017 10073-089 10073-016 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-019 10073-018 10073-030 Data Sheet AD9633 0 100 AIN1 AND AIN2 = –7dBFS SFDR = 84.6dBc 90 –20 IMD2 = 94.7dBc SFDR (dBc) IMD3 = 84.6dBc 80 –40 70 SNR (dBFS) 60 –60 50 –80 40 30 –100 20 –120 10 –140 0 01 50 152025 30 35 40 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 16. Two-Tone 16k FFT with f = 70.5 MHz and f = 72.5 MHz, IN1 IN2 Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 80 MSPS f = 80 MSPS SAMPLE 100 0 SFDR (dBc) 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 SFDR (dBFS) 75 –100 SNR (dBFS) IMD3 (dBFS) 70 –120 –40 –15 103560 85 –90 –78 –66 –54 –42 –30 –18 –6 TEMPERATURE (°C) INPUT AMPLITUDE (dBFS) Figure 19. SNR/SFDR vs. Temperature, f = 10.3 MHz, f = 80 MSPS IN SAMPLE Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 70.5 MHz and f = 72.5 MHz, f = 80 MSPS IN1 IN2 SAMPLE Rev. 0 | Page 15 of 40 SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) 10073-033 10073-036 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10073-042 10073-039 AD9633 Data Sheet AD9633-105 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 71.7dB SNR = 70.3dB –20 –20 ENOB = 11.4 BITS ENOB = 11.3 BITS SFDR = 94.7dBc SFDR = 90.6dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 10 203040 50 0 10203040 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 105 MSPS Figure 23. Single-Tone 16k FFT with fIN = 140 MHz, fSAMPLE = 105 MSPS 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 70.6dB SNR = 69.8dB –20 –20 ENOB = 11.4 BITS ENOB = 10.9 BITS SFDR = 89.1dBc SFDR = 87.9dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 10 203040 50 0 10203040 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. Single-Tone 16k FFT with fIN = 30.5 MHZ, fSAMPLE = 105 MSPS Figure 24. Single-Tone 16k FFT with f = 200 MHz, f = 105 MSPS IN SAMPLE 0 120 AIN = –1dBFS SNR = 71.1dB SFDRFS –20 ENOB = 11.4 BITS 100 SFDR = 87.9dBc –40 80 SNRFS –60 SFDR 60 –80 SNR 40 –100 20 –120 –140 0 0 10 203040 50 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 22. Single-Tone 16k FFT with f = 70 MHz, f = 105 MSPS IN SAMPLE Figure 25. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 105 MSPS Rev. 0 | Page 16 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-021 10073-090 10073-020 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-023 10073-022 10073-031 Data Sheet AD9633 0 100 AIN1 AND AIN2 = –7dBFS 90 SFDR = 85.8dBc –20 SFDR (dBc) IMD2 = 92.9dBc 80 IMD3 = 85.8dBc –40 70 SNR (dBFS) 60 –60 50 –80 40 30 –100 20 –120 10 –140 0 0 10 203040 50 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 26. Two-Tone 16k FFT with f = 70.5 MHz and f = 72.5 MHz, IN1 IN2 Figure 28. SNR/SFDR vs. fIN, fSAMPLE = 105 MSPS f = 105 MSPS SAMPLE 100 0 SFDR (dBc) 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 –60 80 –80 SFDR (dBFS) 75 SNR (dBFS) –100 IMD3 (dBFS) 70 –120 –40 –15 10 35 60 85 –90 –78 –66 –54 –42 –30 –18 –6 TEMPERATURE (°C) INPUT AMPLITUDE (dBFS) Figure 29. SNR/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 105 MSPS Figure 27. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 70.5 MHz and f = 72.5 MHz, f = 105 MSPS IN1 IN2 SAMPLE Rev. 0 | Page 17 of 40 SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) 10073-034 10073-037 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10073-043 10073-040 AD9633 Data Sheet AD9633-125 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 71.2dB SNR = 70dB –20 –20 ENOB = 11.4 BITS ENOB = 11.3 BITS SFDR = 94.1dBc SFDR = 86.9dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 102030405060 0 10 20304050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. Single-Tone 16k FFT with f = 9.7 MHz, f = 125 MSPS Figure 33. Single-Tone 16k FFT with f = 140 MHz, f = 125 MSPS IN SAMPLE IN SAMPLE 0 0 AIN = –1dBFS AIN = –1dBFS SNR = 70.4dB –20 SNR = 69.4dB ENOB = 11.4 BITS –20 ENOB = 10.9 BITS SFDR = 91.4dBc SFDR = 86.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 102030405060 0 10 20304050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. Single-Tone 16k FFT with f = 30.5 MHZ, f = 125 MSPS IN SAMPLE Figure 34. Single-Tone 16k FFT with f = 200 MHz, f = 125 MSPS IN SAMPLE 0 120 AIN = –1dBFS SNR = 71.1dB –20 ENOB = 11.3 BITS SFDRFS 100 SFDR = 91dBc –40 80 SNRFS –60 SFDR 60 –80 40 SNR –100 –120 20 –140 0 102030405060 0 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 32. Single-Tone 16k FFT with f = 70 MHz, f = 125 MSPS IN SAMPLE Figure 35. SNR/SFDR vs. Analog Input Level, f = 9.7 MHz, f = 125 MSPS IN SAMPLE Rev. 0 | Page 18 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-025 10073-091 10073-024 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10073-027 10073-026 10073-032 Data Sheet AD9633 0 100 AIN1 AND AIN2 = –7dBFS SFDR = 87.1dBc SFDR (dBc) –20 IMD2 = 87.1dBc IMD3 = 87.7dBc –40 90 –60 –80 80 –100 –120 SNR (dBFS) –140 70 0 10 20304050 60 –40 –15 103560 85 FREQUENCY (MHz) TEMPERATURE (°C) Figure 39. SNR/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 125 MSPS Figure 36. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS 0.5 0 0.4 –20 0.3 SFDR (dBc) 0.2 –40 IMD3 (dBc) 0.1 –60 0 –0.1 –80 SFDR (dBFS) –0.2 –100 –0.3 IMD3 (dBFS) –0.4 –120 04 500 1000 1500 2000 2500 3000 3500000 –90 –78 –66 –54 –42 –30 –18 –6 OUTPUT CODE INPUT AMPLITUDE (dBFS) Figure 40. INL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 37. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS 1.0 100 0.8 90 SFDR (dBc) 0.6 80 0.4 70 SNR (dBFS) 0.2 60 0 50 –0.2 40 –0.4 30 –0.6 20 –0.8 10 –1.0 0 0 500 1000 1500 2000 2500 3000 3500 4000 0 20 40 60 80 100 120 140 160 180 200 OUTPUT CODE INPUT FREQUENCY (MHz) Figure 41. DNL, f = 9.7 MHz, f = 125 MSPS IN SAMPLE Figure 38. SNR/SFDR vs. fIN, fSAMPLE = 125 MSPS Rev. 0 | Page 19 of 40 SNR/SFDR (dBFS/dBc) SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) 10073-035 10073-041 10073-038 INL (LSB) DNL (LSB) SNR/SFDR (dBFS/dBc) 10073-044 10073-046 10073-045 AD9633 Data Sheet 1,200,000 105 SFDR 0.25 LSB rms 100 1,000,000 95 800,000 90 85 600,000 80 400,000 75 SNRFS 200,000 70 65 0 20 40 60 80 100 120 N – 2 N – 1 N N + 1 N + 2 SAMPLE FREQUENCY (MSPS) CODE Figure 44. SNR/SFDR vs. Encode, f = 9.7 MHz, f = 125 MSPS Figure 42. Input-Referred Noise Histogram, f = 125 MSPS IN SAMPLE SAMPLE 100 105 90 DRVDD 100 80 SFDR 95 70 60 90 50 85 AVDD 40 80 30 75 20 SNRFS 10 70 0 65 110 20 40 60 80 100 120 FREQUENCY (MHz) SAMPLE FREQUENCY (MSPS) Figure 43. PSRR vs. Frequency, fCLK = 125 MHz, fSAMPLE = 125 MSPS Figure 45. SNR/SFDR vs. Encode, f = 70 MHz, f = 125 MSPS IN SAMPLE Rev. 0 | Page 20 of 40 NUMBER OF HITS PSRR (dB) 10073-087 10073-050 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 10073-029 10073-028 Data Sheet AD9633 EQUIVALENT CIRCUITS AVDD AVDD 350Ω SCLK/DTP, SYNC, VIN±x AND PDWN 30kΩ Figure 46. Equivalent Analog Input Circuit Figure 50. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit AVDD 5Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 375Ω RBIAS AND VCM 5Ω CLK– Figure 51. Equivalent RBIAS and VCM Circuit Figure 47. Equivalent Clock Input Circuit AVDD AVDD 30kΩ 350Ω SDIO/OLM 30kΩ 350Ω 30kΩ CSB Figure 52. Equivalent CSB Input Circuit Figure 48. Equivalent SDIO/OLM Input Circuit DRVDD AVDD V V D0–x, D1–x D0+x, D1+x V V 375Ω VREF 7.5kΩ DRGND Figure 49. Equivalent Digital Output Circuit Figure 53. Equivalent VREF Circuit Rev. 0 | Page 21 of 40 10073-008 10073-011 10073-009 10073-010 10073-014 10073-013 10073-015 10073-012 AD9633 Data Sheet THEORY OF OPERATION The AD9633 is a multistage, pipelined ADC. Each stage provides the output stage of the driving source. In addition, low Q inductors sufficient overlap to correct for flash errors in the preceding stage. or ferrite beads can be placed on each leg of the input to reduce The quantized outputs from each stage are combined into a final high differential capacitance at the analog inputs and therefore 12-bit result in the digital correction logic. The pipelined architec- achieve the maximum bandwidth of the ADC. Such use of low ture permits the first stage to operate with a new input sample Q inductors or ferrite beads is required when driving the converter while the remaining stages operate with preceding samples. front end at high IF frequencies. Either a differential capacitor or Sampling occurs on the rising edge of the clock. two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass Each stage of the pipeline, excluding the last, consists of a low filter at the input to limit unwanted broadband noise. See the resolution flash ADC connected to a switched-capacitor DAC AN-742 Application Note, the AN-827 Application Note, and the and an interstage residue amplifier (for example, a multiplying Analog Dialogue article “Transformer-Coupled Front-End for digital-to-analog converter (MDAC)). The residue amplifier Wideband A/D Converters” (Volume 39, April 2005) for more magnifies the difference between the reconstructed DAC output information. In general, the precise values depend on the and the flash input for the next stage in the pipeline. One bit of application. redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Input Common Mode The analog inputs of the AD9633 are not internally dc-biased. The output staging block aligns the data, corrects errors, and Therefore, in ac-coupled applications, the user must provide passes the data to the output buffers. The data is then serialized this bias externally. Setting the device so that V = AVDD/2 is CM and aligned to the frame and data clocks. recommended for optimum performance, but the device can ANALOG INPUT CONSIDERATIONS function over a wider range with reasonable performance, as The analog input to the AD9633 is a differential switched- shown in Figure 55. capacitor circuit designed for processing differential input An on-chip, common-mode voltage reference is included in the signals. This circuit can support a wide common-mode range design and is available from the VCM pin. The VCM pin must while maintaining excellent performance. By using an input be decoupled to ground by a 0.1 μF capacitor, as described in common-mode voltage of midsupply, users can minimize the Applications Information section. signal-dependent errors and achieve optimum performance. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9633, the largest input span available is 2 V p-p. H 100 C PAR H VIN+x 95 C SAMPLE SFDR SS 90 SS C SAMPLE 85 VIN–x H C PAR 80 H 75 SNRFS Figure 54. Switched-Capacitor Input Circuit 70 The clock signal alternately switches the input circuit between 65 sample mode and hold mode (see Figure 54). When the input 60 circuit is switched to sample mode, the signal source must be 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 capable of charging the sample capacitors and settling within V (V) CM one-half of a clock cycle. A small resistor in series with each Figure 55. SNR/SFDR vs. Common-Mode Voltage, fIN = 9.7 MHz, fSAMPLE = 125 MSPS input can help reduce the peak transient current injected from Rev. 0 | Page 22 of 40 10073-051 SNR/SFDR (dBFS/dBc) 10073-052 Data Sheet AD9633 Differential Input Configurations Internal Reference Connection There are several ways to drive the AD9633 either actively or A comparator within the AD9633 detects the potential at the passively. However, optimum performance is achieved by driving SENSE pin and configures the reference into two possible modes, the analog inputs differentially. Using a differential double balun which are summarized in Table 9. If SENSE is grounded, the configuration to drive the AD9633 provides excellent perfor- reference amplifier switch is connected to the internal resistor mance and a flexible interface to the ADC (see Figure 57) for divider (see Figure 56), setting VREF to 1.0 V. baseband applications. Table 9. Reference Configuration Summary For applications where SNR is a key parameter, differential trans- Resulting former coupling is the recommended input configuration (see Selected Resulting Differential Figure 58), because the noise performance of most amplifiers is Mode SENSE Voltage (V) VREF (V) Span (V p-p) not adequate to achieve the true performance of the AD9633. Fixed AGND to 0.2 1.0 internal 2.0 Internal Regardless of the configuration, the value of the shunt capacitor, Reference C, is dependent on the input frequency and may need to be Fixed AVDD 1.0 applied 2.0 reduced or removed. External to external Reference VREF pin It is not recommended to drive the AD9633 inputs single-ended. VIN+A/VIN+B VOLTAGE REFERENCE VIN–A/VIN–B A stable and accurate 1.0 V voltage reference is built into the AD9633. VREF can be configured using either the internal 1.0 V ADC reference or an externally applied 1.0 V reference voltage. The CORE various reference modes are summarized in the Internal Reference Connection section and the External Reference Operation VREF section. The VREF pin should be externally decoupled to 1.0µF 0.1µF SELECT ground with a low ESR, 1.0 μF capacitor in parallel with a low LOGIC ESR, 0.1 μF ceramic capacitor. SENSE 0.5V ADC Figure 56. Internal Reference Configuration 0.1µF 0.1µF R *C1 VIN+x 33Ω 33Ω C 2V p-p C 5pF ADC 33Ω 0.1µF R VCM VIN–x 33Ω ET1-1-I3 *C1 C R 200Ω 0.1µF C 0.1µF *C1 IS OPTIONAL Figure 57. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO *C1 R VIN+x 33Ω 2Vp-p 49.9Ω ADC C 5pF R VIN–x VCM 33Ω *C1 200Ω 0.1µF 0.1μF *C1 IS OPTIONAL Figure 58. Differential Transformer-Coupled Configuration for Baseband Applications Rev. 0 | Page 23 of 40 10073-056 10073-059 10073-060 AD9633 Data Sheet If the internal reference of the AD9633 is used to drive multiple Clock Input Options converters to improve gain matching, the loading of the reference The AD9633 has a flexible clock input structure. The clock by the other converters must be considered. Figure 59 shows input can be a CMOS, LVDS, LVPECL, or sine wave signal. how the internal reference voltage is affected by loading. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations 0 section. –0.5 Figure 61 and Figure 62 show two preferred methods for clock- –1.0 INTERNAL V = 1V REF ing the AD9633 (at clock rates up to 1 GHz prior to internal CLK –1.5 divider). A low jitter clock source is converted from a single-ended –2.0 signal to a differential signal using either an RF transformer or an –2.5 RF balun. –3.0 The RF balun configuration is recommended for clock frequencies –3.5 between 125 MHz and 1 GHz, and the RF transformer is recom- –4.0 mended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun –4.5 secondary winding limit clock excursions into the AD9633 to –5.0 0 0.5 1.0 1.5 2.0 2.53.0 approximately 0.8 V p-p differential. LOAD CURRENT (mA) This limit helps prevent the large voltage swings of the clock Figure 59. V Error vs. Load Current REF from feeding through to other portions of the AD9633 while External Reference Operation preserving the fast rise and fall times of the signal that are criti- The use of an external reference may be necessary to enhance cal to achieving low jitter performance. However, the diode the gain accuracy of the ADC or improve thermal drift charac- capacitance comes into play at frequencies above 500 MHz. teristics. Figure 60 shows the typical drift characteristics of the Care must be taken in choosing the appropriate signal limiting internal reference in 1.0 V mode. diode. 4 ® Mini-Circuits ADT1-1WT, 1:1 Z 2 0.1µF 0.1µF XFMR CLOCK CLK+ INPUT 100Ω 50Ω 0 ADC 0.1µF CLK– SCHOTTKY –2 0.1µF DIODES: HSMS2822 Figure 61. Transformer-Coupled Differential Clock (Up to 200 MHz) –4 –6 0.1µF 0.1µF CLOCK CLK+ –8 INPUT –40 –15 10 35 60 85 50Ω ADC 0.1µF TEMPERATURE (°C) 0.1µF CLK– Figure 60. Typical VREF Drift SCHOTTKY DIODES: When the SENSE pin is tied to AVDD, the internal reference is HSMS2822 disabled, allowing the use of an external reference. An internal Figure 62. Balun-Coupled Differential Clock (Up to 1 GHz) reference buffer loads the external reference with an equivalent If a low jitter clock source is not available, another option is to 7.5 kΩ load (see Figure 53). The internal buffer generates the ac couple a differential PECL signal to the sample clock input positive and negative full-scale references for the ADC core. There- pins, as shown in Figure 64. The AD9510/AD9511/AD9512/ fore, the external reference must be limited to a maximum of 1.0 V. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer It is not recommended to leave the SENSE pin floating. excellent jitter performance. CLOCK INPUT CONSIDERATIONS A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 65. The AD9510/ For optimum performance, clock the AD9633 sample clock inputs, AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 CLK+ and CLK−, with a differential signal. The signal is typi- clock drivers offer excellent jitter performance. cally ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 47) In some applications, it may be acceptable to drive the sample and require no external bias. clock inputs with a single-ended 1.8 V CMOS signal. In such Rev. 0 | Page 24 of 40 V ERROR (mV) REF V ERROR (%) REF 10073-061 10073-062 10073-065 10073-064 Data Sheet AD9633 applications, drive the CLK+ pin directly from a CMOS gate, and ance are nearly flat for a wide range of duty cycles with the DCS bypass the CLK− pin to ground with a 0.1 μF capacitor (see on, as shown in Figure 63. Figure 66). 73 SNRFS (DCS ON) 71 Input Clock Divider The AD9633 contains an input clock divider with the ability 69 SNRFS (DCS OFF) to divide the input clock by integer values between 1 and 8. 67 The AD9633 clock divider can be synchronized using the 65 external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the 63 clock divider to be resynchronized on every SYNC signal or 61 only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. 59 This synchronization feature allows multiple parts to have their 57 clock dividers aligned to guarantee simultaneous input sampling. 55 Clock Duty Cycle 40 42 44 46 48 50 52 54 56 58 60 DUTY CYCLE (%) Typical high speed ADCs use both clock edges to generate a vari- Figure 63. SNR vs. DCS On/Off ety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the Jitter in the rising edge of the input is still of concern and is not clock duty cycle to maintain dynamic performance characteristics. easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than The AD9633 contains a duty cycle stabilizer (DCS) that retimes 20 MHz, nominally. The loop has a time constant associated the nonsampling (falling) edge, providing an internal clock with it that must be considered in applications in which the signal with a nominal 50% duty cycle. This allows the user to clock rate can change dynamically. A wait time of 1.5 μs to 5 μs provide a wide range of clock input duty cycles without affecting is required after a dynamic clock frequency increase or decrease the performance of the AD9633. Noise and distortion perform- before the DCS loop is relocked to the input signal. 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x 100Ω ADC PECL DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 64. Differential PECL Sample Clock (Up to 1 GHz) 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x 100Ω ADC LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 50kΩ 50kΩ Figure 65. Differential LVDS Sample Clock (Up to 1 GHz) V CC OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER INPUT 1 1kΩ 50Ω ADC CLK– 0.1µF 1 50Ω RESISTOR IS OPTIONAL. Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. 0 | Page 25 of 40 SNRFS (dBFS) 10073-068 10073-067 10073-066 10073-069 AD9633 Data Sheet Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 68, the power dissipated by the AD9633 is clock input. The degradation in SNR at a given input frequency proportional to its sample rate. The digital power dissipation (fA) due only to aperture jitter (tJ) can be calculated by does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 1 SNR Degradation = 20 log ( ) 10 350 2π× f ×t A j In this equation, the rms aperture jitter represents the root mean 300 square of all jitter sources, including the clock input, analog input 125 MSPS signal, and ADC aperture jitter specifications. IF undersampling 250 105 MSPS applications are particularly sensitive to jitter (see Figure 67). The clock input should be treated as an analog signal in cases 80 MSPS 200 where aperture jitter may affect the dynamic range of the AD9633. 65 MSPS Power supplies for clock drivers should be separated from the 50 MSPS ADC output driver supplies to avoid modulating the clock signal 150 40 MSPS with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another 20 MSPS 100 type of source (by gating, dividing, or other methods), it should 10 20 30 40 50 60 70 80 90 100 110 120 130 be retimed by the original clock at the last step. SAMPLE RATE (MSPS) Figure 68. Analog Core Power vs. f for f = 10.3 MHz SAMPLE IN Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter The AD9633 is placed in power-down mode either by the SPI performance as it relates to ADCs. port or by asserting the PDWN pin high. In this state, the ADC 130 typically dissipates 2 mW. During power-down, the output drivers RMS CLOCK JITTER REQUIREMENT are placed in a high impedance state. Asserting the PDWN pin 120 low returns the AD9633 to its normal operating mode. Note 110 that PDWN is referenced to the digital output driver supply 100 16 BITS (DRVDD) and should not exceed that supply voltage. 90 14 BITS Low power dissipation in power-down mode is achieved by 80 12 BITS shutting down the reference, reference buffer, biasing networks, 70 and clock. Internal capacitors are discharged when entering power- 10 BITS 60 down mode and then must be recharged when returning to normal 0.125ps 8 BITS operation. As a result, wake-up time is related to the time spent 50 0.25ps 0.5ps in power-down mode, and shorter power-down cycles result in 1.0ps 40 2.0ps proportionally shorter wake-up times. When using the SPI port 30 1 10 100 1000 interface, the user can place the ADC in power-down mode or ANALOG INPUT FREQUENCY (MHz) standby mode. Standby mode allows the user to keep the internal Figure 67. Ideal SNR vs. Input Frequency and Jitter reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details on using these features. Rev. 0 | Page 26 of 40 SNR (dB) 10073-070 ANALOG CORE POWER (mW) 10073-071 Data Sheet AD9633 DIGITAL OUTPUTS AND TIMING The AD9633 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. When operating in reduced range mode, the output current is reduced to 2 mA. This results in a 200 mV swing (or 400 mV p- p differential) across a 100 Ω termination at the receiver. D0 400mV/DIV 4ns/DIV D1 400mV/DIV DCO 400mV/DIV The AD9633 LVDS outputs facilitate interfacing with LVDS FCO 400mV/DIV receivers in custom ASICs and FPGAs for superior switching Figure 70. AD9633-125, LVDS Output Timing Example in Reduced Range Mode performance in noisy environments. Single point-to-point net An example of the LVDS output using the ANSI-644 standard topologies are recommended with a 100 Ω termination resistor (default) data eye and a time interval error (TIE) jitter histogram placed as close to the receiver as possible. If there is no far-end with trace lengths less than 24 inches on standard FR-4 material is receiver termination or there is poor differential trace routing, shown in Figure 71. timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and 500 EYE: ALL BITS ULS: 8000/300062 that the differential output traces be close together and at equal 400 lengths. An example of the FCO and data stream with proper 300 trace length and position is shown in Figure 69. Figure 70 shows 200 the LVDS output timing example in reduced range mode. 100 0 –100 –200 –300 –400 –500 –1.0ns –0.5ns 0ns 0.5ns 1.0ns 5.5k 5.0k 4.5k D0 500mV/DIV 4ns/DIV 4.0k D1 500mV/DIV DCO 500mV/DIV 3.5k FCO 500mV/DIV 3.0k Figure 69. AD9633-125, LVDS Output Timing Example in ANSI-644 Mode (Default) 2.5k 2.0k 1.5k 1.0k 0.5k 0 350ps 400ps 450ps 500ps 550ps 600ps 650ps 700ps Figure 71. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only Rev. 0 | Page 27 of 40 10073-074 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 10073-083 10073-075 AD9633 Data Sheet 600 Figure 72 shows an example of trace lengths exceeding 24 inches ULS: 7000/301593 EYE: ALL BITS on standard FR-4 material. Notice that the TIE jitter histogram 400 reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s responsibility to determine 200 if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the 0 user to further increase the internal termination (increasing the current) of all four outputs to drive longer trace lengths. This can –200 be achieved by programming Register 0x15. Even though this produces sharper rise and fall times on the data edges and is less –400 prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. –600 –1ns –0.5ns 0ns 0.5ns 1ns The format of the output data is twos complement by default. An example of the output coding format can be found in Table 10. 12k To change the output data format to offset binary, see the 10k Memory Map section. 9k Data from each ADC is serialized and provided on a separate 8k channel in two lanes in DDR mode. The data rate for each serial 7k stream is equal to 12 bits times the sample clock rate, with a 6k maximum of 375 Mbps/lane [(12 bits × 125 MSPS)/(2 × 2) = 5k 375 Mbps/lane)]. The lowest typical conversion rate is 10 MSPS. 4k See the Memory Map section for details on enabling this feature. 3k Two output clocks are provided to assist in capturing data from 2k the AD9633. The DCO is used to clock the output data and is 1k equal to three times the sample clock (CLK) rate for the default 0 mode of operation. Data is clocked out of the AD9633 and must –1ns –0.8ns –0.6ns –0.4ns –0.2ns 0ns 0.2ns 0.4ns 0.6ns 0.8ns be captured on the rising and falling edges of the DCO that Figure 72. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths supports double data rate (DDR) capturing. The FCO is used to Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only signal the start of a new output byte and is equal to the sample clock rate in 1× frame mode. See the Timing Diagrams section for more information. Table 10. Digital Output Coding Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000 VIN+ − VIN− −VREF 0000 0000 0000 1000 0000 0000 VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000 VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111 VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111 Rev. 0 | Page 28 of 40 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 10073-076 Data Sheet AD9633 Table 11. Flexible Output Test Modes Subject to Output Test Data Mode Format Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Select Notes 0000 Off (default) N/A N/A N/A 0001 Midscale short 10 0000 0000 (10-bit) N/A Yes Offset binary 1000 0000 0000 (12-bit) code shown 0010 +Full-scale short 11 1111 1111 (10-bit) N/A Yes Offset binary 1111 1111 1111 (12-bit) code shown 0011 −Full-scale short 00 0000 0000 (10-bit) N/A Yes Offset binary 0000 0000 0000 (12-bit) code shown 0100 Checkerboard 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) No 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) 1 0101 PN sequence long N/A N/A Yes PN23 ITU 0.150 23 18 X + X + 1 1 0110 PN sequence short N/A N/A Yes PN9 ITU 0.150 9 5 X + X + 1 0111 One-/zero-word 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) No toggle 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 10 1010 1010 (10-bit) N/A No 1010 1010 1010 (12-bit) 1010 1× sync 00 0011 1111 (10-bit) N/A No 0000 0111 1111 (12-bit) 1011 One bit high 00 0000 0000 (10-bit) N/A No Pattern 0000 0000 0000 (12-bit) associated with the external pin 1100 Mixed frequency 10 0011 0011 (10-bit) N/A No 1000 0110 0111 (12-bit) 1 All test mode options except PN sequence short and PN sequence long can support 10-bit to 12-bit word lengths to verify data capture to the receiver. When the SPI is used, the DCO phase can be adjusted in 60° The PN sequence short pattern produces a pseudorandom bit 9 increments relative to the data edge. This enables the user to sequence that repeats itself every 2 − 1 or 511 bits. A descrip- refine system timing margins if required. The default DCO+ tion of the PN sequence and how it is generated can be found in and DCO− timing, as shown in Figure 2, is 90° relative to the Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value output data edge. is all 1s (see Table 12 for the initial values). The output is a parallel representation of the serial PN9 sequence in MSB-first format. A 10-bit serial stream can also be initiated from the SPI. This The first output word is the first 12 bits of the PN9 sequence in allows the user to implement and test compatibility to lower MSB aligned form. resolution systems. When changing the resolution to a 10-bit serial stream, the data stream is shortened. The PN sequence long pattern produces a pseudorandom bit 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A In default mode, as shown in Figure 2, the MSB is first in the description of the PN sequence and how it is generated can be data output serial stream. This can be inverted so that the LSB is found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The first in the data output serial stream by using the SPI. seed value is all 1s (see Table 12 for the initial values) and the There are 12 digital output test pattern options available that AD9633 inverts the bit stream with relation to the ITU standard. can be initiated through the SPI. This is a useful feature when The output is a parallel representation of the serial PN23 sequence validating receiver capture and timing. Refer to Table 11 for the in MSB-first format. The first output word is the first 12 bits of output bit sequencing options available. Some test patterns have the PN23 sequence in MSB aligned form. two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some Table 12. PN Sequence patterns do not adhere to the data format select option. In Initial First Three Output Samples Sequence Value (MSB First) Twos Complement addition, custom user-defined test patterns can be assigned in PN Sequence Short 0x7F8 0xBDF, 0x973, 0xA09 the 0x19, 0x1A, 0x1B, and 0x1C register addresses. PN Sequence Long 0x7FF 0x7FE, 0x800, 0xFC0 Rev. 0 | Page 29 of 40 AD9633 Data Sheet Consult the Memory Map section for information on how to Table 14. Digital Test Pattern Pin Settings change these additional digital output timing features through Resulting Selected DTP DTP Voltage D0±x and D1±x the SPI. Normal Operation 10 kΩ to AGND Normal operation SDIO/OLM Pin DTP AVDD 1000 0000 0000 For applications that do not require SPI mode operation, the Additional and custom test patterns can also be observed when CSB pin is tied to AVDD, and the SDIO/OLM pin controls the commanded from the SPI port. Consult the Memory Map output lane mode according to Table 13. section for information about the options available. For applications where this pin is not used, CSB should be CSB Pin tied to AVDD. When using the one-lane mode, the encode rate should be ≤83.33 MSPS to meet the maximum output rate The CSB pin should be tied to AVDD for applications that do of 1 Gbps. not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. Table 13. Output Lane Mode Pin Settings RBIAS Pin OLM Pin Voltage Output Mode To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. AVDD (Default) Two-lane. 1× frame, 12-bit serial output GND One-lane. 1× frame, 12-bit serial output OUTPUT TEST MODES SCLK/DTP Pin The output test options are described in Table 11 and controlled The SCLK/DTP pin is for use in applications that do not require by the output test mode bits at Address 0x0D. When an output SPI mode operation. This pin can enable a single digital test test mode is enabled, the analog section of the ADC is discon- pattern if it and the CSB pin are held high during device power- nected from the digital back-end blocks and the test pattern is up. When SCLK/DTP is tied to AVDD, the ADC channel run through the output formatting block. Some of the test patterns outputs shift out the following pattern: 1000 0000 0000. The are subject to output formatting, and some are not. The PN FCO and DCO function normally while all channels shift out the generators from the PN sequence tests can be reset by setting repeatable test pattern. This pattern allows the user to perform Bit 4 or Bit 5 of Register 0x0D. These tests can be performed timing alignment adjustments among the FCO, DCO, and with or without an analog signal (if present, the analog signal is output data. This pin has an internal 10 kΩ resistor to GND. It ignored), but they do require an encode clock. For more can be left unconnected. information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 30 of 40 Data Sheet AD9633 SERIAL PORT INTERFACE (SPI) The AD9633 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 73 offers the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK pin, the SDIO Data follows the instruction phase, and its length is determined pin, and the CSB pin (see Table 15). The SCLK (a serial clock) is by the W0 and W1 bits. used to synchronize the read and write data presented from and In addition to word length, the instruction phase determines to the ADC. The SDIO (serial data input/output) is a dual- whether the serial frame is a read or write operation, allowing purpose pin that allows data to be sent to and read from the the serial port to be used both to program the chip and to read internal ADC memory map registers. The CSB (chip select bar) the contents of the on-chip memory. The first bit of the first byte in is an active low control that enables or disables the read and a multibyte serial data transfer frame indicates whether a read write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial Table 15. Serial Port Interface Pins data input/output (SDIO) pin to change direction from an input to Pin Function an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB- SDIO Serial data input/output. A dual-purpose pin that first mode or in LSB-first mode. MSB-first mode is the default typically serves as an input or an output, depending on on power-up and can be changed via the SPI port configuration the instruction being sent and the relative position in the timing frame. register. For more information about this and other features, CSB Chip select bar. An active low control that gates the read see the AN-877 Application Note, Interfacing to High Speed and write cycles. ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 73. Serial Port Interface Timing Diagram Rev. 0 | Page 31 of 40 10073-078 AD9633 Data Sheet When the device is in SPI mode, the PDWN pin (if enabled) HARDWARE INTERFACE remains active. For SPI control of power-down, the PDWN pin The pins described in Table 15 comprise the physical interface should be set to its default state. between the user programming device and the serial port of the AD9633. The SCLK pin and the CSB pin function as inputs SPI ACCESSIBLE FEATURES when using the SPI interface. The SDIO pin is bidirectional, Table 16 provides a brief description of the general features that functioning as an input during write phases and as an output are accessible via the SPI. These features are described in detail during readback. in the AN-877 Application Note, Interfacing to High Speed ADCs The SPI interface is flexible enough to be controlled by either via SPI. The AD9633 part-specific features are described in detail FPGAs or microcontrollers. One method for SPI configuration following Table 17, the external memory map register table. is described in detail in the AN-812 Application Note, Micro- Table 16. Features Accessible Using the SPI controller-Based Serial Port Interface (SPI) Boot Circuit. Feature Name Description The SPI port should not be active during periods when the full Power Mode Allows the user to set either power-down mode dynamic performance of the converter is required. Because the or standby mode SCLK signal, the CSB signal, and the SDIO signal are typically Clock Allows the user to access the DCS, set the asynchronous to the ADC clock, noise from these signals can clock divider, set the clock divider phase, and enable the sync degrade converter performance. If the on-board SPI bus is used for Offset Allows the user to digitally adjust the other devices, it may be necessary to provide buffers between converter offset this bus and the AD9633 to prevent these signals from transi- Test I/O Allows the user to set test modes to have tioning at the converter inputs during critical sampling periods. known data on output bits Some pins serve a dual function when the SPI interface is not Output Mode Allows the user to set the output mode being used. When the pins are strapped to DRVDD or ground Output Phase Allows the user to set the output clock polarity during device power-on, they are associated with a specific ADC Resolution Allows for power consumption scaling with function. Table 16 describes the strappable functions supported respect to sample rate. on the AD9633. CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, and power-down feature control. In this mode, CSB should be connected to AVDD, which disables the serial port interface. Rev. 0 | Page 32 of 40 Data Sheet AD9633 MEMORY MAP Default Values READING THE MEMORY MAP REGISTER TABLE After the AD9633 is reset, critical registers are loaded with Each row in the memory map register table has eight bit locations. default values. The default values for the registers are given in The memory map is roughly divided into three sections: the chip the memory map register table, Table 17. configuration registers (Address 0x00 to Address 0x02); the device Logic Levels index and transfer registers (Address 0x05 and Address 0xFF); and the global ADC functions registers, including setup, control, An explanation of logic level terminology follows: and test (Address 0x08 to Address 0x109). • “Bit is set” is synonymous with “bit is set to Logic 1” or The memory map register table (see Table 17) lists the default “writing Logic 1 for the bit.” hexadecimal value for each hexadecimal address shown. The • “Clear a bit” is synonymous with “bit is set to Logic 0” or column with the heading Bit 7 (MSB) is the start of the default “writing Logic 0 for the bit.” hexadecimal value given. For example, Address 0x05, the device Channel-Specific Registers index register, has a hexadecimal default value of 0x3F. This means that in Address 0x05, Bits[7:6] = 0, and the remaining Some channel setup functions, such as the signal monitor Bits[5:0] = 1. This setting is the default channel index setting. thresholds, can be programmed differently for each channel. In The default value results in both ADC channels receiving the these cases, channel address locations are internally duplicated next write command. For more information on this function for each channel. These registers and bits are designated in and others, see the AN-877 Application Note, Interfacing to High Table 17 as local. These local registers and bits can be accessed Speed ADCs via SPI. This application note details the functions by setting the appropriate data channel bits (A, B, C, or D) and controlled by Register 0x00 to Register 0xFF. The remaining the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in registers are documented in the Memory Map Register Register 0x05. If all the bits are set, the subsequent write affects Descriptions section. the registers of all channels and the DCO/FCO clock channels. In a read cycle, only one of the channels (A, B, C, or D) should Open Locations be set to read one of the four registers. If all the bits are set All address and bit locations that are not included in Table 17 during a SPI read cycle, the part returns the value for Channel are not currently supported for this device. Unused bits of a A. Registers and bits designated as global in Table 17 affect the valid address location should be written with 0s. Writing to these entire part or the channel features for which independent locations is required only when part of an address location is settings are not allowed between channels. The settings in open (for example, Address 0x05). If the entire address location Register 0x05 do not affect the global registers and bits. is open or not listed in Table 17 (for example, Address 0x13), this address location should not be written. Rev. 0 | Page 33 of 40 AD9633 Data Sheet MEMORY MAP REGISTER TABLE The AD9633 uses a 3-wire interface and 16-bit addressing and, the SPI enters a soft reset, where all of the user registers revert therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 to their default values and Bit 2 is automatically cleared. and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, Table 17. Default Addr Parameter Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 = LSB first Soft reset 1 = 1 = Soft LSB first 0 = SDO 0x18 The nibbles configuration SDO 16-bit 16-bit reset active are mirrored active address address so that LSB- first or MSB- first mode registers correctly. The default for ADCs is 16-bit mode. 0x01 Chip ID (global) 8-bit chip ID, Bits[7:0] 0x90 Unique AD9633 0x90 = quad 12-bit 80 MSPS/105 MSPS/125 MSPS serial LVDS chip ID used to differ- entiate devices; read only. 0x02 Chip grade Open Speed grade ID[6:4] Open Open Open Open Unique speed (global) 100 = 80 MSPS grade ID used 101 = 105 MSPS to differentiate 110 = 125 MSPS graded devices; read only. Device Index and Transfer Registers 0x05 Device index Open Open Clock Clock Data Data Data Data 0x3F Bits are set Channel Channel Channel Channel Channel Channel to determine DCO FCO D C B A which device on chip receives the next write command. The default is all devices on chip. 0xFF Transfer Open Open Open Open Open Open Open Initiate 0x00 Set resolution/ override sample rate override. Global ADC Function Registers 0x08 Power modes Open Open External Open Open Open Power mode 0x00 Determines (global) power- 00 = chip run various generic down pin 01 = full power-down modes of chip function 10 = standby operation. 0 = full 11 = reset power- down 1 = standby 0x09 Clock (global) Open Open Open Open Open Open Open Duty 0x01 Turns duty cycle cycle stabilizer on or stabilize off. 0 = off 1 = on 0x0B Clock divide Open Open Open Open Open Clock divide ratio[2:0] 0x00 (global) 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Rev. 0 | Page 34 of 40 Data Sheet AD9633 Default Addr Parameter Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0C Enhancement Open Open Open Open Open Chop Open Open 0x00 Enables/ control mode disables chop 0 = off mode. 1 = on 0x0D Test mode User input test mode Reset PN Reset PN Output test mode[3:0] (local) 0x00 When set, (local except 00 = single long gen short 0000 = off (default) the test data for PN sequence 01 = alternate gen 0001 = midscale short is placed on resets) 10 = single once 0010 = positive FS the output pins 11 = alternate 0011 = negative FS in place of once (affects user input 0100 = alternating checkerboard normal data. test 0101 = PN 23 sequence mode only, 0110 = PN 9 sequence Bits[3:0] = 1000) 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x10 Offset adjust 8-bit device offset adjustment[7:0] (local) 0x00 Device offset (local) Offset adjust in LSBs from +127 to −128 (twos complement format) trim. 0x14 Output mode Open LVDS-ANSI/ Open Open Open Output Open Output 0x01 Configures invert format the outputs LVDS-IEEE option (local) 0 = offset and the 0 = LVDS- binary format of ANSI 1 = twos the data. 1 = LVDS- comple- IEEE reduced ment range link (global) (global) see Table 18 0x15 Output adjust Open Open Output driver Open Open Open Output 0x00 Determines termination[1:0] drive LVDS or other 00 = none 0 = 1× output 01 = 200 Ω drive properties. 10 = 100 Ω 1 = 2× 11 = 100 Ω drive 0x16 Output phase Open Input clock phase adjust[6:4] Output clock phase adjust[3:0] 0x03 On devices (value is number of input (0000 through 1011) that use clock cycles of phase delay) see Table 20 global clock see Table 19 divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x18 V Open Open Open Open Open Internal V adjustment 0x04 Selects and/ REF REF digital scheme[2:0] or adjusts the 000 = 1.0 V p-p V . REF 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 1 LSB. 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined (global) Pattern 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 2 LSB. 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined (global) Pattern 2 MSB. Rev. 0 | Page 35 of 40 AD9633 Data Sheet Default Addr Parameter Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x21 Serial output LVDS SDR/DDR one-lane/two-lane, Open Select 2× Serial output 0x32 Serial stream data control output bitwise/bytewise[6:4] frame number of bits control. Default (global) LSB 000 = SDR two-lane, bitwise 10 = 12 bits causes MSB first first 001 = SDR two-lane, bytewise 11 = 10 bits and the native 010 = DDR two-lane, bitwise bit stream. 011 = DDR two-lane, bytewise 100 = DDR one-lane 0x22 Serial channel Open Open Open Open Open Open Channel Channel 0x00 Used to power status (local) output power- down individual reset down sections of a converter. 0x100 Resolution/ Open Resolution/ Resolution Open Sample rate 0x00 Resolution/ sample rate sample rate 10 = 12 bits 000 = 20 MSPS sample rate override override 11 = 10 bits 001 = 40 MSPS override enable 010 = 50 MSPS (requires 011 = 65 MSPS transfer 100 = 80 MSPS register, 101 = 105 MSPS 0xFF). 110 = 125 MSPS 0x101 User I/O Control 2 Open Open Open Open Open Open Open SDIO 0x00 Disables SDIO pull- pull-down. down 0x102 User I/O Control 3 Open Open Open Open VCM Open Open Open 0x00 VCM control. power- down 0x109 Sync Open Open Open Open Open Open Sync Enable 0x00 next sync only Rev. 0 | Page 36 of 40 Data Sheet AD9633 Output Mode (Register 0x14) MEMORY MAP REGISTER DESCRIPTIONS Bit 7—Open For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Bit 6—LVDS-ANSI/LVDS-IEEE Option Interfacing to High Speed ADCs via SPI. Setting this bit chooses LVDS-IEEE (reduced range) option. Device Index (Register 0x05) The default setting is LVDS-ANSI. As described in Table 18, There are certain features in the map that can be set when LVDS-ANSI or LVDS-IEEE reduced range link is selected, the user can select the driver termination. The driver current independently for each channel, whereas other features apply globally to all channels (depending on context) regardless of is automatically selected to give the proper output swing. which are selected. The first four bits in Register 0x05 can be Table 18. LVDS-ANSI/LVDS-IEEE Options used to select which individual data channels are affected. The Output Output output clock channels can be selected in Register 0x05 as well. A Mode, Output Driver Output Driver smaller subset of the independent feature list can be applied to Bit 6 Mode Termination Current those devices. 0 LVDS-ANSI User Automatically selectable selected to give Transfer (Register 0xFF) proper swing All registers except Register 0x100 are updated the moment 1 LVDS-IEEE User Automatically they are written. Setting Bit 0 of this transfer register high reduced selectable selected to give initializes the settings in the ADC sample rate override register range link proper swing (Address 0x100). Bits[5:3]—Open Power Modes (Register 0x08) Bit 2—Output Invert Bits[7:6]—Open Setting this bit inverts the output bit stream. Bit 5—External Power-Down Pin Function Bit 1—Open If set, the external PDWN pin initiates power-down mode. Bit 0—Output Format If cleared, the external PDWN pin initiates standby mode. By default, this bit is set to send the data output in twos Bits[4:2]—Open complement format. Resetting this bit changes the output mode Bits[1:0]—Power Mode to offset binary. In normal operation (Bits[1:0] = 00), all ADC channels are Output Adjust (Register 0x15) active. Bits[7:6]—Open In power-down mode (Bits[1:0] = 01), the digital datapath clocks Bits[5:4]—Output Driver Termination are disabled while the digital datapath is reset. Outputs are These bits allow the user to select the internal termination disabled. resistor. In standby mode (Bits[1:0] = 10), the digital datapath clocks Bits[3:1]—Open and the outputs are disabled. Bit 0—Output Drive During a digital reset (Bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, Bit 0 of the output adjust register controls the drive strength on the except the SPI port. Note that the SPI is always left under LVDS driver of the FCO and DCO outputs only. The default control of the user; that is, it is never automatically disabled or values set the drive to 1× while the drive can be increased to 2× by in reset (except by power-on reset). setting the appropriate channel bit in Register 0x05 and then setting Bit 0. These features cannot be used with the output Enhancement Control (Register 0x0C) driver termination select. The termination selection takes prece- Bits[7:3]—Open dence over the 2× driver strength on FCO and DCO when both Bit 2—Chop Mode the output driver termination and output drive are selected. For applications that are sensitive to offset voltages and other Output Phase (Register 0x16) low frequency noise, such as homodyne or direct conversion Bit 7—Open receivers, chopping in the first stage of the AD9633 is a feature Bits[6:4]—Input Clock Phase Adjust that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to f /2 where it can be filtered. CLK Bits[1:0]—Open Rev. 0 | Page 37 of 40 AD9633 Data Sheet Table 19. Input Clock Phase Adjust Options Serial Output Data Control (Register 0x21) Input Clock Phase Number of Input Clock Cycles of The serial output data control register is used to program the Adjust, Bits[6:4] Phase Delay AD9633 in various output data modes depending upon the data 000 (Default) 0 capture solution. Table 21 describes the various serialization 001 1 options available in the AD9633. 010 2 Resolution/Sample Rate Override (Register 0x100) 011 3 This register is designed to allow the user to downgrade the device. 100 4 Any attempt to upgrade the default speed grade results in a chip 101 5 power-down. Settings in this register are not initialized until Bit 0 110 6 of the transfer register (Register 0xFF) is written high. 111 7 User I/O Control 2 (Register 0x101) Bits[3:0]—Output Clock Phase Adjust Bits[7:1]—Open Table 20. Output Clock Phase Adjust Options Bit 0—SDIO Pull-Down Output Clock (DCO), DCO Phase Adjustment (Degrees Bit 0 can be set to disable the internal 30 kΩ pull-down on the Phase Adjust, Bits[3:0] Relative to D0±x/D1±x Edge) SDIO pin, which can be used to limit the loading when many 0000 0 devices are connected to the SPI bus. 0001 60 0010 120 User I/O Control 3 (Register 0x102) 0011 (Default) 180 Bits[7:4]—Open 0100 240 Bit 3—VCM Power-Down 0101 300 0110 360 Bit 3 can be set high to power down the internal VCM 0111 420 generator. This feature is used when applying an external 1000 480 reference. 1001 540 Bits[2:0]—Open 1010 600 1011 660 Table 21. SPI Register Options Serialization Options Selected Register 0x21 Serial Output Number Contents of Bits (SONB) Frame Mode Serial Data Mode DCO Multiplier Timing Diagram 0x32 12-bit 1× DDR two-lane bytewise 3 × fS Figure 2 (default setting) 0x22 12-bit 1× DDR two-lane bitwise 3 × fS Figure 2 0x12 12-bit 1× SDR two-lane bytewise 6 × f Figure 2 S 0x02 12-bit 1× SDR two-lane bitwise 6 × f Figure 2 S 0x36 12-bit 2× DDR two-lane bytewise 3 × f Figure 4 S 0x26 12-bit 2× DDR two-lane bitwise 3 × fS Figure 4 0x16 12-bit 2× SDR two-lane bytewise 6 × fS Figure 4 0x06 12-bit 2× SDR two-lane bitwise 6 × fS Figure 4 0x42 12-bit 1× DDR one-lane 6 × f Figure 6 S 0x33 10-bit 1× DDR two-lane bytewise 2.5 × f Figure 3 S 0x23 10-bit 1× DDR two-lane bitwise 2.5 × fS Figure 3 0x13 10-bit 1× SDR two-lane bytewise 5 × fS Figure 3 0x03 10-bit 1× SDR two-lane bitwise 5 × fS Figure 3 0x37 10-bit 2× DDR two-lane bytewise 2.5 × f Figure 5 S 0x27 10-bit 2× DDR two-lane bitwise 2.5 × f Figure 5 S 0x17 10-bit 2× SDR two-lane bytewise 5 × f Figure 5 S 0x07 10-bit 2× SDR two-lane bitwise 5 × fS Figure 5 0x43 10-bit 1× DDR one-lane 5 × fS Figure 7 Rev. 0 | Page 38 of 40 Data Sheet AD9633 APPLICATIONS INFORMATION VCM DESIGN GUIDELINES Before starting design and layout of the AD9633 as a system, The VCM pin should be decoupled to ground with a 0.1 μF it is recommended that the designer become familiar with these capacitor. guidelines, which describes the special circuit connections and REFERENCE DECOUPLING layout requirements that are needed for certain pins. The VREF pin should be externally decoupled to ground with a POWER AND GROUND RECOMMENDATIONS low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF When connecting power to the AD9633, it is recommended ceramic capacitor. that two separate 1.8 V supplies be used. Use one supply for SPI PORT analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different The SPI port should not be active during periods when the full decoupling capacitors should be used to cover both high and dynamic performance of the converter is required. Because the low frequencies. Place these capacitors close to the point of SCLK, CSB, and SDIO signals are typically asynchronous to the entry at the PCB level and close to the pins of the part, with ADC clock, noise from these signals can degrade converter minimal trace length. performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the A single PCB ground plane should be sufficient when using the AD9633 to keep these signals from transitioning at the con- AD9633. With proper decoupling and smart partitioning of the verter inputs during critical sampling periods. PCB analog, digital, and clock sections, optimum performance is easily achieved. CROSSTALK PERFORMANCE EXPOSED PAD THERMAL HEAT SLUG The AD9633 is available in a 48-lead LFCSP package with the RECOMMENDATIONS input pairs on either corner of the chip. See Figure 9 for the pin configuration. To maximize the crosstalk performance on the It is required that the exposed pad on the underside of the ADC board, add grounded filled vias in between the adjacent be connected to analog ground (AGND) to achieve the best channels as shown in Figure 75. electrical and thermal performance of the AD9633. An exposed continuous copper plane on the PCB should mate to the AD9633 exposed pad, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a VIN silkscreen on the PCB into several uniform sections. This provides CHANNEL A several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions GROUNDED FILLED VIAS VIN only guarantees one tie point. See Figure 74 for a PCB layout FOR ADDED CHANNEL D CROSSTALK example. For detailed information on packaging and the PCB ISOLATION PIN 1 layout of chip scale packages, see the AN-772 Application Note, VIN VIN CHANNEL B CHANNEL C A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. Figure 75. Layout Technique to Maximize Crosstalk Performance SILKSCREEN PARTITION PIN 1 INDICATOR Figure 74. Typical PCB Layout Rev. 0 | Page 39 of 40 10073-080 10073-088 AD9633 Data Sheet OUTLINE DIMENSIONS 7.10 0.30 7.00 SQ 0.23 6.90 0.18 PIN 1 INDICATOR 37 48 36 1 0.50 BSC EXPOSED 5.65 PAD 5.60 SQ 5.55 24 13 0.45 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.35 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. Figure 76. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9633BCPZ-80 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633BCPZRL7-80 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633BCPZ-105 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633BCPZRL7-105 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633BCPZ-125 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633BCPZRL7-125 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13 AD9633-125EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10073-0-10/11(0) Rev. 0 | Page 40 of 40 PIN 1 INDICATOR 02-14-2011-B