ANALOG DEVICES AD9632

Ultralow Distortion, Wide Bandwidth a Voltage Feedback Op Amps AD9631/AD9632 FEATURES PIN CONFIGURATION Wide Bandwidth 8-Lead PDIP (N) AD9631, G = +1 and SOIC (R) Packages AD9632, G = +2 Small Signal AD9631/ 1 8 NC NC 320 MHz AD9632 2 7 –INPUT +V S 250 MHz 3 6 +INPUT OUTPUT Large Signal (4 V p-p) –V 4 5 NC 175 MHz S TOP VIEW 180 MHz NC = NO CONNECT Ultralow Distortion (SFDR), Low Noise –113 dBc Typ @ 1 MHz A proprietary design architecture has produced an amplifier –95 dBc Typ @ 5 MHz that combines many of the best characteristics of both current –72 dBc Typ @ 20 MHz feedback and voltage feedback amplifiers. The AD9631 and 46 dBm Third Order Intercept @ 25 MHz AD9632 exhibit exceptionally fast and accurate pulse response 7.0 nV/÷Hz Spectral Noise Density (16 ns to 0.01%) as well as extremely wide small signal and large High Speed signal bandwidth and ultralow distortion. The AD9631 achieves Slew Rate 1300 V/�s –72 dBc at 20 MHz, and 320 MHz small signal and 175 MHz Settling 16 ns to 0.01%, 2 V Step large signal bandwidths. �3 V to �5 V Supply Operation 17 mA Supply Current These characteristics position the AD9631/AD9632 ideally for driving flash as well as high resolution ADCs. Additionally, the APPLICATIONS balanced high impedance inputs of the voltage feedback archi- ADC Input Driver tecture allow maximum flexibility when designing active filters. Differential Amplifiers IF/RF Amplifiers The AD9631/AD9632 are offered in the industrial (–40�C to Pulse Amplifiers +85�C) temperature range. They are available in PDIP and SOIC. Professional Video –30 DAC Current to Voltage V = �5V S Baseband and Video Communications R = 500� L V = 2V p-p Pin Diode Receivers O –50 Active Filters/Integrators/Log Amps –70 GENERAL DESCRIPTION –90 The AD9631 and AD9632 are very high speed and wide band- SECOND HARMONIC width amplifiers. They are an improved performance alternative to the AD9621 and AD9622. The AD9631 is unity gain stable. –110 THIRD HARMONIC The AD9632 is stable at gains of 2 or greater. Using a voltage feedback architecture, the AD9631/AD9632’s exceptional settling –130 time, bandwidth, and low distortion meet the requirements of 10k 100k 1M 10M 100M many applications that previously depended on current feedback FREQUENCY – Hz amplifiers. Its classical op amp structure works much more Figure 1. AD9631 Harmonic Distortion vs. predictably in many designs. Frequency, G = +1 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. HARMONIC DISTORTION – dBc AD9631/AD9632–SPECIFICATIONS (�V = �5 V; R = 100 �; A = 1 (AD9631); A = 2 (AD9632), unless otherwise noted.) ELECTRICAL CHARACTERISTICS S LOAD V V AD9631A AD9632A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth (–3 dB) Small Signal V � 0.4 V p-p 220 320 180 250 MHz OUT 1 Large Signal V = 4 V p-p 150 175 155 180 MHz OUT Bandwidth for 0.1 dB Flatness V = 300 mV p-p OUT AD9631, R = 140 W; 130 130 MHz F AD9632, R = 425W F Slew Rate, Average ± V = 4 V Step 1000 1300 1200 1500 V/ms OUT Rise/Fall Time V = 0.5 V Step 1.2 1.4 ns OUT V = 4 V Step 2.5 2.1 ns OUT Settling Time To 0.1% V = 2 V Step 11 11 ns OUT To 0.01% V = 2 V Step 16 16 ns OUT HARMONIC/NOISE PERFORMANCE Second Harmonic Distortion 2 V p-p; 20 MHz, R = 100W –64 –57 –54 –47 dBc L R = 500W –72 –65 –72 –65 dBc L Third Harmonic Distortion 2 V p-p; 20 MHz, R = 100W –76 –69 –74 –67 dBc L R = 500W –81 –74 –81 –74 dBc L Third Order Intercept 25 MHz 46 41 dBm Noise Figure R = 50 W 18 14 dB S Input Voltage Noise 1 MHz to 200 MHz 7.0 4.3 nV/÷Hz Input Current Noise 1 MHz to 200 MHz 2.5 2.0 pA/÷Hz Average Equivalent Integrated Input Noise Voltage 0.1 MHz to 200 MHz 100 60 mV rms Differential Gain Error (3.58 MHz) R = 150 W 0.03 0.06 0.02 0.04 % L Differential Phase Error (3.58 MHz) R = 150 W 0.02 0.04 0.02 0.04 Degree L Phase Nonlinearity DC to 100 MHz 1.1 1.1 Degree 2 DC PERFORMANCE R = 150 W , L 3 Input Offset Voltage 310 2 5 mV T –T 13 8 mV MIN MAX Offset Voltage Drift ±10 ±10 mV/�C Input Bias Current 2 7 2 7 mA T –T 10 10 mA MIN MAX Input Offset Current 0.1 3 0.1 3 mA T –T 55 mA MIN MAX Common-Mode Rejection Ratio V = ±2.5 V 70 90 70 90 dB CM Open-Loop Gain V = ±2.5 V 46 52 46 52 dB OUT T –T 40 40 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 500 500 kW Input Capacitance 1.2 1.2 pF Input Common-Mode Voltage Range ±3.4 ±3.4 V OUTPUT CHARACTERISTICS Output Voltage Range, R = 150 W±3.2 ±3.9 ±3.2 ±3.9 V L Output Current 70 70 mA Output Resistance 0.3 0.3 W Short Circuit Current 240 240 mA POWER SUPPLY Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V Quiescent Current 17 18 16 17 mA T –T 21 20 mA MIN MAX Power Supply Rejection Ratio T –T 50 60 56 66 dB MIN MAX NOTES 1 See Absolute Maximum Ratings and Theory of Operation sections of this data sheet. 2 Measured at A = 50. V 3 Measured with respect to the inverting input. Specifications subject to change without notice. –2– REV. C AD9631/AD9632 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by these Supply Voltage (+V to –V ) . . . . . . . . . . . . . . . . . . . . . 12.6 V S S devices is limited by the associated rise in junction temperature. Voltage Swing ¥ Bandwidth Product . . . . . . . . . . . 550 V-MHz 2 The maximum safe junction temperature for plastic encapsulated Internal Power Dissipation devices is determined by the glass transition temperature of the Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W plastic, approximately 150�C. Exceeding this limit temporarily Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W may cause a shift in parametric performance due to a change in Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V S the stresses exerted on the die by the package. Exceeding a junc- Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V tion temperature of 175�C for an extended period can result in Output Short Circuit Duration device failure. . . . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves Storage Temperature Range N, R . . . . . . . . . –65�C to +125�C While the AD9631 and AD9632 are internally short circuit Operating Temperature Range (A Grade) . . . . –40�C to +85�C protected, this may not be sufficient to guarantee that the maxi- Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300�C mum junction temperature (150�C) is not exceeded under all NOTES conditions. To ensure proper operation, it is necessary to observe 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- the maximum power derating curves. nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 2.0 section of this specification is not implied. Exposure to absolute maximum rating T = +150 C J conditions for extended periods may affect device reliability. 2 8-LEAD PDIP PACKAGE Specification is for device in free air: 8-Lead PDIP Package: q = 90∞C/W JA 1.5 8-Lead SOIC Package: q = 140∞C/W JA METALLIZATION PHOTO 1.0 Dimensions shown in inches and (millimeters) Connect Substrate to –V S 8-LEAD SOIC PACKAGE +V S –IN 2 7 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERA TURE – �C 0.046 (1.17) 6 Figure 2. Maximum Power Dissipation OUT vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option 3 4 AD9631 +IN –V S AD9631AN –40∞C to +85∞C PDIP N-8 0.050 (1.27) +V –IN S AD9631AR –40∞C to +85∞C SOIC R-8 2 7 AD9631AR-REEL –40∞C to +85∞C SOIC R-8 AD9631AR-REEL7 –40∞C to +85∞C SOIC R-8 AD9631CHIPS Die AD9632AN –40∞C to +85∞C PDIP N-8 AD9632AR –40∞C to +85∞C SOIC R-8 0.046 AD9632AR-REEL –40∞C to +85∞C SOIC R-8 (1.17) 6 AD9632AR-REEL7 –40∞C to +85∞C SOIC R-8 OUT 3 4 AD9632 +IN –V S CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9631/AD9632 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– MAXIMUM POWER DISSIPATION – W AD9631/AD9632–Typical Performance Characteristics R R F F 10�F 10�F +V +V S S PULSE GENERATOR 0.1�F 0.1�F T /T = 350ps R F 267� PULSE V IN GENERATOR R T V AD9631 V AD9631 OUT T /T = 350ps OUT R F 49.9� 130� V IN R = 100� R = 100� 0.1�F 0.1�F L L R T 100� 49.9� 10�F 10�F –V –V S S TPC 1. AD9631 Noninverting Configuration, G = +1 TPC 4. AD9631 Inverting Configuration, G = –1 1V 5ns 1V 5ns TPC 2. AD9631 Large Signal Transient Response; TPC 5. AD9631 Large Signal Transient Response; V = 4 V p-p, G = +1, R = 250 W V = 4 V p-p, G = –1, R = R = 267 W O F O F IN 100mV 5ns 100mV 5ns TPC 3. AD9631 Small Signal Transient Response; TPC 6. AD9631 Small Signal Transient Response; V = 400 mV p-p, G = +1, R = 140 W V = 400 mV p-p, G = –1, R = R = 267 W O F O F IN –4– REV. C AD9631/AD9632 R R F F 10�F 10�F +V +V S S PULSE PULSE GENERATOR GENERATOR 0.1�F 0.1�F T /T = 350ps R F T /T = 350ps R F R IN R IN V IN R T V AD9632 V AD9632 OUT OUT 49.9� 130� V IN R = 100� R = 100� 0.1�F 0.1�F L L R T 100� 49.9� 10�F 10�F –V –V S S TPC 7. AD9632 Noninverting Configuration, G = +2 TPC 10. AD9632 Inverting Configuration, G = –1 1V 5ns 1V 5ns TPC 11. AD9632 Large Signal Transient Response; TPC 8. AD9632 Large Signal Transient Response; V = 4 V p-p, G = –1, R = R = 422 W, R = 56.2 W V = 4 V p-p, G = +2, R = R = 422 W O F IN T O F IN 5ns 100mV 5ns 100mV TPC 12. AD9632 Small Signal Transient Response; TPC 9. AD9632 Small Signal Transient Response; V = 400 mV p-p, G = –1, R = R = 267 W, R = 61.9 W V = 400 mV p-p, G = +2, R = R = 274 W O F IN T O F IN REV. C –5– AD9631/AD9632 1 R F V = �5V S 150� R F 0 450 R = 100� L GAIN = +1 V = �5V R F –1 S R = 100� 200� L R F –2 V = 300mV p-p AD9631 O 50� 400 130� R L R F –3 100� N PACKAGE –4 350 –5 –6 300 –7 R PACKAGE –8 –9 250 1M 10M 100M 1G 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (R ) – � F TPC 13. AD9631 Small Signal Frequency TPC 16. AD9631 Small Signal –3 dB Bandwidth vs. R F Response, G = +1 0.1 1 R R F F 0 150� 0 250� V = �5V V = �5V –0.1 S S –1 R = 100� R R = 100� L F L R = 50� TO 250� –0.2 G = +1 140� –2 V = 4V p-p F O V = 300mV p-p BY 50� O R F –0.3 –3 100� R F –0.4 –4 120� –0.5 –5 –0.6 –6 –0.7 –7 –0.8 –8 –0.9 –9 1M 10M 100M 500M 1M 10M 100M 500M FREQUENCY – Hz FREQUENCY – Hz TPC 14. AD9631 0.1 dB Flatness, N Package TPC 17. AD9631 Large Signal Frequency (for R Package Add 20 W to R ) F Response, G = +1 90 100 1 80 80 0 70 60 V = �5V –1 S PHASE R = 100� L 60 40 –2 V = 300mV p-p O 50 20 –3 R F 40 0 267� –4 30 –20 GAIN –5 –40 20 –6 10 –60 –80 0 –7 –10 –100 –8 –120 –20 –9 10k 100k 1M 100M 1G 10M 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 15. AD9631 Open-Loop Gain and TPC 18. AD9631 Small Signal Frequency Phase Margin vs. Frequency, R = 100 W L Response, G = –1 –6– REV. C GAIN – dB GAIN – dB GAIN – dB PHASE MARGIN – Degrees –3dB BANDWIDTH – MHz OUTPUT – dB GAIN – dB AD9631/AD9632 –30 0.10 V = �5V S 0.05 R = 500� L G = +1 –50 0.00 V = 2V p-p O –0.05 –70 –0.10 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 0.10 –90 SECOND 0.05 HARMONIC 0.00 THIRD –110 HARMONIC –0.05 –0.10 –130 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 10k 100k 1M 10M 100M FREQUENCY – Hz TPC 19. AD9631 Harmonic Distortion vs. TPC 22. AD9631 Differential Gain and Phase Frequency, R = 500 W Error, G = +2, R = 150 W L L –30 0.3 V = �5V S R = 100� L 0.2 G = +1 –50 V = 2V p-p O 0.1 –70 SECOND 0.0 HARMONIC –90 –0.1 THIRD –110 HARMONIC –0.2 –130 –0.3 10k 100k 1M 10M 100M 0 10 20 30 40 50 60 70 80 FREQUENCY – Hz SETTLING TIME – ns TPC 20. AD9631 Harmonic Distortion vs. TPC 23. AD9631 Short-Term Settling Time, Frequency, R = 100 W 2 V Step, R = 100 W L L 60 0.3 55 0.2 50 45 0.1 40 0.0 35 30 –0.1 25 20 –0.2 10 20 30 40 50 60 70 80 90 100 0 123 45 67 8 910 FREQUENCY – MHz SETTLING TIME – �s TPC 21. AD9631 Third Order Intercept vs. Frequency TPC 24. AD9631 Long-Term Settling Time, 2 V Step, R = 100 W L REV. C –7– HARMONIC DISTORTION – dBc HARMONIC DISTORTION – dBc INTERCEPT – dBm DIFF PHASE – Degrees DIFF GAIN – % ERROR – % ERROR – % AD9631/AD9632 7 R F V = �5V S 350 6 325� R = 100� L R GAIN = +2 F V = �5V 5 S R 425� F R = 100� L 125� R 300 4 V = 300mV p-p F N PACKAGE O 225� 3 250 2 R F 1 R IN R PACKAGE 200 0 AD9632 100� R L –1 49.9� 150 –2 –3 150 200 100 250 300 350 400 450 500 550 1M 10M 100M 1G VALUE OF R , R – � FREQUENCY – Hz F IN TPC 25. AD9632 Small Signal Frequency TPC 28. AD9632 Small Signal –3 dB Bandwidth Response, G = +2 vs. R , R F IN 0.1 7 R F 0 6 525� V = �5V V = �5V S –0.1 S 5 R F R = 100� R = 100� L L 275� –0.2 G = +2 4 V = 4V p-p R O F R = 125� TO 525� F V = 300mV p-p O 325� BY 100� –0.3 3 R F 375� –0.4 2 R F 425� –0.5 1 –0.6 0 –0.7 –1 –0.8 –2 –0.9 –3 1M 10M 100M 1M 10M 100M 500M FREQUENCY – Hz FREQUENCY – Hz TPC 26. AD9632 0.1 dB Flatness, N Package TPC 29. AD9632 Large Signal Frequency (for R Package Add 20 W to R ) F Response, G = +2 65 1 60 0 100 55 50 V = �5V –1 S R = 100� 45 50 L PHASE –2 V = 300mV p-p O 40 35 0 –3 30 R , R 25 –50 F IN –4 267� 20 GAIN –5 15 –100 10 –6 5 –150 –7 0 –200 –5 –8 –10 –250 –15 –9 10k 100k 1M 100M 1G 10M 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 27. AD9632 Open-Loop Gain and Phase TPC 30. AD9632 Small Signal Frequency Margin vs. Frequency, R = 100 W Response, G = –1 L –8– REV. C A – dB OL OUTPUT – dB GAIN – dB PHASE – Degrees GAIN – dB OUTPUT – dB –3dB BANDWIDTH – MHz AD9631/AD9632 –30 0.04 V = �5V S 0.02 R = 500� L G = +2 –50 0.00 V = 2V p-p O –0.02 –70 –0.04 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH SECOND 0.04 –90 HARMONIC 0.02 THIRD 0.00 HARMONIC –110 –0.02 –130 –0.04 10k 100k 1M 10M 100M 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH FREQUENCY – Hz TPC 34. AD9632 Differential Gain and Phase TPC 31. AD9632 Harmonic Distortion vs. Error G = +2, R = 150 W Frequency, R = 500 W L L 0.2 –30 V = �5V S R = 100� L G = +2 –50 0.1 V = 2V p-p O SECOND HARMONIC –70 0.0 –90 –0.1 THIRD HARMONIC –0.2 –110 –130 –0.3 10k 100k 1M 10M 100M 0 10 20 30 40 50 60 70 80 FREQUENCY – Hz SETTLING TIME – ns TPC 32. AD9632 Harmonic Distortion vs. TPC 35. AD9632 Short-Term Settling Time, Frequency, R = 100 W 2 V Step, R = 100 W L L 50 0.3 45 0.2 40 35 0.1 30 0.0 25 20 –0.1 15 10 –0.2 10 20 30 40 50 60 70 80 90 100 0 123 45 67 8 910 FREQUENCY – MHz SETTLING TIME – �s TPC 33. AD9632 Third Order Intercept vs. Frequency TPC 36. AD9632 Long-Term Settling Time, 2 V Step, R = 100 W L REV. C –9– HARMONIC DISTORTION – dBc HARMONIC DISTORTION – dBc INTERCEPT – dBm ERROR – % DIFF PHASE – Degrees DIFF GAIN – % ERROR – % AD9631/AD9632 24 17 V = �5V V = �5V 21 S 15 S 18 13 15 11 12 9 9 7 6 5 3 3 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz TPC 37. AD9631 Noise vs. Frequency TPC 40. AD9632 Noise vs. Frequency 80 80 75 75 70 70 –PSRR 65 65 –PSRR 60 60 +PSRR +PSRR 55 55 50 50 45 45 40 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 0 0 10k 100k 1M 100M 1G 10k 100k 1M 100M 1G 10M 10M FREQUENCY – Hz FREQUENCY – Hz TPC 38. AD9631 PSRR vs. Frequency TPC 41. AD9632 PSRR vs. Frequency 100 100 V = �5V V = �5V S S 90 �V = 1V 90 �V = 1V CM CM R = 100� R = 100� L L 80 80 70 70 60 60 50 50 40 40 30 30 20 20 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 39. AD9631 CMRR vs. Frequency TPC 42. AD9632 CMRR vs. Frequency –10– REV. C INPUT NOISE VOLTAGE – nV/ Hz PSRR – dB CMRR – dB INPUT NOISE VOLTAGE – nV/ Hz PSRR – dB CMRR – dB AD9631/AD9632 1000 1350 V = �5V S 1250 GAIN = +1 100 1150 +A OL 1050 AD9632 10 950 –A OL 850 1 750 650 0.1 550 +A OL AD9631 450 –A OL 0.01 350 10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz JUNCTION TEMPERA TURE – �C TPC 43. AD9631 Output Resistance vs. Frequency TPC 46. Open-Loop Gain vs. Temperature 76 1000 V = �5V S 74 –PSRR GAIN = +1 AD9632 100 72 70 +PSRR 68 10 AD9632 66 –PSRR 64 1 AD9631 62 0.1 60 +PSRR 58 AD9631 56 0.01 10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz JUNCTION TEMPERA TURE – �C TPC 44. AD9632 Output Resistance vs. Frequency TPC 47. PSRR vs. Temperature 4.1 98 V = �5V S +V OUT 4.0 96 –V OUT R = 150� L 3.9 94 3.8 3.7 92 3.6 90 R = 50� L +V OUT 3.5 –V 88 OUT –CMRR 3.4 +CMRR 3.3 86 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERA TURE – �C JUNCTION TEMPERA TURE – �C TPC 45. AD9631/AD9632 Output Swing vs. Temperature TPC 48. AD9631/AD9632 CMRR vs. Temperature REV. C –11– OUTPUT SWING – V R – � R – � OUT OUT OPEN-LOOP GAIN – V/V CMRR – dB PSRR – dB AD9631/AD9632 21 250 AD9631 AD9631 �6V 20 240 SINK SOURCE 19 230 AD9632 �6V 18 220 SINK AD9631 AD9632 �5V 17 210 AD9632 �5V 16 200 15 190 SOURCE 14 180 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERA TURE – �C JUNCTION TEMPERA TURE – �C TPC 49. Supply Current vs. Temperature TPC 52. Short Circuit Current vs. Temperature –1.0 2.0 –1.5 1.5 AD9632 –2.0 1.0 +I B –2.5 0.5 –I V = �5V B S AD9632 AD9631 –3.0 0.0 V = �6V S –3.5 –0.5 –I B –4.0 –1.0 AD9631 V = �5V S –4.5 –1.5 +I V = �6V B S –5.0 –2.0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERA TURE – �C JUNCTION TEMPERA TURE – �C TPC 50. Input Offset Voltage vs. Temperature TPC 53. Input Bias Current vs. Temperature 220 100 180 100 3 WAFER LOTS 3 WAFER LOTS 200 COUNT = 573 COUNT = 1373 90 90 160 CUMULATIVE 180 CUMULATIVE 80 80 140 160 70 70 120 140 60 60 100 120 50 50 100 80 40 FREQ. DIST 40 80 60 30 30 FREQ. DIST 60 40 20 20 40 20 20 10 10 0 0 0 0 –7 –6 –5 –4 –3 –2 –1 0 1 23 45 67 –7 –6 –5 –4 –3 –2 –1 0 1 23 45 67 INPUT OFFSET VOLTAGE – mV INPUT OFFSET VOLTAGE – mV TPC 51. AD9631 Input Offset Voltage Distribution TPC 54. AD9632 Input Offset Voltage Distribution –12– REV. C COUNT INPUT OFFSET VOLTAGE – mV SUPPLY CURRENT – mA PERCENT COUNT INPUT BIAS CURRENT – �A SHORT CIRCUIT CURRENT – mA PERCENT AD9631/AD9632 THEORY OF OPERATION When the AD9631 is used in the transimpedance (I to V) mode, General such as in photodiode detection, the value of R and diode capaci- F The AD9631 and AD9632 are wide bandwidth, voltage feedback tance (C ) are usually known. Generally, the value of R selected I F amplifiers. Since their open-loop frequency response follows the will be in the kW range, and a shunt capacitor (C ) across R will F F conventional 6 dB/octave roll-off, their gain bandwidth product be required to maintain good amplifier stability. The value of is basically constant. Increasing their closed-loop gain results in C required to maintain optimal flatness (<1 dB peaking) and F a corresponding decrease in small signal bandwidth. This can settling time can be estimated as be observed by noting the bandwidth specification between the 1 22 AD9631 (gain of +1) and AD9632 (gain of +2). The AD9631/ 2 CC @21�� R –/R () FOIF OF [] AD9632 typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise peaking. where w is equal to the unity gain bandwidth product of the O amplifier in rad/sec, and C is the equivalent total input Feedback Resistor Choice I 6 capacitance at the inverting input. Typically w = 800 � 10 The value of the feedback resistor is critical for optimum perfor- O rad/sec (see TPC 15). mance on the AD9631 (gain of +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the As an example, choosing R = 10 kW and C = 5 pF requires C F I F AD9631. to be 1.1 pF (Note: C includes both source and parasitic circuit I capacitance). The bandwidth of the amplifier can be estimated At minimum stable gain (+1), the AD9631 provides optimum using the C calculated as dynamic performance with R = 140 W. This resistor acts as a F F parasitic suppressor only against damped RF oscillations that 16 . can occur due to lead (input, feedback) inductance and parasitic f @ 3d� 2�RC capacitance. This value of R provides the best combination of FF F wide bandwidth, low parasitic peaking, and fast settling time. R F In fact, for the same reasons, a 100 W–130 W resistor should be placed in series with the positive input for other AD9631 noninver- C F ting and all AD9631 inverting configurations. The correct connection is shown in Figures 3 and 4. I I C I AD9631 V OUT +V S R F 10�F G = 1 + R G Figure 5. Transimpedance Configuration 0.1�F 100�–130� V IN R IN For general voltage gain applications, the amplifier bandwidth R TERM AD9631/ V OUT AD9632 can be closely estimated as R F � O f @ 3dB 21 � +R/R 0.1�F () FG R G This estimation loses accuracy for gains of +2/–1 or lower due 10�F to the amplifier’s damping factor. For these “low gain” cases, –V S the bandwidth will actually extend beyond the calculated value (see TPCs 13 and 25). Figure 3. Noninverting Operation As a general rule, capacitor C will not be required if F +V S R F 10�F NG G = – RR ¥£ C R () G FG I 4 � O 0.1�F 100�–130� where NG is the noise gain (1 + R /R ) of the circuit. For most F G R IN voltage gain applications, this should be the case. AD9631/ V OUT AD9632 R F R G V IN 0.1�F R TERM 10�F –V S Figure 4. Inverting Operation REV. C –13– AD9631/AD9632 40 Pulse Response Unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the AD9631 and AD9632 provide “on-demand” current that increases proportionally to the input 30 “step” signal amplitude. This results in slew rates (1300 V/ms) comparable to wideband current feedback designs. This, combined with relatively low input noise current (2.0 pA/÷Hz), gives the AD9631 and AD9632 the best attributes of both voltage and 20 current feedback amplifiers. Large Signal Performance The outstanding large signal operation of the AD9631 and AD9632 is due to a unique, proprietary design architecture. In order to 10 maintain this level of performance, the maximum 550 V-MHz 0 510 15 20 25 C – pF product must be observed (e.g., @ 100 MHz, V £ 5.5 V p-p). L O Power Supply Bypassing Figure 7. Recommended R vs. Capacitive Load SERIES Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the APPLICATIONS power supply leads can form resonant circuits that produce The AD9631 and AD9632 are voltage feedback amplifiers well peaking in the amplifier’s response. In addition, if large current suited for applications such as photodetectors, active filters, and transients must be delivered to the load, then bypass capacitors log amplifiers. The devices’ wide bandwidth (320 MHz), phase (typically greater than 1 mF) will be required to provide the best margin (65�), low current noise (2.0 pA/÷Hz), and slew rate settling time and lowest distortion. A parallel combination of at (1300 V/ms) give higher performance capabilities to these appli- least 4.7 mF, and between 0.1 mF and 0.01 mF, is recommended. cations over previous voltage feedback designs. Some brands of electrolytic capacitors will require a small series With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the damping resistor ª4.7 W for optimum results. devices are an excellent choice for DAC I/V conversion. The same Driving Capacitive Loads characteristics along with low harmonic distortion make them The AD9631 and AD9632 were designed primarily to drive a good choice for ADC buffering/amplification. With superb nonreactive loads. If driving loads with a capacitive component is linearity at relatively high signal frequencies, the AD9631 and desired, the best frequency response is obtained by the addition of AD9632 are ideal drivers for ADCs up to 12 bits. a small series resistance as shown in Figure 6. The accompany- Operation as a Video Line Driver ing graph shows the optimum value for R versus capacitive SERIES The AD9631 and AD9632 have been designed to offer outstand- load. It is worth noting that the frequency response of the circuit ing performance as video line drivers. The important specifications when driving large capacitive loads will be dominated by the of differential gain (0.02%) and differential phase (0.02�) meet passive roll-off of R and C . SERIES L the most exacting HDTV demands for driving video loads. R F 274� 274� 10�F +V S R SERIES R IN AD9631/ 0.1�F AD9632 R R L IN C L 75� 1k� CABLE 75� AD9631/ 75� V OUT CABLE AD9632 75� 0.1�F V IN Figure 6. Driving Capacitive Loads 75� 10�F –V S Figure 8. Video Line Driver –14– REV. C R – � SERIES AD9631/AD9632 Active Filters Choose The wide bandwidth and low distortion of the AD9631 and F = Cutoff Frequency = 20 MHz O AD9632 are ideal for the realization of higher bandwidth active a = Damping Ratio = 1/Q = 2 filters. These characteristics, while being more common in –R4 many current feedback op amps, are offered in the AD9631 and H = Absolute Value of Circuit Gain = = 1 R1 AD9632 in a voltage feedback configuration. Many active filter Then configurations are not realizable with current feedback amplifiers. kF =21 � C O A multiple feedback active filter requires a voltage feedback 41 CH() +1 amplifier and is more demanding of op amp performance than C2 = 2 other active filter configurations, such as the Sallen-Key. In � general, the amplifier should have a bandwidth that is at least � R1 = 10 times the bandwidth of the filter if problems due to phase shift 2HK of the amplifier are to be avoided. � R3 = Figure 9 is an example of a 20 MHz low-pass multiple feedback 21 KH() + active filter using an AD9632. RH41 = ()R +5V A/D Converter Driver 10�F C1 R4 50pF As A/D converters move toward higher speeds with higher resolu- 154� 0.1�F R1 R3 tions, there becomes a need for high performance drivers that 154� 78.7� V will not degrade the analog signal to the converter. It is desirable IN C2 from a system’s standpoint that the A/D be the element in the AD9632 V OUT 100pF 100� signal chain that ultimately limits overall distortion. This places 0.1�F new demands on the amplifiers that are used to drive fast, high resolution A/Ds. 10�F With high bandwidth, low distortion, and fast settling time, the AD9631 and AD9632 make high performance A/D drivers for –5V advanced converters. Figure 10 is an example of an AD9631 used Figure 9. Active Filter Circuit as an input driver for an AD872, a 12-bit, 10 MSPS A/D converter. +5V DIGITAL 10� +5V ANALOG 7 DV DD 0.1�F 6 DGND +5V DIGITAL 4 +5V ANALOG AV DD 22 0.1�F DV 140� 5 DD AGND 0.1�F 23 10�F DGND CLOCK INPUT 21 CLK 0.1�F AD872 20 49.9� OTR 19 1 MSB AD9631 V INA 18 BIT2 130� ANALOG 17 BIT3 IN 16 0.1�F 2 BIT4 V INB 15 BIT5 27 14 10�F REF GND DIGITAL OUTPUT BIT6 13 BIT7 0.1�F 12 28 BIT8 –5V ANALOG 11 REF IN BIT9 10 BIT10 26 9 REF OUT BIT11 8 1�F BIT12 AGND AV AV SS SS 325 0.1�F 0.1�F –5V ANALOG Figure 10. AD9631 Used as Driver for an AD872, a 12-Bit, 10 MSPS A/D Converter REV. C –15– AD9631/AD9632 Layout Considerations large (0.47 mF–10 mF) tantalum electrolytic capacitor should be The specified high speed performance of the AD9631 and AD9632 connected in parallel, though not necessarily so close, to supply requires careful attention to board layout and component current for fast, large signal changes at the output. selection. Proper RF design techniques and low-pass parasitic The feedback resistor should be located close to the inverting input component selection are mandatory. pin in order to keep the stray capacitance at this node to a mini- The PCB should have a ground plane covering all unused portions mum. Capacitance variations of less than 1 pF at the inverting of the component side of the board to provide a low impedance input will significantly affect high speed performance. path. The ground plane should be removed from the area near Stripline design techniques should be used for long signal traces the input pins to reduce stray capacitance. (greater than about 1 inch). These should be designed with a Chip capacitors should be used for supply bypassing (see characteristic impedance of 50 W or 75 W and be properly termi- Figure 10). One end should be connected to the ground plane, nated at each end. and the other within 1/8 inch of each power pin. An additional –16– REV. C AD9631/AD9632 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 0.295 (7.49) 0.285 (7.24) 1 4 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.150 (3.81) 0.300 (7.62) BSC 0.135 (3.43) 0.015 0.120 (3.05) 0.180 (0.38) (4.57) MIN MAX 0.015 (0.38) 0.150 (3.81) 0.010 (0.25) SEATING 0.130 (3.30) PLANE 0.008 (0.20) 0.110 (2.79) 0.060 (1.52) 0.022 (0.56) 0.050 (1.27) 0.018 (0.46) 0.045 (1.14) 0.014 (0.36) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2440) 4.00 (0.1574) 3.80 (0.1497) 5.80 (0.2284) 1 4 0.50 (0.0196) 1.27 (0.0500) � 45� 1.75 (0.0688) BSC 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 8� 0.51 (0.0201) 0� 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. C –17– AD9631/AD9632 Revision History Location Page 7/03—Data Sheet changed from REV. B to REV. C. Deleted Evaluation Boards information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Deleted military CERDIP version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Change to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Change to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1/03—Data Sheet changed from REV. A to REV. B. Deleted DIP (N) Inverter, SOIC (R) Inverter, and DIP (N) Noninverter Evaluation Boards in Figures 12–14 . . . . . . . . . . . . . . . 17 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 –18– REV. C –19– –20– C00601–0–7/03(C)