ANALOG DEVICES AD9613

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9613 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 69.6 dBFS at 185 MHz f and 250 MSPS IN SFDR = 86 dBc at 185 MHz f and 250 MSPS IN VIN+A −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS A and PIPELINE IN 12 D0± 12-BIT . 250 MSPS ADC VIN–A . . PARALLEL Total power consumption: 770 mW at 250 MSPS VCM AD9613 . DDR LVDS . AND 1.8 V supply voltages VIN+B PIPELINE 12 D11± DRIVERS 12-BIT LVDS (ANSI-644 levels) outputs VIN–B ADC Integer 1-to-8 input clock divider (625 MHz maximum input) DCO± REFERENCE Sample rates of up to 250 MSPS OR± IF sampling frequencies of up to 400 MHz 1TO 8 Internal ADC voltage reference SERIAL PORT CLOCK OEB DIVIDER Flexible analog input range PDWN 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer SCLK SDIO CSB CLK+ CLK– SYNC 95 dB channel isolation/crosstalk NOTES 1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A Serial port control AND CHANNEL B LVDS OUTPUT DATA. Energy-saving power-down modes Figure 1. User-configurable, built-in self test (BIST) capability APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) Programming for setup and control is accomplished using a with sampling speeds of up to 250 MSPS. The AD9613 is designed 3-wire SPI-compatible serial interface. to support communications applications where low cost, small The AD9613 is available in a 64-lead LFCSP and is specified size, wide bandwidth, and versatility are desired. over the industrial temperature range of −40°C to +85°C. This The dual ADC cores feature a multistage, differential pipelined product is protected by a U.S. patent. architecture with integrated output error correction logic. Each PRODUCT HIGHLIGHTS ADC features wide bandwidth inputs supporting a variety of user- 1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. selectable input ranges. An integrated voltage reference eases design 2. Fast overrange and threshold detect. considerations. A duty cycle stabilizer (DCS) is provided to 3. Proprietary differential input maintains excellent SNR compensate for variations in the ADC clock duty cycle, performance for input frequencies of up to 400 MHz. allowing the converters to maintain excellent performance. 4. SYNC input allows synchronization of multiple devices. The ADC output data is routed directly to the two external 12-bit 5. 3-pin, 1.8 V SPI port for register programming and register LVDS output ports and formatted as either interleaved or channel readback. multiplexed. 6. Pin compatibility with the AD9643, allowing a simple Flexible power-down options allow significant power savings, migration up to 14 bits, and with the AD6649 and the AD6643. when desired. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09637-001 AD9613 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 23 Applications....................................................................................... 1 Voltage Reference ....................................................................... 25 General Description ......................................................................... 1 Clock Input Considerations...................................................... 25 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 27 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 27 Revision History ............................................................................... 2 ADC Overrange (OR)................................................................ 27 Specifications..................................................................................... 3 Channel/Chip Synchronization.................................................... 28 ADC DC Specifications............................................................... 3 Serial Port Interface (SPI).............................................................. 29 ADC AC Specifications ............................................................... 4 Configuration Using the SPI..................................................... 29 Digital Specifications ................................................................... 6 Hardware Interface..................................................................... 29 Switching Specifications .............................................................. 8 SPI Accessible Features.............................................................. 30 Timing Specifications .................................................................. 9 Memory Map .................................................................................. 31 Absolute Maximum Ratings.......................................................... 11 Reading the Memory Map Register Table............................... 31 Thermal Characteristics ............................................................ 11 Memory Map Register Table..................................................... 32 ESD Caution................................................................................ 11 Memory Map Register Description ......................................... 34 Pin Configurations and Function Descriptions ......................... 12 Applications Information .............................................................. 35 Typical Performance Characteristics ........................................... 16 Design Guidelines ...................................................................... 35 Equivalent Circuits ......................................................................... 22 Outline Dimensions....................................................................... 36 Theory of Operation ...................................................................... 23 Ordering Guide .......................................................................... 36 ADC Architecture ...................................................................... 23 Changes to Channel/Chip Synchronization Section ................. 28 REVISION HISTORY Changes to Reading the Memory Map Register Table 9/11—Rev. A to Rev. B Section and Transfer Register Map Section ................................ 31 Changes to Figure 1.......................................................................... 1 Changes to Register 0x02, Bits[5:4] ............................................. 32 Changes to Temperature Drift Parameters ................................... 3 Changes to Register 0x16, Bit 5 .................................................... 33 Changes Output Offset Voltage (V ), ANSI Mode Typ OS Added Register 0x3A ..................................................................... 34 Parameter and Output Offset Voltage (V ), Reduced Swing OS Deleted Register 0x59 .................................................................... 34 Mode Parameter................................................................................ 7 Changes to Bit 0—Master Sync Buffer Enable Section ............. 34 Changes to Output Enable Bar and Power-Down Pin Type Deleted SYNC Pin Control (Register 0x59) Section.................. 34 and Pin 47 Description .................................................................. 13 5/11—Rev. 0 to Rev. A Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ............. 14 Changes to Table 2, AD9613-170: Worst Second or Third Changes to Pin 42 and Pin 43, Output Enable Bar and Power- Harmonic and Worst Other (Harmonic or Spur) Max Values Down Pin Type, and Pin 47 Descriptions ................................... 15 and Spurious Free Dynamic Range Min Value .............................4 Changes to Typical Performance Characteristics Conditions.. 16 Changes to Fiugre 43...................................................................... 22 4/11—Revision 0: Initial Version Added ADC Overrange (OR) Section ......................................... 27 Rev. B | Page 2 of 36 Data Sheet AD9613 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled, unless otherwise noted. Table 1. AD9613-170 AD9613-210 AD9613-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±10 ±10 ±10 mV Gain Error Full +2/−6 +3/−5 ±4 %FSR Differential Nonlinearity (DNL) Full ±0.5 ±0.5 ±0.5 LSB 25°C ±0.25 ±0.25 ±0.25 LSB 1 Integral Nonlinearity (INL) Full ±0.5 ±0.6 ±0.8 LSB 25°C ±2.0 ±2.0 ±2.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±13 ±13 ±13 mV Gain Error Full ±2.5 +3.5/−2 +3.5/−2.5 %FSR TEMPERATURE DRIFT Offset Error Full ±5 ±5 ±5 ppm/°C Gain Error Full ±70 ±80 ±100 ppm/°C INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.39 0.39 0.39 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p 2 Input Capacitance Full 2.5 2.5 2.5 pF 3 Input Resistance Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 I Full 230 250 241 265 252 275 mA AVDD 1 I Full 142 160 159 185 176 210 mA DRVDD POWER CONSUMPTION 1 Sine Wave Input (DRVDD = 1.8 V) Full 670 738 720 810 770 873 mW 4 Standby Power Full 90 90 90 mW Power-Down Power Full 10 10 10 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK± pin inactive (that is, set to AVDD or AGND). Rev. B | Page 3 of 36 AD9613 Data Sheet ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, unless otherwise noted. Table 2. AD9613-170 AD9613-210 AD9613-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) f = 30 MHz 25°C 70.1 70.1 70.0 dBFS IN f = 90 MHz 25°C 70.0 70.0 69.8 dBFS IN Full 69.3 69.2 dBFS fIN = 140 MHz 25°C 69.8 69.8 69.6 dBFS fIN = 185 MHz 25°C 69.5 69.5 69.2 dBFS Full 67.8 dBFS f = 220 MHz 25°C 69.4 69.3 69.0 dBFS IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 69.1 69.1 69.0 dBFS f = 90 MHz 25°C 69.0 69.0 68.8 dBFS IN Full 68.2 68 dBFS fIN = 140 MHz 25°C 68.8 68.8 68.6 dBFS 68.5 68.5 68.2 fIN = 185 MHz 25°C dBFS Full 66.5 dBFS 68.4 68.3 68.0 f = 220 MHz 25°C dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) 25°C 11.2 11.2 11.2 Bits fIN = 30 MHz 25°C 11.2 11.2 11.1 Bits f = 90 MHz IN 25°C 11.1 11.1 11.1 Bits f = 140 MHz IN f = 185 MHz 25°C 11.1 11.1 11.0 Bits IN 25°C 11.1 11.0 11.0 Bits fIN = 220 MHz WORST SECOND OR THIRD HARMONIC 25°C dBc fIN = 30 MHz −94 −94 −90 25°C dBc fIN = 90 MHz −92 −94 −89 Full dBc −78 −80 25°C dBc f = 140 MHz −87 −88 −86 IN 25°C dBc f = 185 MHz −89 −83 −86 IN Full dBc −80 25°C dBc fIN = 220 MHz −80 −83 −85 SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 30 MHz 25°C 94 90 92 dBc IN 25°C dBc fIN = 90 MHz 92 90 89 Full dBc 78 80 25°C dBc fIN = 140 MHz 87 88 86 25°C dBc f = 185 MHz 89 83 86 IN Full dBc 80 25°C dBc fIN = 220 MHz 83 83 85 WORST OTHER (HARMONIC OR SPUR) 25°C dBc f = 30 MHz −97 −95 −93 IN 25°C dBc fIN = 90 MHz −96 −95 −92 Full dBc −78 −80 25°C dBc fIN = 140 MHz −97 −97 −91 25°C dBc f = 185 MHz −91 −96 −91 IN Full dBc −80 f = 220 MHz 25°C −93 −94 −89 dBc IN Rev. B | Page 4 of 36 Data Sheet AD9613 AD9613-170 AD9613-210 AD9613-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit TWO-TONE SFDR 25°C dBc f = 184.12 MHz (−7 dBFS), 88 88 88 IN 187.12 MHz (−7 dBFS) 2 Full dB CROSSTALK 95 95 95 3 FULL POWER BANDWIDTH 25°C 400 400 400 MHz 4 NOISE BANDWIDTH 25°C 1000 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved. 4 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally. Rev. B | Page 5 of 36 AD9613 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Full 0.3 3.6 Differential Input Voltage V p-p Full AGND AVDD Input Voltage Range V Full 0.9 1.4 Input Common-Mode Range V High Level Input Current Full 10 22 μA Low Level Input Current Full −22 −10 μA Full 4 Input Capacitance pF Full 8 10 12 Input Resistance kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −5 +5 μA Low Level Input Current Full −5 +5 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −5 +5 μA Low Level Input Current Full −80 +45 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUTS (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF Rev. B | Page 6 of 36 Data Sheet AD9613 Parameter Temp Min Typ Max Unit 2 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.22 1.35 V Differential Output Voltage (V ), Reduced Swing Mode Full 150 200 280 mV OD Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.22 1.35 V OS 1 Pull up. 2 Pull down. Rev. B | Page 7 of 36 AD9613 Data Sheet SWITCHING SPECIFICATIONS Table 4. AD9613-170 AD9613-210 AD9613-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 40 170 40 210 40 250 MSPS CLK Period, Divide-by-1 Mode (t) Full 5.8 4.8 4 ns CLK CLK Pulse Width High (t) CH Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 0.8 ns Aperture Delay (t) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (t) Full 4.8 4.8 4.8 ns PD DCO Propagation Delay (t) Full 5.5 5.5 5.5 ns DCO DCO to Data Skew (tSKEW) Full 0.3 0.7 1.1 0.3 0.7 1.1 0.3 0.7 1.1 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power Down) Full 250 250 250 μs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider. Rev. B | Page 8 of 36 Data Sheet AD9613 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SYNC TIMING REQUIREMENTS See Figure 3 for timing details t SYNC to the rising edge of CLK setup time 0.3 ns SSYNC tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS See Figure 58 for SPI timing diagram t Setup time between the data and the rising edge of SCLK 2 ns DS tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns t Hold time between CSB and SCLK 2 ns H t Minimum period that SCLK should be in a logic high state 10 ns HIGH t Minimum period that SCLK should be in a logic low state 10 ns LOW tEN_SDIO Time required for the SDIO pin to switch from an input to an output 10 ns relative to the SCLK falling edge (not shown in Figure 58) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input 10 ns relative to the SCLK rising edge (not shown in Figure 58) Rev. B | Page 9 of 36 AD9613 Data Sheet Timing Diagrams t A N – 1 N + 4 N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO– DCO+ t SKEW t PD PARALLEL INTERLEAVED D0± CH A CH B CH A CH B CH A CH B CH A CH B CH A (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . CHANNEL A AND . CHANNEL B . D11± CH A CH B CH A CH B CH A CH B CH A CH B CH A (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 CHANNEL MULTIPLEXED D0±/D1± CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 (EVEN/ODD) MODE (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . . CHANNEL A . D10±/D11± CH A10 CH A11 CH A10 CH A11 CH A10 CH A11 CH A10 CH A11 CH A10 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 CHANNEL MULTIPLEXED D0±/D1± CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 (EVEN/ODD) MODE (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . . CHANNEL B . D10±/D11± CH B10 CH B11 CH B10 CH B11 CH B10 CH B11 CH B10 CH B11 CH B10 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 Figure 2. Interleaved LVDS Mode Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Timing Inputs Rev. B | Page 10 of 36 09637-003 09637-002 Data Sheet AD9613 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the Electrical printed circuit board (PCB) increases the reliability of the AVDD to AGND −0.3 V to +2.0 V solder joints, maximizing the thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with solid ground CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V plane. As shown in Figure 40, airflow increases heat dissipation, SYNC to AGND −0.3 V to AVDD + 0.2 V which reduces θJA. In addition, metal in direct contact with the VCM to AGND −0.3 V to AVDD + 0.2 V package leads from metal traces, through holes, ground, and CSB to AGND −0.3 V to DRVDD + 0.3 V power planes reduces the θ . JA SCLK to AGND −0.3 V to DRVDD + 0.3 V SDIO to AGND −0.3 V to DRVDD + 0.3 V Table 7. Thermal Resistance OEB to AGND −0.3 V to DRVDD + 0.3 V Airflow PDWN to AGND −0.3 V to DRVDD + 0.3 V Velocity 1, 2 1, 3 1, 4 Package Type (m/sec) θJA θJC θJB Unit OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V D0−/D0+ Through D11−/D11+ to −0.3 V to DRVDD + 0.3 V 64-Lead LFCSP 0 26.8 1.14 10.4 °C/W AGND 9 mm × 9 mm 1.0 21.6 °C/W (CP-64-4) DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V 2.0 20.2 °C/W Environmental 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Operating Temperature Range −40°C to +85°C Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. (Ambient) 4 Per JEDEC JESD51-8 (still air). Maximum Junction Temperature 150°C Under Bias Storage Temperature Range −65°C to +125°C (Ambient) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 11 of 36 AD9613 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR CLK+ 1 48 PDWN CLK– 2 47 OEB SYNC 3 46 CSB 4 45 SCLK DNC DNC 5 44 SDIO DNC 6 43 OR+ AD9613 DNC 7 42 OR– DNC 8 PARALLEL LVDS 41 D11+ (MSB) DNC 9 TOP VIEW 40 D11– (MSB) DRVDD 10 (Not to Scale) 39 D10+ DNC 11 38 D10– DNC 12 37 DRVDD D0– (LSB) 13 36 D9+ D0+ (LSB) 14 35 D9– D1– 15 34 D8+ D1+ 16 33 D8– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode Pin No. Mnemonic Type Description ADC Power Supplies 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of the Exposed Paddle package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 4 to 9, 11, 12, 55, 56, 58 DNC Do not connect. Do not connect to these pins. 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). ADC Analog 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. B | Page 12 of 36 AVDD D2– 17 64 D2+ 18 63 AVDD DRVDD 19 62 VIN+B D3– 20 61 VIN–B D3+ 21 60 AVDD D4– 22 59 AVDD D4+ 23 58 DNC DCO– 57 VCM 24 DNC DCO+ 25 56 D5– 26 55 DNC D5+ 27 54 AVDD DRVDD 28 53 AVDD D6– 29 52 VIN–A D6+ 30 51 VIN+A D7– 31 50 AVDD D7+ 32 49 AVDD 09637-004 Data Sheet AD9613 Pin No. Mnemonic Type Description Digital Outputs 14 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 13 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 16 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 15 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 18 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 17 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 21 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 20 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 23 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 22 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 27 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 26 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 30 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 29 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 32 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 31 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 34 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 33 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 36 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 35 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 39 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 38 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 41 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 40 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data I/O. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power-Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev. B | Page 13 of 36 AD9613 Data Sheet PIN 1 INDICATOR CLK+ 1 48 PDWN CLK– 2 47 OEB SYNC 3 46 CSB DNC 4 45 SCLK DNC 5 44 SDIO AD9613 ORB– 6 43 ORA+ CHANNEL ORB+ 7 42 ORA– MULTIPLEXED DNC 8 41 A D10+/D11+ (MSB) (EVEN/ODD) DNC 9 40 A D10–/D11– (MSB) LVDS DRVDD 10 39 A D8+/D9+ TOP VIEW B D0–/D1– (LSB) 11 38 A D8–/D9– (Not to Scale) B D0+/D1+ (LSB) 12 37 DRVDD B D2–/D3– 13 36 A D6+/D7+ B D2+/D3+ 14 35 A D6–/D7– B D4–/D5– 15 34 A D4+/D5+ B D4+/D5+ 16 33 A D4–/D5– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 5. Pin Configuration (Top View) for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode Table 9. Pin Function Descriptions for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4 to 9, 26, 27, 55, 56, 58 DNC Do Not Connect. Do not connect to these pins. 0 AGND, Exposed Ground The exposed thermal paddle on the bottom of the package provides Paddle the analog ground for the part. This exposed paddle must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 7 ORB+ Output Channel B LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 6 ORB− Output Channel B LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. Rev. B | Page 14 of 36 B D6–/D7– 17 64 AVDD B D6+/D7+ 18 63 AVDD DRVDD 19 62 VIN+B B D8–/D9– 20 61 VIN–B B D8+/D9+ 21 60 AVDD B D10–/D11– (MSB) 59 AVDD 22 B D10+/D11+ (MSB) 23 58 DNC DCO– 24 57 VCM DCO+ 25 56 DNC DNC 26 55 DNC DNC 27 54 AVDD DRVDD 28 53 AVDD A D0–/D1– (LSB) 29 52 VIN–A A D0+/D1+ (LSB) 30 51 VIN+A A D2–/D3– 31 50 AVDD 49 A D2+/D3+ 32 AVDD 09637-005 Data Sheet AD9613 Pin No. Mnemonic Type Description 11 B D0−/D1− (LSB) Output Channel B LVDS Output Data 1/Data 0—Complement. 12 B D0+/D1+ (LSB) Output Channel B LVDS Output Data 1/Data 0—True. 13 B D2−/D3− Output Channel B LVDS Output Data 3/Data 2—Complement. 14 B D2+/D3+ Output Channel B LVDS Output Data 3/Data 2—True. 15 B D4−/D5− Output Channel B LVDS Output Data 5/Data 4—Complement. 16 B D4+/D5+ Output Channel B LVDS Output Data 5/Data 4—True. 17 B D6−/D7− Output Channel B LVDS Output Data 7/Data 6—Complement. 18 B D6+/D7+ Output Channel B LVDS Output Data 7/Data 6—True. 20 B D8−/D9− Output Channel B LVDS Output Data 9/Data 8—Complement. 21 B D8+/D9+ Output Channel B LVDS Output Data 9/Data 8—True. 22 B D10−/D11− Output Channel B LVDS Output Data 11/Data 10—Complement. 23 B D10+/D11+ Output Channel B LVDS Output Data 11/Data 10—True. 29 A D0−/D1− (LSB) Output Channel A LVDS Output Data 1/Data 0—Complement. 30 A D0+/D1+ (LSB) Output Channel A LVDS Output Data 1/Data 0—True. 31 A D2−/D3− Output Channel A LVDS Output Data 3/Data 2—Complement. 32 A D2+/D3+ Output Channel A LVDS Output Data 3/Data 2—True. 33 A D4−/D5− Output Channel A LVDS Output Data 5/Data 4—Complement. 34 A D4+/D5+ Output Channel A LVDS Output Data 5/Data 4—True. 35 A D6−/D7− Output Channel A LVDS Output Data 7/Data 6—Complement. 36 A D6+/D7+ Output Channel A LVDS Output Data 7/Data 6—True. 38 A D8−/D9− Output Channel A LVDS Output Data 9/Data 8—Complement. 39 A D8+/D9+ Output Channel A LVDS Output Data 9/Data 8—True. 40 A D10−/D11− Output Channel A LVDS Output Data 11/Data 10—Complement. 41 A D10+/D11+ Output Channel A LVDS Output Data 11/Data 10—True. 43 ORA+ Output Channel A LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 42 ORA− Output Channel A LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data I/O. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power-Down 47 OEB Input Output Enable Bar Input (Active Low). 48 PDWN Input Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev. B | Page 15 of 36 AD9613 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted. 0 120 170MSPS 90.1MHz @ –1dBFS SFDR (dBFS) –20 SNR = 69.7dB (70.7dBFS) 100 SFDR = 88dBc –40 80 SNR (dBFS) –60 60 SECOND HARMONIC THIRD HARMONIC –80 SFDR (dBc) 40 –100 SNR (dBc) 20 –120 –140 0 02 100304050607080 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 6. AD9613-170 Single-Tone FFT with f = 90.1 MHz IN Figure 9. AD9613-170 Single-Tone SNR/SFDR vs. Input Amplitude (A ) with f = 90.1 MHz IN IN 0 100 170MSPS SFDR (dBc) 185.1MHz @ –1dBFS 95 –20 SNR = 68.9dB (69.9dBFS) SFDR = 80dBc 90 –40 85 –60 THIRD HARMONIC 80 –80 75 –100 SNR (dBFS) 70 –120 65 –140 60 02 100304050607080 60 90 120 150 180 210 240 270 300 330 360 390 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD9613-170 Single-Tone FFT with f = 185.1 MHz Figure 10. AD9613-170 Single-Tone SNR/SFDR vs. Input Frequency (f ) IN IN 0 0 170MSPS 305.1MHz @ –1dBFS –20 SNR = 67dB (68dBFS) –20 SFDR = 79dBc SFDR (dBc) –40 –40 SECOND HARMONIC –60 IMD3 (dBc) THIRD HARMONIC –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 02 100304050607080 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 8. AD9613-170 Single-Tone FFT with fIN = 305.1 MHz Figure 11. AD9613-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 170 MSPS Rev. B | Page 16 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09637-015 09637-014 09637-013 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09637-017 09637-016 09637-018 Data Sheet AD9613 100 0 95 –20 SFDR (dBc) 90 –40 IMD3 (dBc) 85 SNR, CHANNEL B –60 SFDR, CHANNEL B 80 SNR, CHANNEL A SFDR, CHANNEL A –80 75 SFDR (dBFS) –100 70 IMD3 (dBFS) –120 65 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 40 50 60 70 80 90 100 110 120 130 140 150 160 170 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 12. AD9613-170 Two-Tone SFDR/IMD3 vs. Figure 15. AD9613-170 Single-Tone SNR/SFDR vs. Sample Rate (f ) S Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 170 MSPS with f = 90 MHz IN 0 16,000 170MSPS 0.38LSB rms 89.12MHz @ –7dBFS 16,384 TOTAL HITS 14,000 –20 92.12MHz @ –7dBFS SFDR = 87dBc (94dBFS) 12,000 –40 10,000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 02 100304050607080 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 13. AD9613-170 Two-Tone FFT with f = 89.12, f = 92.12 MHz, IN1 IN2 Figure 16. AD9613-170 Grounded Input Histogram f = 170 MSPS S 0 0 170MSPS 210MSPS 184.12MHz @ –7dBFS 90.1MHz @ –1dBFS –20 –20 187.12MHz @ –7dBFS SNR = 69.5dB (70.5dBFS) SFDR = 84dBc (91dBFS) SFDR = 88dBc –40 –40 –60 –60 THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 02 100304050607080 02 100304050607080 90 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. AD9613-170 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz, Figure 17. AD9613-210 Single-Tone FFT with fIN = 90.1 MHz f = 170 MSPS S Rev. B | Page 17 of 36 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09637-021 09637-020 09637-019 NUMBER OF HITS AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09637-024 09637-022 09637-023 AD9613 Data Sheet 0 100 210MSPS 185.1MHz @ –1dBFS 95 –20 SNR = 68.5dB (69.5dBFS) SFDR (dBc) SFDR = 88dBc 90 –40 85 –60 80 THIRD HARMONIC –80 75 –100 SNR (dBFS) 70 –120 65 –140 60 0 10 20 30 40 50 607080 90 100 60 90 120 150 180 210 240 270 300 330 360 390 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9613-210 Single-Tone FFT with fIN = 185.1 MHz Figure 21. AD9613-210 Single-Tone SNR/SFDR vs. Input Frequency (f ) IN 0 0 210MSPS 305.1MHz @ –1dBFS –20 SNR = 66.5dB (67.5dBFS) –20 SFDR = 75dBc SFDR (dBc) –40 –40 THIRD HARMONIC –60 IMD3 (dBc) –60 SECOND HARMONIC –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –120 0 10 20 30 40 50 607080 90 100 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 19. AD9613-210 Single-Tone FFT with f = 305.1 MHz IN Figure 22. AD9613-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 , fIN2 = 92.12 MHz, fS = 210 MSPS 120 0 SFDR (dBFS) 100 –20 SFDR (dBc) 80 –40 SNR (dBFS) IMD3 (dBc) 60 –60 SFDR (dBc) 40 –80 SNR (dBc) SFDR (dBFS) 20 –100 IMD3 (dBFS) –120 0 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 20. AD9613-210 Single-Tone SNR/SFDR vs. Input Amplitude (A ) with IN Figure 23. AD9613-210 Two-Tone SFDR/IMD3 vs. f = 90.1 MHz IN Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 210 MSPS Rev. B | Page 18 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09637-027 09637-026 09637-025 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09637-028 09637-030 09637-029 Data Sheet AD9613 0 14,000 210MSPS 0.437LSB rms 89.12MHz @ –7dBFS 16,384 TOTAL HITS –20 12,000 92.12MHz @ –7dBFS SFDR = 90dBc (97dBFS) –40 10,000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 02 100304050607080 90 100 N – 2 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 27. AD9613-210 Grounded Input Histogram Figure 24. AD9613-210 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 210 MSPS 0 0 250MSPS 210MSPS 90.1MHz @ –1dBFS 184.12MHz @ –7dBFS –20 –20 SNR = 68.9dB (69.9dBFS) 187.12MHz @ –7dBFS SFDR = 88dBc SFDR = 88dBc (95dBFS) –40 –40 SECOND HARMONIC –60 –60 THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 10 203040 5060 7080 90 100110120 02 100304050607080 90 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. AD9613-210 Two-Tone FFT with f = 184.12, f = 187.12 MHz, Figure 28. AD9613-250 Single-Tone FFT with fIN = 90.1 MHz IN1 IN2 f = 210 MSPS S 100 0 250MSPS 185.1MHz @ –1dBFS 95 –20 SNR = 68.1dB (69.1dBFS) SFDR = 85dBc 90 –40 –60 85 THIRD HARMONIC SNR, CHANNEL B SECOND HARMONIC SFDR, CHANNEL B 80 –80 SNR, CHANNEL A SFDR, CHANNEL A –100 75 70 –120 –140 65 40 60 80 100 120 140 160 180 200 0 10 203040 5060 7080 90 100110120 SAMPLE RATE (MSPS) FREQUENCY (MHz) Figure 26. AD9613-210 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 29. AD9613-250 Single-Tone FFT with f = 185.1 MHz IN with fIN = 90 MHz Rev. B | Page 19 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09637-033 09637-032 09637-031 NUMBER OF HITS AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09637-036 09637-035 09637-034 AD9613 Data Sheet 0 0 250MSPS 305.1MHz @ –1dBFS –20 SNR = 66.5dB (67.5dBFS) –20 SFDR = 83dBc SFDR (dBc) –40 –40 IMD3 (dBc) –60 SECOND HARMONIC –60 THIRD HARMONIC –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 0 10 20 30 40 50 60 70 80 90 100 110 120 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 30. AD9613-250 Single-Tone FFT with fIN = 305.1 MHz Figure 33. AD9613-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 250 MSPS 120 0 SFDR (dBFS) 100 –20 SFDR (dBc) 80 –40 SNR (dBFS) IMD3 (dBc) 60 –60 SFDR (dBc) –80 40 SFDR (dBFS) SNR (dBc) 20 –100 IMD3 (dBFS) –120 0 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 34. AD9613-250 Two-Tone SFDR/IMD3 vs. Figure 31. AD9613-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 250 MSPS fIN = 90.1 MHz 0 100 250MSPS 89.12MHz @ –7dBFS 95 –20 92.12MHz @ –7dBFS SFDR = 86dBc (93dBFS) SFDR (dBc) 90 –40 85 –60 80 –80 75 –100 SNR (dBFS) 70 –120 65 –140 60 0 10 20 30 40 50 60 70 80 90 100 110 120 60 80 100 120 140 160 180 200 220 240 260 FREQUENCY (MHz) FREQUENCY (MHz) Figure 35. AD9613-250 Two-Tone FFT with f = 89.12, f = 92.12 MHz, IN1 IN2 Figure 32. AD9613-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) f = 250 MSPS S Rev. B | Page 20 of 36 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09637-039 09637-038 09637-037 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) 09637-042 09637-041 09637-040 Data Sheet AD9613 0 16,000 250MSPS 0.39LSB rms 184.12MHz @ –7dBFS 16,384 TOTAL HITS 14,000 –20 187.12MHz @ –7dBFS SFDR = 86dBc (93dBFS) 12,000 –40 10,000 –60 8000 –80 6000 –100 4000 –120 2000 –140 0 0 10 20 30 40 50 60 70 80 90 100 110 120 N – 1 N N + 1 FREQUENCY (MHz) OUTPUT CODE Figure 38. AD9613-250 Grounded Input Histogram Figure 36. AD9613-250 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 250 MSPS 100 95 90 85 SNR, CHANNEL B SFDR, CHANNEL B 80 SNR, CHANNEL A SFDR, CHANNEL A 75 70 65 40 60 80 100 120 140 160 180 200 220 240 SAMPLE RATE (MSPS) Figure 37. AD9613-250 Single-Tone SNR/SFDR vs. Sample Rate (f ) S with f = 90.1 MHz IN Rev. B | Page 21 of 36 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09637-044 09637-043 NUMBER OF HITS 09637-045 AD9613 Data Sheet EQUIVALENT CIRCUITS AVDD 350Ω SCLK VIN OR 26kΩ PDWN OR OEB Figure 39. Equivalent Analog Input Circuit Figure 43. Equivalent SCLK, PDWN, or OEB Input Circuit AVDD AVDD AVDD AVDD 26kΩ 0.9V 350Ω CSB 15kΩ 15kΩ CLK+ CLK– Figure 40. Equivalent Clock lnput Circuit Figure 44. Equivalent CSB Input Circuit DRVDD AVDD AVDD V+ V– DATAOUT– DATAOUT+ SYNC 0.9V V– V+ 16kΩ 0.9V Figure 41. Equivalent LVDS Output Circuit Figure 45. Equivalent SYNC Input Circuit DRVDD 350Ω SDIO 26kΩ Figure 42. Equivalent SDIO Circuit . Rev. B | Page 22 of 36 09637-006 09637-063 09637-009 09637-007 09637-012 09637-011 09637-010 Data Sheet AD9613 THEORY OF OPERATION A small resistor in series with each input can help reduce the The AD9613 has two analog input channels, two filter channels, peak transient current required from the output stage of the and two digital output channels. The intermediate frequency (IF) driving source. A shunt capacitor can be placed across the input signal passes through several stages before appearing at the inputs to provide dynamic charging currents. This passive output port(s) as a filtered, and optionally, decimated digital signal. network creates a low-pass filter at the ADC input; therefore, The dual ADC design can be used for diversity reception of signals, the precise values are dependent on the application. where the ADCs operate identically on the same carrier but from In intermediate frequency (IF) undersampling applications, the two separate antennae. The ADCs can also be operated with shunt capacitors should be reduced. In combination with the independent analog inputs. The user can sample frequencies driving source impedance, the shunt capacitors limit the input from dc to 300 MHz using appropriate low-pass or band-pass bandwidth. Refer to the AN-742 Application Note, Frequency filtering at the ADC inputs with little loss in ADC performance. Domain Response of Switched-Capacitor ADCs; the AN-827 Operation to 400 MHz analog input is permitted but occurs at Application Note, A Resonant Approach to Interfacing Amplifiers to the expense of increased ADC noise and distortion. Switched-Capacitor ADCs; and the Analog Dialogue article, Synchronization capability is provided to allow synchronized “Transformer-Coupled Front-End for Wideband A/D Converters,” timing between multiple devices. for more information on this subject. Programming and control of the AD9613 are accomplished BIAS using a 3-pin, SPI-compatible serial interface. S S C C S FB ADC ARCHITECTURE VIN+ The AD9613 architecture consists of a dual front-end sample- C C PAR1 PAR2 and-hold circuit, followed by a pipelined, switched-capacitor H S S ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined C S VIN– architecture permits the first stage to operate on a new input C C PAR1 C FB PAR2 S sample and the remaining stages to operate on the preceding S samples. Sampling occurs on the rising edge of the clock. BIAS Figure 46. Switched-Capacitor Input Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digital- For best dynamic performance, the source impedances driving to-analog converter (DAC) and an interstage residue amplifier VIN+ and VIN− should be matched, and the inputs should be (MDAC). The MDAC magnifies the difference between the differentially balanced. reconstructed DAC output and the flash input for the next stage Input Common Mode in the pipeline. One bit of redundancy is used in each stage to The analog inputs of the AD9613 are not internally dc biased. facilitate digital correction of flash errors. The last stage simply In ac-coupled applications, the user must provide this bias consists of a flash ADC. externally. Setting the device so that VCM = 0.5 × AVDD (or The input stage of each channel contains a differential sampling 0.9 V) is recommended for optimum performance. An on-board circuit that can be ac- or dc-coupled in differential or single-ended common-mode voltage reference is included in the design and modes. The output staging block aligns the data, corrects errors, is available from the VCM pin. Using the VCM output to set the and passes the data to the output buffers. The output buffers are input common mode is recommended. Optimum performance powered from a separate supply, allowing digital output noise to be is achieved when the common-mode voltage of the analog input separated from the analog core. During power-down, the output is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM buffers go into a high impedance state. pin must be decoupled to ground by a 0.1 μF capacitor, as described ANALOG INPUT CONSIDERATIONS in the Applications Information section. Place this decoupling capacitor close to the pin to minimize the series resistance and The analog input to the AD9613 is a differential switched-capacitor inductance between the part and this capacitor. circuit that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in Figure 46). When the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. Rev. B | Page 23 of 36 09637-050 AD9613 Data Sheet Differential Input Configurations The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies Optimum performance is achieved while driving the AD9613 below a few megahertz. Excessive signal power can also cause in a differential input configuration. For baseband applications, the core saturation, which leads to distortion. AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential drivers provide excellent performance and a flexible interface to At input frequencies in the second Nyquist zone and above, the the ADC. noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9613. For applications where The output common-mode voltage of the ADA4930-2 is easily SNR is a key parameter, differential double balun coupling is set with the VCM pin of the AD9613 (see Figure 47), and the the recommended input configuration (see Figure 49). In this driver can be configured in a Sallen-Key filter topology to configuration, the input is ac-coupled, and the CML is provided provide band limiting of the input signal. to each input through a 33 Ω resistor. These resistors compensate 15pF for losses in the input baluns to provide a 50 Ω impedance to 200Ω the driver. 33Ω 15Ω 90Ω VIN– AVDD VIN 76.8Ω In the double balun and transformer configurations, the value 5pF of the input capacitors and resistors is dependent on the input ADC ADA4930-2 0.1µF frequency and source impedance. Based on these parameters, 33Ω 15Ω VCM VIN+ 120Ω the value of the input resistors and capacitors may need to be 15pF adjusted or some components may need to be removed. Table 10 200Ω displays recommended values to set the RC network for different 33Ω 0.1µF input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as Figure 47. Differential Input Configuration Using the ADA4938-2 a starting guide. Note that the values given in Table 10 are for For baseband applications where SNR is a key parameter, each R1, R2, C2, and R3 component shown in Figure 48 and differential transformer coupling is the recommended input Figure 49. configuration. An example is shown in Figure 48. To bias the An alternative to using a transformer-coupled input at frequencies analog input, the VCM voltage can be connected to the center in the second Nyquist zone is to use an amplifier with variable tap of the secondary winding of the transformer. gain. The AD8375 or AD8376 digital variable gain amplifier C2 (DVGAs) provides good performance for driving the AD9613. R3 R2 Figure 50 shows an example of the AD8376 driving the AD9613 VIN+ R1 through a band-pass antialiasing filter. 2V p-p 49.9Ω C1 ADC R2 R1 VCM VIN– 33Ω R3 0.1µF 0.1µF C2 Figure 48. Differential Transformer-Coupled Configuration Table 10. Example RC Network Frequency Range (MHz) R1 Series (Ω) C1 Differential (pF) R2 Series (Ω) C2 Shunt (pF) R3 Shunt (Ω) 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– 33Ω R3 0.1µF C2 Figure 49. Differential Double Balun Input Configuration Rev. B | Page 24 of 36 09637-052 09637-051 09637-053 Data Sheet AD9613 1000pF 180nH 220nH 1µH 165Ω VPOS 15pF AD9613 AD8376 5.1pF 3.9pF 301Ω VCM 2.5kΩ║2pF 165Ω 1nF 1µH 1nF 68nH 180nH 220nH 1000pF NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz) the clock from feeding through to other portions of the AD9613, VOLTAGE REFERENCE while preserving the fast rise and fall times of the signal, which are A stable and accurate voltage reference is built into the AD9613. critical to low jitter performance. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference ® Mini-Circuits voltage changes linearly. ADT1-1WT, 1:1Z ADC 390pF 390pF XFMR CLOCK CLOCK INPUT CONSIDERATIONS CLK+ INPUT 100Ω 50Ω For optimum performance, the AD9613 sample clock inputs, 390pF CLK– CLK+ and CLK−, should be clocked with a differential signal. The SCHOTTKY DIODES: HSMS2822 signal is typically ac-coupled into the CLK+ and CLK− pins via Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz) a transformer or via capacitors. These pins are biased internally (see Figure 51) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. 25Ω ADC AVDD 390pF 390pF CLOCK CLK+ INPUT 390pF 0.9V CLK– SCHOTTKY 25Ω DIODES: CLK+ CLK– HSMS2822 Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz) 4pF 4pF If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input Figure 51. Simplified Equivalent Clock Input Circuit pins, as shown in Figure 54. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, Clock Input Options AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ The AD9613 has a very flexible clock input structure. Clock ADCLK925 clock drivers offer excellent jitter performance. input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations 0.1µF 0.1µF ADC CLOCK section. CLK+ INPUT AD95xx 100Ω Figure 52 and Figure 53 show two preferable methods for clocking PECL DRIVER 0.1µF 0.1µF the AD9613 (at clock rates of up to 625 MHz). A low jitter clock CLOCK CLK– INPUT source is converted from a single-ended signal to a differential 240Ω 240Ω 50kΩ 50kΩ signal using an RF balun or RF transformer. Figure 54. Differential PECL Sample Clock (Up to 625 MHz) The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9613 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of Rev. B | Page 25 of 36 09637-055 09637-054 09637-057 09637-056 09637-058 AD9613 Data Sheet A third option is to ac-couple a differential LVDS signal to the Jitter Considerations sample clock input pins, as shown in Figure 55. The AD9510, High speed, high resolution ADCs are sensitive to the quality of AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, the clock input. The degradation in SNR at a given input frequency AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers (fIN) due to jitter (tJ) can be calculated by offer excellent jitter performance. (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF IN JRMS In the equation, the rms aperture jitter represents the root- 0.1µF ADC 0.1µF CLOCK mean-square of all jitter sources, which include the clock input, CLK+ INPUT the analog input signal, and the ADC aperture jitter specification. AD95xx 100Ω LVDS DRIVER 0.1µF IF undersampling applications are particularly sensitive to jitter, 0.1µF CLOCK CLK– as shown in Figure 56. INPUT 50kΩ 50kΩ 80 Figure 55. Differential LVDS Sample Clock (Up to 625 MHz) 75 Input Clock Divider 70 The AD9613 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The 65 duty cycle stabilizer (DCS) is enabled by default on power-up. The AD9613 clock divider can be synchronized using the external 60 0.05ps SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock 0.2ps 0.5ps divider to be resynchronized on every SYNC signal or only on 1ps 55 the first SYNC signal after the register is written. A valid SYNC 1.5ps MEASURED causes the clock divider to reset to its initial state. This synchro- 50 nization feature allows multiple parts to have their clock dividers 1 10 100 1000 INPUT FREQUENCY (MHz) aligned to guarantee simultaneous input sampling. Figure 56. AD9613-250 SNR vs. Input Frequency and Jitter Clock Duty Cycle The clock input should be treated as an analog signal in cases Typical high speed ADCs use both clock edges to generate a where aperture jitter may affect the dynamic range of the AD9613. variety of internal timing signals and, as a result, may be sensitive to Power supplies for clock drivers should be separated from the clock duty cycle. Commonly, a ±5% tolerance is required on the ADC output driver supplies to avoid modulating the clock signal clock duty cycle to maintain dynamic performance characteristics. with digital noise. Low jitter, crystal-controlled oscillators make The AD9613 contains a duty-cycle stabilizer (DCS) that retimes the best clock sources. If the clock is generated from another type the nonsampling (falling) edge, providing an internal clock of source (by gating, dividing, or another method), it should be signal with a nominal 50% duty cycle. This allows the user to retimed by the original clock at the last step. provide a wide range of clock input duty cycles without affecting Refer to the AN-501 Application Note, Aperture Uncertainty and the performance of the AD9613. ADC System Performance, and the AN-756 Application Note, Jitter on the rising edge of the input clock is still of paramount Sample Systems and the Effects of Clock Phase Noise and Jitter, concern and is not reduced by the duty cycle stabilizer. The for more information about jitter performance as it relates to duty cycle control loop does not function for clock rates less ADCs. than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Rev. B | Page 26 of 36 09637-059 SNR (dBc) 09637-060 Data Sheet AD9613 POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS As shown in Figure 57, the power dissipated by the AD9613 is The AD9613 output drivers can be configured for either ANSI proportional to its sample rate. The data in Figure 57 was taken LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. using the same operating conditions as those used for the Typical As detailed in Application Note AN-877, Interfacing to High Performance Characteristics section. Speed ADCs via SPI, the data format can be selected for offset 0.8 0.5 binary, twos complement, or gray code when using the SPI control. 0.7 TOTAL POWER 0.4 Digital Output Enable Function (OEB) 0.6 The AD9613 has a flexible three-state ability for the digital output 0.5 0.3 pins. The three-state mode is enabled using the OEB pin or I through the SPI interface. If the OEB pin is low, the output data 0.4 AVDD drivers are enabled. If the OEB pin is high, the output data drivers 0.2 0.3 are placed in a high impedance state. This OEB function is not I DRVDD intended for rapid access to the data bus. Note that OEB is 0.2 0.1 referenced to the digital output driver supply (DRVDD) and 0.1 should not exceed that supply voltage. 0 0 When using the SPI interface, the data outputs of each channel 40 60 80 100 120 140 160 180 200 220 240 ENCODE FREQUENCY (MSPS) can be independently three-stated by using the output enable bar Figure 57. AD9613-250 Power and Current vs. Sample Rate bit (Bit 4) in Register 0x14. Because the output data is interleaved, if only one of the two channels is disabled, the output data of By asserting PDWN (either through the SPI port or by asserting the remaining channel is repeated in both the rising and falling the PDWN pin high), the AD9613 is placed in power-down mode. output clock cycles. In this state, the ADC typically dissipates 10 mW. During power- down, the output drivers are placed in a high impedance state. Timing Asserting the PDWN pin low returns the AD9613 to its normal The AD9613 provides latched data with a pipeline delay of 10 input operating mode. Note that PDWN is referenced to the digital sample clock cycles. Data outputs are available one propagation output driver supply (DRVDD) and should not exceed that delay (t ) after the rising edge of the clock signal. PD supply voltage. Minimize the length of the output data lines and loads placed Low power dissipation in power-down mode is achieved by on them to reduce transients within the AD9613. These shutting down the reference, reference buffer, biasing networks, transients can degrade converter dynamic performance. and clock. Internal capacitors are discharged when entering The lowest typical conversion rate of the AD9613 is 40 MSPS. At power-down mode and then must be recharged when returning clock rates below 40 MSPS, dynamic performance can degrade. to normal operation. As a result, wake-up time is related to the Data Clock Output (DCO) time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. The AD9613 also provides data clock output (DCO) intended for capturing the data in an external register. Figure 2 shows a timing When using the SPI port interface, the user can place the ADC diagram of the AD9613 output modes. in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when ADC OVERRANGE (OR) faster wake-up times are required. See the Memory Map Register The ADC overrange indicator is asserted when an overrange is Description section and the AN-877 Application Note, detected on the input of the ADC. The overrange condition is Interfacing to High Speed ADCs via SPI, for additional details. determined at the output of the ADC pipeline and, therefore, is subject to a latency of 10 ADC clock. An overrange at the input is indicated by this bit 10 clock cycles after it. Table 11. Output Data Format VIN+ − VIN−, Input (V) Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR VIN+ − VIN– Less than –0.875 0000 0000 0000 1000 0000 0000 1 VIN+ − VIN– –0.875 0000 0000 0000 1000 0000 0000 0 VIN+ − VIN– 0 1000 0000 0000 0000 0000 0000 0 VIN+ − VIN– +0.875 1111 1111 1111 0111 1111 1111 0 VIN+ − VIN– Greater than +0.875 1111 1111 1111 0111 1111 1111 1 Rev. B | Page 27 of 36 TOTAL POWER (W) 09637-061 SUPPLY CURRENT (A) AD9613 Data Sheet CHANNEL/CHIP SYNCHRONIZATION The AD9613 has a SYNC input that allows the user flexible The SYNC input is internally synchronized to the sample clock. synchronization options for synchronizing the internal blocks. However, to ensure that there is no timing uncertainty between The sync feature is useful for guaranteeing synchronized operation multiple parts, the SYNC input signal should be synchronized across multiple ADCs. The input clock divider can be synchronized to the input clock signal. The SYNC input should be driven using the SYNC input. The divider can be enabled to synchronize using a single-ended CMOS type signal. on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. Rev. B | Page 28 of 36 Data Sheet AD9613 SERIAL PORT INTERFACE (SPI) The AD9613 SPI allows the user to configure the converter for All data is composed of 8-bit words. The first bit of each individual specific functions or operations through a structured register byte of serial data indicates whether a read or write command is space provided inside the ADC. The SPI gives the user added issued. This allows the serial data input/output (SDIO) pin to flexibility and customization, depending on the application. change direction from an input to an output. Addresses are accessed via the serial port and can be written to In addition to word length, the instruction phase determines or read from via the port. Memory is organized into bytes that can whether the serial frame is a read or write operation, allowing be further divided into fields. These fields are documented in the the serial port to be used both to program the chip and to read Memory Map section. For detailed operational information, see the contents of the on-chip memory. If the instruction is a readback the AN-877 Application Note, Interfacing to High Speed ADCs operation, performing a readback causes the serial data input/ via SPI. output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin port configuration register. For more information about this is used to synchronize the read and write data presented from/to and other features, see the AN-877 Application Note, Interfacing the ADC. The SDIO (serial data input/output) pin is a dual- to High Speed ADCs via SPI. purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an HARDWARE INTERFACE active-low control that enables or disables the read and write cycles. The pins described in Table 12 comprise the physical interface Table 12. Serial Port Interface Pins between the user programming device and the serial port of the Pin Function AD9613. The SCLK pin and the CSB pin function as inputs SCLK Serial Clock. The serial shift clock input, which is used to when using the SPI interface. The SDIO pin is bidirectional, synchronize serial interface reads and writes. functioning as an input during write phases and as an output SDIO Serial Data Input/Output. A dual-purpose pin that during readback. typically serves as an input or an output, depending on The SPI interface is flexible enough to be controlled by either the instruction being sent and the relative position in the timing frame. FPGAs or microcontrollers. One method for SPI configuration CSB Chip Select Bar. An active-low control that gates the read is described in detail in the AN-812 Application Note, and write cycles. Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The falling edge of CSB, in conjunction with the rising edge of The SPI port should not be active during periods when the full SCLK, determines the start of the framing. An example of the dynamic performance of the converter is required. Because the serial timing and its definitions can be found in Figure 58 and SCLK signal, the CSB signal, and the SDIO signal are typically Table 5. asynchronous to the ADC clock, noise from these signals can Other modes involving the CSB are available. The CSB can be degrade converter performance. If the on-board SPI bus is used for held low indefinitely, which permanently enables the device; other devices, it may be necessary to provide buffers between this bus and the AD9613 to prevent these signals from transitioning this is called streaming. The CSB can stall high between bytes at the converter inputs during critical sampling periods. to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase and its length is determined by the W0 and W1 bits. Rev. B | Page 29 of 36 AD9613 Data Sheet SPI ACCESSIBLE FEATURES Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9613 part-specific features are described in the Memory Map Register Description section. Table 13. Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power-down mode or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Digital Processing Allows the user to enable the synchronization features t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. B | Page 30 of 36 09637-062 Data Sheet AD9613 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip • “Bit is set” is synonymous with “bit is set to Logic 1” or configuration registers (Address 0x00 to Address 0x02); the “writing Logic 1 for the bit.” channel index and transfer registers (Address 0x05 and • “Clear a bit” is synonymous with “bit is set to Logic 0” or Address 0xFF); and the ADC functions registers, including “writing Logic 0 for the bit.” setup, control, and test (Address 0x08 to Address 0x3A). Transfer Register Map The memory map register table (see Table 14) documents the Address 0x08 to Address 0x20 and Address 0x3A are shadowed. default hexadecimal value for each hexadecimal address shown. Writes to these addresses do not affect part operation until a The column with the heading Bit 7 (MSB) is the start of the default transfer command is issued by writing 0x01 to Address 0xFF, hexadecimal value given. For example, Address 0x14, the output setting the transfer bit. This allows these registers to be updated mode register, has a hexadecimal default value of 0x05. This internally and simultaneously when the transfer bit is set. The means that Bit 0 = 1 and Bit 2 = 1, and the remaining bits are internal update takes place when the transfer bit is set and the 0s. This setting is the default output format value, which is twos bit autoclears. complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs Channel Specific Registers via SPI. This document details the functions controlled by Some channel setup functions, such as the signal monitor Register 0x00 to Register 0x25. The remaining register, Register thresholds, can be programmed to a different value for each 0x3A, is documented in the Memory Map Register Description channel. In these cases, channel address locations are internally section. duplicated for each channel. These registers and bits are designated Open and Reserved Locations in Table 14 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register All address and bit locations that are not included in Table 14 0x05. If both bits are set, the subsequent write affects the registers are not currently supported for this device. Unused bits of a of both channels. In a read cycle, only Channel A or Channel B valid address location should be written with 0s. Writing to these should be set to read one of the two registers. If both bits are set locations is required only when part of an address location is during an SPI read cycle, the part returns the value for Channel A. open (for example, Address 0x18). If the entire address location Registers and bits designated as global in Table 14 affect the entire is open (for example, Address 0x13), this address location should part and the channel features for which independent settings are not be written. not allowed between channels. The settings in Register 0x05 do Default Values not affect the global registers and bits. After the AD9613 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 14). Rev. B | Page 31 of 36 AD9613 Data Sheet MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are mirrored 1 (global) so that LSB- first mode or MSB-first mode registers correctly, regardless of shift mode 0x01 0x83 Read only Chip ID 8-bit chip ID[7:0] (AD9613 = 0x83) (global) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed (global) 00 = 250 MSPS grade ID used to 01 = 210 MSPS differentiate 11 = 170 MSPS devices; read only Channel Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set (global) (default) (default) to determine which device on the chip receives the next write command; applies to local registers only 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchron- (global) ously transfers data from the master shift register to the slave ADC Functions 0x08 Power modes Open Open External Open Open Open Internal power-down mode 0x00 Determines (local) power- (local) various down pin 00 = normal operation generic function 01 = full power-down modes of (local) 10 = standby chip 0 = power- 11 = reserved operation down 1 = standby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 (global) stabilizer (default) 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide (global) 000 = no delay 000 = divide by 1 values other 001 = 1 input clock cycle 001 = divide by 2 than 000 010 = 2 input clock cycles 010 = divide by 3 auto- 011 = 3 input clock cycles 011 = divide by 4 matically 100 = 4 input clock cycles 100 = divide by 5 cause the 101 = 5 input clock cycles 101 = divide by 6 duty cycle 110 = 6 input clock cycles 110 = divide by 7 stabilizer to 111 = 7 input clock cycles 111 = divide by 8 become active Rev. B | Page 32 of 36 Data Sheet AD9613 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0D Test mode User test Open Reset PN Reset PN Output test mode 0x00 When this (local) mode long gen short gen 0000 = off (default) register is control 0001 = midscale short set, the test 0 = 0010 = positive FS data is continuou 0011 = negative FS placed on s/repeat 0100 = alternating checkerboard the output pattern 0101 = PN long sequence pins in 1 = single 0110 = PN short sequence place of pattern, 0111 = one/zero word toggle normal data then 0s 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 (local) sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (local) (twos complement format) 0x14 Output mode Open Open Open Output Open Output invert Output format 0x05 Configures enable bar (local) 00 = offset binary the outputs (local) 1 = normal 01 = twos complement and the (default) (default) format of 0 = inverted 10 = gray code the data 11 = reserved (local) 0x15 Output Adjust Open Open Open Open LVDS output drive current adjust 0x01 (Global) 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 – 1111 = reserved 0x16 Clock phase Invert Open Open Open Open Open Open 0x00 Odd/Even control DCO clock Mode (global) Output Enable 0 = disabled 1 = enabled 0x17 DCO output Enable Open Open DCO clock delay 0x00 delay (global) DCO [delay = (3100 ps × register value/31 +100)] clock 00000 = 100 ps delay 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps 0x18 Input span Open Open Open Full-scale input voltage selection 0x00 Full-scale select (global) 01111 = 2.087 V p-p input … adjustment 00001 = 1.772 V p-p in 0.022 V 00000 = 1.75 V p-p (default) steps 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1[7:0] 0x00 Pattern 1 LSB (global) 0x1A User Test User Test Pattern 1[15:8] 0x00 Pattern 1 MSB (global) 0x1B User Test User Test Pattern 2[7:0] 0x00 Pattern 2 LSB (global) 0x1C User Test User Test Pattern 2[15:8] 0x00 Pattern 2 MSB (global) 0x1D User Test User Test Pattern 3[7:0] 0x00 Rev. B | Page 33 of 36 AD9613 Data Sheet Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Pattern 3 LSB (global) 0x1E User Test User Test Pattern 3[15:8] 0x00 Pattern 3 MSB (global) 0x1F User Test User Test Pattern 4[7:0] 0x00 Pattern 4 LSB (global) 0x20 User Test User Test Pattern 4[15:8] 0x00 Pattern 4 MSB (global) 0x24 BIST signature BIST signature[7:0] 0x00 Read only LSB (local) 0x25 BIST signature BIST signature[15:8] 0x00 Read only MSB (local) 0x3A Sync control Open Open Open Open Open Clock Clock Master sync 0x00 (global) divider divider buffer enable next sync sync only enable 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. it receives and to ignore the rest. The clock divider sync enable MEMORY MAP REGISTER DESCRIPTION bit (Address 0x3A, Bit 1) resets after it syncs. For more information on functions controlled in Register 0x00 Bit 1—Clock Divider Sync Enable to Register 0x25, see the AN-877 Application Note, Interfacing Bit 1 gates the sync pulse to the clock divider. The sync signal is to High Speed ADCs via SPI. enabled when Bit 1 is high and Bit 0 is high. This is continuous Sync Control (Register 0x3A) sync mode. Bits[7:3]—Reserved Bit 0—Master Sync Buffer Enable Bit 2—Clock Divider Next Sync Only Bit 0 must be set high to enable any of the sync functions. If If the master sync buffer enable bit (Address 0x3A, Bit 0) and the sync capability is not used, this bit should remain low to the clock divider sync enable bit (Address 0x3A, Bit 1) are high, conserve power. Bit 2 allows the clock divider to sync to the first sync pulse that Rev. B | Page 34 of 36 Data Sheet AD9613 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC DESIGN GUIDELINES and the PCB, a silkscreen should be overlaid to partition the Before starting system-level design and layout of the AD9613, continuous plane on the PCB into several uniform sections. it is recommended that the designer become familiar with these This provides several tie points between the ADC and the PCB guidelines, which discuss the special circuit connections and during the reflow process. Using one continuous plane with no layout requirements needed for certain pins. partitions guarantees only one tie point between the ADC and Power and Ground Recommendations the PCB. See the evaluation board for a PCB layout example. For detailed information about the packaging and PCB layout When connecting power to the AD9613, it is recommended of chip-scale packages, refer to the AN-772 Application Note, A that two separate 1.8 V supplies be used: one supply should be Design and Manufacturing Guide for the Lead Frame Chip Scale used for analog (AVDD), and a separate supply should be used Package (LFCSP). for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and VCM low frequencies. These capacitors should be located close to the The VCM pin should be decoupled to ground with a 0.1 μF point of entry at the PC board level and close to the pins of the capacitor, as shown in Figure 48. For optimal channel-to-channel part with minimal trace length. isolation, a 33 Ω resistor should be included between the AD9613 A single PCB ground plane should be sufficient when using the VCM pin and the Channel A analog input network connection, AD9613. With proper decoupling and smart partitioning of the as well as between the AD9613 VCM pin and the Channel B PCB analog, digital, and clock sections, optimum performance analog input network connection. is easily achieved. SPI Port Exposed Paddle Thermal Heat Slug Recommendations The SPI port should not be active during periods when the full It is mandatory that the exposed paddle on the underside of the dynamic performance of the converter is required. Because the ADC be connected to analog ground (AGND) to achieve the SCLK, CSB, and SDIO signals are typically asynchronous to the best electrical and thermal performance. A continuous, exposed ADC clock, noise from these signals can degrade converter (no solder mask) copper plane on the PCB should mate to the performance. If the on-board SPI bus is used for other devices, AD9613 exposed paddle, Pin 0. it may be necessary to provide buffers between this bus and the AD9613 to keep these signals from transitioning at the converter The copper plane should have several vias to achieve the lowest input pins during critical sampling periods. possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. Rev. B | Page 35 of 36 AD9613 Data Sheet OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9613BCPZ-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS CP-64-4 AD9613BCPZ-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS CP-64-4 AD9613BCPZ-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS CP-64-4 AD9613BCPZRL7-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS CP-64-4 AD9613BCPZRL7-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS CP-64-4 AD9613BCPZRL7-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS CP-64-4 AD9613-170EBZ Evaluation Board with AD9613, 170 MSPS AD9613-210EBZ Evaluation Board with AD9613, 210 MSPS AD9613-250EBZ Evaluation Board with AD9613, 250 MSPS 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09637-0-9/11(B) Rev. B | Page 36 of 36 091707-C