ANALOG DEVICES AD9609

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9609 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB DRVDD 1.8 V analog supply operation 1.8 V to 3.3 V output supply RBIAS SPI SNR VCM 61.5 dBFS at 9.7 MHz input OR PROGRAMMING DATA 61.0 dBFS at 200 MHz input D9 (MSB) VIN+ ADC SFDR CORE VIN– 75 dBc at 9.7 MHz input D0 (LSB) 73 dBc at 200 MHz input DCO VREF Low power SENSE 45 mW at 20 MSPS AD9609 REF 76 mW at 80 MSPS SELECT Differential input with 700 MHz bandwidth DIVIDE MODE On-chip voltage reference and sample-and-hold circuit DCS BY CONTROLS 1TO 8 2 V p-p differential analog input DNL = ±0.10 LSB CLK+ CLK– PDWN DFS MODE Serial port control options Figure 1. Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer PRODUCT HIGHLIGHTS Integer 1-to-8 input clock divider 1. The AD9609 operates from a single 1.8 V analog power Built-in selectable digital test pattern generation supply and features a separate digital output driver supply Energy-saving power-down modes to accommodate 1.8 V to 3.3 V logic families. Data clock out with programmable clock and data alignment 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is APPLICATIONS designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product Communications features and functions, such as data output formatting, Diversity radio systems internal clock divider, power-down, DCO and data output Multimode digital receivers (D9 to D0) timing and offset adjustments, and voltage GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA reference modes. Smart antenna systems 4. The AD9609 is packaged in a 32-lead RoHS compliant Battery-powered instruments LFCSP that is pin compatible with the AD9629 12-bit ADC Handheld scope meters and the AD9649 14-bit ADC, enabling a simple migration Portable medical imaging path between 10-bit and 14-bit converters sampling from Ultrasound 20 MSPS to 80 MSPS. Radar/LIDAR PET/SPECT imaging Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 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CMOS OUTPUT BUFFER 08541-001 AD9609 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 22 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 22 Revision History ............................................................................... 2 Timing ......................................................................................... 23 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 24 Specif ica t ions ..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 24 DC Specifications ......................................................................... 4 Output Test Modes ..................................................................... 24 AC Specifications .......................................................................... 5 Serial Port Interface (SPI) .............................................................. 25 Digital Specifications ................................................................... 6 Configuration Using the SPI ..................................................... 25 Switching Specifications .............................................................. 7 Hardware Interface ..................................................................... 26 Timing Specifications .................................................................. 8 Configuration Without the SPI ................................................ 26 Absolute Maximum Ratings ............................................................ 9 SPI Accessible Features .............................................................. 26 Thermal Characteristics .............................................................. 9 Memory Map .................................................................................. 27 ESD Caution .................................................................................. 9 Reading the Memory Map Register Table ............................... 27 Pin Configuration and Function Descriptions ........................... 10 Open Locations .......................................................................... 27 Typical Performance Characteristics ........................................... 11 Default Values ............................................................................. 27 AD9609-80 .................................................................................. 11 Memory Map Register Table ..................................................... 28 AD9609-65 .................................................................................. 13 Memory Map Register Descriptions ........................................ 30 AD9609-40 .................................................................................. 14 Applications Information .............................................................. 31 AD9609-20 .................................................................................. 15 Design Guidelines ...................................................................... 31 Equivalent Circuits ......................................................................... 16 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 32 Analog Input Considerations .................................................... 17 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9609 GENERAL DESCRIPTION A differential clock input with selectable internal 1 to 8 divide ratio The AD9609 is a monolithic, single channel 1.8 V supply, controls all internal conversion cycles. An optional duty cycle 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital stabilizer (DCS) compensates for wide variations in the clock duty converter (ADC). It features a high performance sample-and- cycle while maintaining excellent overall ADC performance. hold circuit and on-chip voltage reference. The digital output data is presented in offset binary, gray code, The product uses multistage differential pipeline architecture or twos complement format. A data output clock (DCO) is with output error correction logic to provide 10-bit accuracy at provided to ensure proper latch timing with receiving logic. Both 80 MSPS data rates and to guarantee no missing codes over the 1.8 V and 3.3 V CMOS levels are supported. full operating temperature range. The AD9609 is available in a 32-lead RoHS-compliant LFCSP The ADC contains several features designed to maximize and is specified over the industrial temperature range (−40°C flexibility and minimize system cost, such as programmable to +85°C). clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 0 | Page 3 of 32 AD9609 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. AD9609-20/AD9609-40 AD9609-65 AD9609-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.45 +0.05 +0.55 −0.45 +0.05 +0.55 −0.45 +0.05 +0.55 % FSR 1 Gain Error Full −1.5 −1.5 −1.5 % FSR 2 Differential Nonlinearity (DNL) Full ±0.15/±0.25 ±0.25 ±0.25 LSB 25°C ±0.05/±0.08 ±0.15 ±0.07 LSB 2 Integral Nonlinearity (INL) Full ±0.35 ±0.45 ±0.45 LSB 25°C ±0.15 ±0.15 ±0.15 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.984 0.996 1.008 0.984 0.996 1.008 0.984 0.996 1.008 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.06 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p 3 Input Capacitance Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 IAVDD Full 24.9/29.7 27.0/32.0 37.1 39.5 41.8 45 mA 2 IDRVDD (1.8 V) Full 1.4/2.2 3.6 4.3 mA 2 Full 2.5/4.1 6.6 7.9 mA IDRVDD (3.3 V) POWER CONSUMPTION DC Input Full 45.2/54.7 67.7 76.3 mW 2 Full 46.3/57.4 52.0/61.0 73.3 78.0 83.0 92 mW Sine Wave Input (DRVDD = 1.8 V) 2 Full 53.1/67.0 88.6 89.5 mW Sine Wave Input (DRVDD = 3.3 V) 4 Standby Power Full 34 34 34 mW Power-Down Power Full 0.5 0.5 0.5 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. 0 | Page 4 of 32 AD9609 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. AD9609-20/AD9609-40 AD9609-65 AD9609-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 61.7 61.5 61.5 dBFS IN f = 30.5 MHz 25°C 61.7 61.5 61.5 dBFS IN Full 61.2 61.0 dBFS fIN = 70 MHz 25°C 61.6 61.5 61.5 dBFS Full 61.0 dBFS fIN = 200 MHz 25°C 61.0 61.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 61.6 61.4 61.4 dBFS fIN = 30.5 MHz 25°C 61.5 61.3 61.4 dBFS Full 60.7/60.9 60.5 dBFS f = 70 MHz 25°C 61.5 61.4 61.4 dBFS IN Full 60.5 dBFS fIN = 200 MHz 25°C 60 60 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 9.9 9.9 9.9 Bits fIN = 30.5 MHz 25°C 9.9 9.9 9.9 Bits fIN = 70 MHz 25°C 9.9 9.9 9.9 Bits f = 200 MHz 25°C 9.6 9.6 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −81 −78 −78 dBc f = 30.5 MHz 25°C −80 −80 −80 dBc IN Full −67 −65.5 dBc fIN = 70 MHz 25°C −82 −78 −78 dBc Full −68 dBc fIN = 200 MHz 25°C −73 −73 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 78 75 75 dBc fIN = 30.5 MHz 25°C 80.5 75 75 dBc Full 67 65.5 dBc f = 70 MHz 25°C 78 75 75 dBc IN Full 68 dBc fIN = 200 MHz 25°C 73 73 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −82 −80 −80 dBc IN fIN = 30.5 MHz 25°C −82 −80 −80 dBc Full −74 −72 dBc f = 70 MHz 25°C −82 −80 −80 dBc IN Full −73 dBc f = 200 MHz 25°C −80 −80 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 78 78 dBc IN ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 32 AD9609 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. AD9609-20/AD9609-40/AD9609-65/AD9609-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 μA Full 3.29 V OH High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, I = 50 μA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 32 AD9609 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. AD9609-20/AD9609-40 AD9609-65 AD9609-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (t) Full 3 3 3 ns DCO DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 8 8 8 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO t SKEW DATA N – 8 N – 7 N – 6 N – 5 N – 4 t PD Figure 2. CMOS Output Data Timing Rev. 0 | Page 7 of 32 08541-002 AD9609 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Rev. 0 | Page 8 of 32 AD9609 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. VREF to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance SENSE to AGND −0.3 V to AVDD + 0.2 V Airflow VCM to AGND −0.3 V to AVDD + 0.2 V Package Velocity RBIAS to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 1,2 Type (m/sec) θJA θJC θJB ΨJT Unit CSB to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 0.3 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 0.5 °C/W SDIO/PDWN to AGND −0.3 V to DRVDD + 0.3 V 2.5 29.1 0.8 °C/W MODE/OR to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. D0 through D9 to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCO to AGND −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Typical θJA is specified for a 4-layer PCB with a solid ground Storage Temperature Range (Ambient) −65°C to +150°C plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the Stresses above those listed under Absolute Maximum Ratings package leads from metal traces, through holes, ground, and may cause permanent damage to the device. This is a stress power planes, reduces the θ . JA rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute ESD CAUTION maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 32 AD9609 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 24 AVDD PIN 1 CLK– 2 23 MODE/OR INDICATOR AVDD 3 22 DCO CSB 4 21 D9 (MSB) AD9609 SCLK/DFS 5 20 D8 TOP VIEW SDIO/PDWN 6 19 D7 (Not to Scale) NC 7 18 D6 NC 8 17 D5 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 (Exposed Pad) AGND The exposed paddle is the only ground connection. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull- down. See Table 15 for details. 7 to 10 NC Do not connect. 11 to 12, 14 to 21 D0 (LSB) to ADC Digital Outputs. D9 (MSB) 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 25 VREF 1.0 V Voltage Reference Input/Output. See Table 10. 26 SENSE Reference Mode Selection. See Table 10. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. 0 | Page 10 of 32 08541-003 32 AVDD NC 9 NC 10 31 VIN+ (LSB) D0 11 30 VIN– D1 12 29 AVDD DRVDD 13 28 RBIAS D2 14 27 CM V D3 15 26 SENSE D4 16 25 VREF AD9609 TYPICAL PERFORMANCE CHARACTERISTICS AD9609-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 9.7MHz @ –1dBFS 30.5MHz @ –1dBFS SNR = 60.5dB (61.5dBFS) SNR = 60.5dB (61.5dBFS) –20 –20 SFDR = 83.5dBc SFDR = 80.3dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10152025303540 0 5 10152025303540 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9609-80 Single-Tone FFT with fIN = 9.7 MHz Figure 7. AD9609-80 Single-Tone FFT with fIN = 30.5 MHz 0 0 80MSPS 80MSPS 200MHz @ –1dBFS 70.3MHz @ –1dBFS SNR = 60.4dB (61.4dBFS) SNR = 60.1dB (60.1dBFS) –20 –20 SFDR = 82.2dBc SFDR = 74.176dBc –40 –40 –60 –60 2 –80 –80 3 + 6 5 4 –100 –100 –120 –120 0 5 10152025303540 0 5 10152025303540 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9609-80 Single-Tone FFT with fIN = 70.3 MHz Figure 8. AD9609-80 Single-Tone FFT with fIN = 200 MHz 0 80MSPS –10 30.5MHz @ –7dBFS –15 32.5MHz @ –7dBFS SFDR = 78dBc –30 –30 SFDR (dBc) –45 IMD3 (dBc) –50 –60 F1 + F2 –70 SFDR (dBFS) –75 2F1 – F2 F2 – F1 2F1 – F2 2F2 + F1 –90 –90 IMD3 (dBFS) –105 –110 –120 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 4 8 12 16 20 24 28 32 36 40 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 6. AD9609-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz Rev. 0 | Page 11 of 32 AMPLITUDE (dB) AMPLITUDE (dBFS) AMPLITUDE (dB) 08541-036 08541-062 08541-033 SFDR/IMD3 (dBFS/dBc) AMPLITUDE (dBFS) AMPLITUDE (dB) 08541-134 08541-034 08541-054 AD9609 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 85 0.20 0.16 80 SFDR (dBc) 0.12 75 0.08 0.04 70 0 65 –0.04 SNR (dBFS) –0.08 60 –0.12 55 –0.16 50 –0.20 0 50 100 150 200 24 224 424 624 824 1024 AIN FREQUENCY (MHz) OUTPUT CODE Figure 10. AD9609-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 13. DNL Error with fIN = 9.7 MHz 85 1.0 0.8 SFDR (dBc) 80 0.6 0.4 75 0.2 0 70 –0.2 –0.4 65 –0.6 SNR (dBFS) –0.8 60 –1.0 0 102030405060 70 80 24 224 424 624 824 1024 SAMPLE RATE (MHz) OUTPUT CODE Figure 14. INL with f = 9.7 MHz Figure 11. AD9609-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz IN 90 80 SFDRFS 70 SNRFS 60 50 40 SFDR 30 SNR 20 10 0 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBc) Figure 12. AD9609-80 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN Rev. 0 | Page 12 of 32 SNR/SFDR (dBc/dBFS) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08541-057 08541-055 08541-061 DNL ERROR (LSB) INL ERROR (LSB) 08541-037 08541-038 AD9609 AD9609-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 0 65MSPS –10 9.7MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) –20 SFDR = 83.1dBc –30 SFDR (dBc) –40 –50 IMD3 (dBc) –60 –70 –80 SFDR (dBFS) –90 –100 IMD3 (dBFS) –110 –120 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 5 1015202530 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 18.AD9609-65 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz Figure 15. AD9609-65 Single-Tone FFT with f = 9.7 MHz IN IN 0 85 65MSPS 70.3MHz @ –1dBFS 80 –20 SNR = 60.6dB (61.6dBFS) SFDR (dBc) SFDR = 83.4dBc 75 –40 70 –60 65 SNR (dBFS) –80 60 –100 55 –120 50 0 5 1015202530 0 50 100 150 200 FREQUENCY (MHz) AIN FREQUENCY (MHz) Figure 19. AD9609-65 SNR/SFDR vs. Input Frequency (AIN) with Figure 16. AD9609-65 Single-Tone FFT with fIN = 70.3 MHz 2 V p-p Full Scale 0 65MSPS 30.5MHz @ –1dBFS –20 SNR = 60.6dB (61.6dBFS) SFDR = 83.9dBc –40 –60 –80 –100 –120 0 5 1015202530 FREQUENCY (MHz) Figure 17. AD9609-65 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 13 of 32 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 08541-031 08541-032 08541-030 SFDR/IMD3 (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08541-056 08541-060 AD9609 AD9609-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 90 0 40MSPS 80 SFDRFS 9.7MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) –20 SFDR = 82.0dBc 70 SNRFS 60 –40 50 –60 40 SFDR 30 –80 SNR 20 –100 10 0 –120 0 5 10 15 20 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBc) FREQUENCY (MHz) Figure 20. AD9609-40 Single-Tone FFT with f = 9.7 MHz Figure 22. AD9609-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz IN 0 40MSPS 30.5MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) –20 SFDR = 83.8dBc –40 –60 –80 –100 –120 0 246 8 1012 141618 20 FREQUENCY (MHz) Figure 21. AD9609-40 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 14 of 32 AMPLITUDE (dB) AMPLITUDE (dB) 08541-029 08541-028 SNR/SFDR (dBc/dBFS) 08541-059 AD9609 AD9609-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 90 20MSPS SFDR (dBFS) 80 9.7MHz @ –1dBFS –20 SNR = 60.6dBFS (61.6dBFS) SFDR = 81.3dBc 70 SNR (dBFS) –40 60 50 –60 SFDR (dBc) 40 SNR (dBc) 30 –80 20 –100 10 0 –120 0 2 468 10 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBc) Figure 23. AD9609-20 Single-Tone FFT with f = 9.7 MHz Figure 25. AD9609-20 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN IN 0 20MSPS 30.5MHz @ –1dBFS –20 SNR = 60.6dBFS (61.6dBFS) SFDR = 84.0dBc –40 –60 –80 –100 –120 0 2 468 10 FREQUENCY (MHz) Figure 24. AD9609-20 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 15 of 32 AMPLITUDE (dB) AMPLITUDE (dB) 08541-026 08541-024 SNR/SFDR (dBc/dBFS) 08541-058 AD9609 EQUIVALENT CIRCUITS DRVDD AVDD VIN± Figure 26. Equivalent Analog Input Circuit Figure 30. Equivalent D0 to D9 and OR Digital Output Circuit DRVDD AVDD SCLK/DFS, 350Ω MODE, 375Ω SDIO/PDWN VREF 30kΩ 7.5kΩ Figure 31. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit Figure 27. Equivalent VREF Circuit AVDD DRVDD AVDD 30kΩ 375Ω 350Ω SENSE CSB Figure 28. Equivalent SENSE Circuit Figure 32. Equivalent CSB Input Circuit 5Ω CLK+ 15kΩ 0.9V AVDD 15kΩ 5Ω CLK– 375Ω RBIAS AND VCM Figure 29. Equivalent Clock Input Circuit Figure 33. Equivalent RBIAS and VCM Circuit Rev. 0 | Page 16 of 32 08541-039 08541-046 08541-040 08541-047 08541-042 08541-045 08541-044 08541-043 AD9609 THEORY OF OPERATION high IF frequencies. Either a shunt capacitor or two single-ended The AD9609 architecture consists of a multistage, pipelined ADC. capacitors can be placed on the inputs to provide a matching Each stage provides sufficient overlap to correct for flash errors in passive network. This ultimately creates a low-pass filter at the the preceding stage. The quantized outputs from each stage are input to limit unwanted broadband noise. See the AN-742 combined into a final 10-bit result in the digital correction logic. Application Note, the AN-827 Application Note, and the Analog The pipelined architecture permits the first stage to operate with a Dialogue article “Transformer-Coupled Front-End for Wideband new input sample while the remaining stages operate with pre- A/D Converters” (Volume 39, April 2005) for more information. In ceding samples. Sampling occurs on the rising edge of the clock. general, the precise values depend on the application. Each stage of the pipeline, excluding the last, consists of a low Input Common Mode resolution flash ADC connected to a switched-capacitor DAC The analog inputs of the AD9609 are not internally dc-biased. and an interstage residue amplifier (for example, a multiplying Therefore, in ac-coupled applications, the user must provide a digital-to-analog converter (MDAC)). The residue amplifier dc bias externally. Setting the device so that VCM = AVDD/2 is magnifies the difference between the reconstructed DAC output recommended for optimum performance, but the device can and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction function over a wider range with reasonable performance, as of flash errors. The last stage simply consists of a flash ADC. shown in Figure 35 and Figure 36. 100 The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjust- 90 ment of the output voltage swing. During power-down, the output buffers go into a high impedance state. 80 SFDR (dBc) ANALOG INPUT CONSIDERATIONS The analog input to the AD9609 is a differential switched- 70 capacitor circuit designed for processing differential input SNR (dBFS) signals. This circuit can support a wide common-mode range 60 while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize 50 signal-dependent errors and achieve optimum performance. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 INPUT COMMON-MODE VOLTAGE (V) Figure 35. SNR/SFDR vs. Input Common-Mode Voltage, f = 32.1 MHz, f = 80 MSPS H IN S 100 C PAR H VIN+ C SAMPLE 90 SS SS C SAMPLE VIN– 80 SFDR (dBc) H C PAR H 70 SNR (dBFS) Figure 34. Switched-Capacitor Input Circuit 60 The clock signal alternately switches the input circuit between sample-and-hold mode (see Figure 34). When the input circuit 50 is switched to sample mode, the signal source must be capable 0.50.60.70.80.91.0 1.11.21.3 of charging the sample capacitors and settling within one-half INPUT COMMON-MODE VOLTAGE (V) of a clock cycle. A small resistor in series with each input can Figure 36. SNR/SFDR vs. Input Common-Mode Voltage, help reduce the peak transient current injected from the output fIN = 10.3 MHz, fS = 20 MSPS stage of the driving source. In addition, low Q inductors or ferrite An on-board, common-mode voltage reference is included in beads can be placed on each leg of the input to reduce high diffe- the design and is available from the VCM pin. The VCM pin rential capacitance at the analog inputs and, therefore, achieve must be decoupled to ground by a 0.1 μF capacitor, as described the maximum bandwidth of the ADC. Such use of low Q inductors in the Applications Information section. or ferrite beads is required when driving the converter front end at Rev. 0 | Page 17 of 32 08541-006 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08541-140 08541-139 AD9609 Differential Input Configurations At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve Optimum performance is achieved while driving the AD9609 in a the true SNR performance of the AD9609. For applications above differential input configuration. For baseband applications, the ~10 MHz where SNR is a key parameter, differential double balun AD8138, ADA4937-2, and ADA4938-2 differential drivers provide coupling is the recommended input configuration (see Figure 40). excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily An alternative to using a transformer-coupled input at frequencies set with the VCM pin of the AD9609 (see Figure 37), and the in the second Nyquist zone is to use the AD8352 differential driver. driver can be configured in a Sallen-Key filter topology to An example is shown in Figure 41. See the AD8352 data sheet provide band limiting of the input signal. for more information. 200Ω 33Ω In any configuration, the value of Shunt Capacitor C is dependent VIN– VIN 76.8Ω AVDD on the input frequency and source impedance and may need to 90Ω 10pF ADA4938-2 ADC be reduced or removed. Table 9 displays the suggested values to set 0.1µF the RC network. However, these values are dependent on the 120Ω 33Ω VCM VIN+ input signal and should be used only as a starting guide. 200Ω Figure 37. Differential Input Configuration Using the ADA4938-2 Table 9. Example RC Network R Series For baseband applications below ~10 MHz where SNR is a key Frequency Range (MHz) (Ω Each) C Differential (pF) parameter, differential transformer-coupling is the recommended 0 to 70 33 22 input configuration. An example is shown in Figure 38. To bias 70 to 200 125 Open the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. Single-Ended Input Configuration VIN+ A single-ended input can provide adequate performance in R cost-sensitive applications. In this configuration, SFDR and 2V p-p 49.9Ω C ADC distortion performance degrade due to the large input common- R VCM mode swing. If the source impedances on each input are matched, VIN– there should be little effect on SNR performance. Figure 39 0.1µF shows a typical single-ended input configuration. Figure 38. Differential Transformer-Coupled Configuration 10µF AVDD 1kΩ The signal characteristics must be considered when selecting R VIN+ a transformer. Most RF transformers saturate at frequencies 1V p-p 0.1µF 49.9Ω 1kΩ below a few megahertz (MHz). Excessive signal power can also AVDD ADC C cause core saturation, which leads to distortion. 1kΩ R VIN– 10µF 0.1µF 1kΩ Figure 39. Single-Ended Input Configuration 0.1µF 0.1µF R VIN+ 2V p-p 25Ω P S S P C ADC A 0.1µF 25Ω 0.1µF R VCM VIN– Figure 40. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+ 2 200Ω C ADC AD8352 R R C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN– 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 41. Differential Input Configuration Using the AD8352 Rev. 0 | Page 18 of 32 08541-007 08541-008 08541-010 08541-011 08541-009 AD9609 0 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the –0.5 AD9609. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. –1.0 The various reference modes are summarized in the sections that INTERNAL VREF = 0.996V follow. The Reference Decoupling section describes the best –1.5 practices for PCB layout of VREF. –2.0 Internal Reference Connection A comparator within the AD9609 detects the potential at the –2.5 SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, –3.0 the reference amplifier switch is connected to the internal resistor 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 divider (see Figure 42), setting VREF to 1.0 V. LOAD CURRENT (mA) Figure 43. VREF Accuracy vs. Load Current VIN+ VIN– External Reference Operation The use of an external reference may be necessary to enhance ADC the gain accuracy of the ADC or improve thermal drift charac- CORE teristics. Figure 44 shows the typical drift characteristics of the internal reference in 1.0 V mode. VREF 4 1.0µF 0.1µF SELECT 3 LOGIC 2 SENSE VREF ERROR (mV) 1 0.5V 0 ADC –1 –2 Figure 42. Internal Reference Configuration –3 In either internal or external reference mode, the maximum –4 input range of the ADC can be varied by configuring SPI –5 Address 0x18 as shown in Table 11, resulting in a selectable differential span from 1 V p-p to 2 V p-p. –6 –40 –20 0 20 40 60 80 TEMPERATURE (°C) If the internal reference of the AD9609 is used to drive multiple Figure 44. Typical VREF Drift converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 43 shows When the SENSE pin is tied to AVDD, the internal reference is how the internal reference voltage is affected by loading. disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 27). The internal buffer generates the posi- tive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Table 11. Scaled Differential Span Summary Selected Mode Resulting VREF (V) SPI Register 0x18 (Hex) Resulting Differential Span (V p-p) Fixed Internal or External Reference 1.0 (internal or external) 0xC0 1.0 Fixed Internal or External Reference 1.0 (internal or external) 0xC8 1.14 Fixed Internal or External Reference 1.0 (internal or external) 0xD0 1.33 Fixed Internal or External Reference 1.0 (internal or external) 0xD8 1.6 Fixed Internal or External Reference 1.0 (internal or external) 0xE0 2.0 Rev. 0 | Page 19 of 32 08541-012 REFERENCE VOLTAGE ERROR (%) VREF ERROR (mV) 08541-052 08541-014 AD9609 If a low jitter clock source is not available, another option is to CLOCK INPUT CONSIDERATIONS ac couple a differential PECL signal to the sample clock input For optimum performance, clock the AD9609 sample clock pins, as shown in Figure 48. The AD9510/AD9511/AD9512/ inputs, CLK+ and CLK−, with a differential signal. The signal AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer is typically ac-coupled into the CLK+ and CLK− pins via a excellent jitter performance. transformer or capacitors. These pins are biased internally (see Figure 45) and require no external bias. AVDD 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x 100Ω ADC 0.9V PECL DRIVER 0.1µF 0.1µF CLOCK CLK– CLK+ CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ 2pF 2pF Figure 48. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 49. The AD9510/ Figure 45. Equivalent Clock Input Circuit AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 Clock Input Options clock drivers offer excellent jitter performance. The AD9609 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. 0.1µF 0.1µF Regardless of the type of signal being used, clock source jitter is CLOCK CLK+ INPUT of great concern, as described in the Jitter Considerations section. AD951x 100Ω ADC LVDS DRIVER 0.1µF Figure 46 and Figure 47 show two preferred methods for clock- 0.1µF CLOCK CLK– INPUT ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock 50kΩ 50kΩ source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun. Figure 49. Differential LVDS Sample Clock (Up to 625 MHz) The RF balun configuration is recommended for clock frequencies In some applications, it may be acceptable to drive the sample between 125 MHz and 625 MHz, and the RF transformer is clock inputs with a single-ended 1.8 V CMOS signal. In such recommended for clock frequencies from 10 MHz to 200 MHz. applications, drive the CLK+ pin directly from a CMOS gate, and The back-to-back Schottky diodes across the transformer/ bypass the CLK− pin to ground with a 0.1 μF capacitor (see balun secondary limit clock excursions into the AD9609 to Figure 50). approximately 0.8 V p-p differential. V CC This limit helps prevent the large voltage swings of the clock OPTIONAL 0.1µF 0.1µF 1kΩ AD951x from feeding through to other portions of the AD9609 while 100Ω CLOCK CLK+ CMOS DRIVER INPUT preserving the fast rise and fall times of the signal that are 1 1kΩ 50Ω ADC critical to a low jitter performance. CLK– ® 0.1µF Mini-Circuits ADT1-1WT, 1:1 Z 0.1µF 0.1µF 1 50Ω RESISTOR IS OPTIONAL. XFMR CLOCK CLK+ INPUT Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 100Ω 50Ω ADC 0.1µF Input Clock Divider CLK– SCHOTTKY 0.1µF The AD9609 contains an input clock divider with the ability DIODES: HSMS2822 to divide the input clock by integer values between 1 and 8. Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz) Optimum performance can be obtained by enabling the inter- nal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. 1nF 0.1µF CLOCK CLK+ INPUT 50Ω ADC 0.1µF 1nF CLK– SCHOTTKY DIODES: HSMS2822 Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz) Rev. 0 | Page 20 of 32 08541-016 08541-018 08541-017 08541-021 08541-020 08541-019 AD9609 Clock Duty Cycle Jitter Considerations Typical high speed ADCs use both clock edges to generate High speed, high resolution ADCs are sensitive to the quality a variety of internal timing signals and, as a result, may be of the clock input. The degradation in SNR from the low fre- sensitive to clock duty cycle. Commonly, a ±5% tolerance is quency SNR (SNRLF) at a given input frequency (fINPUT) due to required on the clock duty cycle to maintain dynamic jitter (tJRMS) can be calculated by performance characteristics. (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS The AD9609 contains a duty cycle stabilizer (DCS) that retimes In the previous equation, the rms aperture jitter represents the the nonsampling (falling) edge, providing an internal clock clock input jitter specification. IF undersampling applications signal with a nominal 50% duty cycle. This allows the user to are particularly sensitive to jitter, as illustrated in Figure 52. provide a wide range of clock input duty cycles without 80 affecting the performance of the AD9609. Noise and distortion performance are nearly flat for a wide range of duty cycles with 75 0.05ps the DCS on, as shown in Figure 51. 70 Jitter in the rising edge of the input is still of concern and is not 0.2ps easily reduced by the internal stabilization circuit. The duty 65 cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated 60 0.5ps with it that must be considered in applications in which the 55 1.0ps clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease 1.5ps 50 before the DCS loop is relocked to the input signal. 2.0ps 3.0ps 2.5ps 45 80 1 10 100 1k FREQUENCY (MHz) 75 Figure 52. SNR vs. Input Frequency and Jitter 70 The clock input should be treated as an analog signal when DCS ON aperture jitter may affect the dynamic range of the AD9609. To 65 avoid modulating the clock signal with digital noise, keep power 60 supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best 55 DCS OFF clock sources. If the clock is generated from another type of source 50 (by gating, dividing, or another method), it should be retimed by the original clock at the last step. 45 For more information, see the AN-501 Application Note and 40 10 20 30 40 50 60 70 80 the AN-756 Application Note available at www.analog.com. POSITIVE DUTY CYCLE (%) Figure 51. SNR vs. DCS On/Off Rev. 0 | Page 21 of 32 SNR (dBFS) 08541-053 SNR (dBFS) 08541-022 AD9609 Low power dissipation in power-down mode is achieved by POWER DISSIPATION AND STANDBY MODE shutting down the reference, reference buffer, biasing networks, As shown in Figure 53, the analog core power dissipated by the and clock. Internal capacitors are discharged when entering power- AD9609 is proportional to its sample rate. The digital power down mode and then must be recharged when returning to normal dissipation of the CMOS outputs are determined primarily by operation. As a result, wake-up time is related to the time spent the strength of the digital drivers and the load on each output bit. in power-down mode, and shorter power-down cycles result in The maximum DRVDD current (IDRVDD) can be calculated as proportionally shorter wake-up times. IDRVDD = V × C × f × N DRVDD LOAD CLK When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows where N is the number of output bits (22, in the case of the the user to keep the internal reference circuitry powered when AD9609). faster wake-up times are required. See the Memory Map section This maximum current occurs when every output bit switches for more details. on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of f /2. In practice, the DRVDD current is estab- CLK DIGITAL OUTPUTS lished by the average number of output bits switching, which The AD9609 output drivers can be configured to interface with is determined by the sample rate and the characteristics of the 1.8 V to 3.3 V CMOS logic families. Output data can also be analog input signal. multiplexed onto a single output bus to reduce the total number Reducing the capacitive load presented to the output drivers can of traces required. minimize digital power consumption. The data in Figure 53 was The CMOS output drivers are sized to provide sufficient output taken using the same operating conditions as those used for the current to drive a wide variety of logic families. However, large Typical Performance Characteristics, with a 5 pF load on each drive currents tend to cause current glitches on the supplies and output driver. may affect converter performance. 85 Applications requiring the ADC to drive large capacitive loads 80 or large fanouts may require external buffers or latches. 75 The output data format can be selected to be either offset binary 70 or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). 65 AD9609-80 60 As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset 55 AD9609-65 binary, twos complement, or gray code when using the SPI control. 50 AD9609-40 45 Table 12. SCLK/DFS and SDIO/PDWN Mode Selection 40 (External Pin Mode) AD9609-20 Voltage at Pin SCLK/DFS SDIO/PDWN 35 10 20 30 40 50 60 70 80 AGND Offset binary (default) Normal operation CLOCK RATE (MSPS) (default) Figure 53. AD9609 Analog Core Power vs. Clock Rate DRVDD Twos complement Outputs disabled In SPI mode, the AD9609 can be placed in power-down mode Digital Output Enable Function (OEB) directly via the SPI port, or by using the programmable external MODE pin. In non-SPI mode, power-down is achieved by assert- When using the SPI interface, the data outputs and DCO can be ing the PDWN pin high. In this state, the ADC typically dissipates independently three-stated by using the programmable external 500 μW. During power-down, the output drivers are placed in a MODE pin. The MODE pin (OEB) function is enabled via high impedance state. Asserting PDWN low (or the MODE pin Bits[6:5] of Register 0x08. in SPI mode) returns the AD9609 to its normal operating mode. If the MODE pin is configured to operate in traditional OEB Note that PDWN is referenced to the digital output driver mode, and the MODE pin is low, the output data drivers and supply (DRVDD) and should not exceed that supply voltage. DCOs are enabled. If the MODE pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note the MODE pin is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Rev. 0 | Page 22 of 32 ANALOG CORE POWER (mW) 08541-051 AD9609 The lowest typical conversion rate of the AD9609 is 3 MSPS. At TIMING clock rates below 3 MSPS, dynamic performance can degrade. The AD9609 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation Data Clock Output (DCO) delay (tPD) after the rising edge of the clock signal. The AD9609 provides a data clock output (DCO) signal intended for capturing the data in an external register. The CMOS Minimize the length of the output data lines and loads placed data outputs are valid on the rising edge of DCO, unless the DCO on them to reduce transients within the AD9609. These clock polarity has been changed via the SPI. See Figure 2 for a transients can degrade converter dynamic performance. graphical timing description. Table 13. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 10 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 10 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 00 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 01 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 01 1111 1111 1 Rev. 0 | Page 23 of 32 AD9609 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of The AD9609 includes a built-in test feature designed to enable the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN verification of the integrity of each channel as well as to facili- sequence can be continued from its last value by writing a 0 in tate board level debugging. A built-in self-test (BIST) feature that Bit 2 of Register 0x0E. However, if the PN sequence is not reset, verifies the integrity of the digital datapath of the AD9609 is the signature calculation does not equal the predetermined included. Various output test options are also provided to place value at the end of the test. At that point, the user needs to rely predictable values on the outputs of the AD9609. on verifying the output data. BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES The BIST is a thorough test of the digital portion of the selected The output test options are described in Table 17 at Address AD9609 signal path. Perform the BIST test after a reset to ensure 0x0D. When an output test mode is enabled, the analog section that the part is in a known state. During BIST, data from an internal of the ADC is disconnected from the digital back-end blocks pseudorandom noise (PN) source is driven through the digital and the test pattern is run through the output formatting block. datapath of both channels, starting at the ADC block output. Some of the test patterns are subject to output formatting, and At the datapath output, CRC logic calculates a signature from some are not. The PN generators from the PN sequence tests the data. The BIST sequence runs for 512 cycles and then stops. can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These Once completed, the BIST compares the signature results with a tests can be performed with or without an analog signal (if pre-determined value. If the signatures match, the BIST sets Bit 0 present, the analog signal is ignored), but they do require an of Register 0x24, signifying the test passed. If the BIST test failed, encode clock. For more information, see the AN-877 Bit 0 of Register 0x24 is cleared. The outputs are connected Application Note, Interfacing to High Speed ADCs via SPI. during this test, so the PN sequence can be observed as it runs. Writing 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence Rev. 0 | Page 24 of 32 AD9609 SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of The AD9609 serial port interface (SPI) allows the user to configure SCLK, determines the start of the framing. An example of the the converter for specific functions or operations through a serial timing and its definitions can be found in Figure 54 and structured register space provided inside the ADC. The SPI Table 5. gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port Other modes involving the CSB are available. The CSB can be and can be written to or read from via the port. Memory is held low indefinitely, which permanently enables the device; organized into bytes that can be further divided into fields, this is called streaming. The CSB can stall high between bytes to which are documented in the Memory Map section. For allow for additional external timing. When CSB is tied high, SPI detailed operational information, see the AN-877 Applica- functions are placed in high impedance mode. This mode turns tion Note, Interfacing to High Speed ADCs via SPI. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: SCLK, SDIO, and CSB by the W0 and W1 bits, as shown in Figure 54. (see Table 14). The SCLK (a serial clock) is used to synchronize All data is composed of 8-bit words. The first bit of the first byte in the read and write data presented from and to the ADC. SDIO a multibyte serial data transfer frame indicates whether a read (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. command or a write command is issued. This allows the serial The CSB (chip select bar) is an active-low control that enables data input/output (SDIO) pin to change direction from an input or disables the read and write cycles. to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines Table 14. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial clock. The serial shift clock input, which is used to the contents of the on-chip memory. If the instruction is a readback synchronize serial interface reads and writes. operation, performing a readback causes the serial data input/ SDIO Serial data input/output. A dual-purpose pin that output (SDIO) pin to change direction from an input to an output typically serves as an input or an output, depending on the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip select bar. An active-low control that gates the read first is the default on power-up and can be changed via the SPI and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 54. Serial Port Interface Timing Diagram Rev. 0 | Page 25 of 32 08541-023 AD9609 HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 14 constitute the physical interface In applications that do not interface to the SPI control registers, between the programming device of the user and the serial port the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone of the AD9609. The SCLK pin and the CSB pin function as inputs CMOS-compatible control pins. When the device is powered up, it when using the SPI interface. The SDIO pin is bidirectional, is assumed that the user intends to use the pins as static control functioning as an input during write phases and as an output lines for the power-down and output data format feature control. during readback. In this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI Table 15. Mode Selection configuration is described in detail in the AN-812 Appli- External cation Note, Microcontroller-Based Serial Port Interface Pin Voltage Configuration (SPI) Boot Circuit. SDIO/PDWN DRVDD Chip power-down mode The SPI port should not be active during periods when the full AGND (default) Normal operation (default) dynamic performance of the converter is required. Because the SCLK/DFS DRVDD Twos complement enabled SCLK signal, the CSB signal, and the SDIO signal are typically AGND (default) Offset binary enabled asynchronous to the ADC clock, noise from these signals can SPI ACCESSIBLE FEATURES degrade converter performance. If the on-board SPI bus is used for Table 16 provides a brief description of the general features that other devices, it may be necessary to provide buffers between are accessible via the SPI. These features are described in detail this bus and the AD9609 to prevent these signals from transi- in the AN-877 Application Note, Interfacing to High Speed ADCs tioning at the converter inputs during critical sampling periods. via SPI. The AD9609 part-specific features are described in SDIO/PDWN and SCLK/DFS serve a dual function when the detail in Table 17. SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated Table 16. Features Accessible Using the SPI with a specific function. The Digital Outputs section describes Feature Description the strappable functions supported on the AD9609. Modes Allows the user to set either power-down mode or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Rev. 0 | Page 26 of 32 AD9609 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 17) After the AD9609 is reset, critical registers are loaded with contains eight bit locations. The memory map is roughly default values. The default values for the registers are given in divided into four sections: the chip configuration registers the memory map register table (see Table 17). (Address 0x00 to Address 0x02); the device index and transfer Logic Levels register (Address 0xFF); the program registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x2A); and the AD9609-specific customer SPI control register (Address 0x101). • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 17 documents the default hexadecimal value for each • “Clear a bit” is synonymous with “bit is set to Logic 0” or hexadecimal address shown. The column with the heading Bit 7 “writing Logic 0 for the bit.” (MSB) is the start of the default hexadecimal value given. For example, Address 0x2A, the OR/MODE select register, has a hexa- Transfer Register Map decimal default value of 0x01. This means that in Address 0x2A, Address 0x08 to Address 0x18 are shadowed. Writes to these Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE addresses do not affect part operation until a transfer command setting. The default value results in the programmable external is issued by writing 0x01 to Address 0xFF, setting the transfer bit. MODE/OR pin (Pin 23) functioning as an out-of-range digital This allows these registers to be updated internally and simulta- output. For more information on this function and others, see the neously when the transfer bit is set. The internal update takes AN-877 Application Note, Interfacing to High Speed ADCs via SPI. place when the transfer bit is set, and then the bit autoclears. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x101, is documented in the Memory Map Register Descriptions section that follows Table 17. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these loca- tions is required only when part of an address location is open (for example, Address 0x2A). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. 0 | Page 27 of 32 AD9609 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft 1 1 Soft LSB 0 0x18 The nibbles are configuration first reset reset first mirrored so that LSB or MSB first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID, Bits[7:0] Read only Unique chip ID used AD9609 = 0x71 to differentiate devices; read only 0x02 Chip grade Open Speed grade ID, Bits[6:4] Open Read only Unique speed grade (identify device variants of ID used to chip ID) differentiate 20 MSPS = 000 devices; read only 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Device Index and Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program Registers 0x08 Modes External External Pin 23 Open Open Open 00 = chip run 0x00 Determines various generic modes of Pin 23 function when 01 = full power-down mode high 10 = standby chip operation input 00 = full power 11 = chip wide digital enable down reset 01 = standby 10 = normal mode: output disabled 11 = normal mode: output enabled 0x09 Clock Open Open Open Open Open Duty cycle 0x01 Enable internal duty stabilize cycle stabilizer (DCS) 0x0B Clock divide Open Clock divider, Bits[2:0] 0x00 The divide ratio is Clock divide ratio the value plus 1 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0D Test mode User test mode Reset Reset Output test mode, Bits[3:0] (local) 0x00 When set, the test 00 = single PN PN 0000 = off (default) data is placed on 01 = alternate long short 0001 = midscale short the output pins in gen gen 0010 = positive FS place of normal 10 = single once 0011 = negative FS data 11 = alternate once 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle 1000 = user input 1001 = 1/0 bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency Rev. 0 | Page 28 of 32 AD9609 Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST enable Open Open Open Open Open BIST Open BIST enable 0x00 When Bit 0 is set, INIT the built in self-test function is initiated. 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) 0x00 Device offset trim Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS Open Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS disable invert 01 = twos complement outputs and the 10 = gray code format of the data 11 = offset binary 0x15 Output adjust 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data 0x22 Determines CMOS drive strength drive strength drive strength drive strength output drive 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe strength properties (default) 01 = 2 stripes (default) 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes 01 = 2 stripes 10 = 3 stripes (default) 10 = 3 stripes (default) 10 = 3 stripes 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 Output phase DCO Open Open Open Open Input clock phase adjust, Bits[2:0] 0x00 On devices that Output (Value is number of input clock utilize global clock polarity cycles of phase delay) divide, determines 0 = 000 = no delay which phase of the normal 001 = 1 input clock cycle divider output is 1 = 010 = 2 input clock cycles used to supply the inverted 011 = 3 input clock cycles output clock; 100 = 4 input clock cycles internal latching is 101 = 5 input clock cycles unaffected 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 Output delay Enable Open Enable Open DCO/data delay[2:0] 0x00 Sets the fine output DCO data 000 = 0.56 ns delay of the output delay delay 001 = 1.12 ns clock but does not 010 = 1.68 ns change internal 011 = 2.24 ns timing 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x18 VREF Reserved =11 Internal VREF adjustment, Open 0xE0 Selects and/or Bits[2:0] adjusts the VREF 000 = 1.0 V p-p full-scale span 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.60 V p-p 100 = 2.0 V p-p 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB 0x24 BIST signature LSB BIST signature, Bits[7:0] 0x00 Least significant byte of BIST signature, read only 0x2A OR/MODE select Open Open Open Open Open Open Open 0 = MODE 0x01 Selects I/O 1 = OR functionality in (default) conjunction with Address 0x08 for MODE (input) or OR (output) on external Pin 23 1.1. AD9609-Specific Customer SPI Control 0x101 USR2 1 Open Enable Run Open Disable SDIO 0x88 Enables internal GCLK GCLK pull-down oscillator for clock detect rates <5 MHz Rev. 0 | Page 29 of 32 AD9609 Bit 2—Run GCLK MEMORY MAP REGISTER DESCRIPTIONS This bit enables the GCLK oscillator. For some applications For additional information about functions controlled in with encode rates below 10 MSPS, it may be preferable to set Register 0x00 to Register 0xFF, see the AN-877 Application this bit high to supersede the GCLK detector. Note, Interfacing to High Speed ADCs via SPI. Bit 0—Disable SDIO Pull-Down USR2 (Register 0x101) This bit can be set high to disable the internal 30 kΩ pull-down Bit 3—Enable GCLK Detect on the SDIO pin, which can be used to limit the loading when Normally set high, this bit enables a circuit that detects encode many devices are connected to the SPI bus. rates below about 5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled ensuring the proper operation of several circuits. If set low, the detector is disabled. Rev. 0 | Page 30 of 32 AD9609 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting design and layout of the AD9609 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements needed for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9609, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V supply (LFCSP) at www.analog.com. for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and Encode Clock DRVDD supply must be used, the AVDD and DRVDD domains For optimum dynamic performance a low jitter encode clock must be isolated with a ferrite bead or filter choke and separate source with a 50% duty cycle ±5% should be used to clock the decoupling capacitors. Several different decoupling capacitors AD9609. can be used to cover both high and low frequencies. Locate VCM these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. A single PCB ground plane should be sufficient when using the AD9609. With proper decoupling and smart partitioning of the RBIAS PCB analog, digital, and clock sections, optimum performance The AD9609 requires that a 10 kΩ resistor be placed between is easily achieved. the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for Reference Decoupling the AD9609; therefore, it must be connected to analog ground Externally decoupled the VREF pin to ground with a low ESR, (AGND) on the customer’s PCB. To achieve the best electrical 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic and thermal performance, mate an exposed (no solder mask) capacitor. continuous copper plane on the PCB to the AD9609 exposed SPI Port paddle, Pin 0. The SPI port should not be active during periods when the full The copper plane should have several vias to achieve the dynamic performance of the converter is required. Because the lowest possible resistive thermal path for heat dissipation to SCLK, CSB, and SDIO signals are typically asynchronous to the flow through the bottom of the PCB. Fill or plug these vias ADC clock, noise from these signals can degrade converter with nonconductive epoxy. performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9609 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 31 of 32 AD9609 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 EXPOSED 3.65 BSC TOP 4.75 PAD VIEW 3.50 SQ BSC SQ (BOTTOM VIEW) 3.35 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 FUNCTION DESCRIPTIONS 0.30 COPLANARITY SECTION OF THIS DATA SHEET. 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1, 2 AD9609BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1, 2 AD9609BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4 1 AD9609-80EBZ Evaluation Board 1 AD9609-65EBZ Evaluation Board 1 AD9609-40EBZ Evaluation Board 1 AD9609-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08541-0-10/09(0) Rev. 0 | Page 32 of 32 100608-A