ANALOG DEVICES AD9608

10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9608 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V CMOS or 1.8 V LVDS output SPI SNR = 61.7 dBFS at 70 MHz ORA SFDR = 85 dBc at 70 MHz PROGRAMMING DATA D9A Low power: 71 mW/channel ADC core at 125 MSPS VIN+A ADC Differential analog input with 650 MHz bandwidth VIN–A D0A IF sampling frequencies to 200 MHz DCOA On-chip voltage reference and sample-and-hold circuit VREF 2 V p-p differential analog input SENSE DRVDD DNL = ±0.13 LSB AD9608 REF VCM SELECT Serial port control options ORB RBIAS Offset binary, Gray code, or twos complement data format D9B VIN–B Optional clock duty cycle stabilizer ADC VIN+B Integer 1-to-8 input clock divider D0B Data output multiplex option DCOB Built-in selectable digital test pattern generation DIVIDE DUTY CYCLE MODE Energy-saving power-down modes 1TO 8 STABILIZER CONTROLS Data clock out with programmable clock and data alignment CLK+ CLK– SYNC DCS PDWN DFS OEB NOTES APPLICATIONS 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Communications Figure 1. Diversity radio systems I/Q demodulation systems Broadband data applications PRODUCT HIGHLIGHTS Battery-powered instruments 1. Operates from a single 1.8 V analog power supply and Handheld scope meters features a separate digital output driver supply to accom- Portable medical imaging modate 1.8 V CMOS or 1.8 V LVDS logic families. Ultrasound 2. Provides a patented sample-and-hold circuit that maintains excellent performance for input frequencies up to 200 MHz 1 and is designed for low cost, low power, and ease of use. 3. Includes a standard serial port interface that supports various product features and functions, such as data output format- ting, internal clock divider, power-down, DCO/data timing, and offset adjustments. 4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin compatible with the AD9650, AD9269, and AD9268 16-bit ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628 and AD9231 12-bit ADCs, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. 1 This product is protected by a U.S. patent. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MUX OPTION CMOS/LVDS CMOS/LVDS OUTPUT BUFFER OUTPUT BUFFER 09977-001 AD9608 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 25  Applications....................................................................................... 1  Clock Input Considerations...................................................... 26  Functional Block Diagram .............................................................. 1  Channel/Chip Synchronization................................................ 28  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 28  Revision History ............................................................................... 2  Digital Outputs ........................................................................... 29  General Description ......................................................................... 3  Timing ......................................................................................... 29  Specifications..................................................................................... 4  Built-In Self-Test (BIST) and Output Test .................................. 30  DC Specifications........................................................................... 4  Built-In Self-Test (BIST)............................................................ 30  AC Specifications ........................................................................... 5  Output Test Modes..................................................................... 30  Digital Specifications ................................................................... 6  Serial Port Interface (SPI).............................................................. 31  Switching Specifications ................................................................ 7  Configuration Using the SPI..................................................... 31  Timing Specifications .................................................................. 8  Hardware Interface..................................................................... 32  Absolute Maximum Ratings.......................................................... 10  Configuration Without the SPI ................................................ 32  Thermal Characteristics ............................................................ 10  SPI Accessible Features.............................................................. 32  ESD Caution................................................................................ 10  Memory Map .................................................................................. 33  Pin Configurations and Function Descriptions ......................... 11  Reading the Memory Map Register Table............................... 33  Typical Performance Characteristics ........................................... 17  Memory Map Register Table..................................................... 34  AD9608-125 ................................................................................ 17  Memory Map Register Descriptions........................................ 37  AD9608-105 ................................................................................ 20  Applications Information .............................................................. 39  Equivalent Circuits ......................................................................... 22  Design Guidelines ...................................................................... 39  Theory of Operation ...................................................................... 23  Outline Dimensions....................................................................... 40  ADC Architecture ...................................................................... 23  Ordering Guide .......................................................................... 40  Analog Input Considerations.................................................... 23  REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD9608 GENERAL DESCRIPTION The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, A differential clock input controls all internal conversion cycles. 105 MSPS/125 MSPS analog-to-digital converter (ADC) that An optional duty cycle stabilizer (DCS) compensates for wide features a high performance sample-and-hold circuit and an variations in the clock duty cycle while maintaining excellent on-chip voltage reference. overall ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, Gray code, or with output error correction logic to provide 10-bit accuracy at twos complement format. A data output clock (DCO) is provided 125 MSPS data rates and to guarantee no missing codes over the for each ADC channel to ensure proper latch timing with receiving full operating temperature range. logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable The AD9608 is available in a 64-lead RoHS-compliant LFCSP and clock and data alignment and programmable digital test pattern is specified over the industrial temperature range (−40°C to generation. The available digital test patterns include built-in +85°C). This product is protected by a U.S. patent. deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 0 | Page 3 of 40 AD9608 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −1.0 −0.3 +0.4 −1.0 −0.3 +0.4 % FSR Gain Error Full −2.8 ±1.5 +9.0 −2.8 ±1.5 +9.0 % FSR 1 Differential Nonlinearity (DNL) Full ±0.35 ±0.35 LSB 25°C ±0.12 ±0.13 LSB 1 Integral Nonlinearity (INL) Full ±0.40 ±0.40 LSB 25°C ±0.14 ±0.14 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±1.0 ±0.1 ±1.0 % FSR Gain Error Full ±0.5 ±6.5 ±0.5 ±6.5 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p 2 Input Capacitance Full 5 5 pF Input Resistance (Differential) Full 7.5 7.5 kΩ Input Common-Mode Voltage Full 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 I Full 76.8 82.0 87.7 93.0 mA AVDD 1 Full 14.7 17.4 mA IDRVDD (1.8 V CMOS) 1 Full 48.5 49.7 mA IDRVDD (1.8 V LVDS) POWER CONSUMPTION DC Input Full 125 141 mW 1 Full 165 174 189 199 mW Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) 1 Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Full 226 247 mW 3 Standby Power Full 108 120 mW Power-Down Power Full 2.0 2.0 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode). Rev. 0 | Page 4 of 40 AD9608 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. AD9608-105 AD9608-125 1 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz 25°C 61.7 61.7 dBFS f = 30.5 MHz 25°C 61.7 61.7 dBFS IN fIN = 70 MHz 25°C 61.7 61.7 dBFS Full 61.3 61.3 dBFS 25°C 61.6 61.6 dBFS fIN = 100 MHz fIN = 200 MHz 25°C 61.4 61.4 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 9.7 MHz 25°C 61.6 61.6 dBFS IN fIN = 30.5 MHz 25°C 61.6 61.6 dBFS fIN = 70 MHz 25°C 61.6 61.6 dBFS Full 61.1 61.1 dBFS fIN = 100 MHz 25°C 61.5 61.5 dBFS 61.3 61.3 f = 200 MHz 25°C dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) 25°C 9.9 9.9 Bits f = 9.7 MHz IN 25°C 9.9 9.9 Bits fIN = 30.5 MHz 25°C 9.9 9.9 Bits f = 70 MHz IN 25°C 9.9 9.9 Bits fIN = 100 MHz 25°C 9.9 9.9 Bits fIN = 200 MHz WORST SECOND OR THIRD HARMONIC 25°C dBc f = 9.7 MHz −90 −90 IN 25°C dBc fIN = 30.5 MHz −89 −89 25°C dBc fIN = 70 MHz −89 −89 Full dBc −75 −75 25°C dBc fIN = 100 MHz −89 −89 25°C dBc f = 200 MHz −84 −84 IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) 25°C dBc f = 9.7 MHz 85 85 IN 25°C dBc fIN = 30.5 MHz 85 85 25°C dBc f = 70 MHz 85 85 IN Full dBc 75 75 25°C dBc fIN = 100 MHz 85 85 25°C dBc f = 200 MHz 84 84 IN WORST OTHER (HARMONIC OR SPUR) 25°C dBc fIN = 9.7 MHz −85 −85 25°C dBc fIN = 30.5 MHz −85 −85 25°C dBc f = 70 MHz −85 −85 IN Full dBc −75 −75 25°C dBc f = 100 MHz −85 −85 IN 25°C dBc fIN = 200 MHz −85 −85 TWO-TONE SFDR 25°C dBc fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 82 82 2 Full dB CROSSTALK −95 −95 25°C MHz ANALOG INPUT BANDWIDTH 650 650 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 5 of 40 AD9608 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK/DFS/SYNC) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUT/OUTPUT (SDIO/DCS) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 2 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage I = 50 μA Full 1.79 V OH IOH = 0.5 mA Full 1.75 V Low Level Output Voltage IOL = 1.6 mA Full 0.2 V I = 50 μA Full 0.05 V OL Rev. 0 | Page 6 of 40 AD9608 Parameter Temp Min Typ Max Unit LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (V ), Reduced Swing Mode Full 160 200 230 mV OD Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.25 1.35 V OS 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 1000 MHz 1 Conversion Rate DCS Enabled Full 20 105 20 125 MSPS DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 9.52 8 ns CLK Pulse Width High (tCH) Full 4.76 4 ns Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, t) Full 0.07 0.07 ps rms J DATA OUTPUT PARAMETERS CMOS Mode CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (t) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns PD 2 DCO Propagation Delay (tDCO) Full 2.0 3.1 4.4 2.0 3.1 4.4 ns −0.1 −0.1 DCO to Data Skew (tSKEW) Full −1.2 +1.0 −1.2 +1.0 ns LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (t) Full 2.4 2.4 ns PD 2 DCO Propagation Delay (t ) Full 4.4 4.4 ns DCO DCO to Data Skew (t) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns SKEW CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency) Full 16/16.5 16/16.5 Cycles Channel A/Channel B 3 Wake-Up Time (Power-Down) Full 350 350 μs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. 0 | Page 7 of 40 AD9608 TIMING SPECIFICATIONS Table 5. Parameter Descriptions Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min t Hold time between the data and the rising edge of SCLK 40 ns min DH t Period of the SCLK 2 ns min CLK t Setup time between CSB and SCLK 2 ns min S tH Hold time between CSB and SCLK 10 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min t Time required for the SDIO pin to switch from an input to an output relative to the 10 ns min EN_SDIO SCLK falling edge t 2 ns min DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 t PD Figure 2. CMOS Default Output Mode Data Output Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A DATA N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 t PD CH B CH A CH B CH A CH B CH A CH B CH A CH B CH B DATA N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 Figure 3. CMOS Interleaved Output Mode Data Output Timing Rev. 0 | Page 8 of 40 09977-003 09977-002 AD9608 N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO– DCO+ t SKEW t PD D0+ (LSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D0– (LSB) PARALLEL INTERLEAVED MODE D9+ (MSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D9– (MSB) D1+/D0+ (LSB) CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1–/D0– (LSB) MULTIPLEXED MODE D9+/D8+ (MSB) CHANNEL A CH A8 CH A9 CH A8 CH A9 CH A8 CH A9 CH A8 CH A9 CH A8 N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D9–/D8– (MSB) D1+/D0+ (LSB) CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1–/D0– (LSB) MULTIPLEXED MODE D9+/D8+ (MSB) CHANNEL B CH B8 CH B9 CH B8 CH B9 CH B8 CH B9 CH B8 CH B9 CH B8 N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D9–/D8– (MSB) Figure 4. LVDS Modes for Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. 0 | Page 9 of 40 09977-005 09977-004 AD9608 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating The exposed paddle must be soldered to the ground plane for 1 Electrical the LFCSP package. Soldering the exposed paddle to the PCB AVDD to AGND −0.3 V to +2.0 V increases the reliability of the solder joints and maximizes the DRVDD to AGND −0.3 V to +2.0 V thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Airflow SYNC to AGND −0.3 V to AVDD + 0.2 V Package Velocity VCM to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 1, 2 Type (m/sec) θ θ θ Ψ Unit JA JC JB JT RBIAS to AGND −0.3 V to AVDD + 0.2 V 64-Lead 0 22.3 1.4 N/A 0.1 °C/W CSB to AGND −0.3 V to DRVDD + 0.2 V LFCSP 1.0 19.5 N/A 11.8 0.2 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V 9 mm × 9 mm 2.5 17.5 N/A N/A 0.2 °C/W SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V (CP-64-4) OEB −0.3 V to DRVDD + 0.2 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). PDWN −0.3 V to DRVDD + 0.2 V 3 Per MIL-Std 883, Method 1012.1. D0A, D0B through D9A, D9B to AGND −0.3 V to DRVDD + 0.2 V 4 Per JEDEC JESD51-8 (still air). DCOA, DCOB to AGND −0.3 V to DRVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground Environmental plane. As shown Table 7, airflow improves heat dissipation, Operating Temperature Range −40°C to +85°C (Ambient) which reduces θJA. In addition, metal in direct contact with the Maximum Junction Temperature 150°C package leads from metal traces, through holes, ground, and Under Bias power planes reduces θ . JA Storage Temperature Range −65°C to +150°C (Ambient) ESD CAUTION 1 The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) + 0.2 V but should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 10 of 40 AD9608 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 CLK+ 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS 6 43 ORA NC NC 7 42 D9A (MSB) AD9608 NC 8 41 D8A PARALLEL CMOS NC 9 40 D7A TOP VIEW DRVDD 10 39 D6A (Not to Scale) D0B (LSB) 11 38 D5A D1B 12 37 DRVDD D2B 13 36 D4A D3B 14 35 D3A D4B 15 34 D2A D5B 16 33 D1A NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 NC No Connect. Do not connect to this pin. 4, 5, 6, 7, 8, 9, 25, 26, 27, 29, 30, 31 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground Exposed Pad for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Rev. 0 | Page 11 of 40 D6B 17 64 AVDD D7B 18 63 AVDD DRVDD 19 62 VIN+B D8B 20 61 VIN–B D9B (MSB) 21 60 AVDD ORB 22 59 AVDD DCOB 23 58 RBIAS DCOA 24 57 VCM NC 25 56 SENSE NC 26 55 VREF NC 27 54 AVDD DRVDD 28 53 AVDD NC 29 52 VIN–A NC 30 51 VIN+A NC 31 50 AVDD D0A (LSB) 32 49 AVDD 09977-006 AD9608 Pin No. Mnemonic Type Description Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 32 D0A (LSB) Output Channel A CMOS Output Data. 33 D1A Output Channel A CMOS Output Data. 34 D2A Output Channel A CMOS Output Data. 35 D3A Output Channel A CMOS Output Data. 36 D4A Output Channel A CMOS Output Data. 38 D5A Output Channel A CMOS Output Data. 39 D6A Output Channel A CMOS Output Data. 40 D7A Output Channel A CMOS Output Data. 41 D8A Output Channel A CMOS Output Data. 42 D9A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 11 D0B (LSB) Output Channel B CMOS Output Data. 12 D1B Output Channel B CMOS Output Data. 13 D2B Output Channel B CMOS Output Data. 14 D3B Output Channel B CMOS Output Data. 15 D4B Output Channel B CMOS Output Data. 16 D5B Output Channel B CMOS Output Data. 17 D6B Output Channel B CMOS Output Data. 18 D7B Output Channel B CMOS Output Data. 20 D8B Output Channel B CMOS Output Data. 21 D9B (MSB) Output Channel B CMOS Output Data. 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 12 of 40 AD9608 PIN 1 CLK+ 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS NC 6 43 OR+ NC 7 42 OR– AD9608 NC 8 41 D9+ (MSB) INTERLEAVED PARALLEL LVDS NC 9 40 D9– (MSB) TOP VIEW DRVDD 10 39 D8+ (Not to Scale) NC 11 38 D8– NC 12 37 DRVDD 13 36 NC D7+ NC 14 35 D7– NC 15 34 D6+ NC 16 33 D6– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 4, 5, 6, 7, 8, 9, NC No Connect. Do not connect to this pin. 11, 12, 13, 14, 15, 16 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground for Exposed Pad the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 | Page 13 of 40 D0– (LSB) 17 64 AVDD D0+ (LSB) 18 63 AVDD DRVDD 19 62 VIN+B D1– 20 61 VIN–B D1+ 21 60 AVDD D2– 22 59 AVDD D2+ 23 58 RBIAS DCO– 24 57 VCM 25 56 SENSE DCO+ D3– 26 55 VREF D3+ 27 54 AVDD DRVDD 28 53 AVDD 29 52 VIN–A D4– 30 51 VIN+A D4+ D5– 31 50 AVDD D5+ 32 49 AVDD 09977-007 AD9608 Pin No. Mnemonic Type Description Digital Outputs 18 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 17 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 21 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 20 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 23 D2+ Output Channel A/Channel B LVDS Output Data 2 —True. 22 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 27 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 26 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 30 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 29 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 32 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 31 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 34 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 33 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 36 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 35 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 39 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 38 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 41 D9+ (MSB) Output Channel A/Channel B LVDS Output Data 9—True. 40 D9− (MSB) Output Channel A/Channel B LVDS Output Data 9—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 14 of 40 AD9608 PIN 1 CLK+ 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS NC 6 43 OR+ NC 7 42 OR– AD9608 NC 8 41 A D9+/D8+ (MSB) CHANNEL MULTIPLEXED LVDS NC 9 40 A D9–/D8– (MSB) TOP VIEW DRVDD 10 39 A D7+/D6+ (Not to Scale) A D7–/D6– NC 11 38 NC 12 37 DRVDD B D1–/D0– (LSB) 13 36 A D5+/D4+ B D1+/D0+ (LSB) 14 35 A D5–/D4– B D3–/D2– 15 34 A D3+/D2+ B D3+/D2+ 16 33 A D3–/D2– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View) Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, AVDD Supply Analog Power Supply (1.8 V Nominal). 59, 60, 63, 64 4, 5, 6, 7, 8, 9, NC No Connect. Do not connect to this pin. 11, 12, 26, 27, 29, 30 0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 | Page 15 of 40 B D5–/D4– 17 64 AVDD B D5+/D4+ 18 63 AVDD DRVDD 19 62 VIN+B B D7–/D6– 20 61 VIN–B B D7+/D6+ 21 60 AVDD B D9–/D8– (MSB) 22 59 AVDD B D9+/D8+ (MSB) 23 58 RBIAS DCO– 24 57 VCM DCO+ 25 56 SENSE NC 26 55 VREF NC 27 54 AVDD DRVDD 28 53 AVDD NC 29 52 VIN–A NC 30 51 VIN+A A D1–/D0– (LSB) 31 50 AVDD A D1+/D0+ (LSB) 32 49 AVDD 09977-008 AD9608 Pin No. Mnemonic Type Description Digital Outputs 14 B D1+/D0+ (LSB) Output Channel B LVDS Output Data 1/ Data 0—True. 13 B D1−/D0− (LSB) Output Channel B LVDS Output Data 1/ Data 0—Complement. 16 B D3+/D2+ Output Channel B LVDS Output Data 3/ Data 2—True. 15 B D3−/D2− Output Channel B LVDS Output Data 3/ Data 2—Complement. 18 B D5+/D4+ Output Channel B LVDS Output Data 5/ Data 4—True. 17 B D5−/D4− Output Channel B LVDS Output Data 5/ Data 4—Complement. 21 B D7+/D6+ Output Channel B LVDS Output Data 7/ Data 6—True. 20 B D7−/D6− Output Channel B LVDS Output Data 7/ Data 6—Complement. 23 B D9+/D8+ (MSB) Output Channel B LVDS Output Data 9/ Data 8—True. 22 B D9−/D8− (MSB) Output Channel B LVDS Output Data 9/ Data 8—Complement. 32 A D1+/D0+ (LSB) Output Channel A LVDS Output Data 1/ Data 0—True. 31 A D1−/D0− (LSB) 34 A D3+/D2+ Output Channel A LVDS Output Data 3/ Data 2—True. 33 A D3−/D2− Output Channel A LVDS Output Data 3/ Data 2—Complement. 36 A D5+/D4+ Output Channel A LVDS Output Data 5/ Data 4—True. 35 A D5−/D4− Output Channel A LVDS Output Data 5/ Data 4—Complement. 39 A D7+/D6+ Output Channel A LVDS Output Data 7/ Data 6—True. 38 A D7−/D6− Output Channel A LVDS Output Data 7/ Data 6—Complement. 41 A D9+/D8+ (MSB) Output Channel A LVDS Output Data 9/ Data 8—True. 40 A D9−/D8− (MSB) Output Channel A LVDS Output Data 9/ Data 8—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. 0 | Page 16 of 40 AD9608 TYPICAL PERFORMANCE CHARACTERISTICS AD9608-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 0 125MSPS 125MSPS 9.7MHZ AT –1dBFS 100.5MHz AT –1dBFS SNR = 60.6dB (61.6dBFS) SNR = 60.6dB (61.6dBFS) –20 SFDR = 85.4dBC –20 SFDR = 85.2dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 06 10 20 30 40 500 06 10 20 30 40 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Single-Tone FFT with f = 100.5 MHz Figure 9. Single-Tone FFT with fIN = 9.7 MHz IN 0 0 125MSPS 125MSPS 200.5MHz AT –1dBFS 30.5MHz AT –1dBFS SNR = 60.3dB (61.3dBFS) SNR = 60.7dB (61.7dBFS) –20 SFDR = 83.0dBc –20 SFDR = 86.3dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 06 10 20 30 40 500 06 10 20 30 40 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Single-Tone FFT with f = 200.5 MHz Figure 10. Single-Tone FFT with fIN = 30.5 MHz IN 0 125MSPS 70.1MHz AT –1dBFS SNR = 60.7dB (61.7dBFS) –20 SFDR = 86.5dBc –40 –60 –80 –100 –120 06 10 20 30 40 500 FREQUENCY (MHz) Figure 11. Single-Tone FFT with fIN = 70.1 MHz Rev. 0 | Page 17 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09977-011 09977-010 09977-009 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09977-013 09977-012 AD9608 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 –2 –15 –12 –30 –22 –45 –32 –60 –42 SFDR(dBc) IMD3 (dBc) –75 –52 2F2–F1 2F1–F2 2F1 + F2 –90 –62 + –105 –72 SFDR(dBFS) –120 –82 IMD3 (dBFS) –135 –92 6 121824 303642 485460 –70 –60 –50 –40 –30 –20 –10 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 14. Two-Tone FFT with fIN1 = 29 MHz and fIN2 = 32 MHz Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29 MHz and fIN2 = 32 MHz 100 90 SNRFS SFDR 95 80 SNR SFDRFS 90 70 SFDR 85 60 80 50 75 40 70 30 65 SNRFS 20 60 10 55 50 0 0 50 100 150 200 250 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) ANALOG INPUT FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 18. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 120 120 100 100 SFDR (dBc) SFDR (dBc) 80 80 SNR (dBFS) SNR (dBFS) 60 60 40 40 20 20 0 0 5 25 45 65 85 105 125 5 25 45 65 85 105 125 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) Figure 16. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 19. SNR/SFDR vs. Sample Rate with AIN = 70 MHz Rev. 0 | Page 18 of 40 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) AMPLITUDE (Hz) 09977-067 09977-031 09977-035 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBc AND dBFS) 09977-022 09977-033 09977-032 AD9608 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 1.0 2.0 1.5 1.0 0.5 0.5 0 0 –0.5 –1.0 –0.5 –1.5 –2.0 –1.0 0 200 400 600 800 1000 0 500 1000 OUTPUT CODE OUTPUT CODE Figure 20. DNL Error with fIN = 9.7 MHz Figure 22. INL Error with fIN = 9.7 MHz 1,200 1,000 800 600 400 200 0 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 OUTPUT CODE Figure 21. Shorted Input Histogram Rev. 0 | Page 19 of 40 NUMBER OF HITS (Thousands) DNL ERROR (LSB) 09977-034 09977-021 INL ERROR (LSB) 09977-020 AD9608 AD9608-105 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 0 105MSPS 105MSPS 9.7MHz AT –1dBFS 100.5MHz AT –1dBFS SNR = 60.7dB (61.7dBFS) SNR = 60.7dB (61.7dBFS) –20 –20 SFDR = 84.9dBc SFDR = 85.9dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 05 10 20 30 400 05 10 20 30 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. Single-Tone FFT with fIN = 9.7 MHz Figure 26. Single-Tone FFT with fIN = 100.5 MHz 0 0 105MSPS 105MSPS 30.5MHz AT –1dBFS 200.5MHz AT –1dBFS SNR = 60.6dB (61.6dBFS) SNR = 60.3dB (61.3dBFS) SFDR = 84.5dBc –20 –20 SFDR = 85.9dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 05 10 20 30 400 05 10 20 30 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Single-Tone FFT with fIN = 30.5 MHz Figure 27. Single-Tone FFT with f = 200.5 MHz IN 0 105MSPS 70.1MHz AT –1dBFS SNR = 60.7dB (61.7dBFS) –20 SFDR = 86.8dBc –40 –60 –80 –100 –120 05 10 20 30 400 FREQUENCY (MHz) Figure 25. Single-Tone FFT with fIN = 70.1 MHz Rev. 0 | Page 20 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09977-016 09977-015 09977-014 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09977-017 09977-018 AD9608 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 100 90 SNRFS SFDR 95 80 SNR SFDRFS 90 70 SFDR 85 60 80 50 75 40 70 30 65 SNRFS 20 60 10 55 50 0 050 100 150 200 250 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 28. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 31. SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN 120 120 100 100 SFDR (dBc) SFDR (dBc) 80 80 SNR (dBFS) SNR (dBFS) 60 60 40 40 20 20 0 0 5 152535 4555657585 95 105 5 152535455565758595 105 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70 MHz Figure 29. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 200 400 600 800 1000 0 500 1000 OUTPUT CODE OUTPUT CODE Figure 30. DNL Error with f = 9.7 MHz Figure 33. INL Error with fIN = 9.7 MHz IN Rev. 0 | Page 21 of 40 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) DNLERROR (LSB) 09977-019 09977-026 09977-029 SNR/SFDR (dBFS/dBc) INL ERROR (LSB) SNR/SFDR (dBc AND dBFS) 09977-025 09977-028 09977-027 AD9608 EQUIVALENT CIRCUITS DRVDD AVDD 350Ω SCLK/DFS, SYNC, VIN±x OEB, AND PDWN 30kΩ Figure 34. Equivalent Analog Input Circuit Figure 38. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit 5Ω CLK+ AVDD 15kΩ 0.9V 375Ω SENSE 15kΩ 5Ω CLK– Figure 35. Equivalent Clock Input Circuit Figure 39. Equivalent SENSE Circuit DRVDD DRVDD AVDD 30kΩ PAD 350Ω CSB Figure 40. Equivalent CSB Input Circuit Figure 36. Equivalent Digital Output Circuit AVDD DRVDD AVDD 30kΩ 350Ω SDIO/DCS 375Ω 30kΩ VREF 7.5kΩ Figure 41. Equivalent VREF Circuit Figure 37. Equivalent SDIO/DCS Input Circuit Rev. 0 | Page 22 of 40 09977-039 09977-047 09977-040 09977-042 09977-043 09977-044 09977-048 09977-045 AD9608 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9608 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same The analog input to the AD9608 is a differential switched- carrier but from two separate antennae. The ADCs can also be capacitor circuit designed for processing differential input operated with independent analog inputs. The user can sample signals. This circuit can support a wide common-mode range any f /2 frequency segment from dc to 200 MHz, using appropriate S while maintaining excellent performance. By using an input low-pass or band-pass filtering at the ADC inputs with little loss common-mode voltage of midsupply, users can minimize in ADC performance. Operation to 300 MHz analog input is signal-dependent errors and achieve optimum performance. permitted but occurs at the expense of increased ADC noise and distortion. H In nondiversity applications, the AD9608 can be used as a base- C band or direct downconversion receiver, where one ADC is PAR H VIN+x used for I input data and the other is used for Q input data. C SAMPLE SS Synchronization capability is provided to allow synchronized SS timing between multiple channels or multiple devices. C SAMPLE VIN–x Programming and control of the AD9608 is accomplished using H C PAR a 3-bit SPI-compatible serial interface. H ADC ARCHITECTURE The AD9608 architecture consists of a multistage, pipelined ADC. Figure 42. Switched-Capacitor Input Circuit Each stage provides sufficient overlap to correct for flash errors in The clock signal alternately switches the input circuit between the preceding stage. The quantized outputs from each stage are sample-and-hold mode (see Figure 42). When the input circuit combined into a final 10-bit result in the digital correction logic. is switched to sample mode, the signal source must be capable The pipelined architecture permits the first stage to operate with of charging the sample capacitors and settling within one-half a new input sample while the remaining stages operate with of a clock cycle. A small resistor in series with each input can help preceding samples. Sampling occurs on the rising edge of reduce the peak transient current injected from the output stage the clock. of the driving source. In addition, low Q inductors or ferrite beads Each stage of the pipeline, excluding the last, consists of a low can be placed on each leg of the input to reduce high differential resolution flash ADC connected to a switched-capacitor DAC capacitance at the analog inputs and, therefore, achieve the and an interstage residue amplifier (for example, a multiplying maximum bandwidth of the ADC. Such use of low Q inductors digital-to-analog converter (MDAC)). The residue amplifier or ferrite beads is required when driving the converter front end magnifies the difference between the reconstructed DAC output at high IF frequencies. Either a shunt capacitor or two single-ended and the flash input for the next stage in the pipeline. One bit of capacitors can be placed on the inputs to provide a matching redundancy is used in each stage to facilitate digital correction passive network. This ultimately creates a low-pass filter at the of flash errors. The last stage consists of a flash ADC. input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog The output staging block aligns the data, corrects errors, and Dialogue article “Transformer-Coupled Front-End for Wideband passes the data to the CMOS/LVDS output buffers. The output A/D Converters” (Volume 39, April 2005) for more information. buffers are powered from a separate (DRVDD) supply, allowing In general, the precise values depend on the application. digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state. Rev. 0 | Page 23 of 40 09977-049 AD9608 Input Common Mode The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9608 (see Figure 44), and the The analog inputs of the AD9608 are not internally dc-biased. driver can be configured in a Sallen-Key filter topology to Therefore, in ac-coupled applications, the user must provide provide band limiting of the input signal. a dc bias externally. Setting the device so that VCM = AVDD/2 200Ω is recommended for optimum performance, but the device can 33Ω VIN VIN–x 76.8Ω AVDD function over a wider range with reasonable performance, as 90Ω shown in Figure 43. 10pF ADA4938 ADC 0.1µF An on-board, common-mode voltage reference is included in 120Ω 33Ω VCM VIN+x the design and is available from the VCM pin. The VCM pin 200Ω must be decoupled to ground by a 0.1 μF capacitor, as described Figure 44. Differential Input Configuration Using the ADA4938-2 in the Applications Information section. For baseband applications below ~10 MHz where SNR is a key 100 parameter, differential transformer coupling is the recommended 90 SFDR (dBc) input configuration (see Figure 45). To bias the analog input, 80 the VCM voltage can be connected to the center tap of the 70 secondary winding of the transformer. SNR (dBFS) 60 VIN+x R 50 2V p-p 49.9Ω C ADC 40 R VCM 30 VIN–x 20 0.1µF 10 Figure 45. Differential Transformer-Coupled Configuration 0 The signal characteristics must be considered when selecting 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 a transformer. Most RF transformers saturate at frequencies that INPUT COMMON-MODE VOLTAGE (V) are below a few megahertz (MHz). Excessive signal power can Figure 43. SNR/SFDR vs. Input Common-Mode Voltage, f = 70 MHz, f = 125 MSPS IN S also cause core saturation, which leads to distortion. Differential Input Configurations At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve Optimum performance is achieved while driving the AD9608 in the true SNR performance of the AD9608. For applications above a differential input configuration. For baseband applications, ~10 MHz where SNR is a key parameter, differential double balun the AD8138, ADA4937-2, and ADA4938-2 differential drivers coupling is the recommended input configuration (see Figure 46). provide excellent performance and a flexible interface to the ADC. An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver (see Figure 47). See the AD8352 data sheet for more information. 0.1µF 0.1µF R VIN+x 2V p-p 25Ω P S S P A C ADC 0.1µF 25Ω 0.1µF R VCM VIN–x Figure 46. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+x 2 200Ω C ADC R R AD8352 C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN–x 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 47. Differential Input Configuration Using the AD8352 Rev. 0 | Page 24 of 40 SNR/SFDR (dBFS/dBc) 09977-056 09977-053 09977-054 09977-051 09977-050 AD9608 In any configuration, the value of Shunt Capacitor C is dependent Internal Reference Connection on the input frequency and source impedance and may need to A comparator within the AD9608 detects the potential at the be reduced or removed. Table 11 displays the suggested values to SENSE pin and configures the reference into two possible modes, set the RC network. However, these values are dependent on the which are summarized in Table 12. If SENSE is grounded, the input signal and should be used only as a starting guide. reference amplifier switch is connected to the internal resistor divider (see Figure 49), setting VREF to 1.0 V. Table 11. Example RC Network R Series VIN+A/VIN+B Frequency Range (MHz) (Ω Each) C Differential (pF) VIN–A/VIN–B 0 to 70 33 22 70 to 200 125 Open ADC CORE Single-Ended Input Configuration VREF A single-ended input can provide adequate performance in 1.0µF 0.1µF cost-sensitive applications. In this configuration, SFDR and SELECT LOGIC distortion performance degrade due to the large input common- SENSE mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. 0.5V Figure 48 shows a typical single-ended input configuration. 10µF AVDD ADC 1kΩ R Figure 49. Internal Reference Configuration VIN+x 1V p-p 0.1µF 49.9Ω 1kΩ If the internal reference of the AD9608 is used to drive multiple AVDD C ADC converters to improve gain matching, the loading of the reference 1kΩ R by the other converters must be considered. Figure 50 shows VIN–x 10µF 0.1µF how the internal reference voltage is affected by loading. 1kΩ 0 Figure 48. Single-Ended Input Configuration –0.5 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the –1.0 AD9608. The VREF pin can be configured using either the internal INTERNAL V = 1.00V REF 1.0 V reference or an externally applied 1.0 V reference voltage. –1.5 The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the –2.0 best practices PCB layout of the reference. –2.5 –3.0 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 LOAD CURRENT (mA) Figure 50. V Accuracy vs. Load Current REF Table 12. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. 0 | Page 25 of 40 09977-052 REFERENCE VOLTAGE ERROR (%) 09977-055 09977-057 AD9608 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance The AD9608 has a very flexible clock input structure. The clock the gain accuracy of the ADC or improve thermal drift charac- input can be a CMOS, LVDS, LVPECL, or sine wave signal. teristics. Figure 51 shows the typical drift characteristics of the Regardless of the type of signal being used, clock source jitter is internal reference in 1.0 V mode. of the most concern, as described in the Jitter Considerations 4 section. 3 Figure 53 and Figure 54 show two preferred methods for clock- ing the AD9608 (at clock rates up to 1 GHz prior to internal CLK 2 V ERROR (mV) REF divider). A low jitter clock source is converted from a single- 1 ended signal to a differential signal using either an RF 0 transformer or an RF balun. –1 The RF balun configuration is recommended for clock frequencies –2 between 125 MHz and 1 GHz, and the RF transformer is recom- –3 mended for clock frequencies from 10 MHz to 200 MHz. The –4 back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9608 to approxi- –5 mately 0.8 V p-p differential. –6 –40 –20 0 20 40 60 80 This limit helps prevent the large voltage swings of the clock TEMPERATURE (°C) from feeding through to other portions of the AD9608 while Figure 51. Typical VREF Drift preserving the fast rise and fall times of the signal that are critical When the SENSE pin is tied to AVDD, the internal reference is to a low jitter performance. disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent ® Mini-Circuits ADT1-1WT, 1:1 Z 7.5 kΩ load (see Figure 41). The internal buffer generates the 0.1µF 0.1µF XFMR CLOCK positive and negative full-scale references for the ADC core. CLK+ INPUT 100Ω Therefore, the external reference must be limited to a maximum 50Ω ADC 0.1µF of 1.0 V. CLK– SCHOTTKY 0.1µF CLOCK INPUT CONSIDERATIONS DIODES: HSMS2822 For optimum performance, clock the AD9608 sample clock Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz) inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 52) and require no external bias. AVDD 1nF 0.1µF CLOCK CLK+ INPUT 50Ω ADC 0.1µF 0.9V 1nF CLK– CLK+ CLK– SCHOTTKY DIODES: HSMS2822 2pF 2pF Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz) Figure 52. Equivalent Clock Input Circuit Rev. 0 | Page 26 of 40 V ERROR (mV) REF 09977-058 09977-066 09977-060 09977-059 AD9608 If a low jitter clock source is not available, another option is to Input Clock Divider ac couple a differential PECL signal to the sample clock input The AD9608 contains an input clock divider with the ability pins, as shown in Figure 55. The AD9510/AD9511/AD9512/ to divide the input clock by integer values between 1 and 8. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer The AD9608 clock divider can be synchronized using the excellent jitter performance. external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal 0.1µF 0.1µF or only on the first SYNC signal after the register is written. CLOCK CLK+ INPUT A valid SYNC causes the clock divider to reset to its initial state. AD951x 100Ω ADC This synchronization feature allows multiple parts to have their PECL DRIVER 0.1µF 0.1µF CLOCK CLK– clock dividers aligned to guarantee simultaneous input sampling. INPUT 240Ω 240Ω 50kΩ 50kΩ Clock Duty Cycle Figure 55. Differential PECL Sample Clock (Up to 1 GHz) Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be A third option is to ac couple a differential LVDS signal to the sensitive to clock duty cycle. A ±5% tolerance is commonly sample clock input pins, as shown in Figure 56. The AD9510/ required on the clock duty cycle to maintain dynamic AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 performance characteristics. clock drivers offer excellent jitter performance. The AD9608 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock 0.1µF 0.1µF signal with a nominal 50% duty cycle. This allows the user to CLOCK CLK+ INPUT provide a wide range of clock input duty cycles without affecting AD951x 100Ω ADC LVDS DRIVER the performance of the AD9608. Noise and distortion perform- 0.1µF 0.1µF CLOCK CLK– INPUT ance are nearly flat for a wide range of duty cycles with the DCS 50kΩ 50kΩ on, as shown in Figure 58. Figure 56. Differential LVDS Sample Clock (Up to 1 GHz) Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty In some applications, it may be acceptable to drive the sample cycle control loop does not function for clock rates less than clock inputs with a single-ended 1.8 V CMOS signal. In such 20 MHz, nominally. The loop has a time constant associated applications, drive the CLK+ pin directly from a CMOS gate, and with it that must be considered in applications in which the bypass the CLK− pin to ground with a 0.1 μF capacitor (see clock rate can change dynamically. A wait time of 1.5 μs to 5 μs Figure 57). is required after a dynamic clock frequency increase or decrease V before the DCS loop is relocked to the input signal. CC OPTIONAL 0.1µF 70 0.1µF 1kΩ AD951x 100Ω CLOCK CMOS DRIVER CLK+ INPUT 1 1kΩ 50Ω ADC 65 DCS ON CLK– 0.1µF 60 1 50Ω RESISTOR IS OPTIONAL. 55 Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) DCS OFF 50 45 40 35 40 45 50 55 60 65 POSITIVE DUTY CYCLE (%) Figure 58. SNR vs. DCS On/Off Rev. 0 | Page 27 of 40 09977-062 09977-061 09977-063 SNR (dBFs) 09977-036 AD9608 Jitter Considerations The maximum DRVDD current (I ) can be calculated as DRVDD High speed, high resolution ADCs are sensitive to the quality I = V × C × f × N DRVDD DRVDD LOAD CLK of the clock input. The degradation in SNR from the low fre- where N is the number of output bits (22, in the case of the quency SNR (SNRLF) at a given input frequency (fINPUT) due to AD9608). jitter (tJRMS) can be calculated by This maximum current occurs when every output bit switches (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is estab- In the previous equation, the rms aperture jitter represents the lished by the average number of output bits switching, which clock input jitter specification. IF undersampling applications is determined by the sample rate and the characteristics of the are particularly sensitive to jitter, as illustrated in Figure 59. analog input signal. 80 Reducing the capacitive load presented to the output drivers can 75 0.05ps minimize digital power consumption. The data in Figure 60 was taken in CMOS mode using the same operating conditions as those 70 used for the power supplies and power consumption parameters 0.2ps 65 in Table 1, with a 5 pF load on each output driver. 0.10 I 240 AVDD 60 0.5ps I DRVDD 0.09 TOTAL POWER 55 0.08 1.0ps 190 0.07 1.5ps 50 2.0ps 0.06 2.5ps 3.0ps 45 0.05 140 1 10 100 1k FREQUENCY (MHz) 0.04 Figure 59. SNR vs. Input Frequency and Jitter 0.03 90 The clock input should be treated as an analog signal in cases 0.02 where aperture jitter may affect the dynamic range of the AD9608. 0.01 To avoid modulating the clock signal with digital noise, keep 40 0 5 2545 6585 105 125 power supplies for clock drivers separate from the ADC output ENCODE RATE (Msps) driver supplies. Low jitter, crystal-controlled oscillators make the Figure 60. AD9608-125 Power and Current vs. Clock Rate best clock sources. If the clock is generated from another type of (1.8 V CMOS Output Mode) source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. 0.09 For more information, see the AN-501 Application Note and the I AVDD 240 I DRVDD AN-756 Application Note, available on www.analog.com. 0.08 TOTAL POWER 0.07 CHANNEL/CHIP SYNCHRONIZATION 190 The AD9608 has a SYNC input that offers the user flexible 0.06 synchronization options for synchronizing sample clocks 0.05 across multiple ADCs. The input clock divider can be enabled 140 0.04 to synchronize on a single occurrence of the SYNC signal or on 0.03 every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing 90 0.02 uncertainty between multiple parts, the SYNC input signal should 0.01 be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input 0 40 5 152535455565758595 105 using a single-ended CMOS-type signal. ENCODE RATE (Msps) POWER DISSIPATION AND STANDBY MODE Figure 61. AD9608-105 Power and Current vs. Clock Rate (1.8 V CMOS Output Mode) As shown in Figure 60, the analog core power dissipated by the AD9608 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. Rev. 0 | Page 28 of 40 SNR (dBFS) 09977-065 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) POWER (mW) POWER (mW) 09977-030 09977-023 AD9608 The AD9608 is placed in power-down mode either by the SPI As detailed in the AN-877 Application Note, Interfacing to High port or by asserting the PDWN pin high. In this state, the ADC Speed ADCs via SPI, the data format can be selected for offset typically dissipates <2 mW. During power-down, the output binary, twos complement, or Gray code when using the SPI control. drivers are placed in a high impedance state. Asserting the Table 13. SCLK/DFS Mode Selection (External Pin Mode) PDWN pin low returns the AD9608 to its normal operating Voltage at Pin SCLK/DFS SDIO/DCS mode. Note that PDWN is referenced to the digital output driver AGND Offset binary (default) DCS disabled supply (DRVDD) and should not exceed that supply voltage. DRVDD Twos complement DCS enabled (default) Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, Digital Output Enable Function (OEB) and clock. Internal capacitors are discharged when entering power- The AD9608 has a flexible three-state ability for the digital output down mode and then must be recharged when returning to normal pins. The three-state mode is enabled through the SPI interface operation. As a result, wake-up time is related to the time spent and can subsequently be controlled using the OEB pin or through in power-down mode, and shorter power-down cycles result in the SPI. Once enabled via the SPI (Bit 7) in Register 0x101 and proportionally shorter wake-up times. the OEB pin is low, the output data drivers and DCOs are enabled. When using the SPI port interface, the user can place the ADC If the OEB pin is high, the output data drivers and DCOs are in power-down mode or standby mode. Standby mode allows placed in a high impedance state. This OEB function is not the user to keep the internal reference circuitry powered when intended for rapid access to the data bus. Note that OEB is faster wake-up times are required. See the Memory Map section referenced to the digital output driver supply (DRVDD) and for more details. should not exceed that supply voltage. DIGITAL OUTPUTS When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the The AD9608 output drivers can be configured to interface with output port disable bit (Bit 4) in Register 0x14. either 1.8 V CMOS or 1.8 V LVDS logic families. The default output mode is CMOS, with each channel output on separate TIMING busses as shown in Figure 2. The AD9608 provides latched data with a pipeline delay of In CMOS output mode, the CMOS output drivers are sized to 16 clock cycles. Data outputs are available one propagation provide sufficient output current to drive a wide variety of logic delay (tPD) after the rising edge of the clock signal. families. However, large drive currents tend to cause current Minimize the length of the output data lines and loads placed glitches on the supplies and may affect converter performance. on them to reduce transients within the AD9608. These Applications requiring the ADC to drive large capacitive loads transients can degrade converter dynamic performance. or large fanouts may require external buffers or latches. The lowest typical conversion rate of the AD9608 is 10 MSPS. The CMOS output can also be configured for interleaved CMOS At clock rates below 10 MSPS, dynamic performance can degrade. output mode via the SPI port. In interleaved CMOS mode, the Data Clock Output (DCO) data for both channels is output onto a single output bus to reduce The AD9608 provides two data clock output (DCO) signals the total number of traces required. The timing diagram for intended for capturing the data in an external register. In CMOS interleaved CMOS output mode is shown in Figure 3. output mode, the data outputs are valid on the rising edge of DCO, The interleaved CMOS output mode is enabled globally onto both unless the DCO clock polarity has been changed via the SPI. In output channels via Bit 5 in Register 0x14. The unused channel LVDS output mode, the DCO and data output switching edges output can be disabled by selecting the appropriate bit (Bit 1 or are closely aligned. Additional delay can be added to the DCO Bit 0) in Register 0x05 and then writing a 1 to the local (channel- output using SPI Register 0x17 to increase the data setup time. specific) output port disable bit (Bit 4) in Register 0x14. In this case, the Channel A output data is valid on the rising The output data format can be selected to be either offset binary edge of DCO, and the Channel B output data is valid on the or twos complement by setting the SCLK/DFS pin when operating falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for in the external pin mode (see Table 13). a graphical timing description of the output modes. Table 14. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 10 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 10 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 00 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 01 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 01 1111 1111 1 Rev. 0 | Page 29 of 40 AD9608 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST Writing the value 0x05 to Register 0x0E runs the BIST. This enables The AD9608 includes a built-in test feature designed to enable Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence verification of the integrity of each channel, as well as to generator, Bit 2 (initialize BIST sequence) of Register 0x0E. At the facilitate board level debugging. A built-in self-test (BIST) feature completion of the BIST, Bit 0 of Register 0x24 is automatically that verifies the integrity of the digital datapath of the AD9608 cleared. The PN sequence can be continued from its last value is included. Various output test options are also provided to place by writing a 0 in Bit 2 of Register 0x0E. However, if the PN predictable values on the outputs of the AD9608. sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the BUILT-IN SELF-TEST (BIST) user needs to rely on verifying the output data. The BIST is a thorough test of the digital portion of the selected AD9608 signal path. Perform the BIST test after a reset to ensure OUTPUT TEST MODES that the part is in a known state. During BIST, data from an internal The output test options are described in Table 18 at Address 0x0D. pseudorandom noise (PN) source is driven through the digital When an output test mode is enabled, the analog section of the datapath of both channels, starting at the ADC block output. ADC is disconnected from the digital back-end blocks and the At the datapath output, CRC logic calculates a signature from test pattern is run through the output formatting block. Some of the data. The BIST sequence runs for 512 cycles and then stops. the test patterns are subject to output formatting, and some are Once completed, the BIST compares the signature results with a not. The PN generators from the PN sequence tests can be reset predetermined value. If the signatures match, the BIST sets Bit 0 by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be of Register 0x24, signifying that the test passed. If the BIST test performed with or without an analog signal (if present, the fails, Bit 0 of Register 0x24 is cleared. The outputs are connected analog signal is ignored), but they do require an encode clock. during this test, so the PN sequence can be observed as it runs. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 30 of 40 AD9608 SERIAL PORT INTERFACE (SPI) The AD9608 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 62 gives the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK/DFS pin, the Data follows the instruction phase, and its length is determined SDIO/DCS pin, and the CSB pin (see Table 15). The SCLK/DFS by the W0 and W1 bits. (a serial clock) is used to synchronize the read and write data In addition to word length, the instruction phase determines presented from and to the ADC. The SDIO/DCS (serial data whether the serial frame is a read or write operation, allowing input/output) is a dual-purpose pin that allows data to be sent the serial port to be used both to program the chip and to read to and read from the internal ADC memory map registers. The the contents of the on-chip memory. The first bit of the first byte CSB (chip select bar) is an active low control that enables or in a multibyte serial data transfer frame indicates whether a read disables the read and write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial Table 15. Serial Port Interface Pins data input/output (SDIO) pin to change direction from an input Pin Function to an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB- SDIO Serial data input/output. A dual-purpose pin that typically first mode or in LSB-first mode. MSB first is the default on serves as an input or an output, depending on the power-up and can be changed via the SPI port configuration instruction being sent and the relative position in the register. For more information about this and other features, timing frame. CSB Chip select bar. An active low control that gates the read see the AN-877 Application Note, Interfacing to High Speed and write cycles. ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 62. Serial Port Interface Timing Diagram Rev. 0 | Page 31 of 40 09977-046 AD9608 When the device is in SPI mode, the PDWN and OEB pins (if HARDWARE INTERFACE enabled) remain active. For SPI control of output enable and The pins described in Table 15 comprise the physical interface power-down, the OEB and PDWN pins should be set to their between the user programming device and the serial port of the default states. AD9608. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, Table 16. Mode Selection functioning as an input during write phases and as an output Pin External Voltage Configuration during readback. SDIO/DCS DRVDD (default) Duty cycle stabilizer enabled The SPI interface is flexible enough to be controlled by either AGND Duty cycle stabilizer disabled FPGAs or microcontrollers. One method for SPI configuration SCLK/DFS DRVDD Twos complement enabled is described in detail in the AN-812 Application Note, Micro- AGND (default) Offset binary enabled controller-Based Serial Port Interface (SPI) Boot Circuit. OEB DRVDD Outputs in high impedance AGND (default) Outputs enabled The SPI port should not be active during periods when the full PDWN DRVDD Chip in power-down or dynamic performance of the converter is required. Because the standby SCLK signal, the CSB signal, and the SDIO signal are typically AGND (default) Normal operation asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for SPI ACCESSIBLE FEATURES other devices, it may be necessary to provide buffers between this bus and the AD9608 to prevent these signals from transi- Table 17 provides a brief description of the general features that tioning at the converter inputs during critical sampling periods. are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs Some pins serve a dual function when the SPI interface is not via SPI. The AD9608 part-specific features are described in detail being used. When the pins are strapped to DRVDD or ground following Table 18, the external memory map register table (see the during device power-on, they are associated with a specific Memory Map Register Descriptions section). function. Table 16 describes the strappable functions supported on the AD9608. Table 17. Features Accessible Using the SPI CONFIGURATION WITHOUT THE SPI Feature Name Description In applications that do not interface to the SPI control registers, Mode Allows user to set either power-down mode or the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin standby mode serve as standalone CMOS-compatible control pins. When the Clock Allows user to access the DCS, set the clock device is powered up, it is assumed that the user intends to use the divider, set the clock divider phase, and enable pins as static control lines for the duty cycle stabilizer, output the sync data format, and power-down feature control. In this mode, the Offset Allows user to digitally adjust the converter offset CSB chip select bar should be connected to AVDD, which Test I/O Allows user to set test modes to have known disables the serial port interface. data on output bits Output Mode Allows user to set the output mode, including LVDS Output Phase Allows user to set the output clock polarity Output Delay Allows user to vary the DCO delay Rev. 0 | Page 32 of 40 AD9608 MEMORY MAP Default Values READING THE MEMORY MAP REGISTER TABLE After the AD9608 is reset, critical registers are loaded with Each row in the memory map register table has eight bit locations. default values. The default values for the registers are given in The memory map is roughly divided into three sections: the chip the memory map register table, Table 18. configuration registers (Address 0x00 to Address 0x02); the Logic Levels channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x102). • “Bit is set” is synonymous with “bit is set to Logic 1” or The memory map register table (see Table 18) lists the default “writing Logic 1 for the bit.” hexadecimal value for each hexadecimal address shown. The • “Clear a bit” is synonymous with “bit is set to Logic 0” or column with the heading Bit 7 (MSB) is the start of the default “writing Logic 0 for the bit.” hexadecimal value given. For example, Address 0x05, the device Channel-Specific Registers index register, has a hexadecimal default value of 0x03. This means that in Address 0x05, Bits[7:2] = 0, and Bits[1:0] = 1. Some channel setup functions, such as the signal monitor This setting is the default channel index setting. The default thresholds, can be programmed differently for each channel. In value results in both ADC channels receiving the next write these cases, channel address locations are internally duplicated for command. For more information about this function and others, each channel. These registers and bits are designated in Table 18 see the AN-877 Application Note, Interfacing to High Speed ADCs as local. These local registers and bits can be accessed by setting via SPI. This application note details the functions controlled by the appropriate Channel A or Channel B bits in Register 0x05. Register 0x00 to Register 0xFF. The remaining registers are If both bits are set, the subsequent write affects the registers of documented in the Memory Map Register Descriptions section. both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set Open Locations during an SPI read cycle, the part returns the value for Channel A. All address and bit locations that are not included in Table 18 Registers and bits designated as global in Table 18 affect the entire are not currently supported for this device. Unused bits of a part or the channel features for which independent settings are not valid address location should be written with 0s. Writing to these allowed between channels. locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open (for example, Address 0x13), this address location should not be written to. Rev. 0 | Page 33 of 40 AD9608 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 18 are not currently supported for this device. Table 18. Memory Map Registers Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port Open LSB first Soft reset 1 1 Soft reset LSB first Open 0x18 Nibbles are config mirrored so LSB-first (global) mode or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID, Bits[7:0] Read Unique AD9608 = 0x9C only chip ID (global) used to differentiate devices; read only 0x02 Chip Open Speed grade ID Open Open Open Open Read Unique grade only speed 100 = 105 MSPS grade ID (global) 101 = 125 MSPS used to differentiate devices; read only Channel Index and Transfer Registers 0x05 Device Open Open Open Open Open Open Channel B Channel A 0x03 Bits are index set to (global) determine which device on the chip receives the next write command; applies to local registers only 0xFF Open Open Open Open Open Open Open Transfer 0x00 Transfer Synchronous (global) transfer of data from the master shift register to the slave ADC Functions 0x08 Power Open Open External Open Open Open Internal power-down mode 0x00 Determines modes power- various 00 = normal operation down pin generic (local) 01 = full power-down function modes of 10 = standby chip 0 = PDWN 11 = digital reset operation 1 = standby 0x09 Global Open Open Open Open Open Open Open Duty cycle 0x01 clock stabilizer (global) 0 = disabled 1 = enabled Rev. 0 | Page 34 of 40 AD9608 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0B Clock Open Open Open Open Open Clock divide ratio 0x00 The divide divide ratio is 000 = divide by 1 value plus 1 (global) 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0C Enhance- Open Open Open Open Open Chop mode Open Open 0x00 Chop mode ment enabled if 0 = disabled control Bit 2 = 1 1 = enabled (global) 0x0D Test User test mode control Reset PN Reset PN Output test mode 0x00 When this mode long gen short gen register is 00 = single pattern 0000 = off (default) (local) set, the test mode 0001 = midscale short data is 01 = alternate 0010 = positive FS placed on continuous/repeat 0011 = negative FS the output pattern mode 0100 = alternating checkerboard pins in 10 = single once 0101 = PN long sequence place of pattern mode 0110 = PN short sequence normal data 11 = alternate once 0111 = one/zero word toggle pattern mode 1000 = user test mode 1111 = ramp output 0x0E BIST Open Open Open Open Open Initialize Open BIST enable 0x00 enable BIST sequence (global) 0x10 Customer Offset adjust in LSBs from +127 to −128 0x00 offset (twos complement format) adjust (local) 0x14 Output Output port logic Output Output Open Output Output format 0x00 Configures mode type (global) interleave port disable invert the outputs (global) 00 = offset binary enable (local) (local) and the 00 = CMOS, 1.8 V 01 = twos complement format of (global) 10 = LVDS, ANSI 10 = Gray code the data 11 = LVDS, reduced range 0x15 Output Open Open CMOS 1.8 V DCO drive Open Open CMOS 1.8 V data 0x00 Determines adjust strength drive strength CMOS output 00 = 1× 00 = 1× drive 01 = 2× 01 = 2× strength 10 = 3× 10 = 3× properties 11 = 4× 11 = 4× 0x16 Clock Invert Open Open Open Open Input clock divider phase adjust 0x00 Allows phase DCO relative to the encode clock selection of control clock clock delays 000 = no delay into the (global) 0 = not 001 = 1 input clock cycle input clock inverted 010 = 2 input clock cycles divider 1 = 011 = 3 input clock cycles inverted 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 Output DCO Open Data delay Open Open Delay selection 0x00 This sets delay clock the fine 0 = disabled 000 = 0.56 ns (global) delay output 1 = enabled 001 = 1.12 ns delay of the 0 = 010 = 1.68 ns output disabled 011 = 2.24 ns clock but 1 = 100 = 2.80 ns does not enabled 101 = 3.36 ns change 110 = 3.92 ns internal 111 = 4.48 ns timing Rev. 0 | Page 35 of 40 AD9608 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x18 VREF Open Open Open Open Open Internal VREF digital adjustment 0x04 Select select and/or 000 = 1.0 V p-p adjust VREF (global) 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p 0x19 User B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Pattern 1, Defined LSB Pattern 1, (global) LSB 0x1A User B15 B14 B13 B12 B11 B10 B9 B8 0x00 User- Pattern 1, Defined MSB Pattern 1, (global) MSB 0x1B User B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Pattern 2, Defined LSB Pattern 2, (global) LSB 0x1C B15 B14 B13 B12 B11 B10 B9 B8 0x00 User User- Pattern 2, Defined MSB Pattern 2, MSBs 0x24 MISR LSB MISR LSB, Bits[7:0] 0xFF Read only 0x25 MISR MSB MISR MSB, Bits[15:8] 0xFF Read only 0x2A Overrange Open Open Open Open Open Open Open Overrange 0x01 Overrange control output control settings (global) 0 = disabled 1 = enabled 0x2E Output Open Open Open Open Open Open Open 0 = ADC A 0x00 = Assign an assign 1 = ADC B ADC A ADC to an (local) (local) output 0x01 = channel ADC B 0x3A Sync Open Open Open Open Open Clock Clock Open 0x00 Sets the control divider divider global sync (global) next sync sync options only enable 0x100 Sample Open Sample Open Open Open Sample rate 0x00 rate rate 011 = 80 MSPS override override 100 = 105 MSPS enable 101 = 125 MSPS 0x101 User I/O Output Open Open Open Open Open Open Disable SDIO 0x00 OEB and Control enable pull-down SDIO pin Register 2 bar controls (OEB) pin enable 0x102 User I/O Open Open Open Open VCM Open 0x00 Control power-down Register 3 Rev. 0 | Page 36 of 40 AD9608 interleaving feature. Channel A is sent on least significant bits MEMORY MAP REGISTER DESCRIPTIONS (LSBs), and Channel B is sent on most significant bits (MSBs). For additional information about functions controlled in The even bits are sent coincident with a high DCO clock, and Register 0x00 to Register 0xFF, see the AN-877 Application Note, the odd bits are sent coincident with a low DCO clock. Interfacing to High Speed ADCs via SPI. For CMOS outputs, setting Bit 5 enables interleaving in CMOS Power Modes (Register 0x08) DDR mode. On ADC Output Port A, Channel A is sent coincident Bits[7:6]—Open with a low DCO clock, and Channel B is coincident with a high Bit 5—External Power-Down Pin Function DCO clock. On ADC Output Port B, Channel B is sent coincident with a low DCO clock, and Channel A is coincident with a high If set, the external PDWN pin initiates power-down mode. DCO clock. Clearing Bit 5 disables the interleaving feature, and If clear, the external PDWN pin initiates standby mode. data is output in CMOS SDR mode. Channel A is sent to Port A, Bits[4:2]—Open and Channel B is sent to Port B. Bits[1:0]—Internal Power-Down Mode Bit 4—Output Port Disable In normal operation (Bits[1:0] = 00), both ADC channels are Setting Bit 4 high disables the output port for the channels active. selected in Bits[1:0] of the device index register (Register 0x05). In power-down mode (Bits[1:0] = 01), the digital data path clocks Bit 3—Open are disabled while the digital data path is reset. Outputs are Bit 2—Output Invert disabled. Setting Bit 2 high inverts the output port data for the channels In standby mode (Bits[1:0] = 10), the digital data path clocks selected in Bits[1:0] of the device index register (Register 0x05). and the outputs are disabled. Bits[1:0]—Output Format During a digital reset (Bits[1:0] = 11), the digital data path clocks are disabled while the digital data path is held in reset. The outputs 00 = offset binary are enabled in this state. For optimum performance, it is recom- 01 = twos complement mended that both ADC channels be reset simultaneously. This 10 = Gray code is accomplished by ensuring that both channels are selected via Sync Control (Register 0x3A) Register 0x05 prior to issuing the digital reset instruction. Bits[7:3]—Open Enhancement Control (Register 0x0C) Bit 2—Clock Divider Next Sync Only Bits[7:3]—Open If the clock divider sync enable bit (Address 0x3A, Bit 1) is high, Bit 2—Chop Mode Bit 2 allows the clock divider to sync to the first sync pulse it For applications that are sensitive to offset voltages and other receives and to ignore the rest. The clock divider sync enable bit low frequency noise, such as homodyne or direct-conversion resets after it syncs. receivers, chopping in the first stage of the AD9628 is a feature Bit 1—Clock Divider Sync Enable that can be enabled by setting Bit 2. In the frequency domain, Bit 1 gates the sync pulse to the clock divider. The sync signal is chopping translates offsets and other low frequency noise to enabled when Bit 1 is high. This is continuous sync mode. fCLK/2 where it can be filtered. Bit 0—Open Bits[1:0]—Open Transfer (Register 0xFF) Output Mode (Register 0x14) All registers except Register 0x100 are updated the moment they Bits[7:6]—Output Port Logic Type are written. Setting Bit 0 of this transfer register high initializes the 00 = CMOS, 1.8 V settings in the ADC sample rate override register (Address 0x100). 10 = LVDS, ANSI Sample Rate Override (Register 0x100) 11 = LVDS, reduced range This register is designed to allow the user to downgrade the device. Bit 5—Output Interleave Enable Any attempt to upgrade the default speed grade results in a chip For LVDS outputs, setting Bit 5 enables interleaving. Channel A power-down. Settings in this register are not initialized until Bit 0 is sent coincident with a high DCO clock, and Channel B is of the transfer register (Register 0xFF) is written high. coincident with a low DCO clock. Clearing Bit 5 disables the Rev. 0 | Page 37 of 40 AD9608 User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) Bit 7—OEB Pin Enable Bits[7:4]—Open If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. Bit 3—VCM Power-Down If Bit 7 is clear, the OEB pin is disabled (default). Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external Bits[6:1]—Open reference. Bit 0—SDIO Pull-Down Bits[2:0]—Open Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Rev. 0 | Page 38 of 40 AD9608 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting design and layout of the AD9608 as a system, the bottom of the PCB. These vias should be filled or plugged to it is recommended that the designer become familiar with these prevent solder wicking through the vias, which can compromise guidelines, which discuss the special circuit connections and the connection. layout requirements that are needed for certain pins. To maximize the coverage and adhesion between the ADC and Power and Ground Recommendations the PCB, a silkscreen should be overlaid to partition the continuous When connecting power to the AD9608, it is recommended that plane on the PCB into several uniform sections. This provides two separate 1.8 V supplies be used. Use one supply for analog several tie points between the ADC and the PCB during the reflow (AVDD); use a separate supply for the digital outputs (DRVDD). process. Using one continuous plane with no partitions guarantees For both AVDD and DRVDD, several different decoupling capa- only one tie point between the ADC and the PCB. For detailed citors should be used to cover both high and low frequencies. information about packaging and PCB layout of chip scale Place these capacitors close to the point of entry at the PCB level packages, see the AN-772 Application Note, A Design and and close to the pins of the part, with minimal trace length. Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. A single PCB ground plane should be sufficient when using the AD9608. With proper decoupling and smart partitioning of the VCM PCB analog, digital, and clock sections, optimum performance The VCM pin should be decoupled to ground with a 0.1 μF is easily achieved. capacitor. LVDS Operation Reference Decoupling The AD9608 defaults to CMOS output mode on power-up. The VREF pin should be externally decoupled to ground with If LVDS operation is desired, this mode must be programmed, a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF using the SPI configuration registers after power-up. When the ceramic capacitor. AD9608 powers up in CMOS mode with LVDS termination SPI Port resistors (100 Ω) on the outputs, the DRVDD current can be The SPI port should not be active during periods when the full higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage dynamic performance of the converter is required. Because the to the AD9608, but it should be taken into account when consid- SCLK, CSB, and SDIO signals are typically asynchronous to the ering the maximum DRVDD current for the part. ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, To avoid this additional DRVDD current, the AD9608 outputs it may be necessary to provide buffers between this bus and the can be disabled at power-up by taking the PDWN pin high. AD9608 to keep these signals from transitioning at the converter After the part is placed into LVDS mode via the SPI port, the inputs during critical sampling periods. PDWN pin can be taken low to enable the outputs. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9608 exposed paddle, Pin 0. Rev. 0 | Page 39 of 40 AD9608 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 63. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9608BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZRL7-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZRL7-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608-125EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09977-0-7/11(0) Rev. 0 | Page 40 of 40 091707-C