ANALOG DEVICES AD9481

8-Bit, 250 MSPS 3.3 V A/D Converter AD9481 FEATURES FUNCTIONAL BLOCK DIAGRAM VREF SENSE AGND DRGND DRVDD AVDD DNL = ±0.35 LSB INL = ±0.26 LSB AD9481 Single 3.3 V supply operation (3.0 V to 3.6 V) REFERENCE 8 PORT Power dissipation of 439 mW at 250 MSPS D7A TO D0A A 1 V p-p analog input range VIN+ 8-BIT T AND H 8 Internal 1.0 V reference ADC VIN– PIPELINE Single-ended or differential analog inputs PORT 8 CORE DS+ D7B TO D0B B De-multiplexed CMOS outputs DS– Power-down mode CLK+ CLOCK DCO+ Clock duty cycle stabilizer MGMT CLK– DCO– LOGIC APPLICATIONS Digital oscilloscopes PDWN S1 Instrumentation and measurement Figure 1. Communications Point-to-point radios Digital predistortion loops The AD9481 is available in a Pb-free, 44-lead, surface-mount GENERAL DESCRIPTION package (TQFP-44) specified over the industrial temperature The AD9481 is an 8-bit, monolithic analog-to-digital converter range (−40°C to +85°C). (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a PRODUCT HIGHLIGHTS 250 MSPS conversion rate, with excellent linearity and dynamic 1. Superior linearity. A DNL of ±0.35 makes the AD9481 performance over its full operating range. suitable for many instrumentation and measurement To minimize system cost and power dissipation, the AD9481 applications includes an internal reference and track-and-hold circuit. The 2. Power-down mode. A power-down function may be exercised user only provides a 3.3 V power supply and a differential to bring total consumption down to 15 mW. encode clock. No external reference or driver components are required for many applications. 3. De-multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and standard logic. The digital outputs are TTL/CMOS-compatible with an option of twos complement or binary output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 05045-001 AD9481 TABLE OF CONTENTS DC Specifications ............................................................................. 3 Data Clock Out........................................................................... 20 Digital Specifications........................................................................ 4 Power-Down Input..................................................................... 20 AC Specifications.............................................................................. 5 AD9481 Evaluation Board ............................................................ 21 Switching Specifications .................................................................. 6 Power Connector........................................................................ 21 Timing Diagram ........................................................................... 7 Analog Inputs.............................................................................. 21 Absolute Maximum Ratings............................................................ 8 Gain.............................................................................................. 21 Explanation of Test Levels........................................................... 8 Optional Operational Amplifier............................................... 21 ESD Caution.................................................................................. 8 Clock ............................................................................................ 21 Pin Configuration and Function Descriptions............................. 9 Optional Clock Buffer ............................................................... 21 Terminology .................................................................................... 10 DS ................................................................................................. 21 Typical Performance Characteristics ........................................... 12 Optional XTAL ........................................................................... 22 Equivalent Circuits ......................................................................... 16 Voltage Reference ....................................................................... 22 Applications..................................................................................... 17 Data Outputs............................................................................... 22 Analog Inputs.............................................................................. 17 Evaluation Board Bill of Materials (BOM) ................................. 23 Voltage Reference ....................................................................... 17 PCB Schematics .............................................................................. 24 Clocking the AD9481................................................................. 19 PCB Layers ...................................................................................... 26 DS Inputs ..................................................................................... 19 Outline Dimensions ....................................................................... 28 Digital Outputs ........................................................................... 20 Ordering Guide .......................................................................... 28 Interleaving Two AD9481s........................................................ 20 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9481 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 1. AD9481-250 Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error 25°C I −40 40 mV 1 Gain Error 25°C I −6.0 6.0 % FS Differential Nonlinearity (DNL) Full VI −0.85 ±0.35 0.85 LSB Integral Nonlinearity (INL) Full VI −0.9 ±0.26 0.9 LSB TEMPERATURE DRIFT Offset Error Full V 30 µV/°C Gain Error Full V 0.03 % FS/°C Reference Full V ±0.025 mV/°C REFERENCE Internal Reference Voltage Full VI 0.97 1.0 1.03 V 2 Output Current 25°C IV 1.5 mA 3 IVREF Input Current 25°C I 100 µA 2 ISENSE Input Current 25°C I 10 µA ANALOG INPUTS (VIN+, VIN−) 4 Differential Input Voltage Range Full V 1 V p-p Common-Mode Voltage Full VI 1.6 1.9 2.1 V Input Resistance Full VI 8.4 10 11.2 kΩ Input Capacitance 25°C V 4 pF Analog Bandwidth, Full Power 25°C V 750 MHz POWER SUPPLY AVDD Full IV 3.0 3.3 3.6 V DRVDD Full IV 3.0 3.3 3.6 V Supply Currents 5 IAVDD Full VI 133 145 mA 5 IDRVDD Full VI 39 42.5 mA 5 Power Dissipation 25°C V 439 mW Power-Down Dissipation 25°C V 15 37 mW Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and 1 V p-p input range). 2 Internal reference mode; SENSE = AGND. 3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Supply current measured with rated encode and a 20 MHz analog input. Power dissipation measured with dc input, see the Terminology section for power vs. clock rate. Rev. 0 | Page 3 of 28 AD9481 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 2. AD9481-250 Parameter Temp Test Level Min Typ Max Unit CLOCK AND DS INPUTS (CLK+, CLK−, DS+, DS−) Differential Input Full IV 200 mV p-p 1 Common-Mode Voltage Full VI 1.38 1.5 1.68 V Input Resistance Full VI 4.2 5.5 6.0 kΩ Input Capacitance 25°C V 4 pF LOGIC INPUTS (PDWN, S1) Logic 1 Voltage Full IV 2.0 V Logic 0 Voltage Full IV 0.8 V Logic 1 Input Current Full VI ±160 µA Logic 0 input Current Full VI 10 µA Input Resistance 25°C V 30 kΩ Input Capacitance 25°C V 4 pF DIGITAL OUTPUTS 2 Logic 1 Voltage Full VI DRVDD − 0.05 mV Logic 0 Voltage Full VI 0.05 V Output Coding Full IV Twos complement or binary 1 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V. 2 Capacitive loading only. Rev. 0 | Page 4 of 28 AD9481 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 3. AD9481-250 Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 19.7 MHz 25°C V 46 dB f = 70.1 MHz 25°C I 44.5 45.7 dB IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 19.7 MHz 25°C V 45.9 dB f = 70.1 MHz 25°C I 44.4 45.7 dB IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 19.7 MHz 25°C V 7.5 Bits f = 70.1 MHz 25°C I 7.2 7.5 Bits IN WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz 25°C V −64.8 dBc f = 70.1 MHz 25°C I −64.8 −54 dBc IN WORST OTHER fIN = 19.7 MHz 25°C V −68 dBc f = 70.1 MHz 25°C I −65.8 −56 dBc IN 1 SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 19.7 MHz 25°C V −64.8 dBc IN f = 70.1 MHz 25°C I −64.8 −54 dBc IN TWO-TONE INTERMODULATION DISTORTION (IMD) f = 69.3 MHz, f = 70.3 MHz 25°C V −64.9 dBc IN1 IN2 1 DC and Nyquist bin energy ignored. Rev. 0 | Page 5 of 28 AD9481 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted. Table 4. AD9481-250 Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full IV 20 MSPS Clock Pulse-Width High (t) Full IV 1.2 2 ns EH Clock Pulse-Width Low (t) Full IV 1.2 2 ns EL DS Input Setup Time (t) Full IV 0.5 ns SDS DS Input Hold Time (tHDS) Full IV 0.5 ns 1 OUTPUT PARAMETERS 2 Valid Time (t ) Full VI 2.5 ns V Propagation Delay (tPD) Full VI 4 5.4 ns Rise Time (tR) 10% to 90% Full V 670 ps Fall Time (t ) 10% to 90% Full V 360 ps F 3 DCO Propagation Delay (t ) Full VI 2.5 3.9 5.3 ns CPD 4 Data-to-DCO Skew (t − t ) Full VI −0.5 +0.5 ns PD CPD 5 A Port Data to DCO− Rising (tSKA) Full IV 4 ns B Port Data to DCO+ Rising (tSKB) Full IV 4 ns Pipeline Latency (A, B) Full IV 8 Cycles APERTURE Aperture Delay (tA) 25°C V 1.5 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms OUT-OF-RANGE RECOVERY TIME 25°C V 1 Cycle 1 C equals 5 pF maximum for all output switching specifications. LOAD 2 Valid time is approximately equal to minimum tPD. 3 T equals clock rising edge to DCO (+ or −) rising edge delay. CPD 4 Data changing to (DCO+ or DCO−) rising edge delay. 5 T , T are both clock rate dependent delays equal to T − (Data to DCO skew). SKA SKB CYCLE Rev. 0 | Page 6 of 28 AD9481 TIMING DIAGRAM N–1 N+9 t A N N+8 N+10 VIN N+1 N+7 8 CYCLES t t EH EL 1/f S CLK+ CLK– t HDS DS+ DS– t SDS t V INTERLEAVED DATA OUT t PD PORT A STATIC INVALID N D7A TO D0A PORT B STATIC INVALID INVALID N+1 D7B TO D0B t SKA t SKB t CPD DCO+ STATIC DCO– Figure 2. Timing Diagram Rev. 0 | Page 7 of 28 05045-002 AD9481 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB). EXPLANATION OF TEST LEVELS Table 5. Table 6. Min. Max. Level Description Parameter Rating Rating I 100% production tested. ELECTRICAL II 100% production tested at 25°C and guaranteed by AVDD (With respect to AGND) −0.5 V +4.0 V design and characterization at specified temperatures. DRVDD −0.5 V +4.0 V III Sample tested only. (With respect to DRGND) IV Parameter is guaranteed by design and characterization AGND (With respect to DRGND) −0.5 V +0.5 V testing. Digital I/0 −0.5 V DRVDD + 0.5 V V Parameter is a typical value only. (With respect to DRGND) VI 100% production tested at 25°C and guaranteed by Analog Inputs −0.5 V AVDD + 0.5 V design and characterization for industrial temperature (With respect to AGND) range. ENVIRONMENTAL Operating Temperature −40°C +85°C Junction Temperature 150°C Storage Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 28 AD9481 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 1 33 CLK+ SENSE PIN 1 CLK– 2 32 AGND AVDD 3 31 AVDD 4 30 AGND AVDD AD9481 5 29 PDWN DRVDD TOP VIEW (Not to Scale) 6 28 DRGND S1 7 27 D7A (MSB) DRGND 8 26 D6A D7B (MSB) 9 25 D5A D6B D4A 10 24 D5B D3A 11 23 D4B 12 13 14 15 16 17 18 19 20 21 22 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin Pin No. Name Description No. Name Description 1 CLK+ Input Clock—True 25 D6B Data Output Bit 6—Channel B 2 CLK− Input Clock—Complement 26 D7B Data Output Bit 7—Channel B (MSB) 3 AVDD 3.3 V Analog Supply 27 DRGND Digital Ground 4 AGND Analog Ground 28 S1 Data Format Select and Duty Cycle Stabilizer Select 5 DRVDD 3.3 V Digital Output Supply 29 PDWN Power-Down Selection 6 DRGND Digital Ground 30 AVDD 3.3 V Analog Supply 7 D7A Data Output Bit 7—Channel A (MSB) 31 AVDD 3.3 V Analog Supply 8 D6A Data Output Bit 6—Channel A 32 AGND Analog Ground 9 D5A Data Output Bit 5—Channel A 33 SENSE Reference Mode Selection 10 D4A Data Output Bit 4—Channel A 34 VREF Voltage Reference Input/Output 11 D3A Data Output Bit 3—Channel A 35 AGND Analog Ground 12 D2A Data Output Bit 2—Channel A 36 AVDD 3.3 V Analog Supply 13 D1A Data Output Bit 1—Channel A 37 AGND Analog Ground 14 D0A Data Output Bit 0—Channel A (LSB) 38 VIN− Analog Input—Complement 15 DRGND Digital Ground 39 VIN+ Analog Input—True 16 DCO− Data Clock Output—Complement 40 AGND Analog Ground 17 DCO+ Data Clock Output—True 41 AVDD 3.3 V Analog Supply 18 DRVDD 3.3 V Digital Output Supply 42 S3 DCO Enable Select (Tie to AVDD for DCO 19 D0B Data Output Bit 0—Channel B (LSB) Active) 20 D1B Data Output Bit 1—Channel B 43 DS− Data Sync Complement (If Unused, Tie to 21 D2B Data Output Bit 2—Channel B DRVDD) 22 D3B Data Output Bit 3—Channel B 44 DS+ Data Sync True (If Unused, Tie to DGND) 23 D4B Data Output Bit 4—Channel B 24 D5B Data Output Bit 5—Channel B Rev. 0 | Page 9 of 28 D2A DS+ D1A DS– D0A (LSB) S3 DRGND AVDD DCO– AGND DCO+ VIN+ DRVDD VIN– D0B (LSB) AGND D1B AVDD D2B AGND D3B VREF 05045-003 AD9481 TERMINOLOGY Analog Bandwidth Full-Scale Input Power The analog input frequency at which the spectral power of the Expressed in dBm. Computed using the following equation fundamental frequency (as determined by the FFT analysis) is 2 ⎛ ⎞ reduced by 3 dB. V FULLSCALErms ⎜ ⎟ Z ⎜ ⎟ INPUT Power = 10 log Aperture Delay FULLSCALE ⎜ ⎟ 0.001 The delay between the 50% point of the rising edge of the ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ encode command and the instant the analog input is sampled. Gain Error Aperture Uncertainty (Jitter) Gain error is the difference between the measured and ideal The sample-to-sample variation in aperture delay. full-scale input voltage range of the ADC. Clock Pulse-Width/Duty Cycle Harmonic Distortion, Second Pulse-width high is the minimum amount of time that the clock The ratio of the rms signal amplitude to the rms value of the pulse should be left in a Logic 1 state to achieve rated second harmonic component, reported in dBc. performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing Harmonic Distortion, Third t in the Clocking the AD9481 section. At a given clock rate, EH The ratio of the rms signal amplitude to the rms value of the these specifications define an acceptable clock duty cycle. third harmonic component, reported in dBc. Crosstalk Integral Nonlinearity Coupling onto one channel being driven by a low level The deviation of the transfer function from a reference line (−40 dBFS) signal when the adjacent interfering channel is measured in fractions of 1 LSB using a best straight line driven by a full-scale signal. determined by a least square curve fit. Differential Analog Input Resistance, Differential Analog Minimum Conversion Rate Input Capacitance, and Differential Analog Input Impedance The encode rate at which the SNR of the lowest analog signal The real and complex impedances measured at each analog frequency drops by no more than 3 dB below the guaranteed input port. The resistance is measured statically and the limit. capacitance and differential input impedances are measured with a network analyzer. Maximum Conversion Rate The encode rate at which parametric testing is performed. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to Output Propagation Delay the converter to generate a full-scale response. Peak differential The delay between a differential crossing of CLK+ and CLK− voltage is computed by observing the voltage on a single pin and the time when all output data bits are within valid logic and subtracting the voltage from the other pin, which is 180° levels. out of phase. Peak-to-peak differential is computed by rotating Noise (for Any Range within the ADC) the inputs phase 180° and taking the peak measurement again. This value includes both thermal and quantization noise. The difference is then computed between both peak measurements. FS −SNR −Signal ⎛ ⎞ dBm dBc dBFS V = Z×0 .001×10⎜ ⎟ noise Differential Nonlinearity ⎜ ⎟ 10 ⎝ ⎠ The deviation of any code width from an ideal 1 LSB step. where: Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the Z is the input impedance. equation (assuming full-scale input) FS is the full scale of the device for the frequency in question. SINAD − 1.76 dB MEASURED ENOB= SNR is the value for the particular input level. 6.02 Signal is the signal level within the ADC reported in dB below full scale. Rev. 0 | Page 10 of 28 AD9481 Power Supply Rejection Ratio Two-Tone SFDR The ratio of a change in input offset voltage to a change in The ratio of the rms value of either input tone to the rms value power supply voltage. of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in Signal-to-Noise and Distortion (SINAD) dBc (degrades as signal level is lowered) or in dBFS (always The ratio of the rms signal amplitude (set 1 dB below full scale) relates back to converter full scale). to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the Signal-to-Noise Ratio (without Harmonics) worst spurious component (excluding the second and third The ratio of the rms signal amplitude (set at 1 dB below full harmonic), reported in dBc. scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Transient Response Time The time it takes for the ADC to reacquire the analog input Spurious-Free Dynamic Range (SFDR) after a transient from 10% above negative full scale to 10% The ratio of the rms signal amplitude to the rms value of the below positive full scale. peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be Out-of-Range Recovery Time reported in dBc (degrades as signal level is lowered) or dBFS This is the time it takes for the ADC to reacquire the analog (always related back to converter full scale). input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale Two-Tone Intermodulation Distortion Rejection to 10% below positive full scale. The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc. Rev. 0 | Page 11 of 28 AD9481 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, internal reference mode, unless otherwise noted. 0 0 SNR = 45.8dB SNR = 45.6dB H2 = –65.2dBc H2 = –72.9dBc –10 –10 H3 = –63.2dBc H3 = –65.2dBc SFDR = 63.2dBc SFDR = 59.6dBc –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 04 200 6080 100 120 04 200 6080 100 120 (MHz) (MHz) Figure 4. FFT: f = 250 MSPS, A = 10.3 MHz @ −1 dBFS Figure 7. FFT: f = 250 MSPS, A = 170 MHz @ −1 dBFS S IN S IN 0 90 SNR = 45.8dB H2 = –68.5dBc 85 –10 H3 = –63.5dBc SFDR = 63.8dBc 80 –20 H3 75 –30 H2 70 –40 65 –50 60 –60 55 SFDR –70 50 SNR –80 45 SINAD 40 –90 0 50 100 150 200 250 300 350 400 04 200 6080 100 120 A (MHz) (MHz) IN Figure 5. FFT: f = 250 MSPS, A = 70 MHz @ −1 dBFS S IN Figure 8. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 1 V, fS = 250 MSPS 0 90 SNR = 45.9dB H2 = –66.6dBc 85 –10 H3 = –70.1dBc SFDR = 65.9dBc 80 –20 H3 75 –30 H2 70 –40 65 –50 60 SFDR –60 55 –70 50 SNR –80 45 SINAD –90 40 04 200 6080 100 120 0 50 100 150 200 250 300 350 400 (MHz) A (MHz) IN Figure 6. FFT: fS = 250 MSPS, AIN = 70 MHz @ −1 dBFS, Single-Ended Input Figure 9. Analog Input Frequency Sweep, A =−1 dBFS, FS = 0.75 V, f = 250 MSPS, External VREF Mode IN S Rev. 0 | Page 12 of 28 (dB) (dB) (dB) 05045-006 05045-005 05045-004 (dB) (dB) (dB) 05045-009 05045-008 05045-007 AD9481 75 140 I AVDD 70 120 SFDR 65 100 60 80 55 60 50 40 SNR I DRVDD 20 45 SINAD 0 40 0 50 100 150 200 250 300 0 50 100 150 200 250 300 SAMPLE CLOCK (MSPS) SAMPLE CLOCK (MHz) Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ −1 dBFS AIN = 70 MHz @ −1 dB 80 50 49 70 SFDR (dBFS) 48 60 DCS ON 47 50 46 40 45 SFDR (dBc) 44 30 DCS OFF 43 20 60dB 42 REFERENCE LINE 10 41 0 40 –70 –60 –50 –40 –30 –20 –10 0 20 30 40 50 60 70 80 ANALOG INPUT DRIVE LEVEL (dBFS) CLOCK POSITIVE DUTY CYCLE (%) Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS Figure 14. SNR, SINAD vs. Clock Pulse-Width High, AIN = 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off 0 50.0 75 F1, F2 = –7dBFS 2F2–F1 = –65.9dBc –10 2F1–F2 = –64.9dBc SNR –20 47.5 70 –30 –40 SINAD 45.0 65 –50 SFDR –60 42.5 60 –70 –80 –90 40.0 55 04 200 6080 100 120 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 (MHz) EXTERNAL VREF VOLTAGE (V) Figure 12. Two-Tone Intermodulation Distortion Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN = = 250 MSPS) (69.3 MHz and 70.3 MHz; fS 70 MHz @ −1 dBFS, 250 MSPS Rev. 0 | Page 13 of 28 (dB) (dB) (dB) 05045-012 05045-011 05045-010 SNR, SINAD (dB) (dB) CURRENT (mA) 05045-014 05045-013 SFDR (dBc) 05045-015 AD9481 2.0 70 1.5 FS = 1V 65 EXTERNAL REFERENCE 1.0 SFDR 0.5 60 0 55 –0.5 –1.0 FS = 1V 50 INTERNAL REFERENCE SINAD SNR –1.5 –2.0 45 –40 –20 0 204060 80 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (°C) AVDD (V) Figure 16. Full-Scale Gain Error vs. Temperature, Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS AIN = 70.3 MHz @ −1 dBFS, 250 MSPS 70 0.5 0.4 65 0.3 SFDR 0.2 60 0.1 55 0 –0.1 50 –0.2 SINAD –0.3 45 –0.4 40 –0.5 –40 –20 0 204060 80 0 50 100 150 200 250 TEMPERATURE (°C) CODE Figure 17. SINAD, SFDR vs. Temperature, Figure 20. Typical DNL Plot, A = 70 MHz @ −1 dBFS, 250 MSPS IN AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS 0.10 0.50 0.05 0.25 0 0 –0.05 –0.25 –0.10 –0.15 –0.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250 AVDD (V) CODE Figure 18. VREF Sensitivity to AVDD Figure 21. Typical INL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS Rev. 0 | Page 14 of 28 CHANGE IN VREF (%) (dB) GAIN ERROR (%) 05045-018 05045-017 05045-016 LSB LSB (dB) 05045-021 05045-020 05045-019 AD9481 T _F PD 0.2 0.1 T _F CPD 0 –0.1 –0.2 T _R CPD –0.3 T _R PD –0.4 –40 –20 0 20 406080 TEMPERATURE (°C) Figure 22. Propagation Delay Sensitivity vs. Temperature Rev. 0 | Page 15 of 28 DELAY CHANGE (ps) 05045-048 AD9481 EQUIVALENT CIRCUITS AVDD AVDD 16.7kΩ 16.7kΩ 150Ω 150Ω PDWN VIN+ VIN– 1.2pF 1.2pF 25kΩ 25kΩ 30kΩ Figure 26. Power-Down Input Figure 23. Analog Inputs AVDD DRVDD 12kΩ 12kΩ CLK+ CLK– 150Ω 150Ω 10kΩ 10kΩ Figure 27. Data, DCO Outputs Figure 24. Clock Inputs VDD 30kΩ S1 Figure 25. S1 Input Rev. 0 | Page 16 of 28 05045-025 05045-024 05045-023 05045-027 05045-026 AD9481 APPLICATIONS The AD9481 uses a 1.5 bit per stage architecture. The analog 49.9Ω inputs drive an integrated high bandwidth track-and-hold 499Ω AVDD circuit that samples the signal prior to quantization by the 8-bit 33Ω 499Ω VIN+ core. For ease of use, the part includes an on-board reference 20pF AD9481 AD8138 and input logic that accepts TTL, CMOS, or LVPECL levels. The 1.3kΩ 33Ω VIN– digital output logic levels are CMOS-compatible. 523Ω 2kΩ AGND 0.1µF 499Ω ANALOG INPUTS The analog input to the AD9481 is a differential buffer. For best Figure 29. Driving the ADC with the AD8138 dynamic performance, impedances at VIN+ and VIN− should The AD9481 can be easily configured for different full-scale match. Optimal performance is obtained when the analog ranges. See the Voltage Reference section for more information. inputs are driven differentially. SNR and SINAD performance Optimal performance is achieved with a 1 V p-p analog input. can degrade if the analog input is driven with a single-ended signal. The analog inputs self-bias to approximately 1.9 V; this SENSE = GND common-mode voltage can be externally overdriven by approximately ±300 mV if required. VIN+ A wideband transformer, such as the Mini-Circuits ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the 500mV 2.0V 2.0V filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at the VIN– secondary side helps reduce any wideband noise getting aliased DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s by the ADC. (R, C OPTIONAL) AVDD 33Ω VIN+ Figure 30. Analog Input Full Scale 49.9Ω 10pF AD9481 VOLTAGE REFERENCE 33Ω VIN– A stable and accurate 1.0 V reference is built into the AD9481. AGND Users can choose this internal reference or provide an external 0.1µF reference for greater accuracy and flexibility. Figure 32 shows Figure 28. Driving the ADC with an RF Transformer the typical reference variation with temperature. Table 8 summarizes the available reference configurations. For dc-coupled applications, the AD8138/AD8139 or AD8351 can serve as a convenient ADC driver, depending on VIN+ requirements. Figure 29 shows an example with the AD8138. VIN– The AD9481 PCB has an optional AD8351 on board, as shown in Figure 39 and Figure 40. The AD8351 typically yields better ADC performance for frequencies greater than 30 MHz to 40 MHz. CORE The AD9481’s linearity and SFDR start to degrade at higher analog frequencies (see the Typical Performance Characteristics section). For higher frequency applications, the AD9480 with VREF LVDS outputs and superior AC performance should be + 10µF 0.1µF considered. 7kΩ SELECT LOGIC SENSE 0.5V 7kΩ Figure 31. Internal Reference Equivalent Circuit Rev. 0 | Page 17 of 28 05045-029 05045-032 05045-030 05045-031 AD9481 Fixed Reference The internal reference can be configured for a differential span of 1 V p-p (see Figure 34). It is recommended to place a 0.1 µF VREF 10µF 0.1µF capacitor as close as possible to the VREF pin; a 10 µF capacitor is also required (see the PCB layout for guidance). If the internal SENSE reference of the AD9481 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 depicts how the Figure 33. Internal Fixed Reference (1 V p-p) internal reference voltage is affected by loading. 0 1.0085 1.0080 –0.1 1.0075 1.0070 –0.2 1.0065 1.0060 –0.3 1.0055 1.0050 –0.4 1.0045 1.0040 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 1.0035 IREF (mA) –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 34. Internal VREF vs. Load Current Figure 32. Typical Reference Variation with Temperature Table 8. Reference Configurations SENSE Voltage Resulting VREF Reference Differential Span AVDD N/A (external reference input) External 1 × external reference voltage 0.5 V (Self-Biased) 0.5 × (1 + R1/R2) V Programmable 1 × VREF (0.75 V p-p to 1.5 V p-p) AGND to 0.2 V 1.0 V Internal fixed 1 V p-p Rev. 0 | Page 18 of 28 VREF (V) 05045-033 % CHANGE IN VREF VOLTAGE 05045-034 05045-035 AD9481 External Reference change dynamically, requiring a wait time of 5 µs after a dynamic clock frequency increase before valid data is available. An external reference can be used for greater accuracy and The clock duty cycle stabilizer can be disabled at Pin 28 (S1). temperature stability when required. The gain of the AD9481 can also be varied using this configuration. A voltage output The clock inputs are internally biased to 1.5 V (nominal) and DAC can be used to set VREF, providing for a means to digitally support either differential or single-ended signals. For best adjust the full-scale voltage. VREF can be externally set to dynamic performance, a differential signal is recommended. An voltages from 0.75 V to 1.5 V; optimum performance is typically MC100LVEL16 performs well in the circuit to drive the clock obtained at VREF = 1 V. (See the Typical Performance inputs (ac coupling is optional). If the clock buffer is greater Characteristics section.) than two inches from the ADC, a standard LVPECL MAY REQUIRE termination may be required instead of the simple pull-down RC FILTER termination shown in Figure 37. EXTERNAL REFERENCE OR VREF DAC INPUT AD9481 0.1µF CLK+ AVDD PECL SENSE GATE CLK– 0.1µF Figure 35. External Reference 510kΩ 510kΩ Programmable Reference The programmable reference can be used to set a differential Figure 37. Clocking the AD9481 input span anywhere between 0.75 V p-p and 1.5 V p-p by using an external resistor divider. The SENSE pin self-biases to 0.5 V, DS INPUTS and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is The data sync inputs (DS+, DS−) can be used in applications recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit which require that a given sample appear at a specific output VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2 port (A or B) relative to a given external timing signal. equal to 3.5 kΩ). The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on VREF separate ADCs (in effect, synchronizing multiple DCO outputs). 10µF 0.1µF R1 The DS inputs are internally biased to 1.5 V (nominal) and SENSE support either differential or single-ended signals. When DS+ is R2 held high (DS− low), the ADC data outputs and DCO outputs do not switch and are held static. Synchronization is Figure 36. Programmable Reference accomplished by the assertion (falling edge) of DS+ within the CLOCKING THE AD9481 timing constraints t and t , relative to a clock rising edge. SDS HDS (On initial synchronization, t is not relevant.) If DS+ falls HDS Any high speed ADC is extremely sensitive to the quality of the within the required setup time (t ) before a given clock rising SDS sampling clock provided by the user. A track-and-hold circuit is edge N, the analog value at that point in time is digitized and essentially a mixer, and any noise, distortion, or timing jitter on available at Port A, eight cycles later in interleaved mode. The the clock is combined with the desired signal at the A/D output. next sample, N + 1, is sampled by the next rising clock edge and Considerable care has been taken in the design of the CLOCK available at Port B, eight cycles after that clock edge. input of the AD9481, and the user is advised to give commensurate thought to the clock source. Driving each ADC’s DS inputs by the same sync signal accomplishes synchronization between multiple ADCs. In The AD9481 has an internal clock duty cycle stabilization applications which require synchronization, one-shot circuit that locks to the rising edge of CLOCK and optimizes synchronization is recommended. An easy way to accomplish timing internally for sample rates between 100 MSPS and synchronization is by a one-time sync at power-on reset. 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 70 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can Rev. 0 | Page 19 of 28 05045-037 05045--036 05045-028 AD9481 Table 9. S1 Voltage Levels INTERLEAVING TWO AD9481s Duty Cycle Instrumentation applications may prefer to interleave (or ping- S1 Voltage Data Format Stabilizer pong) two AD9481s to achieve twice the sample rate, or (0.9 × AVDD)→ AVDD Offset binary Disabled 500 MSPS. In these applications, it is important to match the (2/3 × AVDD) ± (0.1 × AVDD) Offset binary Enabled gain and offset of the two ADCs. Varying the reference voltage (1/3 × AVDD) ± (0.1 × AVDD) Twos complement Enabled allows the gain of the ADCs to be adjusted; external dc offset AGND → (0.1 × AVDD) Twos complement Disabled compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs DIGITAL OUTPUTS is extremely important as well and requires very low skew between clock signals driving the ADCs (< 2 ps clock skew The CMOS digital outputs are TTL-/CMOS-compatible for for a 100 MHz analog input frequency). lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external DATA CLOCK OUT logic. The outputs are CMOS devices that swing from ground to A data clock is available at DCO+ and DCO−. These clocks can DRVDD (with no dc load). It is recommended to minimize the facilitate latching off-chip, providing a low skew clocking capacitive load the ADC drives by keeping the output traces solution. The on-chip delay of the DCO clocks tracks with the short (< 2 inch, for a total C < 5 pF). When operating in LOAD on-chip delay of the data bits, (under similar loading) such that CMOS mode, it is also recommended to place low value series the variation between t and t is minimized. It is PD CPD damping resistors on the data lines close to the ADC to reduce recommended to keep the trace lengths on the data and DCO switching transient effects on performance. pins matched and 2 inches maximum. A series damping resistor Table 10. Output Coding (FS = 1 V) at the clock outputs is also recommended. The DCO outputs Code (VIN+) − (VIN−) Offset Binary Twos Complement can be disabled and placed in a high impedance state by tying 255 > +0.512 V 1111 1111 0111 1111 S3 to ground (tie to AVDD for DCO active). Switching both 255 +0.512 V 1111 1111 0111 1111 into and out of high impedance is accomplished in 4 ns from S3 254 +0.508 V 1111 1110 0111 1110 switching. • • • • • • • • POWER-DOWN INPUT 129 +0.004 V 1000 0001 0000 0001 The ADC can be placed into a low power state by setting the 128 +0.0 V 1000 0000 0000 0000 PDWN pin to AVDD. Time to go into (or come out of) power 127 −0.004 V 0111 1111 1111 1111 down equals 30 ns typically from PDWN switching. • • • • • • • • 2 −0.504 V 0000 0010 1000 0010 1 −0.508 V 0000 0001 1000 0001 0 −0.512 V 0000 0000 1000 0000 0 < −0.512 V 0000 0000 1000 0000 Rev. 0 | Page 20 of 28 AD9481 AD9481 EVALUATION BOARD The AD9481 evaluation board offers an easy way to test the ANALOG INPUTS device. It requires a clock source, an analog input signal, and a The evaluation board accepts a 700 mV p-p analog input signal 3.3 V power supply. The clock source is buffered on the board to centered at ground at SMB Connector J3. This signal is provide the clocks for the ADC and a data-ready signal. The terminated to ground through 50 Ω by R22. The input can be digital outputs and output clocks are available at an 80-pin alternatively terminated at the T1 transformer secondary by output connector, P3, P23. (Note that P3, P23 are represented R21 and R28. T1 is a wideband RF transformer that provides schematically as two 40-pin connectors, and this connector is the single-ended-to-differential conversion, allowing the ADC implemented as one 80-pin connector on the PCB.) The board to be driven differentially, minimizing even-order harmonics. has several different modes of operation and is shipped in the An optional transformer, T4, can be placed if desired (remove following configuration: T1, as shown in Figure 39 and Figure 40). • Offset binary The analog signal can be low-pass filtered by R21, C8 and R28, C9 at the ADC input. • Internal voltage reference GAIN POWER CONNECTOR Full scale is set by the sense jumper. This jumper applies a bias Power is supplied to the board via two detachable 4-pin power to the SENSE pin to vary the full-scale range; the default strips. position is SENSE = ground, setting the full scale to 1 V p-p. Table 11. Power Connector OPTIONAL OPERATIONAL AMPLIFIER Terminal Comments The PCB has been designed to accommodate an optional VDL (3.3 V) Output supply for external latches and data AD8351 op amp that can serve as a convenient solution for dc- ready clock buffer ~ 30 mA coupled applications. To use the AD8351 op amp, remove R29, 1 AVDD 3.3 V Analog supply for ADC ~ 140 mA R31, and C3. Populate R12, R17, and R36 with 25 Ω resistors, 1 DRVDD 3.3 V Output supply for ADC ~ 30 mA and populate C1, C21, C23, C31, C39, and C30 with 0.1 µF 1 VCTRL 3.3 V Supply for support clock circuitry ~ 60 mA capacitors. Populate R54, R10, and R11 with 10 Ω resistors, and Op amp, ext. ref Optional supply for op amp and ADR510 R34 and R32 with 1 kΩ resistors. Populate R15 with a 1.2 kΩ reference resistor and R14 with a 100 Ω resistor. Populate R37 with a 10 kΩ resistor. 1 AVDD, DRVDD, VDL, and VCTRL are the minimum required power connections. CLOCK The clock input is terminated to ground through 50 Ω at SMA Connector J1. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for best performance. J1 input should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL (default) or AVDD by jumper placement at the device. OPTIONAL CLOCK BUFFER The PCB has been designed to accommodate the SNLVDS1 line driver. The SNLVDS1 is used as a high speed LVDS-level optional encode clock. To use this clock, please remove C2, C5, and C6. Place 0.1 µF capacitors on C34, C35, and C26. Place a 10 Ω resistor on R48, and place a 100 Ω resistor on R6. Place a 0 Ω resistor on both R49 and R53. For best results using the line driver, J1 input should be > 2.5 V p-p. DS The DS inputs are available on the PCB at J2 and J4. If driving DS+ externally, place a 0 Ω resistor at C48 and remove R53. Rev. 0 | Page 21 of 28 AD9481 OPTIONAL XTAL To use either crystal, populate C38 and C40 with 0.1 µF capaci- tors. Populate R48 and R49 with 0 Ω resistors. Place R50, R51, The PCB has been designed to accommodate an optional R59, and R60 with 1 kΩ resistors. Remove C6 and C5. If the crystal oscillator that can serve as a convenient clock source. The footprint can accept both through-hole and surface-mount Vectron VCC6 family crystal is being used, populate R57 with a devices, including Vectron XO-400 and Vectron VCC6 family 10 Ω resistor. If using the XO-400 crystal, place jumper E21 or oscillators. E22 to E23. VOLTAGE REFERENCE The AD9481 has an internal 1 V reference mode. The ADC uses OUT+ the internal 1 V reference as the default when sense is set to VCC ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper on E5 to E3, and by placing a 0 Ω resistor on R55. When using an external programmable reference, (R20, R30) remove the sense jumper. OUT– DATA OUTPUTS GND The ADC outputs are buffered on the PCB by LVT574 latches VCC on the data outputs. The latch outputs have series terminating resistors at the output pins to minimize reflections. Figure 38. XTAL Footprint Rev. 0 | Page 22 of 28 05045-038 AD9481 EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. No. Quantity Reference Designator Device Package Value 1 24 C1 to C6, C10 to C12, C14 to C15, Capacitors 0402 0.1 µF C17 to C19, C22 to C29, C31, C48 to C49 2 1 C13 Capacitor Tantalum (3528) 10 µF 3 5 C32 to C36 Capacitors Tantalum (6032) 10 µF 4 4 J1 to J4 SMA SMA Degrees 5 3 P1, P12 to P13 4-pin power connectors Post Z5.531.3425.0 6 3 P1, P12 to P13 4-pin power connectors Detachable connector 25.602.5453.0 7 2 P3, P23 80-pin connectors Connector TSW-140-08-L-D-RA 8 7 R1, R5, R19, R22, R27, R35, R53 Resistors 0603 50 Ω 9 8 R2 to R4, R6 to R9, R18, R14 Resistors 0603 100 Ω 10 7 R13, R42 to R45, R32, R34 Resistors 0603 1 kΩ 11 2 R16, R52 Resistors 0603 130 Ω 12 2 R23, R24 Resistors 0603 510 Ω 13 2 R25, R26 Resistors 0603 82 Ω 14 2 R29, R31 Resistors 0603 00 Ω 15 2 R33, R37 Resistors 0603 10 kΩ 16 1 R46 Resistor 0603 2 kΩ 17 3 R12, R17, R36 Resistors 0603 25 Ω 18 1 R15 Resistor 0603 1.2 kΩ 19 3 R54, R10 to R11 Resistors 0603 10 Ω 20 2 RP1 to RP2 Resistor Pack 100 Ω Res. Array 742C163100JTR 21 4 U3, U5 to U6, U8 Resistor Pack 100 Ω 100 Ω Res. Array EXB-38V101JV 22 2 U4, U7 74LVT574 SO20 74LVT574WM 23 1 T1 Transformer CD542 ADT1-1WT 24 1 U1 AD8351 MSOP-10 Op Amp 25 1 U2 74VCX86 SO-14 XOR 1 26 1 U10 ADR510 SOT-23 Voltage Regulator 1 27 1 U9 VCC6PECL6 VCC6-QAB-250M000 Vectron Crystal 28 1 U12 AD9481 TQFP-44 ADC 29 1 U11 MC100-LVEL16D S08NB Clock Buffer 1 30 1 T2 ETC1-1-13 1-1 TX M/A-COM/ETC 1-1-13 1 31 11 C1, C7 to C9, C16, C20, C30, C31, C38 to C40 Capacitors 0402 X 1 32 18 R20 to R21, R28, R30, R38 to R41, Resistors 0603 X R48 to R51, R55 to R60 33 16 E98 to E102, E73 to E84 Jumpers 1 Not placed. Rev. 0 | Page 23 of 28 AD9481 PCB SCHEMATICS 1 P1 2 P2 3 P3 GND 4 P4 VAMP 1 P1 GND 2 P2 VDL 3 P3 GND 4 P4 DRVDD 1 P1 GND 2 P2 AVDD 3 P3 GND 4 P4 VCTRL Figure 39. PCB Schematic (1 of 2) Rev. 0 | Page 24 of 28 P13 P12 P1 U4 100Ω 74LVT574 OUTPUT RP1 GND CONNECTOR 1 20 GND OUT_EN VCC VDL 100Ω P40 P39 2 GND 19 1 16 RPAK_4 40 39 D0 Q0 DB7X P38 P37 DR+ 1 8 3 18 2 15 38 37 E25 DB7 P36 P35 GND D1 Q1 DB6X 2 7 36 35 DB6 3 6 4 17 3 14 P34 P33 DB7X GND DB5 D2 Q2 DB5X 4 5 34 33 P32 P31 DB6X DB4 5 DB7 16 4 13 32 31 D3 Q3 DB4X P30 P29 DB5X 6 15 5 12 30 29 DB6 R20 P28 P27 DB4X D4 Q4 DB3X E13 E14 U8 28 27 XX 7 14 6 11 AVDD DB5 1 8 P26 P25 DB3X DB3 D5 Q5 DB2X 26 25 E15 E16 2 7 P24 P23 DB2X U10 DB4 DB2 8 GND 3 13 7 10 6 24 23 D6 Q6 DB1X R33 DB1 ADR510 E2 E1 4 5 P22 P21 DB1X 33 32 31 30 29 28 27 26 25 24 23 R30 9 12 8 9 22 21 E5 E3 10kΩ DB0 P20 P19 DB0X 1 D7 Q7 DB0X XX 20 19 VAMP V+ 10 11 3 P18 P17 RPAK_4 GND GND CLOCK TRIM/NC 18 17 U3 P16 P15 2 16 15 V– VDL P14 P13 14 13 P12 P11 GND GND 34 22 12 11 VREF D3B DB3 P10 P9 R40 35 21 10 9 + DB2 C14 R55 C13 C12 GND AGND D2B P8 P7 X CLKLAT+ 36 20 8 7 R1 0.1µF X 10µF 0.1µF AVDD AVDD D1B DB1 E19 C20 P6 P5 37 19 50Ω R2 6 5 DB0 GND AGND D0B X P4 P3 38 18 100Ω 4 3 GND GND GND VIN– DRVDD DRVDD R41 J4 P2 P1 39 U12 17 COUT+ X 2 1 DS– VIN+ DCO+ C49 40 AD9481 16 AGND DCO– GND P23 0.1µF E27 41 15 COUT– AVDD AVDD DRGND GND GND 42 GND 14 R3 S3 D0A DA0 S3 C16 43 13 100Ω DS– D1A DA1 E18 X J2 44 NOTE: TWO 40 PIN OUTPUT CONNECTOR 12 DS+ D2A DA2 DS+ IMPLEMENTED AS ONE 80 PIN CONNECTOR C48 AMPOUT AMPOUT GND 0.1µF R35 R53 E26 E28 E29 U7 100Ω GND 50Ω 50Ω 74LVT574 RP2 OUTPUT C8 C9 GND CONNECTOR X X 1 20 1 2 3 4 5 6 7 8 9 10 11 OUT_EN VCC GND VDL GND GND 100Ω GND GND P40 P39 GND 2 19 1 16 RPAK_4 40 39 D0 Q0 DA0X P38 P37 DA3 DR– J3 3 18 38 37 1 8 2 15 R31 DA0 D1 Q1 DA1X P36 P35 GND DA4 2 7 ANALOG PRI SEC E30 DA1 36 35 0Ω T1– 3 6 4 17 3 14 P34 P33 DA7X 3 4 DA5 INPUT DA2 D2 Q2 DA2X 34 33 4 5 5 2 DA3 P32 P31 DA6X GND DA6 5 16 4 13 CM CM 32 31 D3 Q3 DA3X 1 6 R28 P30 P29 DA5X DA7 C10 6 15 30 29 5 12 X D4 Q4 DA4X P28 P27 DA4X R22 T1-1T 0.1µF U6 28 27 C3 7 14 6 11 P26 P25 DA3X 50Ω T1 CM 1 8 DA4 D5 Q5 DA5X 26 25 2 7 0.1µF GND TIN1 DA5 P24 P23 DA2X 8 13 7 10 3 6 GND 24 23 D6 Q6 DA6X DA6 P22 P21 4 5 DA1X R21 9 22 21 DA7 12 8 9 R29 D7 Q7 DA7X P20 P19 DA0X X 20 19 T1+ 0Ω 10 11 P18 P17 GND RPAK_4 GND CLOCK 18 17 AMPIN U5 P16 P15 16 15 VDL P14 P13 14 13 VCTRL OP AMP CONFIGURATION P12 P11 C11 12 11 REMOVE C3 P10 P9 R38 E9 R16 9 0.1µF REMOVE R29 AND R31 10 AVDD E10 X P8 P7 CLKLAT– 130Ω 8 7 GND P6 P5 5 6 VCTRL P4 P3 VCTRL C6 E6 4 3 E11 1 8 R39 P2 P1 0.1µF J1 1 Q X 2 R VCC CLK+ 2 7 CLK CLK Q P3 E8 R25 R52 100LVEL16 GND C2 3 6 82Ω 130Ω CLKN Q CLK– 0.1µF R27 GND VBB VEE R26 Q– 50Ω C5 4 5 R23 R24 82Ω U11 GND 0.1µF GND 510Ω 510Ω OPTIONAL TRANSFORMER GND T2 ETC1-1-13 6 1 TIN1 T1+ C4 PADS FOR SHORTING EL16, 0.1µF USED IF BYPASSING EL16 5 2 VCTRL E72 CM CM GND P14 P15 VDL E7 4 3 CLK Q GND T1– DRVDD E12 P16 P17 PRI SEC AVDD E4 CLKN Q– AVDD E70 X = NOT NORMALLY POPULATED XX = NOT POPULATED, USER SELECTED DRVDD E71 CLK+ SENSE CLK– AGND GND AVDD AVDD AVDD AVDD GND AGND AVDD AVDD DRVDD DRVDD PWDN PWDN GND DRGND S1 S1 D7A DRGND GND D6A D7B D5A D6B D4A D5B D3A D4B 05045-040 AD9481 Figure 40. PCB Schematic (2 of 2) Rev. 0 | Page 25 of 28 U2 R54 VDL 74VCX86 X + C32 C26 C27 C28 C29 VAMP VAMPF R18 10µF 0.1µF 0.1µF 0.1µF 0.1µF 1 1A + C36 C1 R9 E56 COUT+ 3 100Ω 1Y VDL 10µF X 100Ω CLKLAT+ GND E54 2 1B E55 GND AVDD GND R19 4 2A R8 E53 COUT+ 50Ω 2Y 6 VDL + C33 C25 C18 C24 C17 100Ω DR+ E51 5 2B 10µF 0.1µF 0.1µF 0.1µF 0.1µF E52 GND R4 9 3A GND R6 E50 100Ω COUT– 3Y 8 VDL 100Ω 10 3B CLKAT– E45 DRVDD E46 R5 GND 12 + 4A C34 C19 C22 R7 E49 50Ω COUT– 4Y 11 10µF 0.1µF 0.1µF VDL 100Ω 13 DR– E48 4B 14 GND E47 VDL GND PWR 7 VCTRL VDL GND R58 GND + C35 C15 X VCTRL 10µF 0.1µF GND E35 E36 E20 E21 VCTRL VCTRL PWDN R42 1kΩ S3 R45 E32 E39 X R44 R43 E90 AVDD S1 1kΩ 1kΩ R46 E33 E38 X E88 R13 1kΩ E89 OPTIONAL XTALS GND E34 E37 GND GND GND C31 U13 C40 X XO-400 X E24 GND VAMPF AVDD E22 14 8 VCC OUT R32 R34 7 1 X X VCTRL R37 VEE –OUT U1 E23 VAMPF GND X AD8351 PWUP 1 C39 VCTRL GND VOCM GND 10 R17 X C21 RGP1 2 X GND VPOS 9 X AMPOUT VAMPF VCC 6 PECL6 R59 R60 INHI 3 8 OPHI AMPIN R48 C38 X X 1 6 R56 C7 X R10 X NC VC 2 5 INLO OPLO X X 4 7 X R36 VCTRL CLK– E/D OUTPUTB 3 4 X R57 CLK+ GND OUTPUT AMPOUT X R11 RPG2 R49 C23 5 R12 6 COMM C30 X GND GND X X R50 R51 X X XX XX R14 R15 X = NOT NORMALLY POPULATED GND X X XX = NOT POPULATED, USER SELECTED VCTRL GND 05045-041 AD9481 PCB LAYERS August 3, 2004 Figure 41. PCB Top-Side Silkscreen Figure 43. PCB Ground Layer Figure 42. PCB Top-Side Copper Routing Figure 44. PCB Split Power Plane Rev. 0 | Page 26 of 28 05045-043 05045-042 05045-045 05045-044 AD9481 Figure 45. PCB Bottom-Side Copper Routing Figure 46. PCB Bottom-Side Silkscreen Rev. 0 | Page 27 of 28 05045-046 05045-047 AD9481 OUTLINE DIMENSIONS 1.20 MAX 12.00 SQ 0.75 44 34 0.60 1 33 0.45 PIN 1 TOP VIEW 10.00 (PINS DOWN) SQ 0° MIN 1.05 0.20 VIEW A 1.00 0.09 11 23 0.95 7° 12 22 3.5° 0.15 0° SEATING 0.05 0.08 MAX 0.80 0.45 PLANE COPLANARITY BSC 0.37 VIEW A 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026ACB Figure 47. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44)—Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9481BSUZ-250 –40°C to +85°C 44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44 2 AD9481-PCB Evaluation Board 1 Z = Pb-free part. 2 Evaluation board shipped with AD9481BSUZ-250 installed. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05045–0–10/04(0) Rev. 0 | Page 28 of 28