ANALOG DEVICES AD9480

8-Bit, 250 MSPS 3.3 V A/D Converter AD9480 FUNCTIONAL BLOCK DIAGRAM FEATURES VREF SENSE AGND DrGND DRVDD AVDD DNL = ± 0.25 LSB INL = ± 0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) REFERENCE AD9480 Power dissipation of 590 mW at 250 MSPS 1 V p-p analog input range VIN+ 8-BIT T&H 8 Internal 1.0 V reference ADC 16 VIN– LVDS D7–D0 PIPELINE (LVDS) Single-ended or differential analog inputs CORE LVDS outputs (ANSI 644 levels) Power-down mode CLK+ CLOCK DCO+ Clock duty-cycle stabilizer MGMT CLK– DCO- (LVDS) LOGIC APPLICATIONS Digital oscilloscopes PDWN S1 LVDSBIAS Instrumentation and measurement Communications Figure 1. Point-to-point radios Predistortion loops GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9480 is an 8-bit, monolithic analog-to-digital converter 1. Superior linearity. A DNL of ±0.25 makes the AD9480 (ADC) optimized for high speed and low power consumption. suitable for instrumentation and measurement Small in size and easy to use, the product operates at a applications. 250 MSPS conversion rate, with excellent linearity and dynamic 2. Power-down mode. A power-down function may be performance over its full operating range. exercised to bring total consumption down to 15 mW. To minimize system cost and power dissipation, the AD9480 3. LVDS outputs (ANSI-644). LVDS outputs simplify timing includes an internal reference and track-and-hold circuit. The and improve noise performance user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are LVDS (ANSI 644) compatible with an option of twos complement or binary output format. The output data bits are provided in parallel fashion along with an LVDS output clock, which simplifies data capture. Fabricated on an advanced BiCMOS process, the AD9480 is available in a 44-lead surface-mount package (TQFP) specified over the industrial temperature range −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 04619-001 AD9480 TABLE OF CONTENTS DC Specifications ............................................................................. 3 Interleaving Two AD9480s........................................................ 18 Digital Specifications........................................................................ 4 Data Clock Out........................................................................... 18 AC Specifications.............................................................................. 5 Power-Down ............................................................................... 18 Switching Specifications .................................................................. 6 AD9480 Evaluation Board ............................................................ 19 Timing Diagram ........................................................................... 6 Power Connector........................................................................ 19 Absolute Maximum Ratings............................................................ 7 Analog Inputs ............................................................................. 19 Explanation of Test Levels........................................................... 7 Gain.............................................................................................. 19 ESD Caution.................................................................................. 7 Optional Operational Amplifier .............................................. 19 Pin Configuration and Function Descriptions............................. 8 Clock ............................................................................................ 19 Terminology ...................................................................................... 9 Optional Clock Buffer ............................................................... 19 Typical Performance Characteristics ........................................... 11 Optional XTAL ........................................................................... 19 Equivalent Circuits ......................................................................... 15 Voltage Reference ....................................................................... 20 Application Notes ........................................................................... 16 Data Outputs............................................................................... 20 Clocking the AD9480 ................................................................ 16 Evaluation Board Bill of Materials (BOM) ................................. 21 Analog Inputs.............................................................................. 16 PCB Schematics .............................................................................. 22 Voltage Reference ....................................................................... 17 PCB Layers ...................................................................................... 24 Digital Outputs ........................................................................... 18 Outline Dimensions ....................................................................... 26 Output Coding............................................................................ 18 Ordering Guide .......................................................................... 26 REVISION HISTORY 4/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Features.......................................................................... 1 Changes to Table 3............................................................................ 5 Changes to Table 7............................................................................ 8 Changes to Analog Inputs ............................................................. 16 Changes to Figure 30...................................................................... 16 Added Power Down Section ......................................................... 18 Changes to Table 12........................................................................ 21 7/04—Revision 0: Initial Version Rev. A | Page 2 of 28 AD9480 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 1. AD9480-250 Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error 25°C I −40 +40 mV 1 Gain Error 25°C I −6.0 +6.0 % FS Differential Nonlinearity (DNL) AD9480BSUZ-250 Full VI −0.5 ±0.28 +0.5 LSB AD9480ASUZ-250 Full VI −0.85 ±0.35 +0.85 LSB Integral Nonlinearity (INL) Full VI −0.9 ±0.26 +0.9 LSB TEMPERATURE DRIFT Offset Error Full V 30 µV/°C Gain Error Full V 0.03 %FS/°C Reference Full V ±0.025 mV/°C REFERENCE Internal Reference Voltage Full VI 0.97 1.0 1.03 V 2 Output Current 25°C IV 1.5 mA 3 IVREF Input Current 25°C I 100 µA 2 ISENSE Input Current 25°C I 10 µA ANALOG INPUTS (VIN+, VIN−) 4 Differential Input Voltage Range (FS = 1) Full V 1 V p-p Common-Mode Voltage Full VI 1.7 1.9 2.1 V Input Resistance 25°C I 8.6 10 10.7 kΩ Full VI 8.4 10 11.2 kΩ Input Capacitance 25°C V 4 pF Analog Bandwidth, Full Power 25°C V 750 MHz POWER SUPPLY AVDD Full IV 3.0 3.3 3.6 V DRVDD Full IV 3.0 3.3 3.6 V 5 Power Dissipation 25°C V 590 mW Power-Down Dissipation 25°C V 15 mW 5 I Full VI 145 156 mA AVDD 5 I Full VI 34 38 mA DRVDD Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input). 2 Internal reference mode; SENSE = AGND. 3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Power dissipation and current measured with rated encode and a dc analog input (outputs static). See Figure 13 for active operation. Rev. A | Page 3 of 28 AD9480 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 2. AD9480-250 Parameter Temp Test Level Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Differential Input Full IV 200 mV p-p 1 Common-Mode Voltage Full VI 1.4 1.5 1.68 V Input Resistance Full VI 4.2 5.5 6.0 kΩ Input Capacitance 25°C V 4 pF 2 LOGIC INPUTS (PDWN, S1) PDWN Logic 1 Voltage Full IV 2.0 V PDWN Logic 0 Voltage Full IV 0.8 V PDWN Logic 1 Input Current Full VI ±160 µA PDWN Logic 0 input Current Full VI 10 µA PDWN, S1 Input Resistance 25°C V 30 kΩ PDWN, S1 Input Capacitance 25°C V 4 pF DIGITAL OUTPUTS 3 Differential Output Voltage (VOD) Full VI 247 454 mV Output Offset Voltage (VOS) Full VI 1.125 1.375 V Output Coding Full IV Twos complement or binary 1 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V. 2 S1 is a multilevel logic input, see Table 8. 3 LVDSBIAS resistor = 3.74 kΩ. Rev. A | Page 4 of 28 AD9480 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, AIN = –1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 3. AD9480-250 Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 19.7 MHz 25°C V 47 dB f = 70.1 MHz 25°C I 45 47 dB IN f = 170 MHz 25°C I 45 46 dB IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 19.7 MHz 25°C V 46.5 dB IN f = 70.1 MHz 25°C I 44.8 46.5 dB IN f = 170 MHz 25°C I 44.8 46.5 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 19.7 MHz 25°C V 7.6 Bits IN fIN = 70.1 MHz 25°C I 7.3 7.6 Bits fIN = 170 MHz 25°C I 7.3 7.6 Bits WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz 25°C V −65 dBc fIN = 70.1 MHz 25°C I −65 −60 dBc fIN = 170 MHz 25°C I −65 −60 dBc WORST OTHER fIN = 19.7 MHz 25°C V −70 dBc fIN = 70.1 MHz 25°C I −70 −63 dBc f = 170 MHz 25°C I −70 −63 dBc IN 1 SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 19.7 MHz 25°C V −65 dBc f = 70.1 MHz 25°C I −65 −60 dBc IN f = 170 MHz 25°C I −65 −60 dBc IN TWO-TONE INTERMODULATION DISTORTION (IMD) f = 69.3 MHz, f = 70.3 MHz 25°C V −68 dBc IN1 IN2 1 Nyquist bin energy ignored. Rev. A | Page 5 of 28 AD9480 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted. Table 4. AD9480-250 Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full VI 20 MSPS Clock Pulse Width High (tEH) Full IV 1.2 2 ns Clock Pulse Width Low (tEL) Full IV 1.2 2 ns OUTPUT PARAMETERS 1 Valid Time (tV) Full VI 1.9 ns Propagation Delay (tPD) Full VI 2.8 3.8 ns Rise Time (tR) 20% to 80% Full V 0.5 ns Fall Time (t ) 20% to 80% Full V 0.5 ns F DCO Propagation Delay (t) Full VI 1.9 2.7 3.7 ns CPD Data-to-DCO Skew (tPD − tCPD) Full IV 0 0.1 0.6 ns Pipeline Latency 25°C VI 8 Cycles APERTURE Aperture Delay (tA) 25°C V 1.5 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms 1 Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum. TIMING DIAGRAM N–1 t N+10 A N+11 N N+9 AIN N+1 N+8 8 CYCLES t t 1/f EH EL S CLK+ CLK– t t PD V DATA N–8 N–7 N N+1 N+2 OUT t CPD DCO+ DCO– Figure 2. Timing Diagram Rev. A | Page 6 of 28 04619-002 AD9480 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB). Table 5. Parameter Min Rating Max Rating Stresses above those listed under Absolute Maximum Ratings ELECTRICAL may cause permanent damage to the device. This is a stress AVDD −0.5 V +4.0 V rating only; functional operation of the device at these or any (With Respect to AGND) other conditions above those indicated in the operational DRVDD −0.5 V +4.0 V section of this specification is not implied. Exposure to absolute (With Respect to DRGND) maximum rating conditions for extended periods may affect AGND −0.5 V +0.5 V device reliability. (With Respect to DRGND) Digital I/O −0.5 V DRVDD + 0.5 V (With Respect to DRGND) Analog Inputs −0.5 V AVDD + 0.5 V (With Respect to AGND) ENVIRONMENTAL Operating Temperature −40°C 85°C Junction Temperature 150°C Case Temperature 150°C Storage Temperature 150°C EXPLANATION OF TEST LEVELS Table 6. Level Descriptions I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 28 AD9480 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 1 33 CLK+ SENSE PIN 1 2 32 CLK– AGND 3 31 AVDD AVDD 4 30 AGND AGND AD9480 5 29 DRVDD PDWN TOP VIEW (Not to Scale) 6 28 DRGND S1 7 27 D0_C (LSB) DRGND 8 26 D0_T (LSB) D7_T (MSB) 9 25 D1_C D7_C (MSB) 10 24 D6_T D1_T 11 23 D2_C D6_C 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description 1 CLK+ Input Clock—True 23 D6_C Data Output Bit 6—Complement 2 CLK− Input Clock—Complement 24 D6_T Data Output Bit 6—True 3 AVDD 3.3 V Analog Supply 25 D7_C Data Output Bit 7—Complement (MSB) 4 AGND Analog Ground 26 D7_T Data Output Bit 7—True (MSB) 5 DRVDD 3.3 V Digital Output Supply 27 DRGND Digital Ground 6 DRGND Digital Ground 28 S1 Data Format Select and Duty-Cycle Stabilizer Selection (See Table 8) 7 D0_C Data Output Bit 0—Complement (LSB) 29 PDWN Power-Down Selection (AVDD = Power Down) 8 D0_T Data Output Bit 0—True (LSB) 30 AGND Analog Ground 9 D1_C Data Output Bit 1—Complement 31 AVDD 3.3 V Analog Supply 10 D1_T Data Output Bit 1—True 32 AGND Analog Ground 11 D2_C Data Output Bit 2—Complement 33 SENSE Reference Mode Selection (See Table 9) 12 D2_T Data Output Bit 2—True 34 VREF Voltage Reference Input/Output 13 D3_C Data Output Bit 3—Complement 35 AGND Analog Ground 14 D3_T Data Output Bit 3—True 36 AVDD 3.3 V Analog Supply 15 DRGND Digital Ground 37 AGND Analog Ground 16 DCO− Data Clock Output—Complement 38 VIN− Analog Input—Complement 17 DCO+ Data Clock Output—True 39 VIN+ Analog Input—True 18 DRVDD 3.3 V Digital Output Supply 40 AGND Analog Ground 19 D4_C Data Output Bit 4—Complement 41 AVDD 3.3 V Analog Supply 20 D4_T Data Output Bit 4—True 42 LVDSBIAS LVDS Output Current Adjust 1 21 D5_C Data Output Bit 5—Complement 43 NC No Connect (Leave Floating) 22 D5_T Data Output Bit 5—True 44 AGND Analog Ground 1 Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects. Rev. A | Page 8 of 28 D2_T AGND D3_C NC D3_T LVDSBIAS DRGND AVDD DCO– AGND DCO+ VIN+ DRVDD VIN– D4_C AGND D4_T AVDD D5_C AGND D5_T VREF 04619-003 AD9480 TERMINOLOGY Analog Bandwidth Full-Scale Input Power The analog input frequency at which the spectral power of the Expressed in dBm. Computed by fundamental frequency (as determined by the FFT analysis) is 2 ⎛ ⎞ V rms FULLSCALE reduced by 3 dB. ⎜ ⎟ ⎜ Z ⎟ INPUT Power = 10 log Aperture Delay ⎜ ⎟ FULLSCALE 0.001 ⎜ ⎟ The delay between the 50% point of the rising edge of the ⎜ ⎟ ⎝ ⎠ encode command and the instant the analog input is sampled. Gain Error Aperture Uncertainty (Jitter) The difference between the measured and ideal full-scale input The sample-to-sample variation in aperture delay. voltage range of the ADC. Clock Pulse Width/Duty Cycle Harmonic Distortion, Second Pulse width high is the minimum amount of time that the The ratio of the rms signal amplitude to the rms value of the clock pulse should be left in a Logic 1 state to achieve rated second harmonic component, reported in dBc. performance; pulse width low is the minimum time that the clock pulse should be left in a low state. See the timing Harmonic Distortion, Third implications of changing t in the Clocking the AD9480 EH The ratio of the rms signal amplitude to the rms value of the section. At a given clock rate, these specifications define an third harmonic component, reported in dBc. acceptable clock duty cycle. Integral Nonlinearity Crosstalk The deviation of the transfer function from a reference line Coupling onto one channel being driven by a low level measured in fractions of 1 LSB using a best straight line (−40 dBFS) signal when the adjacent interfering channel determined by a least square curve fit. is driven by a full-scale signal. Minimum Conversion Rate Differential Analog Input Resistance, Differential Analog The encode rate at which the SNR of the lowest analog Input Capacitance, and Differential Analog Input Impedance signal frequency drops by no more than 3 dB below the The real and complex impedances measured at each analog guaranteed limit. input port. The resistance is measured statically, and the capacitance and differential input impedances are measured Maximum Conversion Rate with a network analyzer. The encode rate at which parametric testing is performed. Differential Analog Input Voltage Range Output Propagation Delay The peak-to-peak differential voltage that must be applied to The delay between a differential crossing of CLK+ and the converter to generate a full-scale response. Peak differential CLK− and the time when all output data bits are within voltage is computed by observing the voltage on a single pin valid logic levels. and subtracting the voltage from the other pin, which is 180° Noise (For Any Range Within the ADC) out of phase. Peak-to-peak differential is computed by rotating This value includes both thermal and quantization noise. the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak FS − SNR − Signal ⎛ ⎞ dBm dBc dBFS measurements. V = Z× .001×10⎜ ⎟ noise ⎜ ⎟ 10 ⎝ ⎠ Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. where: Z is the input impedance. Effective Number of Bits FS is the full scale of the device for the frequency in question. The effective number of bits (ENOB) is calculated by the SNR is the value for the particular input level. measured SINAD based on (assuming full-scale input) Signal is the signal level within the ADC reported in dB below full scale. SINAD − 1.76 dB MEASURED ENOB= 6.02 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Rev. A | Page 9 of 28 AD9480 Signal-to-Noise and Distortion (SINAD) Two-Tone SFDR The ratio of the rms signal amplitude (set 1 dB below full scale) The ratio of the rms value of either input tone to the rms value to the rms value of the sum of all other spectral components, of the peak spurious component. The peak spurious component including harmonics, but excluding dc. may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that Signal-to-Noise Ratio (Without Harmonics) is, always relates back to converter full scale). The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral Worst Other Spur components, excluding the first five harmonics and dc. The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third Spurious-Free Dynamic Range (SFDR) harmonic), reported in dBc. The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious Transient Response Time component may or may not be a harmonic. It also may be The time it takes for the ADC to reacquire the analog input reported in dBc (that is, degrades as signal level is lowered) or after a transient from 10% above negative full scale to 10% dBFS (that is, always related back to converter full scale). below positive full scale. Two-Tone Intermodulation Distortion Rejection Out-of-Range Recovery Time The ratio of the rms value of either input tone to the rms value The time it takes for the ADC to reacquire the analog input of the worst third-order intermodulation product in dBc. after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Rev. A | Page 10 of 28 AD9480 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, unless otherwise noted. 0 0 SNR = 46.2dB SNR = 45.9dB H2 = 72.8dBc H2 = 71.9dBc –10 –10 H3 = 73.2dBc H3 = 67dBc SFDR = 69.8dBc SFDR = 67dBc –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 06 20 400 80 100 120 06 20 400 80 100 120 MHz MHz Figure 4. FFT: fS = 250 MSPS, AIN = 10.3 MHz @ −1 dBFS Figure 7. FFT: fS = 250 MSPS, AIN = 170 MHz @ −1 dBFS 0 90 SNR = 46.1dB 85 H2 = 71.4dBc –10 H3 H3 = 74.3dBc 80 SFDR = 68.7dBc –20 75 –30 70 –40 H2 SFDR 65 –50 60 –60 55 –70 50 SNR –80 45 SINAD –90 40 06 20 400 80 100 120 0 50 100 150 200 250 300 350 400 MHz A (MHz) IN Figure 5. FFT: fS = 250 MSPS, AIN = 70 MHz @ –1 dBFS Figure 8. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 1 V, fS = 250 MSPS 0 80 SNR = 45.9dB H3 H2 = 67dBc –10 75 H3 = 73.3dBc H2 SFDR = 67dBc –20 70 –30 65 SFDR –40 60 –50 55 –60 50 –70 SNR 45 –80 SINAD –90 40 06 20 400 80 100 120 0 50 100 150 200 250 300 350 400 MHz A (MHz) IN Figure 6. FFT: fS = 250 MSPS, AIN = 70 MHz @ –1 dBFS, Single-Ended Input Figure 9. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 0.75 V, fS = 250 MSPS Rev. A | Page 11 of 28 dB dB dB 04619-022 04619-021 04619-020 dB dB dB 04619-025 04619-024 04619-023 AD9480 75 180 160 70 140 65 120 SFDR I AVDD 60 100 80 55 60 50 I DRVDD 40 SNR 45 SINAD 20 40 0 0 50 100 150 200 250 300 0 50 100 150 200 250 300 SAMPLE CLOCK (MHz) ENCODE (MSPS) Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ −1 dBFS Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF AIN = 70 MHz @ –1 dBFS 80 50 49 70 SFDRdBFS 48 DCS ON 60 47 50 46 40 45 44 DCS OFF 30 43 20 42 SFDRdBc 10 41 65dB REF LINE 0 40 –70 –60 –50 –40 –30 –20 –10 0 20 30 40 50 60 70 80 ANALOG INPUT DRIVE LEVEL (dBFS) CLOCK POSITIVE DUTY CYCLE (%) Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS Figure 14. SNR, SINAD vs. Clock Pulse Width High, AIN = 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off 0 50.0 80 F1, F2 = –7dBFS SNR 2F2-F1 = –71.1dBc –10 2F1-F2 = –68dBc –20 47.5 75 SINAD –30 –40 70 45.0 –50 SFDR –60 42.5 65 –70 –80 40.0 50 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 –90 EXTERNAL VREF VOLTAGE (V) 06 20 400 80 100 120 MHz Figure 12. Two-Tone Intermodulation Distortion Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, (69.3 MHz and 70.3 MHz; fS = 250 MSPS) AIN = 70 MHz @ –1 dBFS, 250 MSPS Rev. A | Page 12 of 28 dB dB dB 04619-028 04619-027 04619-026 SNR, SINAD dB dB CURRENT IN mA SFDR dB 04619-031 046190-030 04619-029 AD9480 3 70 FS = 1V EXT REF 2 SFDR 65 1 60 FS = 1V INT REF 0 55 –1 SNR 50 –2 SINAD –3 45 –40 –20 0 20 40 60 80 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (°C) AVDD (V) Figure 16. Full-Scale Gain Error vs. Temperature, Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS, FS = 1 AIN = 70.3 MHz @ −1 dBFS, 250 MSPS 75 0.5 SFDR 1V INT REF 0.4 70 0.3 65 0.2 0.1 60 0 55 –0.1 –0.2 50 SINAD 1V INT REF –0.3 45 –0.4 40 –0.5 –40 –2004 2006080 0 50 100 150 200 250 TEMPERATURE (°C) CODE Figure 17. SINAD, SFDR vs. Temperature, AIN = 70 MHz @ −1 dBFS, 250 MSPS Figure 20. Typical DNL Plot, AIN = 10.3 MHz @ –0.5 dBFS, 250 MSPS 0.10 0.50 0.05 0.25 0 0 –0.05 –0.25 –0.10 –0.15 –0.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250 AVDD (V) CODE Figure 18. VREF Sensitivity to AVDD Figure 21. Typical INL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS Rev. A | Page 13 of 28 CHANGE IN VREF (%) dB GAIN ERROR (%) 04619-034 04619-033 04619-032 LSB LSB dB 04619-037 04619-036 04619-035 AD9480 0.30 900 1.4 800 1.3 0.25 V OS 700 1.2 0.20 600 1.1 0.15 500 1.0 0.10 400 0.9 V OD 300 0.8 0.05 200 0.7 0 100 0.6 –0.05 0 0.5 02 4 6 8 10 12 14 –0.10 –40 –2004 2006080 RSET (kΩ) TEMPERATURE (°C) Figure 23. LVDS Output Swing, Common-Mode Voltage vs. RSET, Figure 22. Propagation Delay Adder vs. Temperature Placed at LVDSBIAS Rev. A | Page 14 of 28 DELAY SENSITIVITY (nS) 04619-038 VDIF (mV) V (V) 04619-039 OS AD9480 EQUIVALENT CIRCUITS AVDD AVDD 16.7kΩ 16.7kΩ 150Ω 150Ω VIN+ VIN– PDWN 1.2pF 1.2pF 25kΩ 25kΩ 30kΩ Figure 24. Analog Inputs Figure 27. Power-Down Input AVDD DRVDD DRVDD 12kΩ 12kΩ K 1.2V CLK+ CLK– 150Ω 150Ω ILVDS OUT LVDSBIAS 10kΩ 10kΩ 3.7kΩ Figure 28. LVDSBIAS Input Figure 25. Clock Inputs VDD DRVDD 30kΩ V+ V– S1 DX– DX+ V– V+ Figure 26. S1 Input Figure 29. LVDS Data, DCO Outputs Rev. A | Page 15 of 28 04619-006 04619-005 04619-004 04619-009 04619-007 04619-008 AD9480 APPLICATION NOTES The AD9480 uses a 1.5-bit per stage architecture. The analog ANALOG INPUTS inputs drive an integrated high bandwidth track-and-hold The analog input to the AD9480 is a differential buffer. For best circuit that samples the signal prior to quantization by the 8-bit dynamic performance, impedances at VIN+ and VIN− should core. For ease of use, the part includes an on-board reference match. Optimal performance is obtained when the analog and input logic that accepts TTL, CMOS, or LVPECL levels. inputs are driven differentially. SNR and SINAD performance The digital output logic levels are LVDS (ANSI 644 compatible). can degrade if the analog input is driven with a single-ended signal; however, performance can be adequate for some CLOCKING THE AD9480 applications (see Figure 6). The analog inputs self-bias to Any high speed ADC is extremely sensitive to the quality of the approximately 1.9 V; this common-mode voltage can be sampling clock provided by the user. A track-and-hold circuit is externally overdriven by approximately ±300 mV if required. essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. A wideband transformer, such as the Mini-Circuits® ADT1-1WT, Considerable care has been taken in the design of the CLOCK can provide the differential analog inputs for applications that input of the AD9480, and the user is advised to give require a single-ended-to-differential conversion. Note that the commensurate thought to the clock source. filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at The AD9480 has an internal clock duty-cycle stabilization the secondary side helps reduce any wideband noise aliased circuit that locks to the rising edge of CLOCK and optimizes by the ADC. timing internally for sample rates between 100 MSPS and (R, C OPTIONAL) 250 MSPS. This allows for a wide range of input duty cycles at AVDD 33Ω the input without degrading performance. Jitter on the rising VIN+ edge of the input is still of paramount concern and is not 49.9Ω 10pF AD9480 reduced by the internal stabilization circuit. The duty-cycle 33Ω VIN– control loop does not function for clock rates less than 70 MHz AGND nominally. The loop is associated with a time constant that 0.1µF needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of 5 µs after a Figure 31. Driving the ADC with an RF Transformer dynamic clock frequency increase before valid data is available. The clock duty-cycle stabilizer can be disabled at Pin 28 (S1). For dc-coupled applications, the AD8138/AD8139 or AD8351 can serve as a convenient ADC driver, depending on The clock inputs are internally biased to 1.5 V (nominal) and requirements. Figure 32 shows an example with the AD8138. support either differential or single-ended signals. For best The AD9480 PCB has an optional AD8351 on board, as shown dynamic performance, a differential signal is recommended. An in Figure 41 and Figure 42. The AD8351 typically yields better MC100LVEL16 performs well in the circuit to drive the clock performance for frequencies greater than 30 MHz to 40 MHz. inputs (ac coupling is optional). If the clock buffer is greater than 2 inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination, 49.9Ω 499Ω as shown in Figure 30. AVDD 33Ω 499Ω VIN+ AD9480 0.1µF 20pF AD9480 AD8138 1.3kΩ CLK+ 33Ω VIN– PECL 523Ω GATE 2kΩ AGND 0.1µF 499Ω CLK– 0.1µF 510Ω 510Ω Figure 32. Driving the ADC with the AD8138 Figure 30. Clocking the AD9480 Table 8. S1 Voltage Levels S1 Voltage Data Format Duty-Cycle Stabilizer 0.9 × AVDD −> AVDD Offset binary Disabled 2/3 AVDD ± (0.1 × AVDD) Offset binary Enabled 1/3 AVDD ± (0.1 × AVDD) Twos complement Enabled AGND −> (0.1 × AVDD) Twos complement Disabled Rev. A | Page 16 of 28 04619-010 04619-011 04619-012 AD9480 The AD9480 can be easily configured for different full-scale Fixed Reference ranges. See the Voltage Reference section for more information. The internal reference can be configured for a differential span Optimal performance is achieved with a 1 V p-p analog input. of 1 V p-p (see Figure 37). It is recommended to place a 0.1 µF capacitor as close as possible to the VREF pin; a 10 µF capacitor SENSE = GND is also required (see the PCB layout for guidance). If the internal reference of the AD9480 is used to drive multiple converters to improve gain matching, the loading of the VIN+ reference by the other converters must be considered. Figure 37 depicts how the internal reference voltage is affected by loading. 500mV 2.0V 2.0V 1.0085 1.0080 VIN– 1.0075 DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s 1.0070 1.0065 Figure 33. Analog Input Full Scale 1.0060 1.0055 VOLTAGE REFERENCE 1.0050 A stable and accurate 1.0 V reference is built into the AD9480. Users can choose this internal reference or provide an external 1.0045 reference for greater accuracy and flexibility. Figure 35 shows 1.0040 the typical reference variation with temperature. Table 9 1.0035 summarizes the available reference configurations. –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 35. Typical Reference Variation with Temperature VIN+ VIN– VREF 10µF 0.1µF ADC CORE SENSE Figure 36. Internal Fixed Reference (1 V p-p) VREF 0 + 10µF 0.1µF 7kΩ –0.1 SELECT LOGIC SENSE –0.2 –0.3 0.5V 7kΩ –0.4 Figure 34. Internal Reference Equivalent Circuit –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 IREF (mA) Figure 37. Internal VREF vs. Load Current Table 9. Reference Configurations SENSE Voltage Resulting VREF Reference Differential Span AVDD N/A (External Reference Input) External 1 × External Reference Voltage 0.5 V (Self-Biased) 0.5 × (1 + R1/R2) V Programmable 1 × VREF (0.75 V p-p to 1.5 V p-p) AGND to 0.2 V 1.0 V Internal Fixed 1 V p-p Rev. A | Page 17 of 28 04619-014 04619-013 % CHANGE IN VREF VOLTAGE VREF (V) 04619-016 04619-017 04619-049 AD9480 External Reference trace length 3 inches to 4 inches maximum and the differential output trace lengths as equal as possible. An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9480 OUTPUT CODING can also be varied using this configuration. A voltage output Table 10. DAC can be used to set VREF, providing for a means to digitally Code (VIN+) − (VIN−) Offset Binary Twos Complement adjust the full-scale voltage. VREF can be externally set to 255 >+0.512 V 1111 1111 0111 1111 voltages from 0.75 V to 1.5 V; optimum performance is typically 255 +0.512 V 1111 1111 0111 1111 obtained at VREF = 1 V. (See the Typical Performance 254 +0.508 V 1111 1110 0111 1110 Characteristics section.) • • • • MAY REQUIRE • • • • RC FILTER 129 +0.004 V 1000 0001 0000 0001 EXTERNAL 128 +0.0 V 1000 0000 0000 0000 REFERENCE OR VREF DAC INPUT 127 –0.004 V 0111 1111 1111 1111 • • • • AVDD • • • • SENSE 2 −0.504 V 0000 0010 1000 0010 1 −0.508 V 0000 0001 1000 0001 0 −0.512 V 0000 0000 1000 0000 Figure 38. External Reference 0 <−0.512 V 0000 0000 1000 0000 Programmable Reference The programmable reference can be used to set a differential input span anywhere between 0.75 V p-p and 1.5 V p-p by INTERLEAVING TWO AD9480s using an external resistor divider. The sense pin will self-bias to Instrumentation applications may prefer to interleave or ping- 0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is pong two AD9480s to achieve twice the sample rate, or recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit 500 MSPS. In these applications, it is important to match the VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2 gain and offset of the two ADCs. Varying the reference voltage equal to 3.5 kΩ). allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is VREF extremely important as well and requires very low skew 10µF 0.1µF R1 between clock signals driving the ADCs (<2 ps clock skew for a 100 MHz analog input frequency). SENSE DATA CLOCK OUT R2 An LVDS data clock is available at DCO+ and DCO−. These clocks can facilitate latching off-chip, providing a low skew Figure 39. Programmable Reference clocking solution. The on-chip delay of the DCO clocks tracks DIGITAL OUTPUTS with the on-chip delay of the data bits (under similar loading), LVDS outputs are available when a 3.7 kΩ RSET resistor is such that the variation between TPD and TCPD is minimized. It is placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor recommended to keep the trace lengths on the data and DCO current (~1.2 V/RSET) is ratioed on-chip, setting the output pins matched and to 3 inches to 4 inches maximum. The output current at each output equal to a nominal 3.5 mA with an RSET and DCO outputs should be designed for a differential of 3.74 kΩ. Varying the RSET current also linearly changes the characteristic impedance of 100 Ω and terminated differentially LVDS output current, resulting in a variable output swing for a at the receiver with 100 Ω. fixed termination resistance. POWER-DOWN A 100 Ω differential termination resistor placed at the LVDS The chip can be placed in a low power state by driving the receiver inputs results in a nominal 350 mV swing at the PDWN pin to logic high. Typical power-down dissipation is receiver. LVDS mode facilitates interfacing with LVDS receivers 15 mW. The data outputs and DCO outputs are high impedance in custom ASICs and FPGAs that have LVDS capability for in power-down state. The time it takes to go into power-down superior switching performance in noisy environments. Single from assertion of PDWN is one cycle; recovery from power- point-to-point net topologies are recommended with a 100 Ω down is accomplished in three cycles. termination resistor as close to the receiver as possible. Keep the Rev. A | Page 18 of 28 04619-019 04619-018 AD9480 AD9480 EVALUATION BOARD with a 1.2 kΩ resistor and R42 with a 100 Ω resistor. Populate The AD9480 evaluation board offers an easy way to test the R52 with a 10 kΩ resistor. device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board CLOCK to provide the clocks for the ADC and a data-ready signal. The The clock input is terminated to ground through 50 Ω at SMA digital outputs and output clocks are available at a 40-pin Connector J1. The input is ac-coupled to a high speed connector, P10. The board has several modes of operation and differential receiver (LVEL16) that provides the required low is shipped in the following configuration: jitter and fast edge rates needed for best performance. J1 input • Offset binary should be >0.5 V p-p. Power to the LVEL16 is set to VCTRL • Internal voltage reference (default) or AVDD by jumper placement at the device. POWER CONNECTOR OPTIONAL CLOCK BUFFER Power is supplied to the board via two detachable 4-pin The PCB has been designed to accommodate the SNLVDS1 power strips. line driver. The SNLVDS1 is used as a high speed LVDS-level Table 11. Power Connector optional encode clock. To use this clock, remove C2, C5, and Terminal Comments C6. Place a 0.1 µF capacitor on C34, C35, and C26. Place a 10 Ω 1 AVDD 3.3 V Analog supply for ADC ~ 150 mA resistor on R48, a 100 Ω resistor on R6, and a 0 Ω resistor on 1 DRVDD 3.3 V Output supply for ADC ~ 40 mA R49 and R53. For best results using the LVDS line driver, J1 1, 2 VCTRL 3.3 V Supply for support clock circuitry ~ 50 mA input should be >2.5 V p-p. Op Amp, Optional supply for op amp and OPTIONAL XTAL External Reference ADR510 reference 1 The PCB has been designed to accommodate an optional AVDD, DRVDD, and VCTRL are the minimum required power connections. 2 LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer crystal oscillator that can serve as a convenient clock source. jumper. The footprint can accept both through-hole and surface-mount ANALOG INPUTS devices, including Vectron XO-400 and Vectron VCC6 family oscillators. The evaluation board accepts a 700 mV p-p analog input signal centered at ground at SMB Connector J3. This signal is terminated to ground through 50 Ω by R22. The input can be alternatively terminated at the T1 transformer secondary by R21 and R28. T1 is a wideband RF transformer that provides OUT+ VCC the single-ended-to-differential conversion, allows the ADC to be driven differentially, and minimizes even-order harmonics. An optional transformer, T4, can be placed, if desired (remove T1, as shown in Figure 41 and Figure 42). The analog signal can be low-pass filtered by R31, C8, and OUT– R29, C9 at the ADC input. GAIN GND Full scale is set by the sense jumper. This jumper applies a bias VCC to the SENSE pin to vary the full-scale range; the default position is SENSE = ground, setting the full scale to 1 V p-p. Figure 40. XTAL Footprint OPTIONAL OPERATIONAL AMPLIFIER To use either crystal, populate C26 and C27 with 0.1 µF capaci- The PCB has been designed to accommodate an optional tors. Populate R49 and R53 with 0 Ω resistors. Place 1 kΩ AD8351 op amp, which can serve as a convenient solution for resistors on R54, R55, R56, and R57 and remove C6 and C5. dc-coupled applications. To use the AD8351 op amp, remove If the Vectron VCC6 family crystal is being used, populate R29, R31, and C3. Populate R40, R43, and R47 with 25 Ω R48 with a 10 Ω resistor. If using the XO-400 crystal, place resistors, and populate C24, C28, C29, C30, C31, and C32 with Jumper E21 or Jumper E22 to Jumper E23. 0.1 µF capacitors. Populate R38, R39, and R51 with a 10 Ω resistor, and R44 and R45 with a 1 kΩ resistor. Populate R41 Rev. A | Page 19 of 28 04619-040 AD9480 VOLTAGE REFERENCE DATA OUTPUTS The AD9480 has an internal 1 V reference mode. The ADC The off-chip drivers provide LVDS-compatible output levels uses the internal 1 V reference as the default when SENSE is set with an LVDS RSET resistor of 3.74 kΩ. to ground. An optional on-board external 1.0 V reference The ADC digital outputs can be terminated on the board by (ADR510) can be used by setting the SENSE jumper to AVDD, 100 Ω resistors at the connector if receiving logic does not have by placing a jumper on E20 to E3, and by placing a 0 Ω resistor the required termination resistance. (The on-chip LVDS output on R36. When using an external programmable reference drivers require a far-end, 100 Ω differential termination.) (R20, R30), the SENSE jumper must be removed. Rev. A | Page 20 of 28 AD9480 EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. No. Quantity Reference Designator Device Package Value 1 23 C1 to C6, C10 to C12, Capacitors 0402 0.1 µF C17 to C23, C26 to C28, C31 to C33, C35 2 1 C13 Capacitor Tantalum (3528) 10 µF 3 4 C7, C14 to C16 Capacitors Tantalum (6032) 10 µF 4 2 J1, J3 SMAs 5 2 P12, P13 4-pin power connector posts Z5.531.3425.0 Wieland 6 2 P12, P13 4-pin power detachable connectors 25.602.5453.0 Wieland 7 2 R22, R27 Resistors 0603 50 Ω 8 10 R2 to R5, R7 to R10, R15, R42 Resistors 0603 100 Ω (All not placed) 9 6 R1, R44, R45, R50, R58, R59 Resistors 0603 1000 Ω 10 1 R41 Resistors 0603 1200 Ω 11 3 R40, R43, R47 Resistors 0603 25 Ω 12 3 R38, R39, R51 Resistors 0603 10 Ω 13 2 R25, R26 Resistors 0603 82 Ω 14 2 R23, R24 Resistors 0603 510 Ω 15 2 R32, R34 Resistors 0603 130 Ω 16 2 R29, R31 Resistors 0603 0 Ω 17 2 R33, R52 Resistors 0603 10 kΩ 18 1 R63 Resistor 0603 3.74 kΩ 19 1 T1 Transformer CD542 Mini-Circuits T1-1WT 20 1 U13 AD8351 MSOP-10 21 1 U2 SN65LVDS1 SN65LVDS1 DBV Not placed 22 1 U14 ADR510 SOT-23 Not placed 23 1 U15 VCC6PECL6 VCC6-QAB-250M000 Not placed 24 1 U1 XO-400 Dip4(14) Not placed 25 1 U12 AD9480 TQFP-44 26 1 U11 MC100LVEL16D S08NB 27 1 T2 ETC1-1-13 1-1 TX Not placed 28 7 C8, C9, C24, C25, C29, C30, Capacitors 0402 Not placed and C34 (All not placed) 29 12 R6, R20, R21, R28, R30, R36, Resistors 0603 User-determined R46, R48, R49, and R55 to R57 (All not placed) 30 18 E5 to E8, E17, Jumpers E35, E73 to E84 31 1 P10 Output Data Connector 40-pin right angle Digi-Key S2131-20-ND Rev. A | Page 21 of 28 AD9480 PCB SCHEMATICS 1 P1 GND 2 P2 VAMP 3 P3 GND 4 DRVDD P4 1 GND P1 2 AVDD P2 3 GND P3 4 P4 VCTRL Figure 41. PCB Schematic (1 of 2) Rev. A | Page 22 of 28 POWER CONN. P13 P12 PTMICRO4 PTMICRO4 1 3 V+ TRIM/NC EXTVREF 2 V– R33 GND 10kΩ ADR510 FOR ON BOARD EXT. REF VAMP GND U14 E20 E3 JUMPER E13 TO 14 AND E20 TO E3 E14 E13 PLACE R36 0Ω AND R33 10kΩ R36 R20 VCTRL D7T X E16 XX E15 R2 GND 100Ω R30 C1 D7C E2 E1 XX 0.1µF D6T GND + C13 C12 R3 10µF 0.1µF 100Ω D6C 33 32 31 30 29 28 27 26 25 24 23 GND GND D5T R4 100Ω D5C 34 22 VREF D5T D4T 35 21 GND AGND D5C R5 36 20 D4T AVDD AVDD 100Ω 37 19 OUTPUT DATA CONN. E17 GND AGND D4C D4C 18 R36 38 VIN– DRVDD DRVDD 1kΩ 17 39 DR+ GND P40 P39 GND VIN+ DCO+ 40 39 OPTIONAL 16 40 AD9480 R15 DR+ P38 P37 DR– DCO– VCTRL E7 GND AGND 38 37 R63 15 100Ω 41 P36 P35 GND GND 3.7kΩ AVDD AVDD DRGND GND 36 35 DR– 42 14 P34 P33 D7C D7T GND LVDSBIAS D3T 34 33 OPTIONAL 43 13 P32 P31 D6C D6T NC D3C TRANSFORMER D3T 32 31 12 44 D5C P30 P29 D5T GND AGND R7 D2T 30 29 6 1 AMPOUT AMPOUT TIN1 T1+ D4C P28 P27 100Ω D4T 28 27 C8 C9 D3C D3C P26 P25 D3T 5 2 26 25 CM CM X X P24 P23 D2C D2T D2T 4 3 24 23 GND GND P22 P21 GND T1– D1C D1T R10 21 22 U12 P20 P19 D0C D0T 100Ω R31 19 20 12 345 6 7 891011 P18 P17 D2C 00 T1– 18 17 GND P16 P15 6 1 16 15 D1T C10 R28 P14 P13 E8 CM 14 13 0.1µF R9 R22 5 2 X P12 P11 100Ω 12 11 50 FOR OP AMP CONFIGURATION CM P10 P9 4 3 J3 D1C R21 GND 9 REMOVE RESISTORS R29, R31, AND C3 10 P8 P7 ANALOG X T1+ 8 7 D0T INPUT C10 P6 P5 AMPIN 6 5 R29 R8 0.1µF P4 P3 00 100Ω 4 3 GND GND P2 P1 GND D0C 2 1 C40MS C11 P10 VCTRL PROBE POINTS E9 0.1µF AVDD E10 GND E77 GND R34 GND E78 VCTRL 82Ω VCTRL C6 CLK+ CLK– 1 8 E79 E11 GND 0.1µF PADS FOR SHORTING EL16, E17 J1 CLKINPUT R VCC GND E81 2 7 CLK Q CLK GND E80 P14 P15 100LVEL16 R26 R32 R6 GND E82 C11 CLK D+ 3 6 E17 130Ω 82Ω X CLKN Q 0.1µF GND E83 P16 P17 GND VBB VEE GND E84 R25 CLKN D– C5 4 5 R27 R23 R24 130Ω U11 GND 0.1µF 50Ω 510Ω 510Ω C33 P6 GND GND 0.1µF AVDD E4 E35 GND C4 AVDD E70 0.1µF GND E12 04619-041 GND P7 VCTRL E32 CLK+ SENSE CLK– AGND GND AVDD AVDD AVDD AVDD GND AGND AGND GND PWDN DRVDD DRVDD PWDN S1 GND DRGND S1 D0C DRGND GND D0T D7T D1C D7C D1T D6T D2C D6C AD9480 Figure 42. PCB Schematic (2 of 2) Rev. A | Page 23 of 28 E25 U2 E24 VCTRL PWDN 1 5 AVDD VCC D 2 GND GND C34 4 3 CLKINPUT Z Y X SN65LVDS1 VCTRL OPTIONAL OUT+ E28 OUT+ E26 P4 P3 VAMP R38 VIVIS VAMPF AVDD R59 X E34 E36 + + 1kΩ C16 C32 C7 C17 C18 C19 C20 C35 10µF 0.1µF 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R58 S1 1kΩ E29 E27 GND GND R50 1kΩ E31 E30 GND DRVDD VCTRL + + X= NOT NORMALLY POPULATED C14 C21 C22 C15 C23 XX = USER SELECTED, IS NOT NORMALLY POPULATED 10µF 0.1µF 0.1µF 10µF 0.1µF GND GND OPTIONAL OPTIONAL XTALS C28 0.1µF U1 GND VAMPF XO-400 E22 AVDD 14 8 VAMPF GND VCC OUT E23 R44 R45 1 7 VCTRL R52 VEE –OUT X X E21 C27 U13 X AD8351 X GND PWUP 1 C24 10 VOCM X C30 RGP1 2 VPOS 9 X AMPOUT VAMPF GND INHI 3 OPHI 8 AMPIN GND R46 C25 VCTRL GND R39 INLO 4 7 OPLO X X X R56X C23 R55 AMPOUT VCC 6 PECL6 OUT– R49 R51 X X C31 RPG2 5 1 6 COMM 6 C29 X X GND X R40 2 5 X VCTRL CLK– X 3 4 R48 CLK+ X OUT+ R53 R54 R57 X GND GND R42 R41 X X X X VCTRL GND 04619-042 AD9480 PCB LAYERS Figure 45. PCB Ground Layer Figure 43. PCB Top-Side Silkscreen Figure 46. PCB Split Power Plane Figure 44. PCB Top-Side Copper Routing Rev. A | Page 24 of 28 04619-044 04619-043 04619-046 04619-045 AD9480 Figure 47. PCB Bottom-Side Copper Routing Figure 48. PCB Bottom-Side Silkscreen Rev. A | Page 25 of 28 04619-047 04619-048 AD9480 OUTLINE DIMENSIONS 1.20 MAX 12.00 BSC SQ 34 0.75 44 0.60 1 33 0.45 PIN 1 TOP VIEW 10.00 (PINS DOWN) BSC SQ 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 11 23 3.5° 0.15 12 22 0° SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A 0.80 0.45 BSC 0.37 LEAD PITCH VIEW A 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026ACB Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Description Package Option 1, 2 AD9480BSUZ-250 44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44 −40°C to +85°C 1 AD9480ASUZ-250 44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44 −40°C to +85°C 3 AD9480-LVDS/PCB Evaluation Board 1 Z = Pb-free part. 2 Optimized differential nonlinearity. 3 Evaluation board shipped with AD9480BSUZ-250 installed. Rev. A | Page 26 of 28 AD9480 NOTES Rev. A | Page 27 of 28 AD9480 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04619–0–4/05(A) Rev. A | Page 28 of 28