ANALOG DEVICES AD9467

16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter Data Sheet AD9467 FEATURES FUNCTIONAL BLOCK DIAGRAM AGND AVDD1 AVDD2 AVDD3 SPIVDD DRVDD DRGND 75.5 dBFS SNR to 210 MHz at 250 MSPS CSB 90 dBFS SFDR to 300 MHz at 250 MSPS AD9467 SDIO SFDR at 170 MHz at 250 MSPS BUFFER SCLK 92 dBFS at −1 dBFS VIN+ 16 PIPELINE 2 OR+/OR– ADC 100 dBFS at −2 dBFS VIN– LVDS OUTPUT D15+/D15– 16 60 fs rms jitter STAGING TO D0+/D0– Excellent linearity at 250 MSPS CLK+ CLOCK 2 DNL = ±0.5 LSB typical AND TIMING DCO+/DCO– CLK– MANAGEMENT REF INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential XVREF full-scale input (programmable) Figure 1. Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. APPLICATIONS The internal power-down feature supported via the SPI typically Multicarrier, multimode cellular receivers consumes less than 5 mW when disabled. Antenna array positioning Power amplifier linearization Optional features allow users to implement various selectable Broadband wireless operating conditions, including input range, data format select, Radar and output data test patterns. Infrared imaging The AD9467 is available in a Pb-free, 72-lead, LFCSP specified Communications instrumentation over the −40°C to +85°C industrial temperature range. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. IF optimization capability used to improve SFDR. The AD9467 is a 16-bit, monolithic, IF sampling analog-to- 2. Outstanding SFDR performance for IF sampling digital converter (ADC). It is optimized for high performance applications such as multicarrier, multimode 3G, and 4G over wide bandwidths and ease of use. The product operates at cellular base station receivers. a 250 MSPS conversion rate and is designed for wireless 3. Ease of use: on-chip reference, high input impedance receivers, instrumentation, and test equipment that require a buffer, adjustable analog input range, and an output clock high dynamic range. to simplify data capture. The ADC requires 1.8 V and 3.3 V power supplies and a low 4. Packaged in a Pb-free, 72-lead LFCSP package. voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of input clock pulse widths. many applications. Data outputs are LVDS compatible (ANSI-644 6. Standard serial port interface (SPI) supports various compatible) and include the means to reduce the overall current product features and functions, such as data formatting needed for short trace distances. (offset binary, twos complement, or Gray coding). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09029-001 AD9467 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Equivalent Circuits......................................................................... 11  Applications....................................................................................... 1  Typical Performance Characteristics ........................................... 12  General Description ......................................................................... 1  Theory of Operation ...................................................................... 19  Functional Block Diagram .............................................................. 1  Analog Input Considerations ................................................... 19  Product Highlights ........................................................................... 1  Clock Input Considerations...................................................... 22  Revision History ............................................................................... 2  Serial Port Interface (SPI).............................................................. 26  Specifications..................................................................................... 3  Hardware Interface..................................................................... 26  AC Specifications.......................................................................... 4  Memory Map .................................................................................. 28  Digital Specifications ................................................................... 6  Reading the Memory Map Table.............................................. 28  Switching Specifications .............................................................. 7  Reserved Locations .................................................................... 28  Absolute Maximum Ratings............................................................ 8  Default Values ............................................................................. 28  Thermal Impedance..................................................................... 8  Logic Levels................................................................................. 28  ESD Caution.................................................................................. 8  Outline Dimensions....................................................................... 32  Pin Configuration and Function Descriptions............................. 9  Ordering Guide .......................................................................... 32  REVISION HISTORY 9/11—Rev. B to Rev. C Changes to Figure 44 and Figure 45............................................. 17 3/11—Rev. A to Rev. B Change Parameter Name to Full Power Bandwidth, Table 1...... 3 Changes to Switching Specifications, Table 4 ............................... 7 Change to VIN+, VIN− Parameter, Table 5.................................. 8 Deleted Figure 43............................................................................ 17 Added New Figure 43..................................................................... 17 2/11—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Figure 24 and Figure 25; Renumbered Sequentially ..... 14 Changes to Differential Configurations Section and Figure 54 .......................................................................................... 21 Added Figure 55 to Figure 57........................................................ 21 Changes to Figure 65 and Figure 66............................................. 24 Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0], and Addr. (Hex) 10, Default Notes Column ............................... 29 Changes to Addr. (Hex) 36, Default Value (Hex) Column and Addr. (Hex) 107, Default Value (Hex) Column.......................... 30 10/10—Revision 0: Initial Version Rev. C | Page 2 of 32 Data Sheet AD9467 SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 1. AD9467BCPZ-200 AD9467BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −150 0 +150 −150 0 +150 LSB Gain Error Full −3.5 −0.2 +2.5 −3.5 −0.1 +2.5 %FSR 2 Differential Nonlinearity (DNL) Full −0.8 ±0.4 +0.7 −0.6 ±0.5 +1.3 LSB 2 Integral Nonlinearity (INL) Full −9.5 ±5 +9.5 −11.8 ±3.5 +9.5 LSB TEMPERATURE DRIFT Offset Error Full ±0.020 ±0.023 %FSR/°C Gain Error Full ±0.011 ±0.036 %FSR/°C ANALOG INPUTS Differential Input Voltage Range (Internal VREF = 1 V to 1.25 V) Full 2 2.5 2.5 2 2.5 2.5 V p-p Common-Mode Voltage 25°C 2.3 2.15 V Differential Input Resistance 25°C 530 530 Ω Differential Input Capacitance 25°C 3.5 3.5 pF Full Power Bandwidth 900 900 MHz 25°C XVREF INPUT Input Voltage Full 1 1.25 1 1.25 V Input Capacitance Full 3 3 pF POWER SUPPLY AVDD1 Full 1.75 1.8 1.85 1.75 1.8 1.85 V AVDD2 Full 3.0 3.3 3.6 3.0 3.3 3.6 V AVDD3 Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V I Full 485 536 580 514 567 618 mA AVDD1 IAVDD2 Full 49 55 61 49 55 61 mA I Full 21 24 27 27 31 35 mA AVDD3 I Full 35 38 41 36 40 43 mA DRVDD Total Power Dissipation (Including Output Drivers) Full 1.14 1.26 1.37 1.2 1.33 1.45 W Power-Down Dissipation Full 4.4 90 4.4 90 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. C | Page 3 of 32 AD9467 Data Sheet AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 2. AD9467BCPZ-200 AD9467BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Unit ANALOG INPUT FULL SCALE 2.5 2/2.5 2.5 2/2.5 V p-p SIGNAL-TO-NOISE RATIO (SNR) f = 5 MHz 25°C 74.6/76.4 74.7/76.4 dBFS IN fIN = 97 MHz 25°C 75.1 74.5/76.2 74.5/76.1 dBFS fIN = 97 MHz Full 73.8 dBFS fIN = 140 MHz 25°C 74.3/76.0 74.4/76.0 dBFS fIN = 170 MHz 25°C 74.2/75.8 74.7 74.3/75.8 dBFS fIN = 170 MHz Full 72.3 dBFS fIN = 210 MHz 25°C 73.9/75.5 74.0/75.5 dBFS fIN = 300 MHz 25°C 73.5/74.7 73.3/74.6 dBFS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f = 5 MHz 25°C 74.6/76.3 74.6/76.3 dBFS IN f = 97 MHz 25°C 74.7 74.5/76.2 74.4/76.0 dBFS IN f = 97 MHz Full 73.1 dBFS IN f = 140 MHz 25°C 74.3/75.9 74.4/76.0 dBFS IN fIN = 170 MHz 25°C 74.1/75.6 74.4 74.2/75.8 dBFS fIN = 170 MHz Full 71.8 dBFS fIN = 210 MHz 25°C 73.9/75.3 73.9/75.4 dBFS fIN = 300 MHz 25°C 73.3/74.3 73.1/74.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) f = 5 MHz 25°C 12.1/12.4 12.1/12.4 Bits IN f = 97 MHz 25°C 12.1/12.4 12.1/12.3 Bits IN f = 97 MHz Full Bits IN f = 140 MHz 25°C 12.1/12.3 12.1/12.3 Bits IN f = 170 MHz 25°C 12.0/12.3 12.0/12.3 Bits IN fIN = 170 MHz Full Bits fIN = 210 MHz 25°C 12.0/12.2 12.0/12.2 Bits fIN = 300 MHz 25°C 11.9/12.0 11.9/12.1 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING 2 SECOND AND THIRD HARMONIC DISTORTION) f = 5 MHz 25°C 95/95 98/97 dBFS IN f = 97 MHz 25°C 86 95/95 95/93 dBFS IN f = 97 MHz Full 83 dBFS IN f = 140 MHz 25°C 94/93 94/95 dBFS IN f = 170 MHz 25°C 95/90 84 93/92 dBFS IN fIN = 170 MHz Full 84 dBFS fIN = 210 MHz 25°C 93/88 93/92 dBFS fIN = 300 MHz 25°C 92/86 93/90 dBFS SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND 2 AND THIRD HARMONIC DISTORTION) f = 5 MHz @ −2 dB Full Scale Full 100/96 100/100 dBFS IN f = 97 MHz @ −2 dB Full Scale Full 100/98 97/97 dBFS IN f = 140 MHz @ −2 dB Full Scale Full 98/96 100/95 dBFS IN f = 170 MHz @ −2 dB Full Scale Full 96/93 100/100 dBFS IN f = 210 MHz @ −2 dB Full Scale Full 94/93 93/93 dBFS IN fIN = 300 MHz @ −2 dB Full Scale Full 90/89 90/90 dBFS Rev. C | Page 4 of 32 Data Sheet AD9467 AD9467BCPZ-200 AD9467BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Unit WORST OTHER (EXCLUDING SECOND AND THIRD HARMONIC 2 DISTORTION) fIN = 5 MHz 25°C 96/98 98/97 dBFS fIN = 97 MHz 25°C 86 97/97 97/93 dBFS fIN = 97 MHz Full 83 dBFS f = 140 MHz 25°C 97/96 97/95 dBFS IN f = 170 MHz 25°C 98/98 90 97/93 dBFS IN f = 170 MHz Full 87 dBFS IN f = 210 MHz 25°C 96/97 97/95 dBFS IN f = 300 MHz 25°C 95/95 97/95 dBFS IN TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS @ 2.5 V p-p FS fIN1 = 70 MHz, fIN2 = 72 MHz 25°C 95 97 dBFS fIN1 = 170 MHz, fIN2 = 172 MHz 25°C 93 91 dBFS 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 See the SFDR Optimization—Buffer Current Adjustment section for optimum settings. Rev. C | Page 5 of 32 AD9467 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 3. AD9467BCPZ-200 AD9467BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 250 mV p-p Input Common-Mode Voltage Full 0.8 0.8 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 2.5 2.5 pF LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF 3 LOGIC OUTPUT (SDIO) Logic 1 Voltage (I = 800 μA) Full 1.7/3.1 1.7/3.1 V OH Logic 0 Voltage (IOL = 50 μA) Full 0.3 0.3 V DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 545 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply. Rev. C | Page 6 of 32 Data Sheet AD9467 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 4. AD9467BCPZ-200 AD9467BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Unit 2 CLOCK Clock Rate Full 50 200 50 250 MSPS Clock Pulse Width High (t) Full 2.5 2 ns CH Clock Pulse Width Low (t) Full 2.5 2 ns CL 2, 3 OUTPUT PARAMETERS Propagation Delay (t) 25°C 3 3 ns PD Rise Time (t ) (20% to 80%) 25°C 200 200 ps R Fall Time (tF) (20% to 80%) 25°C 200 200 ps DCO Propagation Delay (tCPD) 25°C 3 3 ns DCO to Data Delay (tSKEW) Full −200 +200 −200 +200 ps Wake-Up Time (Power-Down) Full 100 100 ms Pipeline Latency Full 16 16 Clock cycles APERTURE Aperture Delay (t) 25°C 1.2 1.2 ns A Aperture Uncertainty (Jitter) 25°C 60 60 fs rms Out-of-Range Recovery Time 25°C 1 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material. Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN± N + 1 N + 2 t t CH CL 1/fs CLK+ CLK– t CPD DCO+ DCO– t SKEW t PD D14–/D15– (MSB) D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D14+/D15+ (MSB) . . . D0–/D1– (MSB) D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D0+/D1+ (MSB) Figure 2. 16-Bit Output Data Timing Rev. C | Page 7 of 32 09029-002 AD9467 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD1, AVDD3 AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AVDD2, SPIVDD AGND −0.3 V to +3.9 V maximum rating conditions for extended periods may affect DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V device reliability. AVDD2, SPIVDD AVDD1, −2.0 V to +3.9 V THERMAL IMPEDANCE AVDD3 AVDD1, AVDD3 DRVDD −2.0 V to +2.0 V Table 6. AVDD2, SPIVDD DRVDD −2.0 V to +3.9 V 1, 2 1, 3, 4 1, 5 Air Flow Velocity (m/sec) θ θ θ Unit JA JB JC Digital Outputs (Dx+, DRGND −0.3 V to DRVDD + 0.2 V 0.0 15.7°C/W 7.5°C/W 0.5° °C/W Dx−, OR+, OR−, 1.0 13.7°C/W N/A N/A °C/W DCO+, DCO−) CLK+, CLK− AGND −0.3 V to AVDD1 + 0.2 V 2.5 12.3°C/W N/A N/A °C/W VIN+, VIN− AGND −0.3 V to +0.3 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. XVREF AGND −0.3 V to AVDD1 + 0.2 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 SCLK, CSB, SDIO AGND −0.3 V to SPIVDD + 0.2 V Per JEDEC JESD51-8 (still air). 4 N/A = not applicable. Environmental 5 Per MIL-STD 883, Method 1012.1. Operating Temperature −40°C to +85°C Range (Ambient) Maximum Junction 150°C ESD CAUTION Temperature Lead Temperature 300°C (Soldering, 10 sec) Storage Temperature −65°C to +150°C Range (Ambient) Rev. C | Page 8 of 32 Data Sheet AD9467 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD1 1 54 AVDD1 PIN 1 INDICATOR AVDD1 2 53 AVDD1 AVDD1 3 52 AVDD1 AVDD1 4 51 SPIVDD CLK+ 5 50 CSB CLK– 6 49 SCLK AVDD1 7 48 SDIO AD9467 AVDD1 8 47 DNC AVDD1 9 46 AVDD1 TOP VIEW AGND 10 (Not to Scale) 45 AGND AVDD1 11 44 AVDD3 AVDD1 12 43 AGND AVDD1 13 42 AVDD3 AGND 14 41 AGND AVDD1 15 40 OR+ AGND 16 39 OR– DRGND 17 38 DRGND DRVDD 18 37 DRVDD NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND. Figure 3. Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Paddle. The exposed paddle must be connected to AGND. 10, 14, 16, 41, 43, 45 AGND Analog Ground. 1, 2, 3, 4, 7, 8, 9, 11, 12, 13, 15, 46, 52, 53, 54, 55, AVDD1 1.8 V Analog Supply. 56, 58, 59, 60, 61, 62, 63, 70, 71, 72 64, 65, 68, 69 AVDD2 3.3 V Analog Supply. 42, 44 AVDD3 1.8 V Analog Supply. 51 SPIVDD 1.8 V or 3.3 V SPI Supply 17, 38 DRGND Digital Output Driver Ground. 18, 37 DRVDD 1.8 V Digital Output Driver Supply. 67 VIN− Analog Input Complement. 66 VIN+ Analog Input True. 6 CLK− Clock Input Complement. 5 CLK+ Clock Input True. 19 D1−/D0− D1 and D0 (LSB) Digital Output Complement. 20 D1+/D0+ D1 and D0 (LSB) Digital Output True. 21 D3−/D2− D3 and D2 Digital Output Complement. 22 D3+/D2+ D3 and D2 Digital Output True. 23 D5−/D4− D5 and D4 Digital Output Complement. 24 D5+/D4+ D5 and D4 Digital Output True. 25 D7−/D6− D7 and D6 Digital Output Complement. 26 D7+/D6+ D7 and D6 Digital Output True. 29 D9−/D8− D9 and D8 Digital Output Complement. 30 D9+/D8+ D9 and D8 Digital Output True. 31 D11−/D10− D11 and D10 Digital Output Complement. 32 D11+/D10+ D11 and D10 Digital Output True. 33 D13−/D12− D13 and D12 Digital Output Complement. 34 D13+/D12+ D13 and D12 Digital Output True. 35 D15−/D14− D15 (MSB) and D14 Digital Output Complement. Rev. C | Page 9 of 32 D1–/D0– 19 72 AVDD1 D1+/D0+ 20 71 AVDD1 D3–/D2– 21 70 AVDD1 D3+/D2+ 22 69 AVDD2 D5–/D4– 23 68 AVDD2 D5+/D4+ 24 67 VIN– D7–/D6– 25 66 VIN+ D7+/D6+ 26 65 AVDD2 DCO– 27 64 AVDD2 28 DCO+ 63 AVDD1 D9–/D8– 29 62 AVDD1 D9+/D8+ 30 61 AVDD1 D11–/D10– 31 60 AVDD1 D11+/D10+ 32 59 AVDD1 D13–/D12– 33 58 AVDD1 D13+/D12+ 34 57 XVREF D15–/D14– 35 56 AVDD1 D15+/D14+ 36 55 AVDD1 09029-003 AD9467 Data Sheet Pin No. Mnemonic Description 36 D15+/D14+ D15 (MSB) and D14 Digital Output True. 27 DCO− Data Clock Digital Output Complement. 28 DCO+ Data Clock Digital Output True. 39 OR− Out-of-Range Digital Output Complement. 40 OR+ Out-of-Range Digital Output True. 47 DNC Do Not Connect (Leave Pin Floating). 48 SDIO Serial Data Input/Output. 49 SCLK Serial Clock. 50 CSB Chip Select Bar. 57 XVREF External VREF Option. Rev. C | Page 10 of 32 Data Sheet AD9467 EQUIVALENT CIRCUITS AVDD2 VIN+ BUF AVDD2 265Ω 345Ω SCLK, SDIO V CML BUF AND CSB 2.15V/2.30V AVDD2 30kΩ 265Ω VIN– BUF Figure 4. Equivalent Analog Input Circuit Figure 7. Equivalent SCLK, SDIO, and CSB Input Circuit AVDD1 SPIVDD 10kΩ 10kΩ 0.8V 10kΩ 10kΩ CLK+ CLK– SDIO Figure 5. Equivalent Clock Input Circuit Figure 8. Equivalent SDIO Output Circuit DRVDD V V Dx– Dx+ 1kΩ V V XVREF 3pF DRGND Figure 6. Equivalent Digital Output Circuit Figure 9. Equivalent External VREF Input Circuit (When Enabled) Rev. C | Page 11 of 32 09029-007 09029-004 09029-005 09029-011 09029-109 09029-008 AD9467 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted, buffer current optimized for best SFDR performance. 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 76.5dBFS SNR = 75.8dBFS –20 –20 ENOB = 12.4 BITS ENOB = 12.3 BITS SFDR = 95.4dBFS SFDR = 94.1dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 102030 40 50 60 70 80 90 100 0 102030 40 50 60 70 80 90 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Single-Tone FFT with fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 13. Single-Tone FFT with fIN = 170.3 MHz, 2.5 V p-p FS, AD9467-200 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 76.2dBFS SNR = 75.5dBFS –20 –20 ENOB = 12.3 BITS ENOB = 12.1 BITS SFDR = 92.0dBFS SFDR = 90.0dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 102030 40 50 60 70 80 90 100 0 102030 40 50 60 70 80 90 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Single-Tone FFT with f = 97.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 14. Single-Tone FFT with fIN = 210.3 MHz, 2.5 V p-p FS, AD9467-200 IN 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 75.9dBFS SNR = 74.7dBFS –20 ENOB = 12.3 BITS –20 ENOB = 12.0 BITS SFDR = 95.2dBFS SFDR = 86.5dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 102030 40 50 60 70 80 90 100 0 102030 40 50 60 70 80 90 100 FREQUENCY (MHz) FREQUENCY (MHz) = 290.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 12. Single-Tone FFT with f = 140.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 15. Single-Tone FFT with fIN IN Rev. C | Page 12 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09029-112 09029-111 09029-110 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09029-115 09029-114 09029-113 Data Sheet AD9467 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 76.4dBFS SNR = 75.8dBFS –20 –20 ENOB = 12.4 BITS ENOB = 12.2 BITS SFDR = 100.0dBFS SFDR = 94.1dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 020 40 60 80 100 120 020 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Single-Tone FFT with fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 19. Single-Tone FFT with fIN = 170.3 MHz, 2.5 V p-p FS, AD9467-250 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 75.9dBFS SNR = 75.5dBFS –20 –20 ENOB = 12.3 BITS ENOB = 12.1 BITS SFDR = 94.8dBFS SFDR = 90.8dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 020 40 60 80 100 120 020 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Single-Tone FFT with f = 97.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 20. Single-Tone FFT with f = 210.3 MHz, 2.5 V p-p FS, AD9467-250 IN IN 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 76.0dBFS SNR = 74.2dBFS –20 –20 ENOB = 12.2 BITS ENOB = 12.0 BITS SFDR = 91.0dBFS SFDR = 93.6dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 020 40 60 80 100 120 020 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Single-Tone FFT with f = 140.3 MHz, 2.5 V p-p FS, AD9467-250 IN Figure 21. Single-Tone FFT with fIN = 300.3 MHz, 2.5 V p-p FS, AD9467-250 Rev. C | Page 13 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09029-118 09029-117 09029-116 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09029-121 09029-120 09029-119 AD9467 Data Sheet 78 100 110 f = 4.3MHz IN 98 f = 97.3MHz IN 105 77 f = 170.3MHz IN SNR 96 f = 300.3MHz IN 100 76 94 SFDR 95 92 75 90 90 74 88 85 86 73 80 84 72 75 82 70 80 71 160 170 180 190 200 210 220 230 240 250 100 120 140 160 180 200 220 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) Figure 22. SNR/SFDR vs. fSAMPLE, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 25. SFDR vs. f , 2.5 V p-p FS, AD9467-250 SAMPLE 78 110 110 78 105 105 77 77 100 100 76 76 SNR 95 95 75 75 SFDR 90 90 74 74 85 85 SNR = 2.0V p-p FS SNR = 2.5V p-p FS 73 73 SFDR = 2.0V p-p FS 80 80 SFDR = 2.5V p-p FS 72 72 75 75 70 71 71 70 210 215 220 225 230 235 240 245 250 0 50 100 150 200 250 300 SAMPLE RATE (MSPS) ANALOG INPUT FREQUENCY (MHz) Figure 23. SNR/SFDR vs. fSAMPLE, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 26. SNR/SFDR vs. fIN, 2.0/2.5 V p-p FS, AD9467-200 105 78 110 f = 4.3MHz IN f = 97.3MHz IN 105 f = 170.3MHz 77 IN f = 290.3MHz 100 IN 100 76 95 95 75 90 74 90 85 SNR = 2.0V p-p FS SNR = 2.5V p-p FS 73 SFDR = 2.0V p-p FS 80 SFDR = 2.5V p-p FS 85 72 75 80 71 70 100 120 140 160 180 200 220 0 50 100 150 200 250 300 SAMPLE RATE (MSPS) ANALOG INPUT FREQUENCY (MHz) Figure 24. SFDR vs. fSAMPLE, 2.5 V p-p FS, AD9467-200 Figure 27. SNR/SFDR vs. f , 2.0/2.5 V p-p FS, AD9467-250 IN Rev. C | Page 14 of 32 SNR (dBFS) SNR (dBFS) SFDR (dBFS) 09029-224 SFDR (dBFS) SFDR (dBFS) 09029-125 09029-123 SNR (dBFS) SNR (dBFS) SFDR (dBFS) 09029-225 SFDR (dBFS) SFDR (dBFS) 09029-127 09029-126 Data Sheet AD9467 0 0 AIN1 AND AIN2 = –7dBFS AIN1 AND AIN2 = –7dBFS SFDR = 94.6dBFS SFDR = 91.3dBFS –20 –20 IMD2 = 94.6dBFS IMD2 = 96.3dBFS IMD3 = 95.9dBFS IMD3 = 91.3dBFS –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 1020 3040 50 6070 80 90 100 020 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. Two-Tone FFT with fIN1 = 70 MHz and fIN2 = 72 MHz, Figure 31. Two-Tone FFT with f = 170 MHz and f = 172 MHz, IN1 IN2 2.5 V p-p FS, AD9467-200 2.5 V p-p FS, AD9467-250 0 120 AIN1 AND AIN2 = –7dBFS SFDR = 92.7dBFS –20 IMD2 = 98.2dBFS 100 IMD3 = 92.7dBFS –40 80 –60 60 –80 40 SNR FS SFDR FS –100 SFDR dBc SNR dBc 20 –120 –140 0 0 1020 3040 50 6070 80 90 100 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 97.3 MHz, 2.5 V p-p FS, Figure 29. Two-Tone FFT with f = 170 MHz and f = 172 MHz, IN1 IN2 AD9467-200 2.5 V p-p FS, AD9467-200 120 0 AIN1 AND AIN2 = –7dBFS SFDR = 96.7dBFS –20 IMD2 = 103.2dBFS 100 IMD3 = 96.7dBFS –40 80 –60 60 –80 SFDR FS 40 SFDR dBc –100 SNR FS SNR dBc 20 –120 0 –140 0 20 40 60 80 100 120 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 33. SNR/SFDR vs. Analog Input Level, f = 97.3 MHz, 2.5 V p-p FS, Figure 30. Two-Tone FFT with f = 70 MHz and f = 72 MHz, IN IN1 IN2 AD9467-250 2.5 V p-p FS, AD9467-250 Rev. C | Page 15 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09029-130 09029-129 09029-128 AMPLITUDE (dBFS) SNR/SFDR (dB) SNR/SFDR (dB) –65 –65 –55 –55 –45 –45 –35 –35 –25 –25 –23 –23 –21 –21 –19 –19 –17 –17 –15 –15 –13 –13 –11 –11 –9 –9 –7 –7 –5 –5 –3 –3 –1 –1 09029-133 09029-132 09029-131 AD9467 Data Sheet 100 0.8 SFDR 95 0.6 0.4 90 0.2 0 85 –0.2 80 –0.4 SINAD –0.6 75 –0.8 70 TEMPERATURE (°C) CODE Figure 34. SINAD/SFDR vs. Temperature, fIN = 97.3 MHz, Figure 37. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 2.5 V p-p FS, AD9467-200 8 100 SFDR 6 95 4 90 2 0 85 –2 80 –4 SINAD 75 –6 70 –8 TEMPERATURE (°C) CODE Figure 35. SINAD/SFDR vs. Temperature, f = 97.3 MHz, IN Figure 38. INL, f = 4.3 MHz, 2.5 V p-p FS, AD9467-250 IN 2.5 V p-p FS, AD9467-250 3.75 0.8 3.00 0.6 2.25 1.50 0.4 0.75 0.2 0 0 0.75 –0.2 –1.50 –0.4 –2.25 –0.6 –3.00 –0.8 –3.75 CODE CODE Figure 36. INL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 39. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 Rev. C | Page 16 of 32 INL ERROR (LSB) SNR/SFDR (dBFS) SNR/SFDR (dBFS) –40 –40 –35 –35 –30 –30 6000 –25 –25 –20 –20 12000 –15 –15 –10 –10 –5 –5 18000 0 0 5 5 24000 10 10 15 15 30000 20 20 25 25 30 30 36000 35 35 40 40 42000 45 45 50 50 48000 55 55 60 60 65 65 54000 70 70 75 75 60000 80 80 85 85 09029-135 09029-134 09029-136 DNL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 6000 6000 10000 12000 12000 18000 18000 20000 24000 24000 30000 30000 30000 36000 36000 40000 42000 42000 48000 48000 50000 54000 54000 60000 60000 60000 09029-138 09029-139 09029-137 Data Sheet AD9467 100 0 SFDR –1 90 –2 80 SNR –3 –3dB = 2.24GHz 70 –4 60 –5 –6 50 DEFAULT CMV –7 40 –8 30 –9 20 –10 1M 10M 100M 1G 10G 1.51.61.71.81.9 2.02.12.2 2.32.42.5 FREQUENCY (Hz) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 40. SNR/SFDR vs. Analog Input Common-Mode Voltage, Figure 43. Converter AC Bandwidth AD9467-250 AIN = 100 MHz, 2.5 V p-p FS, AD9467-250 100 140,000 SFDR 3.427LSB rms 90 120,000 80 SNR 100,000 70 80,000 60 60,000 50 DEFAULT CMV 40,000 40 20,000 30 20 0 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) CODE Figure 44. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-200 Figure 41. SNR/SFDR vs. Analog Input Common-Mode Voltage, AIN = 100 MHz, 2.5 V p-p FS, AD9467-200 140,000 0 3.385LSB rms 120,000 –10 100,000 –20 80,000 –30 60,000 –40 40,000 –50 20,000 –60 0 –70 0 50 100 150 200 250 300 FREQUENCY (MHz) CODE Figure 42. Common-Mode Rejection Ratio (CMRR), AD9467-250 Figure 45. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-250 Rev. C | Page 17 of 32 CMRR (dB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 09029-141 09029-140 09029-142 AMPLITUDE (dB) NUMBER OF HITS NUMBER OF HITS N – 17 N – 17 N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 N – 5 N – 4 N – 4 N – 3 N – 3 N – 2 N – 2 N – 1 N – 1 N N N + 1 N + 1 N + 2 N + 2 N + 3 N + 3 N + 4 N + 4 N + 5 N + 5 N + 6 N + 6 N + 7 N + 7 N + 8 N + 8 N + 9 N + 9 N + 10 N + 10 N + 11 N + 11 N + 12 N + 12 N + 13 N + 13 N + 14 N + 14 N + 15 N + 15 N + 16 N + 16 N + 17 N + 17 09029-145 09029-144 09029-143 AD9467 Data Sheet 105 –55 –60 100 –65 95 AVDD2 –70 90 AVDD1 –75 4MHz 85 97MHz –80 140MHz 170MHz DRVDD 210MHz 80 –85 290MHz –90 75 0 50 100 150 200 250 300 BUFFER CURRENT PERCENTAGE (%) ANALOG INPUT FREQUENCY (MHz) Figure 46. Power Supply Rejection (PSR), AD9467-250 Figure 48. SFDR Performance vs. Buffer Current Percentage Over Analog Input Frequency, AD9467-250 100 95 90 85 4MHz 97MHz 80 140MHz 170MHz 210MHz 75 290MHz 70 0 50 100 150 200 250 300 BUFFER CURRENT PERCENTAGE (%) Figure 47. SFDR Performance vs. Buffer Current Percentage Over Analog Input Frequency, AD9467-200 Rev. C | Page 18 of 32 SFDR (dBFS) PSRR (dB) 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 09029-146 09029-247 SFDR (dBFS) 09029-248 Data Sheet AD9467 THEORY OF OPERATION For best dynamic performance, the source impedances driving The AD9467 architecture consists of an input-buffered pipe- lined ADC that consists of a 3-bit first stage, a 4-bit second VIN+ and VIN− should be matched such that common-mode stage, followed by four 3-bit stages and a final 3-bit flash. Each settling errors are symmetrical. These errors are reduced by the stage provides sufficient overlap to correct for flash errors in common-mode rejection of the ADC. the preceding stage. Maximum SNR performance is achieved by setting the ADC to The input buffer provides a linear high input impedance (for the largest span in a differential configuration. In the default ease of drive) and reduces the kick-back from the ADC. The case of the AD9467, the largest input span available is 2.5 V p-p. buffer is optimized for high linearity, low noise, and low power. For other input full-scale options, see the Full-Scale and Reference Options section. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined SFDR Optimization—Buffer Current Adjustment architecture permits the first stage to operate with a new input Using Register 36 and Register 107, the buffer currents can be sample while the remaining stages operate with preceding samples. changed as a percentage to optimize the SFDR over various Sampling occurs on the rising edge of the clock. input frequencies and bandwidths of interest. As the input Each stage of the pipeline, excluding the last, consists of a low buffer currents are set, this does change the amount of current resolution flash ADC connected to a switched-capacitor DAC required by AVDD2. However, the current consumption is and an interstage residue amplifier (for example, a multiplying small in comparison to the overall currents required by this digital-to-analog converter (MDAC)). The residue amplifier supply. The current specifications listed in Table 1 incorporate magnifies the difference between the reconstructed DAC output this variation. For a complete list of buffer current settings, see and the flash input for the next stage in the pipeline. One bit of Table 13 for more details. redundancy is used in each stage to facilitate digital correction The following buffer current settings reflect the performance of flash errors. The last stage simply consists of a flash ADC. that can be achieved using the input networks as described in The output staging block aligns the data, corrects errors, and Figure 51 and Figure 52. These curves describe the percentages passes the data to the output buffers. used to obtain data sheet typical specifications for both the 250 MSPS and 200 MSPS parts. For example, when using IFs ANALOG INPUT CONSIDERATIONS from 150 MHz to 250 MHz, 160% is actually the average of the The analog input to the AD9467 is a differential buffer. For best entire buffer current. Therefore, both Register 36 and Register 107 dynamic performance, the source impedances driving VIN+ need to be set to 160%. and VIN− should be matched such that common-mode settling AD9467BCPZ-250 buffer current settings: errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog • DC to 150 MHz at 80% (default setting) inputs be driven differentially. SNR and SINAD performance • 150 MHz to 250 MHz at 160% degrades significantly if the analog input is driven with a single- • 250 MHz and higher at 210% ended signal. 100 In either case, a small resistor in series with each input can help 80% 98 160% reduce the peak transient current injected from the output stage 210% 96 of the driving source. In addition, low Q inductors or ferrite beads 94 can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the 92 maximum bandwidth of the ADC. Such use of low Q inductors 90 or ferrite beads is required when driving the converter front end at 88 high IF frequencies. Either a shunt capacitor or two single-ended 86 capacitors can be placed on the inputs to provide a matching 84 passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 82 Application Note, the AN-827 Application Note, the AN-935 80 0 50 100 150 200 250 300 Application Note, and the Analog Dialogue article “Transformer- ANALOG INPUT FREQUENCY (MHz) Coupled Front-End for Wideband A/D Converters” (Volume 39, Figure 49. Buffer Current Sweeps, 2.5 V p-p, AD9467-250 April 2005) for more information. In general, the precise values depend on the application. Rev. C | Page 19 of 32 SFDR (dBFS) 09029-147 AD9467 Data Sheet AD9467BCPZ-200 buffer current settings: Differential Input Configurations There are several ways to drive the AD9467, either actively or • DC to 150 MHz at 80% (default setting) passively; however, optimum performance is achieved by • 150 MHz to 250 MHz at 100% driving the analog input differentially. • 250 MHz and higher at 160% For applications where SNR and SFDR are key parameters, 100 80% differential transformer coupling is the recommended input 98 100% 160% configuration (see Figure 51 and Figure 52) because the noise 96 performance of most amplifiers is not adequate to achieve the 94 true performance of the AD9467. 92 Regardless of the configuration, the value of the shunt capacitor, 90 C, is dependent on the input frequency and may need to be 88 reduced or removed (see Figure 51, Figure 52, and Figure 53) 86 Using the ADL5562 or ADL5201 differential drivers to drive the AD9467 provides an excellent and flexible gain option to interface 84 to the ADC (see Figure 54 and Figure 56) for both baseband and 82 high IF applications. Using an amplifier also provides better 80 0 50 100 150 200 250 300 isolation from the preceding stages as well as better pass-band ANALOG INPUT FREQUENCY (MHz) flatness. Performance plots of these amplifiers can also be seen Figure 50. Buffer Current Sweeps, 2.5 V p-p, AD9467-200 in Figure 55 and Figure 57. Note that for sample rates less than 150 MSPS and analog inputs When using any dc-coupled amplifier, the user has the option less than 100 MHz, it is recommended to set the buffer current to disconnect the input common-mode voltage buffer from the to 0%. Depending on the input network design and frequency analog inputs. This allows the common-mode output pin of the band of interest, the optimum buffer current settings may be amplifier to set this voltage between the interface of the two slightly different than the input network recommendations shown devices. Otherwise, use an ac coupling capacitor in series on in Figure 53 and Figure 54. each of the analog input as shown in Figure 54 for IF applica- tions that do not require dc coupling. See the Memory Map section for more details. 0.1µF 0.1µF 10nH SMA ADT1-1WT ADT1-1WT 33Ω AIN+ AD9467 33Ω 24Ω INPUT 4.7pF 530Ω 3.5pF 0.1µF 0.1µF Z = 50Ω ADC 33Ω 24Ω 0.1µF INTERNAL INPUT Z AIN– 33Ω 0.1µF 0.1µF Figure 51. Differential Transformer-Coupled Configuration for Baseband Applications up to 150 MHz 0.1µF 0.1µF SMA 10nH 15Ω ADT1-1WT ADT1-1WT AIN+ AD9467 33Ω 20Ω INPUT 1.8pF 530Ω 3.5pF 0.1µF 0.1µF Z = 50Ω ADC 33Ω 20Ω 0.1µF INTERNAL INPUT Z 15Ω AIN– 0.1µF 0.1µF Figure 52. Differential Transformer-Coupled Configuration for IF Applications from 150 MHz to 300 MHz C1 R5 R7 0.1μF 15Ω 15Ω R3 C6 50Ω R1 8.2pF ANALOG 33Ω IN 8 1 AIN+ VCM 2 7 C5 AD9467 3 6 8.2pF C3 0.1μF AIN– R2 45 33Ω R4 R6 50Ω R8 ANAREN 15Ω 15Ω B0205F5050A00 C2 0.1μF Figure 53. Wideband Balun-Coupled Configuration for IF Applications Up Greater Than 100 MHz Rev. C | Page 20 of 32 SFDR (dBFS) 09029-148 09029-151 09029-041 09029-040 Data Sheet AD9467 3.3V 40Ω 0.1µF 0.1µF 220nH 15Ω 20Ω 1:1 RATIO ADL5562 750Ω 5pF AD9467 50Ω AC 15Ω 220nH 20Ω 0.1µF 40Ω 0.1µF Figure 54. Wideband Differential Amplifier Input Configuration Using the ADL5562 0 AIN = –1dBFS SNR = 73.8dBFS –15 SFDR = 91.1dBFS IF = 100MHz f = 250MSPS –30 S –45 –60 –75 –90 * 3 6 2 4 5 –105 –120 –135 015 30 45 60 75 90 105 120 FREQUENCY (MHz) Figure 55. Single-Tone FFT Performance Plot Using the ADL5562 Amplifier, Gain = 6 dB, and the AD9467-250 5V 5V 1µH 1:3 0.1µF 0.1µF 47nH 33Ω RATIO 75Ω 0.1µF 14pF AD5201 AD9467 50Ω 75Ω AC 47nH 33Ω 0.1µF 0.1µF 1µH DIGITAL INTERFACE 5V Figure 56. Wideband Differential VGA Input Configuration Using the ADL5201 0 AIN = –1dBFS SNR = 69.2dBFS –15 SFDR = 88.8dBFS IF = 100MHz f = 250MSPS –30 S –45 –60 –75 3 –90 2 * 4 5 6 –105 –120 –135 015 30 45 60 75 90 105 120 FREQUENCY (MHz) Figure 57. Single-Tone FFT Performance Plot Using the ADL5201 VGA, Gain = 20 dB, and the AD9467-250 Rev. C | Page 21 of 32 AMPLITUDE (dB) AMPLITUDE (dB) 09029-257 09029-255 09029-256 09029-254 AD9467 Data Sheet Clock Duty Cycle Considerations CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a For optimum performance, the AD9467 sample clock inputs variety of internal timing signals. As a result, these ADCs may (CLK+ and CLK−) should be clocked with a differential signal. be sensitive to clock duty cycle. Commonly, a 5% tolerance is This signal is typically ac-coupled to the CLK+ and CLK− pins required on the clock duty cycle to maintain dynamic performance via a transformer or capacitors. These pins are biased internally characteristics. The AD9467 contains a duty cycle stabilizer (DCS) and require no additional biasing. that retimes the nonsampling edge, providing an internal clock Figure 58 shows a preferred method for clocking the AD9467. The signal with a nominal 50% duty cycle. This allows a wide range low jitter clock source is converted from a single-ended signal of clock input duty cycles without affecting the performance of to a differential signal using an RF transformer. The back-to- the AD9467. back Schottky diodes across the secondary transformer limit Any changes to the sampling frequency require several clock clock excursions into the AD9467 to approximately 0.8 V p-p cycles to allow the internal timing to acquire and lock at the differential. This helps prevent the large voltage swings of the new sampling rate. clock from feeding through to other portions of the AD9467, and it preserves the fast rise and fall times of the signal, which Clock Jitter Considerations are critical to low jitter performance. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency ® MINI-CIRCUITS ADT1-1WT, 1:1 Z (fA) due only to aperture jitter (tJ) can be calculated by 0.1µF 0.1µF XFMR CLOCK INPUT CLK+ SNR = 20 × log 10(2 × π × fA × tJ) 100Ω 50Ω ADC 0.1µF In this equation, the rms aperture jitter represents the root mean CLK– square of all jitter sources, including the clock input, analog input SCHOTTKY 0.1µF DIODES: signal, and ADC aperture jitter specifications. IF undersampling HSM2812 applications are particularly sensitive to jitter (see Figure 61). Figure 58. Transformer-Coupled Differential Clock The clock input should be treated as an analog signal in cases Another option is to ac-couple a differential PECL or LVDS where aperture jitter may affect the dynamic range of the AD9467. signal to the sample clock input pins, as shown in Figure 59 and Power supplies for clock drivers should be separated from the Figure 60. The AD9510/AD9511/AD9512/AD9513/AD9514/ ADC output driver supplies to avoid modulating the clock signal AD9515/AD9516/AD9517/AD9520/AD9522/AD9523/AD9524 with digital noise. Low jitter, crystal-controlled oscillators make family of clock drivers offers excellent jitter performance. the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 0.1µF 0.1µF CLOCK INPUT CLK CLK+ Refer to the AN-501 Application Note and the AN-756 100Ω ADC PECL DRIVER Application Note for more in-depth information about jitter 0.1µF 0.1µF CLOCK INPUT CLK– CLK performance as it relates to ADCs. 1 1 240Ω 240Ω 50Ω 50Ω 130 RMS CLOCK JITTER REQUIREMENT 1 120 50Ω RESISTORS ARE OPTIONAL. Figure 59. Differential PECL Sample Clock 110 16 BITS 100 90 0.1µF 0.1µF 14 BITS CLOCK INPUT CLK+ CLK 80 12 BITS 100Ω ADC LVDS DRIVER 70 0.1µF 0.1µF 10 BITS CLOCK INPUT CLK– CLK 60 1 1 50Ω 50Ω 0.125ps 8 BITS 0.25ps 50 0.5ps 1 50Ω RESISTORS ARE OPTIONAL. 1.0ps 40 2.0ps Figure 60. Differential LVDS Sample Clock 30 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) Figure 61. Ideal SNR vs. Input Frequency and Jitter Rev. C | Page 22 of 32 09029-056 09029-058 09029-057 SNR (dB) 09029-061 Data Sheet AD9467 Power Dissipation and Power-Down Mode Power Supplies As shown in Figure 62, the power dissipated by the AD9467 is To achieve the best dynamic performance of the AD9467, it is proportional to its sample rate. The output power dissipation recommended that each power supply pin be decoupled as does not vary much because it is determined primarily by the closely to the package as possible with 0.1 μF, X7R or X5R type DRVDD supply and bias current of the LVDS output drivers. decoupling capacitors. For optimum performance, all supplies 0.6 1.2 should be at typical values or slightly higher to accommodate elevated temperature drifts, which depend on the application. 0.5 1.1 Full-Scale and Reference Options The analog inputs support both an input full scale of 2.5 V p-p 0.4 1.0 (default) and 2.0 V p-p differentially. Choosing one full-scale input range over the other presents some trade-offs to the user. 0.3 0.9 Using an input full scale of 2.5 V p-p yields the best SNR TOTAL POWER I AVDD1 performance. If system trade-offs require improved SFDR I 0.2 AVDD2 0.8 I DRVDD performance, then a 2.0 V p-p input full scale should be used. However, in this mode, SNR degrades by roughly 2 dB. Other 0.7 0.1 input full-scale ranges are available for use between 2.0 V p-p and 2.5 V p-p. See Register 18 in Table 13 and the Memory Map 0.6 0 100 110 120 130 140 150 160 170 180 190 200 210 220 section for details. SAMPLE RATE (MSPS) The use of an external reference may be necessary to enhance Figure 62. Supply Current vs. f for f = 5 MHz, AD9467-200 SAMPLE IN the gain accuracy of the ADC or to improve gain matching 0.6 1.20 when using multiple ADCs. The internal reference can be disabled via the SPI, allowing the 0.5 1.18 use of an external reference. See the Memory Map section for more details. The external reference is loaded by the input of an 0.4 1.16 internal buffer amplifier having 3 pF of capacitance to ground. There is also a 1 kΩ internal resistor in series with the input of 0.3 1.14 that buffer. The external reference must be limited to a nominal TOTAL POWER 1.25 V for an input full-scale swing of 2.5 V p-p. Additional 0.2 1.12 I AVDD1 I AVDD2 capacitance may be necessary to keep this pin quiet depending I DRVDD on the external reference used. 0.1 1.10 When not using the XVREF pin, it can be tied to ground 1.08 0 directly or through a 0.1 μF decoupling capacitor. However, 210 215 220 225 230 235 240 245 250 keep this pin quiet regardless. SAMPLE RATE (MSPS) Figure 63. Supply Current vs. f for f = 5 MHz, AD9467-250 SAMPLE IN Digital Outputs and Timing By asserting the power-down option via the SPI register map The AD9467 differential outputs conform to the ANSI-644 LVDS (0x08[1:0]), the AD9467 is placed into power-down mode. In standard on default power-up. The LVDS driver current is this state, the ADC typically dissipates 5 mW. During power-down, derived on chip and sets the output current at each output equal the LVDS output drivers are placed in a high impedance state. to a nominal 3.0 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 300 mV In power-down mode, low power dissipation is achieved by swing at the receiver. shutting down the internal reference, reference buffer, digital output, and biasing networks. The device requires approx- The AD9467 LVDS outputs facilitate interfacing with LVDS imately 100 ms to restore full operation. receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net See the Memory Map section for more details on using these topologies are recommended with a 100 Ω termination resistor features. placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be no longer than 18 inches and that the differential output traces be kept close together and at equal lengths. An example of the DCO and data with proper trace length and position is shown in Figure 64. Rev. C | Page 23 of 32 CURRENT (mA) CURRENT (mA) POWER (W) POWER (W) 09029-157 09029-158 AD9467 Data Sheet 400 CLOCK 300 200 1 DCO 100 0 2 –100 –200 3 –300 DATA –400 CH1 500mV Ω 5.0ns/DIV A CH2 10.0V –2 –1 0 1 2 CH2 500mV Ω 20.0GS/s IT 25.0pt/pt TIME (ns) CH3 500mV Ω Figure 64. Output Timing Example in LVDS Mode (Default), AD9467-250 50 45 An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram 40 with trace lengths of six inches on standard FR-4 material is shown 35 in Figure 65. It is the responsibility of the user to determine if 30 the waveforms meet the timing budget of the design. 25 400 20 300 15 200 10 100 5 0 0 –40 –20 0 20 40 60 TIME (ps) –100 Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 18-Inch Trace –200 Lengths on Standard FR-4, AD9467-250 –300 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. –400 To change the output data format to twos complement or Gray –2 –1 0 1 2 TIME (ns) code, see the Memory Map section. 14 Table 8. Digital Output Coding (VIN+) − (VIN−), Input Digital Output Offset Binary 12 Code Span = 2.5 V p-p (V) (D15:D0) 65,536 +1.25 1111 1111 1111 1111 10 32,768 0.00 1000 0000 0000 0000 8 32,767 −0.000038 0111 1111 1111 1111 0 −1.25 0000 0000 0000 0000 6 An output clock is provided to assist in capturing data from the AD9467. Data is clocked out of the AD9467 and must be 4 captured on the rising and falling edges of the DCO that supports 2 double data rate (DDR) capturing. See the timing diagram shown in Figure 2 for more information. 0 –20 –10 0 10 20 30 40 When the SPI is used, the DCO phase can be adjusted in 100 ps TIME (ps) increments relative to the data edge. This enables the user to Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 6-Inch Trace refine system timing margins if required. The default DCO+ Lengths on Standard FR-4, AD9467-250 and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. Rev. C | Page 24 of 32 VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) 09029-159 09029-160 VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) 09029-161 Data Sheet AD9467 There are eight digital output test pattern options available that Consult the Memory Map section for information on how to can be initiated through the SPI. This is a useful feature when change these additional digital output timing features through validating receiver capture and timing. Refer to Table 10 for the the SPI. output bit sequencing options available. Some test patterns have Overrange (OR) Output Pins two serial sequential words and can be alternated in various The OR+ and OR− output pins indicate when an applied analog ways, depending on the test pattern chosen. Note that some input is above or below the input full scale of the converter. patterns may not adhere to the data format select option. If the analog input is in an overrange condition, the OR bit goes The PN sequence short pattern produces a pseudorandom bit high, coinciding with output data hitting above or below full- 9 sequence that repeats itself every 2 − 1 or 511 bits. A descrip- scale. The delay between the time the part actually overranges tion of the PN sequence and how it is generated can be found and the OR bit going high is the pipeline latency of the part. in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only SPI Pins: SCLK, SDIO, CSB difference is that the starting value must be a specific value instead of all 1s (see Table 9 for the initial values). For normal SPI operation, these pins should be tied to AGND through a 100 kΩ resistor on each pin. These pins are both The PN sequence long pattern produces a pseudorandom bit 23 1.8 V and 3.3 V tolerant. However, the SDIO output logic level sequence that repeats itself every 2 – 1 or 8,388,607 bits. A is dependent on the bias of the SPIVDD pin. For 3.3 V output description of the PN sequence and how it is generated can be logic, tie SPIVDD to 3.3 V (AVDD2). For 1.8 V output logic, tie found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The SPIVDD to 1.8 V (AVDD1). only differences are that the starting value must be a specific value instead of all 1s (see Table 9 for the initial values) and the The CSB pin should be tied to AVDD1 for applications that do AD9467 inverts the bit stream with relation to the ITU standard. not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. Table 9. PN Sequence Initial First Three Output Sequence Value Samples (MSB First) PN 9 Sequence, Short 0xFFFF 0x87BE, 0xAE64, 0x929D PN 23 Sequence, Long 0x7FFF 0x7E00, 0x807C, 0x801F Table 10. Flexible Output Test Modes Subject to Data Output Test Mode Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 1 1 1 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 0000 Same Yes 0010 +Full-scale short 1111 1111 1111 1111 Same Yes 0011 −Full-scale short 0000 0000 0000 0000 Same Yes 0100 Checkerboard 1010 1010 1010 1010 0101 0101 0101 0101 No 2 1 1 0101 PN sequence long N/A N/A Yes 2 1 1 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 1111 0000 0000 0000 0000 No 1 N/A = not applicable. 2 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver. Rev. C | Page 25 of 32 AD9467 Data Sheet SERIAL PORT INTERFACE (SPI) In addition to the operation modes, the SPI port configuration The AD9467 serial port interface allows the user to configure influences how the AD9467 operates. When operating in 2-wire the converter for specific functions or operations through a mode, it is recommended to use a 1-, 2-, or 3-byte transfer structured register space provided inside the ADC. This gives exclusively. Without an active CSB line, streaming mode can be the user added flexibility and customization, depending on the entered but not exited. application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized In addition to word length, the instruction phase determines if into bytes that can be further divided down into fields, as the serial frame is a read or write operation, allowing the serial detailed in the Memory Map section. Detailed operational port to be used to both program the chip and read the contents information can be found in the AN-877 Application Note, of the on-chip memory. If the instruction is a readback operation, Interfacing to High Speed ADCs via SPI. performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame. There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 11). The SCLK pin is used to synchronize the read Data can be sent in MSB- or LSB-first mode. MSB-first mode and write data presented to the ADC. The SDIO pin is a dual- is the default at power-up and can be changed by adjusting the purpose pin that allows data to be sent to and read from the configuration register. For more information about this and internal ADC memory map registers. The CSB pin is an active other features, see the AN-877 Application Note, Interfacing to low control that enables or disables the read and write cycles. High Speed ADCs via SPI. HARDWARE INTERFACE Table 11. Serial Port Pins The pins described in Table 11 compose the physical interface Pin Function between the programming device of the user and the serial port SCLK Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. of the AD9467. The SCLK and CSB pins function as inputs SDIO Serial data input/output. A dual-purpose pin. The typical when using the SPI. The SDIO pin is bidirectional, functioning as role for this pin is an input or output, depending on the an input during write phases and as an output during readback. instruction sent and the relative position in the timing If multiple SDIO pins share a common connection, care should frame. be taken to ensure that proper V levels are met. Assuming the CSB Chip select bar (active low). This control gates the read OH and write cycles. same load for each AD9467, Figure 67 shows the number of SDIO pins that can be connected together and the resulting V level. OH The falling edge of the CSB, in conjunction with the rising edge 1.80 of the SCLK, determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by 1.79 one or more data bytes, which is determined by Bit Field W0 and 1.78 Bit Field W1. An example of the serial timing and its definitions can be found in Figure 68 and Table 12. During normal operation, 1.77 CSB is used to signal to the device that SPI commands are to be 1.76 received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, 1.75 CSB remains low until the communication cycle is complete. 1.74 However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough 1.73 time to transfer data into shift registers. CSB can be stalled 1.72 when transferring one, two, or three bytes of data. When W0 and 0 102030 40 5060 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER W1 are set to 11, the device enters streaming mode and continues Figure 67. SDIO Pin Loading to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete This interface is flexible enough to be controlled by either serial memory transfers without requiring additional instructions. PROMS or PIC mirocontrollers, providing the user with an Regardless of the mode, if CSB is taken high in the middle of a alternative method, other than a full SPI controller, to program byte transfer, the SPI state machine is reset and the device waits the ADC (see the AN-812 Application Note). for a new instruction. Rev. C | Page 26 of 32 V (V) OH 09029-074 Data Sheet AD9467 t DS t t CLK H t HIGH t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 68. Serial Timing Details Table 12. Serial Timing Definitions Parameter Timing (Minimum, ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock t 5 Setup time between CSB and SCLK S t 2 Hold time between CSB and SCLK H tHIGH 16 Minimum period that SCLK should be in a logic high state tLOW 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 68) t 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising DIS_SDIO edge (not shown in Figure 68) Rev. C | Page 27 of 32 09029-072 AD9467 Data Sheet MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map register table (see Table 13) has when writing the default values suggested in this data sheet. eight address locations. The memory map is divided into three Addresses that have values marked as 0 should be considered sections: the chip configuration register map (Address 0x00 reserved and have a 0 written into their registers during power-up. to Address 0x02), the device index and transfer register map (Address 0xFF), and the ADC functions register map DEFAULT VALUES (Address 0x08 to Address 0x107). When the AD9467 comes out of a reset, critical registers are The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in address number, and the default value is shown in the second right- Table 13, where an X refers to an undefined feature. most column. The (MSB) Bit 7 column is the start of the default LOGIC LEVELS hexadecimal value given. For example, Address 0x2C, the analog An explanation of various registers follows: “Bit is set” is input register, has a default value of 0x00, meaning Bit 7 = 0, synonymous with “bit is set to Logic 1” or “writing Logic 1 for Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Bit 0 = 0, or 0000 0000 in binary. This setting is the default for an Logic 0” or “writing Logic 0 for the bit.” ac-coupled analog input condition. By writing a 1 to Bit 2 of this address, the internal input common-mode buffer is disabled allowing a dc-coupled input for which the input common mode voltage can be set externally. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. 1 Table 13. Memory Map Register Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip Configuration Register 00 chip_port_config X LSB first Soft 1 1 X X X 0x18 The nibbles 1 = on reset should be 0 = off 1 = on mirrored so (default) 0 = off that LSB- or (default) MSB-first mode is set correctly regardless of shift mode. 01 chip_id 8-Bit Chip ID Bits[7:0] Read Default is (AD9467 = 0x50, default) only unique chip ID, different for each device. This is a read- only register. 02 chip_grade X Child ID Bits[6:4] X X X X Read Child ID used to (identify device variants of chip ID) only differentiate 001 = 200 MSPS graded devices. 010 = 250 MSPS Device Index and Transfer Register FF device_update X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the 0 = off master shift (default) register to the slave. Rev. C | Page 28 of 32 Data Sheet AD9467 Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments ADC Functions 08 modes X X X X X X Internal power- 0x00 Determines down mode various generic 00 = chip run modes of chip (default) operation. 01 = full power- down 0D test_io X X Reset PN Reset PN Output test mode—see Table 10 in the 0x00 When this long short gen Digital Outputs and Timing section register is set, gen 1 = on 0000 = off (default) the test data is 1 = on 0 = off 0001 = midscale short placed on the 0 = off (default) 0010 = +FS short output pins in (default) 0011 = −FS short place of normal 0100 = checkerboard output data. 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 0F adc_input XVREF X X X X Analog X X 0x00 Analog input disconnect functions. 1 = on 1 = on 0 = off 0 = off (default) (default) 10 offset 8-bit digital offset adjustment 0x00 Bipolar, twos complement 0111 1111 = 127 digital offset 0111 1110 = 126 adjustment in … LSBs. 0000 0010 = 2 0000 0001 = 1 0000 0000 = 0 1111 1111 = -1 1111 1110 = -2 … 1000 0001 = -126 1000 0000 = -127 14 output_mode X 0 X Digital 1 Output Data format 0x08 Configures the output invert select outputs and disable 1 = on the format of 00 = offset 0 = off the data. 1 = on binary (default) (default) 0 = off 01 = twos (default) complement 10 = Gray code 15 output_adjust X X X X Coarse Output current drive adjust 0x00 Determines LVDS LVDS or other 001 = 3.0 mA (default) adjust output 010 = 2.79 mA properties. 0 = 011 = 2.57 mA 3.0 mA 100 = 2.35 mA (default) 101 = 2.14 mA 1 = 110 = 1.93 mA 1.71 mA 111 = 1.71 mA 16 output_phase DCO X X X X X X X 0x00 Determines output digital clock invert output phase. 1 = on 0 = off (default) 17 output_delay DCO X X 5-bit digital clock output delay adjustment 0x00 Determines delay digital clock 0 0000 enable output delay. 0 0001 1 = on 0 0010 0 = off 0 0011 (default) … 1 1111 Rev. C | Page 29 of 32 AD9467 Data Sheet Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 18 vref X X X X Input full-scale range adjust 0x0A 0000 = 2.0 V p-p 0110 = 2.1 V p-p 0111 = 2.2 V p-p 1000 = 2.3 V p-p 1001 = 2.4 V p-p 1010 = 2.5 V p-p (default) 2C analog_input X X X X X Input X X 0x00 Determines the coupling input coupling mode mode. 0 = ac coupling (default) 1 = dc coupling 36 Buffer Current 110101 = +530% 1 0 0x22 Select 1 110100 = +520% … 001000 = +80% (default) … 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% … 110111 = −90% 110110 = −100% 107 Buffer Current 110101 = +530% X X 0x20 Select 2 110100 = +520% … 001000 = +80% (default) … 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% … 110111 = −90% 110110 = −100% 1 X = undefined feature, don’t write. Rev. C | Page 30 of 32 Data Sheet AD9467 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9467, it is recommended It is required that the exposed paddle on the underside of the that three separate supplies be used: one for analog AVDD1 and ADC be connected to analog ground (AGND) to achieve the AVDD3 (1.8 V), one for analog AVDD2 (3.3 V), and one for best electrical and thermal performance of the AD9467. An digital output drivers DRVDD (1.8 V). If only one 1.8 V supply exposed continuous copper plane on the PCB should be con- is available, it should be routed to AVDD1 and AVDD3 first and nected to the AD9467 exposed paddle, Pin 0. The copper plane then tapped off and isolated with a ferrite bead or a filter choke should have several vias to achieve the lowest possible resistive preceded by decoupling capacitors for the DRVDD. The user thermal path for heat dissipation to flow through the bottom of can employ several different decoupling capacitors to cover the PCB. These vias should be solder-filled or plugged. both high and low frequencies. These should be located close to To maximize the coverage and adhesion between the ADC and the point of entry at the PC board level and close to the parts, PCB, partition the continuous copper plane by overlaying a with minimal trace lengths. silkscreen on the PCB into several uniform sections. This provides A single PC board ground plane should be sufficient when several tie points between the ADC and PCB during the reflow using the AD9467. With proper decoupling and smart parti- process, whereas using one continuous plane with no partitions tioning of the PC board’s analog, digital, and clock sections, only guarantees one tie point. See Figure 69 for a PCB layout optimum performance can be easily achieved. example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). SILKSCREEN PARTITION PIN 1 INDICATOR Figure 69. Typical PCB Layout Rev. C | Page 31 of 32 09029-073 AD9467 Data Sheet OUTLINE DIMENSIONS 0.60 10.00 0.42 0.60 BSC SQ 0.24 0.42 PIN 1 0.24 55 72 INDICATOR 54 1 PIN 1 INDICATOR 0.50 9.75 BSC EXPOSED PAD 8.60 BSC SQ (BOTTOM VIEW) 8.50 SQ 8.40 0.50 0.40 37 18 0.30 36 19 0.25 MIN TOP VIEW 8.50 REF 0.70 0.65 12° MAX 0.90 0.60 FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.01 NOM FUNCTION DESCRIPTIONS COPLANARITY SEATING 0.30 SECTION OF THIS DATA SHEET. 0.08 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 70. 72-Lead Lead Frame Chip Scale Package, Exposed Pad [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9467BCPZ-200 –40°C to +85°C 72-Lead LFCSP_VQ CP-72-5 AD9467BCPZRL7-200 –40°C to +85°C 72-Lead LFCSP_VQ CP-72-5 AD9467BCPZ-250 –40°C to +85°C 72-Lead LFCSP_VQ CP-72-5 AD9467BCPZRL7-250 –40°C to +85°C 72-Lead LFCSP_VQ CP-72-5 AD9467-200EBZ AD9467-200 Evaluation Board AD9467-250EBZ AD9467-250 Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09029-0-9/11(C) Rev. C | Page 32 of 32 07-26-2010-C