ANALOG DEVICES AD9460

16-Bit, 80 MSPS/105 MSPS ADC AD9460 FEATURES FUNCTIONAL BLOCK DIAGRAM 105 MSPS guaranteed sampling rate (AD9460-105) AGND AVDD1 AVDD2 DRGND DRVDD 79.4 dBFS SNR/91 dBc SFDR with 10 MHz input DFS AD9460 (3.4 V p-p input, 80 MSPS) DCS MODE BUFFER 78.3 dBFS SNR/ with 170 MHz input OUTPUT MODE 16 VIN+ 2 PIPELINE (4.0 V p-p input, 80 MSPS) T/H CMOS OR ADC VIN– OR 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input LVDS 32 OUTPUT D15 TO D0 (3.4 V p-p input, 80 MSPS) STAGING 2 77.2 dBFS SNR/84 dBc SFDR with 170 MHz input CLK+ CLOCK DCO AND TIMING (3.4 V p-p input, 105 MSPS) REF CLK– MANAGEMENT 90 dBFS two-tone SFDR with 139 MHz/140 MHz input (3.4 V p-p input, 105 MSPS) VREF SENSE REFT REFB 60 fsec rms jitter Excellent linearity Figure 1. DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available 3.3 V and 5 V supply operation Optional features allow users to implement various selectable APPLICATIONS operating conditions, including input range, data format select, MRI receivers and output data mode. Multicarrier, multimode, cellular receivers The AD9460 is available in a Pb-free, 100-lead, surface-mount, Antenna array positioning plastic package (TQFP_EP) specified over the industrial tem- Power amplifier linearization perature range of −40°C to +85°C. Broadband wireless Radar PRODUCT HIGHLIGHTS Infrared imaging Communications instrumentation 1. True 16-bit linearity. GENERAL DESCRIPTION 2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital magnetic resonance imaging, and radar receivers. converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The 3. Ease of use: on-chip reference and high input impedance, AD9460 operates up to 105 MSPS, providing a superior signal- track-and-hold with adjustable analog input range, and an to-noise ratio (SNR) for instrumentation, medical imaging, and output clock simplifies data capture. radar receivers using baseband (<100 MHz) and IF frequencies. 4. Packaged in a Pb-free, 100-lead TQFP/EP. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of clock pulse widths. many applications. Data outputs are CMOS or LVDS compatible 6. Out-of-range (OR) outputs indicate when the signal is (ANSI-644 compatible) and include the means to reduce the beyond the selected input range. overall current needed for short trace distances. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06006-001 AD9460 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8 Functional Block Diagram .............................................................. 1 Equivalent Circuits......................................................................... 12 Applications....................................................................................... 1 Typical Performance Characteristics ........................................... 13 General Description ......................................................................... 1 Terminology.................................................................................... 19 Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 20 Revision History ............................................................................... 2 Analog Input and Reference Overview ................................... 20 Specifications..................................................................................... 3 Clock Input Considerations...................................................... 21 DC Specifications ......................................................................... 3 Power Considerations................................................................ 22 AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 23 Digital Specifications ................................................................... 5 Timing ......................................................................................... 23 Switching Specifications .............................................................. 5 Operational Mode Selection ..................................................... 23 Timing Diagrams.......................................................................... 6 Evaluation Board ............................................................................ 24 Absolute Maximum Ratings............................................................ 7 Outline Dimensions....................................................................... 31 Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 31 ESD Caution.................................................................................. 7 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9460 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted. Table 1. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −5.0 ±0.1 +5.0 −5.0 ±0.1 +5.0 mV Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR Full −3.4 +3.4 −3.4 +3.4 % FSR 1 Differential Nonlinearity (DNL) 25°C −0.8 ±0.5 +0.8 −0.85 ±0.5 +0.85 LSB Full −0.9 +0.9 −1 +1.2 1 Integral Nonlinearity (INL) 25°C −6 ±3 +6 −6 ±3 +6 LSB VOLTAGE REFERENCE Output Voltage VREF = 1.7 V Full 1.7 1.7 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External VREF = 1.7 V) Full 350 350 μA INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms ANALOG INPUT Input Span VREF = 1.7 V Full 3.4 3.4 V p-p VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 3.9 3.2 3.9 V 2 Input Resistance Full 1 1 kΩ 2 Input Capacitance Full 6 6 pF POWER SUPPLIES Supply Voltages AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V 1 Supply Currents AVDD1 Full 290 310 337 373 mA 1, 3 AVDD2 Full 101 110 116 133 mA 1 I —LVDS Outputs Full 70 78.5 71 81 mA DRVDD 1 IDRVDD —CMOS Outputs Full 14 14 mA PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V 3 POWER CONSUMPTION 1.9 LVDS Outputs Full 1.7 1.8 2.2 W 1.7 CMOS Outputs (DC Input) Full 1.5 W 1 Measured at the maximum clock rate, f = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and IN approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For SFDR = AVDD1, IAVDD2 power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. Rev. 0 | Page 3 of 32 AD9460 AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted. Table 2. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 10 MHz 25°C 77.6 78.4 77.2 78.1 dB IN Full 77.4 76.9 f = 170 MHz 25°C 76.1 76.8 75.0 76.2 dB IN Full 75.0 74.5 fIN = 225 MHz 25°C 75.7 75.2 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 76.1 78.0 75.2 77.4 dB Full 74.4 74.5 f = 170 MHz 25°C 74.0 76.1 72.0 75.1 dB IN Full 72.1 71.2 f = 225 MHz 25°C 74.6 73.6 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 10 MHz 25°C 12.8 12.7 bits IN f = 170 MHz 25°C 12.5 12.4 bits IN fIN = 225 MHz 25°C 12.3 12.1 bits SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC) fIN = 10 MHz 25°C 80 91 80 88 dBc Full 78 76 fIN = 170 MHz 25°C 80 87 78 84 dBc Full 78 74 f = 225 MHz 25°C 82 81 dBc IN WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS f = 10 MHz 25°C 94 100 92 98 dBc IN Full 91 91 fIN = 170 MHz 25°C 90 98 89 98 dBc Full 88 85 f = 225 MHz 25°C 97 92 dBc IN TWO-TONE SFDR fIN = 139.6 MHz @ −7 dBFS, 140.6 MHz @ −7 dBFS 25°C 89 90 dBFS ANALOG BANDWIDTH Full 615 615 MHz Rev. 0 | Page 4 of 32 AD9460 DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted. Table 3. AD9460BSVZ-80/105 Parameter Temp Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full 2.0 V Low Level Input Voltage Full 0.8 V High Level Input Current Full 200 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 2 pF 1 DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR) DRVDD = 3.3 V High Level Output Voltage Full 3.25 V Low Level Output Voltage Full 0.2 V DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR) 2 VOD Differential Output Voltage Full 247 545 mV VOS Output Offset Voltage Full 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full 0.2 V Common-Mode Voltage Full 1.3 1.5 1.6 V Input Resistance Full 1.1 1.4 1.7 kΩ Input Capacitance Full 2 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. SWITCHING SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full 80 105 MSPS Minimum Conversion Rate Full 1 1 MSPS CLK Period Full 12.5 9.5 ns 1 CLK Pulse Width High (tCLKH) Full 5.0 3.8 ns 1 CLK Pulse Width Low (tCLKL) Full 5.0 3.8 ns DATA OUTPUT PARAMETERS 2 Output Propagation Delay—CMOS (tPD) (Dx, DCO+) Full 3.35 3.35 ns 3 3 Output Propagation Delay—LVDS (t ) (Dx+), (t ) (DCO+) Full 2.3 3.6 4.8 2.3 3.6 4.8 ns PD CPD Pipeline Delay (Latency) Full 13 13 cycles Aperture Delay (t) Full ns A Aperture Uncertainty (Jitter, tJ) Full 60 60 fs, rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. 3 LVDS R = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition. TERM Rev. 0 | Page 5 of 32 AD9460 TIMING DIAGRAMS N + 15 N – 1 N N + 14 N + 1 VIN N + 13 t CLKL t CLKH 1/f S CLK+ CLK– t PD N N + 1 N – 13 N – 12 Dx 13 CLOCK CYCLES DCO+ DCO– t CPD Figure 2. LVDS Mode Timing Diagram N N – 1 N + 1 VIN N + 2 t CLKL t CLKH CLK– CLK+ t PD 13 CLOCK CYCLES Dx N – 13 N – 12 N – 1 N DCO+ DCO– Figure 3. CMOS Timing Diagram Rev. 0 | Page 6 of 32 06006-002 06006-003 AD9460 ABSOLUTE MAXIMUM RATINGS Table 5. THERMAL RESISTANCE Parameter Rating The heat sink of the AD9460 package must be soldered to ELECTRICAL ground. AVDD1 to AGND −0.3 V to +4 V AVDD2 to AGND −0.3 V to +6 V Airflow increases heat dissipation, effectively reducing θ . Also, JA DRVDD to DGND −0.3 V to +4 V more metal directly in contact with the package leads from AGND to DGND −0.3 V to +0.3 V metal traces through holes, ground, and power planes reduces AVDD1 to DRVDD −4 V to +4 V the θJA. It is required that the exposed heat sink be soldered to AVDD2 to DRVDD −4 V to +6 V the ground plane. AVDD2 to AVDD1 −4 V to +6 V Table 6. D0± Through D15± to DGND −0.3 V to DRVDD + 0.3 V 1 2 3 Package Type θJA θJB θJC Unit CLK+/CLK− to AGND −0.3 V to AVDD1 + 0.3 V 100-Lead TQFP_EP 19.8 8.3 2 °C/W OUTPUT MODE, DCS MODE, and −0.3 V to AVDD1 + 0.3 V DFS to AGND 1 Typical θJA = 19.8°C/W (heat sink soldered) for a multilayer board in still air. 2 VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V Typical θ = 8.3°C/W (heat sink soldered) for a multilayer board in still air. JB 3 Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal VREF to AGND −0.3 V to AVDD1 + 0.3 V resistance through heat sink path SENSE to AGND −0.3 V to AVDD1 + 0.3 V REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V ENVIRONMENTAL Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 32 AD9460 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 DCS MODE DRGND PIN 1 DNC 2 74 D10+ 3 73 OUTPUT MODE D10– 4 72 DFS D9+ 5 71 LVDS_BIAS D9– 6 70 AVDD1 D8+ 7 69 SENSE D8– VREF 8 68 DCO+ AD9460 AGND 9 67 DCO– LVDS MODE 10 66 REFT D7+ TOP VIEW (Not to Scale) 11 65 REFB D7– 12 64 AVDD2 DRVDD AVDD2 13 63 DRGND AVDD2 14 62 D6+ AVDD2 15 61 D6– AVDD2 16 60 D5+ AVDD2 17 59 D5– AVDD1 18 58 D4+ 19 57 AVDD1 D4– 20 56 AVDD1 D3+ 21 55 AGND D3– 22 54 VIN+ D2+ 23 53 VIN– D2– 24 52 AGND D1+ 25 51 AVDD2 D1– 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DNC = DO NOT CONNECT Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode Pin No. Mnemonic Description 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2 DNC Do Not Connect. This pin should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, 38, AVDD1 3.3 V (±5%) Analog Supply. 43 to 45, 92 to 97 7 SENSE Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference. 8 VREF 1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. 9, 21, 24, 39, 42, 46, 91, 98, AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected 99, Exposed Heat Sink to AGND. Rev. 0 | Page 8 of 32 AVDD2 SFDR AVDD2 AGND AVDD2 AGND AVDD2 AVDD1 AVDD2 AVDD1 AVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD2 AGND AVDD1 OR+ AVDD2 OR– AVDD1 DRVDD AGND DRGND CLK+ D15+ (MSB) CLK– D15– AGND D14+ AVDD1 D14– AVDD1 D13+ AVDD1 D13– AGND D12+ DRGND D12– DRVDD D11+ D0– (LSB) D11– D0+ DRVDD 06006-004 AD9460 Pin No. Mnemonic Description 10 REFT Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11) with 0.1 μF and 10 μF capacitors. 11 REFB Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin 10) with 0.1 μF and 10 μF capacitors. 12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 49 D0− (LSB) D0 Complement Output Bit (LVDS Levels). 50 D0+ D0 True Output Bit. 51 D1− D1 Complement Output Bit. 52 D1+ D1 True Output Bit. 53 D2− D2 Complement Output Bit. 54 D2+ D2 True Output Bit. 55 D3− D3 Complement Output Bit. 56 D3+ D3 True Output Bit. 57 D4− D4 Complement Output Bit. 58 D4+ D4 True Output Bit. 59 D5− D5 Complement Output Bit. 60 D5+ D5 True Output Bit. 61 D6− D6 Complement Output Bit. 62 D6+ D6 True Output Bit. 65 D7− D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 69 D8− D8 Complement Output Bit. 70 D8+ D8 True Output Bit. 71 D9− D9 Complement Output Bit. 72 D9+ D9 True Output Bit. 73 D10− D10 Complement Output Bit. 74 D10+ D10 True Output Bit. 77 D11− D11 Complement Output Bit. 78 D11+ D11 True Output Bit. 79 D12− D12 Complement Output Bit. 80 D12+ D12 True Output Bit. 81 D13− D13 Complement Output Bit. 82 D13+ D13 True Output Bit. 83 D14− D14 Complement Output Bit. 84 D14+ D14 True Output Bit. 85 D15− D15 Complement Output Bit. 86 D15+ (MSB) D15 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. Rev. 0 | Page 9 of 32 AD9460 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 DCS MODE DRGND PIN 1 2 74 DNC D4+ OUTPUT MODE 3 73 D3+ 4 72 DFS D2+ LVDS_BIAS 5 71 D1+ AVDD1 6 70 D0+ (LSB) SENSE 7 69 DNC VREF 8 68 DCO+ AD9460 AGND 9 67 DCO– CMOS MODE REFT 10 66 DNC TOP VIEW (Not to Scale) REFB 11 65 DNC 12 64 AVDD2 DRVDD 13 63 AVDD2 DRGND 14 62 AVDD2 DNC 15 61 AVDD2 DNC 16 60 AVDD2 DNC 17 59 AVDD2 DNC 18 58 AVDD1 DNC 19 57 AVDD1 DNC 20 56 AVDD1 DNC 21 55 AGND DNC VIN+ 22 54 DNC VIN– 23 53 DNC AGND 24 52 DNC AVDD2 25 51 DNC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DNC = DO NOT CONNECT Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode Pin No. Mnemonic Description 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, AVDD1 3.3 V (±5%) Analog Supply. 38, 43 to 45, 92 to 97 7 SENSE Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference. 8 VREF 1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. 9, 21, 24, 39, 42, 46, 91, 98, AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected 99, Exposed Heat Sink to AGND. 10 REFT Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11) with 0.1 μF and 10 μF capacitors. Rev. 0 | Page 10 of 32 AVDD2 SFDR AVDD2 AGND AVDD2 AGND AVDD2 AVDD1 AVDD2 AVDD1 AVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD2 AGND AVDD1 OR+ AVDD2 D15+ (MSB) AVDD1 DRVDD AGND DRGND CLK+ D14+ CLK– D13+ AGND D12+ AVDD1 D11+ AVDD1 D10+ AVDD1 D9+ AGND D8+ DRGND D7+ DRVDD D6+ DNC D5+ DNC DRVDD 06006-005 AD9460 Pin No. Mnemonic Description 11 REFB Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin 10) with 0.1 μF and 10 μF capacitors. 12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 70 D0+ (LSB) D0 True Output Bit (CMOS Levels). 71 D1+ D1 True Output Bit. 72 D2+ D2 True Output Bit. 73 D3+ D3 True Output Bit. 74 D4+ D4 True Output Bit. 77 D5+ D5 True Output Bit. 78 D6+ D6 True Output Bit. 79 D7+ D7 True Output Bit. 80 D8+ D8 True Output Bit. 81 D9+ D9 True Output Bit. 82 D10+ D10 True Output Bit. 83 D11+ D11 True Output Bit. 84 D12+ D12 True Output Bit. 85 D13+ D13 True Output Bit. 86 D14+ D14 True Output Bit. 89 D15+ (MSB) D15 True Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. Rev. 0 | Page 11 of 32 AD9460 EQUIVALENT CIRCUITS AVDD2 DRVDD VIN+ 6pF 1kΩ Dx 3.5V X1 T/H 1kΩ AVDD2 VIN– 6pF Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent CMOS Digital Output Circuit DRVDD DRVDD VDD K 1.2V DCS MODE, LVDS_BIAS OUTPUT MODE, 3.74kΩ I LVDSOUT DFS 30kΩ Figure 7. Equivalent LVDS_BIAS Circuit Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE DRVDD AVDD1 3kΩ 3kΩ V V CLK+ CLK– Dx– Dx+ V V 2.5kΩ 2.5kΩ Figure 8. Equivalent LVDS Digital Output Circuit Figure 11. Equivalent Sample Clock Input Circuit Rev. 0 | Page 12 of 32 06006-008 06006-007 06006-006 06006-009 06006-010 06006-011 AD9460 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 3.4 V p-p differential input, AIN = −1 dBFS, internal trimmed reference (nominal VREF = 1.7 V), unless otherwise noted. 0 0 105MSPS 105MSPS –10 –10 10.3MHz @ –1.0dBFS 225.3MHz @ –1.0dBFS SNR = 78.1dB SNR = 75.2dB –20 –20 ENOB = 12.9 BITS ENOB = 12.6 BITS SFDR = 88dBc SFDR = 81dBc –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 13.125 26.250 39.375 52.500 0 13.125 26.250 39.375 52.500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. 105 MSPS, 64k Point, Single-Tone FFT, 10.3 MHz Figure 15. 105 MSPS, 64k Point, Single-Tone FFT, 225.3 MHz 0 0.6 105MSPS –10 170.3MHz @ –1.0dBFS SNR = 76.2dB –20 ENOB = 12.6 BITS 0.4 SFDR = 84dBc –30 –40 0.2 –50 –60 0 –70 –80 –0.2 –90 –100 –0.4 –110 –120 –130 –0.6 0 13.125 26.250 39.375 52.500 0 8192 16384 24576 32768 40960 49152 57344 65536 FREQUENCY (MHz) OUTPUT CODE Figure 13. 105 MSPS, 64k Point, Single-Tone FFT, 170.3 MHz Figure 16. 105 MSPS, DNL Error vs. Output Code, 10.3 MHz 0 4 105MSPS –10 70.3MHz @ –1.0dBFS SNR = 77.8dB 3 –20 ENOB = 12.6 BITS SFDR = 86dBc –30 2 –40 1 –50 –60 0 –70 –80 –1 –90 –2 –100 –110 –3 –120 –130 –4 0 13.125 26.250 39.375 52.500 0 8192 16384 24576 32768 40960 49152 57344 65536 FREQUENCY (MHz) OUTPUT CODE Figure 14. 105 MSPS, 64k Point, Single-Tone FFT, 70.3 MHz Figure 17. 105 MSPS, INL Error vs. Output Code, 10.3 MHz Rev. 0 | Page 13 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06006-014 06006-050 06006-012 AMPLITUDE (dBFS) INL (MSB) DNL (MSB) 06006-017 06006-016 06006-051 AD9460 0 0 80MSPS 80MSPS –10 –10 10.3MHz @ –1.0dBFS 225.3MHz @ –1.0dBFS SNR = 78.4dB SNR = 75.7dB –20 –20 ENOB = 12.9 BITS ENOB = 12.6 BITS SFDR = 91dBc SFDR = 82dBc –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 12.5 25.0 37.5 04 10 20 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. 80 MSPS, 64k Point Single-Tone FFT, 10.3 MHz Figure 21. 80 MSPS, 64k Point Single-Tone FFT, 225.3 MHz 0 0.6 80MSPS –10 170.3MHz @ –1.0dBFS SNR = 76.8dB –20 0.4 ENOB = 12.5 BITS SFDR = 87dBc –30 –40 0.2 –50 –60 0 –70 –80 –0.2 –90 –100 –0.4 –110 –120 –130 –0.6 0 12.5 25.0 37.5 0 8192 16384 24576 32768 40960 49152 57344 65536 FREQUENCY (MHz) OUTPUT CODE Figure 19. 80 MSPS, 64k Point, Single-Tone FFT, 170.3 MHz Figure 22. 80 MSPS, DNL Error vs. Output Code, 10.3 MHz 0 4 80MSPS –10 70.3MHz @ –1.0dBFS SNR = 77.8dB 3 –20 ENOB = 12.5 BITS SFDR = 86dBc –30 2 –40 1 –50 –60 0 –70 –80 –1 –90 –2 –100 –110 –3 –120 –130 –4 0 12.5 25.0 37.5 0 8192 16384 24576 32768 40960 49152 57344 65536 FREQUENCY (MHz) OUTPUT CODE Figure 20. 80 MSPS, 64k Point, Single-Tone FFT, 70.3 MHz Figure 23. 80 MSPS, INL Error vs. Output Code, 10.3 MHz Rev. 0 | Page 14 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06006-020 06006-019 06006-018 AMPLITUDE (dBFS) INL (MSB) DNL (MSB) 06006-023 06006-022 06006-052 AD9460 95 90 SFDR dBc 90 85 SFDR +85°C SFDR –40°C SFDR +25°C 85 80 SNR dB SNR +25°C 80 75 SNR –40°C 75 SNR +85°C 70 70 65 0 50 100 150 200 2.9 3.1 3.3 3.5 3.7 3.9 4.1 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 24. 105 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p Figure 27. 105 MSPS, SNR/SFDR vs. Analog Input Common Mode 95 120 SFDR dBFS SFDR +85°C 100 90 SNR dBFS SFDR –40°C SFDR +25°C 80 85 60 80 SFDR dBc SNR –40°C 40 75 SNR +25°C 20 SNR +85°C SNR dB 70 0 0 50 100 150 200 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT AMPLITUDE (dB) Figure 25. 105 MSPS, SNR/SFDR vs. Analog Input Frequency, Figure 28. 105 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level, 3.4 V p-p, CMOS Mode CMOS Output Mode 120 95 SFDR +85°C SFDR +25°C SFDR dBFS 100 SFDR –40°C 90 SNR dBFS 80 85 60 SNR +25°C 80 SNR –40°C 40 SFDR dBc 75 20 SNR +85°C SNR dB 70 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 ANALOG INPUT AMPLITUDE (dB) ANALOG INPUT FREQUENCY (MHz) Figure 29. 80 MSPS, SNR/SFDR vs. Analog Input Frequency, Figure 26. 105 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level 3.4 V p-p, CMOS Mode Rev. 0 | Page 15 of 32 (dB) (dB) (dB) 06006-025 06006-024 06006-026 (dB) (dB) (dB) 06006-030 06006-029 06006-028 AD9460 120 120 SFDR dBFS SFDR dBFS 100 100 SNR dBFS SNR dBFS 80 80 60 60 SFDR dBc 40 40 SFDR dBc 20 20 SNR dB SNR dB 0 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT AMPLITUDE (dB) ANALOG INPUT AMPLITUDE (dB) Figure 30. 80 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level Figure 33. 80 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level, CMOS Output Mode 0 95 80MSPS 139.63MHz @ –7dBFS SFDR +25°C SFDR +85°C 140.63MHz @ –7dBFS –20 SFDR = 89dBFS 90 –40 85 –60 SFDR –40°C SNR +25°C SNR –40°C –80 80 –100 75 SNR +85°C –120 –140 70 04 10 20 300 0 50 100 150 200 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 34. 80 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz Figure 31. 80 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p 95 0 SFDR dBc –10 –20 90 –30 –40 SFDR dBc 85 –50 –60 80 SNR dB WORST IMD3 dBc –70 –80 75 –90 SFDR dBFS –100 70 –110 –120 WORST IMD3 dBFS 65 –130 2.9 3.1 3.3 3.5 3.7 3.9 4.1 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT AMPLITUDE (dBFS) Figure 32. 80 MSPS, SNR/SFDR vs. Analog Input Common Mode Figure 35. 80 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz Rev. 0 | Page 16 of 32 (dB) (dB) (dB) 06006-032 06006-033 06006-031 (dBFS) (dB) SFDR AND IMD3 (dB) 06006-036 06006-035 06006-034 AD9460 0 6000 105MSPS 139.63MHz @ –7dBFS 140.63MHz @ –7dBFS –20 5000 SFDR = 90dBFS –40 4000 –60 3000 –80 2000 –100 1000 –120 –140 0 0 13.125 26.250 39.375 52.500 FREQUENCY (MHz) BIN Figure 36. 105 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz Figure 38. 80 MSPS, Grounded Input Histogram 0 6000 –10 –20 5000 –30 –40 4000 –50 –60 3000 SFDR dBc –70 –80 2000 WORST IMD3 dBc –90 SFDR dBFS –100 1000 –110 WORST IMD3 dBFS –120 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT AMPLITUDE (dBFS) BIN Figure 37. 105 MSPS, Two-Tone SFDR vs. Analog Input Level, Figure 39 105 MSPS, Grounded Input Histogram 139.6 MHz, 140.6 MHz Rev. 0 | Page 17 of 32 (dBFS) SFDR AND IMD3 (dB) 06006-041 06006-040 FREQUENCY FREQUENCY N–10 N–9 N–9 N–8 N–8 N–7 N–7 N–6 N–6 N–5 N–5 N–4 N–4 N–3 N–3 N–2 N–2 N–1 N–1 N+0 N+0 N+1 N+1 N+2 N+2 N+3 N+3 N+4 N+4 N+5 N+5 N+6 N+6 N+7 N+7 N+8 N+8 N+9 N+9 N+10 N+10 06006-045 06006-042 AD9460 0.6 96 0.5 94 170.3MHz, 80MSPS 0.4 92 0.3 90 0.2 105MSPS 0.1 88 0 86 –0.1 84 80MSPS –0.2 170.3MHz, 105MSPS 82 –0.3 –0.4 80 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 –40 –20 0 20 40 60 80 TEMPERATURE (°C) ANALOG INPUT RANGE (V p-p) Figure 40. Gain vs. Temperature Figure 42. SFDR vs. Analog Input Range 79 90 78 105 SFDR dBc 85 170.3MHz, 80MSPS 77 80 SFDR dBc 80 76 105 SNR dB 170.3MHz, 105MSPS 75 75 80 SNR dB 70 74 73 65 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 45 55 65 75 85 95 105 115 125 135 145 ANALOG INPUT RANGE (V p-p) SAMPLE RATE (MSPS) Figure 41. SNR vs. Analog Input Range Figure 43. Single-Tone SNR/SFDR vs. Sample Rate, 170.3 MHz Rev. 0 | Page 18 of 32 (dBFS) GAIN ERROR (%FS) 06006-048 06006-064 (dB) (dBc) 06006-053 06006-065 AD9460 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Two-Tone SFDR The analog input frequency at which the spectral power of the The ratio of the rms value of either input tone to the rms value fundamental frequency (as determined by the FFT analysis) is of the peak spurious component. The peak spurious component reduced by 3 dB. may or may not be an IMD product. Aperture Delay (t ) Effective Number of Bits (ENOB) A The delay between the 50% point of the rising edge of the clock The effective number of bits for a sine wave input at a given and the instant at which the analog input is sampled. input frequency can be calculated directly from its measured SINAD using the following formula: Aperture Uncertainty (Jitter, t ) J (SINAD−1.76) The sample-to-sample variation in aperture delay. ENOB= 6.02 Clock Pulse Width and Duty Cycle Gain Error Pulse width high is the minimum amount of time that the The first code transition should occur at an analog value of clock pulse should be left in the Logic 1 state to achieve rated ½ LSB above negative full scale. The last transition should occur performance. Pulse width low is the minimum time the clock at an analog value of 1½ LSB below the positive full scale. Gain pulse should be left in the low state. At a given clock rate, these error is the deviation of the actual difference between first and specifications define an acceptable clock duty cycle. last code transitions and the ideal difference between first and Differential Nonlinearity (DNL, No Missing Codes) last code transitions. An ideal ADC exhibits code transitions that are exactly 1 LSB Maximum Conversion Rate apart. DNL is the deviation from this ideal value. Guaranteed The clock rate at which parametric testing is performed. no missing codes to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal Integral Nonlinearity (INL) frequency drops by no more than 3 dB below the guaranteed limit. INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point Offset Error used as negative full scale occurs ½ LSB before the first code The major carry transition should occur for an analog value of transition. Positive full scale is defined as a level 1½ LSB beyond ½ LSB below VIN+ = VIN−. Offset error is defined as the the last code transition. The deviation is measured from the deviation of the actual transition from that point. middle of each particular code to the true straight line. Out-of-Range Recovery Time Signal-to-Noise and Distortion (SINAD) The time it takes for the ADC to reacquire the analog input SINAD is the ratio of the rms input signal amplitude to the rms after a transition from 10% above positive full scale to 10% value of the sum of all other spectral components below the above negative full scale, or from 10% below negative full scale Nyquist frequency, including harmonics but excluding dc. to 10% below positive full scale. Signal-to-Noise Ratio (SNR) Output Propagation Delay (t ) PD SNR is the ratio of the rms input signal amplitude to the rms The delay between the clock rising edge and the time when all value of the sum of all other spectral components below the bits are within valid logic levels. Nyquist frequency, excluding the first six harmonics and dc. Power-Supply Rejection Ratio Spurious-Free Dynamic Range (SFDR) The change in full scale from the value with the supply SFDR is the ratio of the rms signal amplitude to the rms value at the minimum limit to the value with the supply at the of the peak spurious spectral component. The peak spurious maximum limit. component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back Temperature Drift to converter full scale). The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value Total Harmonic Distortion (THD) at TMIN or TMAX. The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Rev. 0 | Page 19 of 32 AD9460 THEORY OF OPERATION ranges <2 V p-p. However, reducing the range can improve SFDR The AD9460 architecture is optimized for high speed and ease performance in some applications. Likewise, increasing the of use. The analog inputs drive an integrated, high bandwidth range up to 3.4 V p-p can improve SNR. Users are cautioned track-and-hold circuit that samples the signal prior to quantization that the differential nonlinearity of the ADC varies with the by the 16-bit pipeline ADC core. The device includes an on-board reference voltage. Configurations that use <2.0 V p-p can reference and input logic that accepts TTL, CMOS, or LVPECL exhibit missing codes and, therefore, degraded noise and levels. The digital output logic levels are user selectable as standard distortion performance. 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin. VIN+ ANALOG INPUT AND REFERENCE OVERVIEW VIN– REFT A stable and accurate 0.5 V band gap voltage reference is built 0.1µF into the AD9460. The input range can be adjusted by varying + ADC 0.1µF 10µF CORE the reference voltage applied to the AD9460, using either the REFB internal reference or an externally applied reference voltage. 0.1µF The input span of the ADC tracks reference voltage changes VREF linearly. + 10µF 0.1µF SELECT LOGIC Internal Reference Connection SENSE A comparator within the AD9460 detects the potential at the SENSE pin and configures the reference into three possible states, 0.5V summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see AD9460 Figure 44), setting VREF to ~1.7 V. If a resistor divider is connected as shown in Figure 45, the switch again sets to the Figure 44. Internal Reference Configuration SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VIN+ R2 ⎛ ⎞ VREF = 0.5 V × 1 + ⎜ ⎟ VIN– ⎝ R1⎠ REFT 0.1µF + In all reference configurations, REFT and REFB drive the ADC 0.1µF 10µF CORE analog-to-digital conversion core and establish its input span. REFB The input range of the ADC always equals twice the voltage at 0.1µF VREF the reference pin for either an internal or an external reference. + 10µF 0.1µF SELECT R2 Internal Reference Trim LOGIC SENSE The internal reference voltage is trimmed during the production test; therefore, there is little advantage to the user supplying an R1 0.5V external voltage reference to the AD9460. The gain trim is performed with the AD9460 input range set to 3.4 V p-p AD9460 nominal (SENSE connected to AGND). Because of this trim, and the maximum ac performance provided by the 3.4 V p-p Figure 45. Programmable Reference Configuration analog input range, there is little benefit to using analog input Rev. 0 | Page 20 of 32 06006-054 06006-055 AD9460 Table 9. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × external reference Programmable Reference 0.2 V to VREF 2 × VREF R2 (See Figure 45) 0.5 × 1+ R1 Programmable Reference 0.2 V to VREF 2.0 R2 ⎛ ⎞ , R1 = R2 = 1 kΩ 0.5 × 1+ ⎜ ⎟ (Set for 2 V p-p) ⎝ R1⎠ Internal Fixed Reference AGND to 0.2 V 1.7 3.4 External Reference Operation The AD9460 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 kΩ resistor When the SENSE pin is tied to AVDD, the internal reference is to the 3.5 V bias voltage and to the input of a differential buffer. disabled, allowing the use of an external reference. An internal The internal bias network on the input properly biases the reference buffer loads the external reference with an equivalent buffer for maximum linearity and range (see the Equivalent 7 kΩ load. The internal buffer continues to generate the positive Circuits section). Therefore, the analog source driving the and negative full-scale references, REFT and REFB, for the ADC AD9460 should be ac-coupled to the input pins. The recom- core. The input span is always twice the value of the reference mended method for driving the analog input of the AD9460 is voltage; therefore, the external reference must be limited to a to use an RF transformer to convert single-ended signals to maximum of 2.0 V. See Figure 40 for gain variation vs. temperature. differential signals (see Figure 47). Analog Inputs ADT1–1WT R ANALOG S VIN+ INPUT As with most new high speed, high dynamic range ADCs, the SIGNAL R T AD9460 analog input to the AD9460 is differential. Differential inputs R S VIN– improve on-chip performance because signals are processed 0.1µF through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of Figure 47. Transformer-Coupled Analog Input Circuit even-order harmonics. There are also benefits at the PCB level. Series resistors between the output of the transformer and the First, differential inputs have high common-mode rejection of AD9460 analog inputs help isolate the analog input source from stray signals, such as ground and power noise. Second, they switching transients caused by the internal sample-and-hold provide good rejection of common-mode signals, such as local circuit. The series resistors, along with the 1 kΩ resisters oscillator feedthrough. The specified noise and distortion of the connected to the internal 3.5 V bias, must be considered in AD9460 cannot be realized with a single-ended analog input; impedance matching the transformer input. For example, if R T therefore, such configurations are discouraged. Contact sales for is set to 51 Ω, RS is set to 33 Ω, and there is a 1:1 impedance ratio recommendations of other 16-bit ADCs that support single-ended transformer, then the input matches a 50 Ω source with a full- analog input configurations. scale drive of 16.0 dBm. The 50 Ω impedance matching can also With the 1.7 V reference, which is the nominal value (see the be incorporated on the secondary side of the transformer, as Internal Reference Trim section), the differential input range of shown in the evaluation board schematic (see Figure 50). the AD9460 analog input is nominally 3.4 V p-p or 1.7 V p-p on CLOCK INPUT CONSIDERATIONS each input (VIN+ or VIN−). Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock combines with the desired signal at the analog-to- VIN+ digital output. For that reason, considerable care was taken in the design of the clock inputs of the AD9460, and the user is 1.7V p-p 3.5V advised to give careful thought to the clock source. VIN– Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance charac- teristics. The AD9460 contains a clock duty cycle stabilizer (DCS) Figure 46. Differential Analog Input Range for VREF = 1.7 V that retimes the nonsampling edge, providing an internal clock Rev. 0 | Page 21 of 32 06006-056 06006-057 AD9460 VT signal with a nominal ~50% duty cycle. Noise and distortion per- 0.1µF formance are nearly flat for a 30% to 70% duty cycle with the DCS ENCODE enabled. The DCS circuit locks to the rising edge of CLK+ and ECL/ AD9460 PECL 0.1µF optimizes timing internally. This allows for a wide range of input ENCODE duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is VT not reduced by the internal stabilization circuit. The duty cycle Figure 49. Differential ECL for Encode control loop does not function for clock rates of less than 30 MHz nominally. The loop is associated with a time constant that Jitter Considerations should be considered in applications where the clock rate can High speed, high resolution ADCs are sensitive to the quality change dynamically, requiring a wait time of 1.5 μs to 5 μs after a of the clock input. The degradation in SNR at a given input dynamic clock frequency increase or decrease before the DCS frequency (fINPUT) and rms amplitude due only to aperture jitter loop is relocked to the input signal. During the time that the (tJ) can be calculated using the following equation: loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock SNR = 20 log[2πfINPUT × tJ] signal. In such an application, it can be appropriate to disable the In the equation, the rms aperture jitter represents the root-mean- duty cycle stabilizer. In all other applications, enabling the DCS square of all jitter sources, including the clock input, analog input circuit is recommended to maximize ac performance. signal, and ADC aperture jitter specification. IF undersampling The DCS circuit is controlled by the DCS MODE pin; a CMOS applications are particularly sensitive to jitter. logic low (AGND) on DCS MODE enables the duty cycle stabilizer, The clock input should be treated as an analog signal in cases and logic high (AVDD1 = 3.3 V) disables the controller. where aperture jitter can affect the dynamic range of the AD9460. The AD9460 input sample clock signal must be a high quality, Power supplies for clock drivers should be separated from the extremely low phase noise source to prevent degradation of per- ADC output driver supplies to avoid modulating the clock signal formance. Maintaining 16-bit accuracy places a premium on the with digital noise. Low jitter crystal-controlled oscillators make encode clock phase noise. SNR performance can easily degrade the best clock sources. If the clock is generated from another type by 3 dB to 4 dB with 70 MHz analog input signals when using a of source (by gating, dividing, or another method), it should be high jitter clock source. See the AN-501 Application Note, synchronized by the original clock during the last step. Aperture Uncertainty and ADC System Performance, for more POWER CONSIDERATIONS information. For optimum performance, the AD9460 must be clocked differentially. The sample clock inputs are internally Care should be taken when selecting a power source. The use of biased to ~1.5 V, and the input signal is usually ac-coupled into linear dc supplies is highly recommended. Switching supplies the CLK+ and CLK− pins via a transformer or capacitors. tend to have radiated components that can be received by the Figure 48 shows one preferred method for clocking the AD9460. AD9460. Each of the power supply pins should be decoupled as The clock source (low jitter) is converted from single-ended to closely to the package as possible using 0.1 μF chip capacitors. differential using an RF transformer. The back-to-back Schottky The AD9460 has separate digital and analog power supply pins. diodes across the secondary of the transformer limit clock The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 excursions into the AD9460 to approximately 0.8 V p-p (5 V), and the digital supply pins are denoted DRVDD. Although differential. This helps prevent the large voltage swings of the the AVDD1 and DRVDD supplies can be tied together, best per- clock from feeding through to other portions of the AD9460 and formance is achieved when the supplies are separate. This is limits the noise presented to the sample clock inputs. because the fast digital output swings can couple switching CRYSTAL ADT1–1WT SINE CLK+ current back into the analog supplies. Note that both AVDD1 SOURCE 0.1µF and AVDD2 must be held within 5% of the specified voltage. AD9460 CLK– HSMS2812 The DRVDD supply of the AD9460 is a dedicated supply for the DIODES digital outputs in either LVDS or CMOS output modes. When Figure 48. Crystal Clock Oscillator, Differential Encode in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply can be connected from 2.5 V to 3.6 V If a low jitter clock is available, it helps to band-pass filter the for compatibility with the receiving logic. clock reference before driving the ADC clock inputs. Another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 49. Rev. 0 | Page 22 of 32 06006-058 06006-059 AD9460 DIGITAL OUTPUTS TIMING LVDS Mode The AD9460 provides latched data outputs with a pipeline delay of 13 clock cycles. Data outputs are available one propagation The off-chip drivers on the chip can be configured to provide delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and LVDS-compatible output levels via Pin 3 (OUTPUT MODE). Figure 3 for detailed timing diagrams. LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET OPERATIONAL MODE SELECTION resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic Data Format Select performance, including both SFDR and SNR, maximizes when The data format select (DFS) pin of the AD9460 determines using the AD9460 in LVDS mode; designers are encouraged to the coding format of the output data. This pin is 3.3 V CMOS take advantage of this mode. The AD9460 outputs include com- plementary LVDS outputs for each data bit (Dx+/Dx−), the compatible, with logic high (or AVDD1, 3.3 V) selecting twos overrange output (OR+/OR−), and the output data clock output complement and DFS logic low (AGND) selecting offset binary (DCO+/DCO−). The R resistor current is multiplied on-chip, format. Table 10 summarizes the output coding. SET setting the output current at each output equal to a nominal Output Mode Select 3.5 mA (11 × IRSET). A 100 Ω differential termination resistor The OUPUT MODE pin controls the logic compatibility, placed at the LVDS receiver inputs results in a nominal 350 mV as well as the pinout of the digital outputs. This pin is a CMOS- swing at the receiver. LVDS mode facilitates interfacing with compatible input. With OUTPUT MODE = 0 (AGND), the LVDS receivers in custom ASICs and FPGAs that have LVDS AD9460 outputs are CMOS compatible, and the pin assignment capability for superior switching performance in noisy environ- for the device is as defined in Table 8. With OUTPUT MODE = 1 ments. Single point-to-point net topologies are recommended, (AVDD1, 3.3 V), the AD9460 outputs are LVDS compatible, and with a 100 Ω termination resistor located as close to the receiver the pin assignment for the device is as defined in Table 7. as possible. It is recommended to keep the trace length less than two inches and to keep differential output trace lengths as equal Duty Cycle Stabilizer as possible. The DCS circuit is controlled by the DCS MODE pin; a CMOS CMOS Mode logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller. In applications that can tolerate a slight degradation in dynamic performance, the AD9460 output drivers can be configured to SFDR Enhancement interface with 2.5 V or 3.3 V logic families by matching Under certain conditions, the SFDR performance of the AD9460 DRVDD to the digital supply of the interfaced logic. CMOS improves by adding some additional power to the core of the outputs are available when OUTPUT MODE is CMOS logic ADC. The SFDR control pin (Pin 100) is a CMOS-compatible low (or AGND for convenience). In this mode, the output data control pin to optimize the configuration of the AD9460 analog bits, Dx, are single-ended CMOS, as is the overrange output, front end. Connecting SFDR to AGND optimizes SFDR OR+. The output clock serves as a differential CMOS signal, performance for applications with analog input frequencies DCO+/DCO−. Lower supply voltages are recommended to <200 MHz for 80 MSPS and 105 MSPS speed grades. For avoid coupling switching transients back to the sensitive analog applications with analog inputs >200 MHz, this pin should be sections of the ADC. Minimize the capacitive load to the CMOS connected to AVDD1 for optimum SFDR performance; power outputs and connect each output to a single gate through a dissipation from AVDD2 increases by ~70 mW for the series resistor (220 Ω) to minimize switching transients caused AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. by the capacitive loading. Table 10. Digital Output Coding VIN+ − VIN− VIN+ − VIN− Digital Output Digital Output Code Input Span = 3.4 V p-p (V) Input Span = 2 V p-p (V) Offset Binary (D15…D0) Twos Complement (D15…D0) 65,536 +1.700 +1.000 1111 1111 1111 1111 0111 1111 1111 1111 32,768 0 0 1000 0000 0000 0000 0000 0000 0000 0000 32,767 −0.000052 −0.000031 0111 1111 1111 1111 1111 1111 1111 1111 0 −1.70 −1.00 0000 0000 0000 0000 1000 0000 0000 0000 Rev. 0 | Page 23 of 32 AD9460 EVALUATION BOARD Evaluation boards are offered to configure the AD9460 in either The LVDS mode evaluation boards include an LVDS-to- CMOS mode or LVDS mode only. This design represents a CMOS translator, making them compatible with the high recommended configuration for using the device over a wide speed ADC FIFO evaluation kit (HSC-ADC-EVALA-SC, range of sampling rates and analog input frequencies. These www.analog.com/FIFO). The kit includes a high speed data evaluation boards provide all the support circuitry required to capture board that provides a hardware solution for capturing operate the ADC in its various modes and configurations. Com- up to 32 kB samples of high speed ADC output data in a FIFO plete schematics are shown in Figure 50 through Figure 53. Gerber memory chip (user upgradeable to 256 kB samples). Software files are available from engineering applications demonstrating is provided to enable the user to download the captured data to the proper routing and grounding techniques that should be a PC via the USB port. This software also includes a behavioral applied at the system level. model of the AD9460 and many other high speed ADCs. It is critical that signal sources with very low phase noise Behavioral modeling of the AD9460 using ADIsimADC™ (<60 fsec rms jitter) are used to realize the ultimate software is also available at www.analog.com/ADIsimADC. The performance of the converter. Proper filtering of the input ADIsimADC software supports virtual ADC evaluation using ADI signal to remove harmonics and lower the integrated noise at proprietary behavioral modeling technology. This allows rapid the input is also necessary to achieve the specified noise comparison between the AD9460 and other high speed ADCs performance. with or without hardware evaluation boards. The evaluation boards are shipped with a 115 V ac to 6 V dc The user can choose to remove the translator and terminations power supply. The evaluation boards include low dropout to access the LVDS outputs directly. regulators to generate the various dc supplies required by the AD9460 and its support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 50). Rev. 0 | Page 24 of 32 AD9460 + Figure 50. Evaluation Board Schematic Rev. 0 | Page 25 of 32 P22 P21 PTMICRO4 PTMICRO4 VCC E19 E36 GND E18 VCC E4 E6 GND E5 GND VCC E10 E1 GND E9 VCC E3 SCLK 1 75 E14 DRGND DCS MODE DRGND 2 74 R11 GND E2 GND DNC D10_T/D5_Y D10_T 1kΩ 73 3 VCC OUTPUT MODE D10_C D10_C/D4_Y 72 4 D9_T/D3_Y DFS D9_T 5 71 D9_C/D2_Y LVDSBIAS D9_C 6 70 GND D8_T VCC AVDD1 D8_T/D1_Y GND 7 69 E26 C86 SENSE D8_C D8_C/D0_Y VCC 0.1µF E25 8 68 VREF DCO DR E27 9 67 E41 DRB GND DCOB AGND R1 E24 10 66 R3 GND REFT D7_T D7_T DNP EXTREF 65 3.74kΩ 11 C3 D7_C GND REFB U1 D7_C 0.1µF 12 64 AVDD2 DRVDD DRVDD 5V AD9460 C2 GND C40 C51 13 63 R2 5V AVDD2 DRGND DRGND 0.1µF 10µF 0.1µF GND C39 DNP 14 62 C9 AVDD2 D6_T D6_T 10µF 5V 0.1µF 15 61 5V D6_C AVDD2 D6_C GND 16 60 D5_T 5V AVDD2 D5_T C98 17 59 5V AVDD2 D5_C D5_C DNP GND 18 58 VCC AVDD1 D4_T D4_T 19 57 AVDD1 D4_C VCC D4_C GND 20 56 T1 VCC AVDD1 D3_T D3_T R5 21 55 ETC1-1-13 D3_C DNP GND AGND D3_C 15 TOUT 54 22 VIN+ D2_T D2_T J4 GND L1 CT 23 53 SMBMST R28 2 10nH GND C7 VIN– D2_C D2_C GND 33Ω 24 52 C12 0.1µF AGND D1_T GND D1_T 34 TINB R4 25 51 C5 0.1µF 5V AVDD2 D1_C D1_C PRI SEC T2 25Ω 0.1µF 3 1 TOUTB ANALOG C13 R9 4 5 DNP DNP 2 E15 R6 25Ω T5 ADT1-1WT GND TOUT 1 6 GND GND 5 2 NC CT 3 4 R35 TINB TOUTB C8 33Ω PRI SEC 0.1µF DNP = DO NOT POPULATE 06006-060 SEC PRI ETC1-1-13 C91 0.1µF OPTIONAL 101 EPAD 26 100 5V AVDD2 SFDR 27 99 AVDD2 AGND 28 98 AVDD2 AGND GND 29 97 AVDD2 AVDD1 VCC 30 96 AVDD2 VCC AVDD1 31 95 AVDD2 AVDD1 VCC 32 94 AVDD1 VCC VCC AVDD1 33 93 VCC AVDD1 VCC AVDD1 92 34 AVDD1 VCC AVDD1 VCC 35 91 5V AVDD2 AGND GND 36 90 VCC AVDD1 OR_T DOR_T/DOR_Y 37 89 AVDD2 DOR_C 5V OR_C 38 88 VCC AVDD1 DRVDD DRVDD 39 87 GND DRGND AGND DRGND 40 86 H2 ENC ENC (MSB) D15_T/D15_Y D15_T 85 MTHOLE6 41 ENCB ENCB D15_C D15_C/D14_Y DRGND 84 42 GND AGND D14_T D14_T/D13_Y H1 43 83 MTHOLE6 VCC D14_C D14_C/D12_Y AVDD1 82 44 GND D13_T/D11_Y VCC AVDD1 D13_T 45 81 D13_C/D10_Y VCC AVDD1 D13_C 46 80 D12_T/D9_Y H3 GND D12_T AGND 47 79 MTHOLE6 DRGND D12_C/D8_Y DRGND D12_C 48 78 DRVDD D11_T D11_T/D7_Y DRVDD H4 77 49 MTHOLE6 D11_C/D6_Y D0_C (LSB) D0_C D11_C 50 76 D0_T DRVDD D0_T DRVDD 4 5V P4 3 GND P3 2 P2 VCC 1 P1 GND 4 DRVDD P4 3 P3 DRGND 2 EXTREF P2 1 P1 XTALPWR AD9460 Figure 51. Evaluation Board Schematic, Encode, Optional Encode and Power Options Rev. 0 | Page 26 of 32 GND OPTIONAL ENCODE CIRCUITS ENCODE GND R7 VXTAL DNP CR2 TO MAKE LAYOUT AND PARASITIC R39 LOADING SYMMETRICAL + 0Ω C1 C41 E31 5V 10µF 0.1µF ENC VXTAL J5 E30 DNP DNP SMBMST 3 2 E20 1 XTALPWR + T3 C44 GND 10µF C36 ADT1-1WT CR2 DNP DNP CR1 1 6 DNP J1 2 NC 5 GND U2 SMBMST ECLOSC 3 4 C42 0.1µF 2 1 3 PRI SEC GND 8 C26 14 R8 VXTAL VCC OUT XTALINPUT ENCB 0.1µF 50Ω 1 7 GND VEE ~OUT GND L5 XTALINPUT FERRITE DRVDD DRVDDX L4 FERRITE VCC VCCX L3 L2 FERRITE 0Ω POWER OPTIONS 5V 5VX GND DRGND ADP3338-5 ADP3338-3.3 ADP3338-3.3 P4 U14 U7 U3 PJ-002A 5V 3.3V 3.3V 2 1 1 1 2 GND GND GND GND GND GND DRGND 3 2 2 2 4 4 4 3 OUT1 5VX OUT1 VCCX OUT1 DRVDDX 5VX OUT VCCX OUT DRVDDX OUT 1 3 3 3 VIN IN VIN IN VIN IN VIN 1 + + + + C33 C34 C6 C4 10µF 10µF 10µF 10µF + C89 + C87 + C88 10µF 10µF 10µF GND GND DRGND GND GND GND DRGND DNP = DO NOT POPULATE 06006-061 AD9460 BYPASS CAPACITORS VCC + C64 C43 C35 C32 C30 C28 C27 C90 C50 C60 C10 C61 C75 10µF 0.1µF 0.1µF 0.1µF 0.01µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DNP DNP GND VCC C11 C14 C17 C16 C15 C31 C38 C29 C19 0.1µF DNP DNP DNP 0.1µF DNP 0.1µF DNP DNP GND DRVDD DRVDD + C65 C47 C23 C21 C20 C69 C70 C45 C49 10µF 0.1µF 0.1µF 0.1µF 0.1µF DNP DNP DNP DNP DRGND DRGND 5V EXTREF + + C56 C85 C53 C52 C58 C37 C48 C18 C55 10µF 0.1µF 0.1µF 0.1µF 0.01µF DNP 0.1µF 0.1µF 10µF DNP GND GND 5V C72 C73 C108 C109 C110 DNP DNP DNP DNP DNP GND 5V C94 C95 C22 C59 C93 C96 C97 C84 C46 0.1µF 0.1µF 0.1µF 0.1µF DNP 0.1µF 0.1µF 0.1µF 0.1µF GND DNP = DO NOT POPULATE Figure 52. Evaluation Board Schematic, Bypass Capacitors Rev. 0 | Page 27 of 32 06006-062 AD9460 Figure 53. Evaluation Board Schematic Rev. 0 | Page 28 of 32 U15 SN75LVDT390 1 16 DR 1A EN_1_2 DRVDD 2 15 DRB 1B 1Y DRO 3 14 R19 2A 2Y 4 13 0Ω 2B VCC DRVDD 5 12 3A GND DRGND R10 6 11 3B 3Y 0Ω 7 10 DRO_T/DOR_Y 4A 4Y ORO 8 9 DOR_C 4B EN_3_4 DRVDD U8 SN75LVDT386 1 64 D15_T/D14_Y A1A GND DRGND 2 63 RZ5 220 D15_C/D14_Y A1B VCC1 DRVDD RSO16ISO 40 39 3 62 40 39 DRGND P39 DRGND D14_T/D13_Y A2A VCC2 DRVDD DRGND P39 DRGND P40 P40 4 61 R1 D14_C/D12_Y 1 16 A2B GND1 DRGND 38 37 38 37 D15O DOR_T/DOR_Y P37 DOR_C 5 60 ORO P37 DRO P38 P38 D13_T/D11_Y A3A ENA DRVDD R2 6 59 2 15 36 35 36 35 D13_C/D10_Y D14O A3B A1Y D15_T/D15_Y P35 D15_C/D14_Y P35 GND P36 P36 7 58 R3 D12_T/D9_Y A4A A2Y 3 14 34 33 34 33 D13O 8 57 D14_T/D13_Y P33 D14_C/D12_Y P33 D15O P34 P34 D12_C/D8_Y A4B A3Y R4 9 56 4 13 32 31 32 31 D11_T/D7_Y B1A A4Y D12O D13_T/D11_Y P31 D13_C/D10_Y P31 D14O P32 P32 10 55 R5 D11_C/D6_Y B1B ENB DRVDD 5 12 30 29 30 29 11 54 D11O D12_T/D9_Y P29 D12_C/D8_Y D10_T/D5_Y P29 D13O P30 B1Y P30 B2A R6 12 53 6 11 D10_C/D4_Y 28 27 B2B B2Y 28 27 D10O D11_T/D7_Y P27 D11_C/D6_Y P27 D12O P28 13 52 P28 D9_T/D3_Y R7 B3A B3Y 7 10 26 25 14 51 26 25 D9O D10_T/D5_Y P25 D10_C/D4_Y D9_C/D2_Y B3B B4Y P25 D11O P26 P26 15 50 R8 D8_T/D1_Y B4A GND2 DRGND 8 9 24 23 24 23 D8O D9_T/D3_Y P23 D9_C/D2_Y 16 49 P23 D10O P24 P24 D8_C/D0_Y B4B VCC3 DRVDD 48 17 22 21 22 21 D7_T C1A VCC4 DRVDD D8_T/D1_Y P21 D8_C/DO_Y P21 D9O P22 220 P22 18 47 D7_C C1B GND3 DRGND RSO16ISO 20 19 20 19 19 46 DR P19 DRB P19 D8O P20 P20 D6_T C2A C1Y R1 20 45 1 16 18 17 18 17 D6_C C2B C2Y D7O D7_T P17 D7_C P17 D7O P18 21 44 P18 D5_T R2 C3A C3Y 2 15 16 15 16 15 22 43 D6O D6_T P15 D6_C P15 D6O P16 D5_C P16 C3B C4Y 23 42 R3 3 14 13 D4_T C4A ENC DRVDD 13 14 14 D5O P13 P13 D5_T D5_C 24 41 D5O P14 P14 D4_C C4B D1Y R4 4 13 25 40 12 11 12 11 D4O P11 D3_T D1A D2Y P11 D4_T D4_C D4O P12 P12 26 39 R5 D3_C D1B D3Y 5 12 10 9 10 9 D3O P9 27 38 P9 D3_T D3_C D3O P10 P10 D2_T D2A D4Y R6 28 37 6 11 8 7 8 7 D2_C D2B END DRVDD D2O D2_T P8 P7 D2_C P8 P7 D2O 29 36 D1_T R7 D3A GND4 DRGND 7 10 6 5 6 5 30 35 D1O D1_T P6 P5 D1_C P6 P5 D1O D1_C D3B VCC5 DRVDD R8 31 34 8 9 4 3 D0_T D4A VCC6 DRVDD D0O 4 3 D0_T P4 P3 D0_C P4 P3 D0O 32 33 D0_C D4B GND5 DRGND 2 1 RZ4 2 1 DRGND P2 P1 DRGND P2 P1 DRGND DRGND P6 P7 C40MS C40MS GND C76 C82 C77 C78 0.1µF 0.1µF 0.1µF 0.1µF GND 06006-063 AD9460 Table 11. AD9460 Customer Evaluation Board Bill of Materials 1 Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No. 1 7 C4, C6, C33, C34, C87, C88, C89 Capacitor TAJD 10 μF Digi-Key 478-1699-2 Corporation 2 45 C2, C3, C5, C7, C8, C9, C10, C11, Capacitor 402 0.1 μF Digi-Key PCC2146CT-ND C12, C15, C18, C20, C21, C22, Corporation C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C97 3 2 C30, C58 Capacitor 201 0.01 μF 445-1796-1-ND Digi-Key Corporation 4 4 C39, C56, C64, C65 Capacitor TAJD 10 μF Digi-Key 478-1699-2 Corporation 5 1 C51 Capacitor 805 10 μF Digi-Key 490-1717-1-ND Corporation 6 1 CR1 Diode SOT23M5 Digi-Key MA3X71600LCT-ND Corporation 1 7 1 CR2 Diode SOT23M5 DNP Digi-Key MA3X71600LCT-ND Corporation 8 20 E1, E2, E3, E4, E5, E6, E9, E10, Header EHOLE Mouser 517-6111TG E14, E18, E19, E20, E24, E25, E26, Electronics E27, E30, E31, E36, E41 9 2 J1, J4 SMA SMA Digi-Key ARFX1231-ND Corporation 10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU 11 3 L3, L4, L5 EMIFIL® 1206MIL Mouser 81-BLM31P500S BLM31PG500SN1L Electronics 12 1 P4 Power jack PJ-002A Digi-Key CP-002A-ND Corporation 13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA 14 1 R3 Resistor 402 3.74 kΩ Digi-Key P3.74KLCT-ND Corporation 15 1 R8 Resistor 402 50 Ω Digi-Key P49.9LCT-ND Corporation 16 4 R10, R19, R39, L2 Resistor 402 0 Ω Digi-Key P0.0JCT-ND Corporation 17 1 R11 BRES402 402 1 kΩ Digi-Key P1.0KLCT-ND Corporation 18 2 R28, R35 Resistor 402 33 Ω Digi-Key P33JCT-ND Corporation 19 2 RZ4, RZ5 Resistor array 16-pin 22 Ω Digi-Key 742C163220JCT-ND Corporation 20 1 T3 Transformer ADT1-1WT Mini-Circuits ADT1-1WT 21 1 U1 AD9460BSVZ SV-100-3 Analog Devices, AD9460BSVZ Inc. 22 1 U14 ADP3338-5 SOT-223HS Analog Devices, ADP3338-5 Inc. 23 2 U3, U7 ADP3338-3.3 SOT-223HS Analog Devices, ADP3338-3.3 Inc. 24 1 U8 SN75LVDT386 TSSOP64 Arrow SN75LVDT386 Electronics, Inc. 25 1 U15 SN75LVDT390 SOIC16PW Arrow SN75LVDT390 Electronics, Inc. 26 2 R4, R6 Resistor 402 25 Ω Digi-Key P36JCT-ND Corporation Rev. 0 | Page 29 of 32 AD9460 1 Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No. 1 27 2 C1, C44, C55 Capacitor TAJD 10 μF, DNP Digi-Key 478-1699-2 Corporation 28 22 C13, C14, C16, C17, C19, C29, CAP402 402 DNP C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, 1 C93, C108, C109, C110 1 29 1 C98 Capacitor 805 DNP Digi-Key 490-1717-1-ND Corporation 1 30 E15 Header EHOLE DNP Mouser 517-6111TG Electronics 1 31 J5 SMA SMA DNP Digi-Key ARFX1231-ND Corporation 1 32 P6 Header C40MS DNP Samtec, Inc. TSW-120-08-L-D-RA 1 33 2 R1, R2 BRES402 402 DNP 1 34 3 R5, R7, R9 BRES402 402 DNP 1 35 1 U2 ECLOSC DIP4(14) DNP 1 36 4 H1, H2, H3, H4 MTHOLE6 MTHOLE6 DNP 1 37 2 T1, T2 Balun transformer SM-22 DNP M/A-COM ETC1-1-13 1 38 1 T5 Transformer ADT1-1WT DNP Mini-Circuits ADT1-WT 1 39 2 P21, P22 Term strip PTMICRO4 DNP Newark Electronics 1 DNP = do not populate. All items listed in this category are not populated. Rev. 0 | Page 30 of 32 AD9460 OUTLINE DIMENSIONS 16.00 BSC SQ 1.20 0.75 MAX 0.60 14.00 BSC SQ 0.45 100 76 76 100 1 75 75 1 PIN 1 EXPOSED 9.50 SQ TOP VIEW PAD (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 (PINS UP) 0.09 51 51 25 25 0.95 7° 26 50 50 26 3.5° 0.50 BSC VIEW A 0.27 0.15 0° SEATING LEAD PITCH 0.22 0.05 0.08 MAX PLANE COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9460BSVZ-80 –40°C to +85°C 100-Lead TQFP_EP SV-100-3 1 AD9460BSVZ-105 –40°C to +85°C 100-Lead TQFP_EP SV-100-3 AD9460-80LVDS/PCB AD9460-80LVDS Mode Evaluation Board AD9460-105LVDS/PCB AD9460-105LVDS Mode Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 31 of 32 040506-A AD9460 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06006-0-7/06(0) Rev. 0 | Page 32 of 32