ANALOG DEVICES AD9444

14-Bit, 80 MSPS, A/D Converter AD9444 FEATURES FUNCTIONAL BLOCK DIAGRAM 80 MSPS guaranteed sampling rate AGND AVDD1 AVDD2 DRGND DRVDD 100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz DFS AD9444 73.1 dB SNR with 70 MHz input DCS MODE BUFFER OUTPUT MODE 97 dBc SFDR with 70 MHz input 14 VIN+ 2 PIPELINE CMOS T/H OR Excellent linearity ADC VIN– OR 28 LVDS DNL = ±0.4 LSB typical D13–D0 OUTPUT STAGING INL = ±0.6 LSB typical 2 CLOCK CLK+ DCO 1.2 W power dissipation AND TIMING REF CLK– MANAGEMENT 3.3 V and 5 V supply operation 2.0 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) VREF SENSE REFT REFB Data format select Figure 1. Output clock available Optional features allow users to implement various selectable operating conditions, including data format select and output APPLICATIONS data mode. Multicarrier, multimode cellular receivers The AD9444 is available in a 100-lead surface-mount plastic Antenna array positioning package (100-lead TQFP/EP) specified over the industrial Power amplifier linearization temperature range (−40°C to +85°C). Broadband wireless Radar, infared imaging PRODUCT HIGHLIGHTS Communications instrumentation 1. High performance: Outstanding SFDR performance for mul- ticarrier, multimode 3G and 4G cellular base station GENERAL DESCRIPTION receivers. The AD9444 is a 14-bit monolithic, sampling analog-to-digital 2. Ease of use: On-chip reference and track-and-hold. An converter (ADC) with an on-chip, track-and-hold circuit and is output clock simplifies data capture. optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized 3. Packaged in a Pb-free, 100-lead TQFP/EP. for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. 4. Clock DCS maintains overall ADC performance over a wide range of clock pulse widths. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. 5. OR (out-of-range) outputs indicate when the signal is beyond No external reference or driver components are required for the selected input range. many applications. Data outputs are LVDS-compatible (ANSI- 644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 05089-001 AD9444 TABLE OF CONTENTS DC Specifications ............................................................................. 3 Clock Input Considerations...................................................... 22 AC Specifications.............................................................................. 4 Power Considerations................................................................ 23 Digital Specifications........................................................................ 5 Digital Outputs ........................................................................... 23 Switching Specifications .................................................................. 6 Timing ......................................................................................... 23 Explanation of Test Levels........................................................... 7 Operational Mode Selection ..................................................... 23 Absolute Maximum Ratings............................................................ 8 Evaluation Board........................................................................ 24 ESD Caution.................................................................................. 8 LVDS Evaluation Board Schematics ........................................ 25 Definitions of Specifications ........................................................... 9 LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30 Pin Configurations and Function Descriptions ......................... 10 CMOS Evaluation Board Schematics ...................................... 32 Equivalent Circuits ......................................................................... 14 CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 39 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 39 Analog Input and Reference Overview ................................... 20 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD9444 DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 1. AD9444BSVZ-80 Parameter Temp Test Level Unit Min Typ Max RESOLUTION Full VI 14 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV 1 Gain Error Full VI −3.0 ±0.4 +3.0 % FSR 2 Differential Nonlinearity (DNL) Full VI −0.8 ±0.4 +0.8 LSB 2 Integral Nonlinearity (INL) 25°C I −1.3 ±0.6 +1.3 LSB Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT Offset Error Full V 12 µV/°C Gain Error Full V 0.002 %FS/°C VOLTAGE REFERENCE 1 Output Voltage Full VI 0.87 1.0 1.13 V Load Regulation @ 1.0 mA Full V ±2 mV Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT Input Span Full V 2 V p-p Input Common-Mode Voltage Full V 3.5 V 3 Input Resistance Full V 1 kΩ 3 Input Capacitance Full V 2.5 pF POWER SUPPLIES Supply Voltage AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V Supply Current AVDD1 Full VI 217 240 mA 2 AVDD2 Full VI 71 80 mA 2 IDRVDD —LVDS Outputs Full VI 55 62 mA 2 IDRVDD —CMOS Outputs Full V 12 mA PSRR Offset Full V 1 mV/V Gain Full V 0.2 %/V POWER CONSUMPTION DC Input—LVDS Outputs Full VI 1.21 1.4 W DC Input—CMOS Outputs Full V 1.07 W 2 Sine Wave Input —LVDS Outputs Full VI 1.25 W 2 Sine Wave Input —CMOS Outputs Full V 1.11 W 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. Rev. 0 | Page 3 of 40 AD9444 AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 2. AD9444BSVZ-80 Parameter Temp Test Level Unit Min Typ Max SIGNAL-TO-NOISE-RATIO (SNR) f = 10 MHz 25°C IV 73.0 74.0 dB IN Full IV 72.7 dB f = 35 MHz 25°C I 72.4 73.7 dB IN Full IV 72.3 dB f = 70 MHz 25°C IV 72.3 73.1 dB IN Full IV 72.0 dB f = 100 MHz 25°C V 72.3 dB IN SIGNAL-TO-NOISE-AND DISTORTION (SINAD) f = 10 MHz 25°C IV 73.0 74.0 dB IN Full IV 72.7 dB f = 35 MHz 25°C I 72.4 73.7 dB IN Full IV 72.2 dB f = 70 MHz 25°C IV 72.2 73.1 dB IN Full IV 72.0 dB f = 100 MHz 25°C V 72.3 dB IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C V 12.1 Bits fIN = 35 MHz 25°C V 12.0 Bits fIN = 70 MHz 25°C V 11.9 Bits f = 100 MHz 25°C V 11.8 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz 25°C IV 91 97 dBc Full IV 87 dBc fIN = 35 MHz 25°C I 91 97 dBc Full IV 87 dBc fIN = 70 MHz 25°C IV 90 97 dBc Full IV 87 dBc fIN = 100 MHz 25°C V 96 dBc WORST HARMONIC, SECOND OR THIRD fIN = 10 MHz 25°C IV −97 −91 dBc Full IV −87 dBc fIN = 35 MHz 25°C I −97 −91 dBc Full IV −87 dBc fIN = 70 MHz 25°C IV −97 −90 dBc Full IV −87 dBc fIN = 100 MHz 25°C V −96 dBc WORST SPUR EXCLUDING SECOND OR HARMONICS f = 10 MHz 25°C IV −102 −93 dBc IN Full IV −93 dBc fIN = 35 MHz 25°C I −103 −93 dBc Full IV −93 dBc fIN = 70 MHz 25°C IV −102 −93 dBc Full IV −93 dBc fIN = 100 MHz 25°C V −99 dBc TWO-TONE SFDR f = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS 25°C V −102 dBFS IN f = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS 25°C V −100 dBFS IN ANALOG BANDWIDTH Full V 650 MHz Rev. 0 | Page 4 of 40 AD9444 DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted. Table 3. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full VI +200 µA Low Level Input Current Full VI −10 +10 µA Input Capacitance Full V 2 pF 1 DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR) DRVDD = 3.3 V High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) 2 V Differential Output Voltage Full VI 247 545 mV OD V Output Offset Voltage Full VI 1.125 1.375 V OS CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full IV 0.2 V Common-Mode Voltage Full VI 1.3 1.5 1.6 V Differential Input Resistance Full V 8 10 12 kΩ Differential Input Capacitance Full V 4 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. Rev. 0 | Page 5 of 40 AD9444 SWITCHING SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 10 MSPS CLK Period Full V 12.5 ns 1 CLK Pulse Width High (tCLKH) Full V 4 ns 1 CLK Pulse Width Low (tCLKL) Full V 4 ns DATA OUTPUT PARAMETERS 2 Output Propagation Delay—CMOS (tPD) (DX, DCO+) Full IV 3 5.25 8 ns 3 Output Propagation Delay—LVDS (tPD) (DX+, DCO+) Full VI 3 5 7.5 ns Pipeline Delay (Latency) Full V 12 Cycles Aperture Delay (t) Full V ns A Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS R = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition. TERM N–1 N N+1 A IN t CLKL t CLKH 1/f S CLK+ CLK– t PD N–11 N N+1 N–12 DATA OUT 12 CLOCK CYCLES DCO+ DCO– t CPD Figure 2. LVDS Mode Timing Diagram Rev. 0 | Page 6 of 40 05089-002 AD9444 N N–1 N+1 VIN N+2 t CLKL t CLKH CLK– CLK+ t PD 12 CYCLES DX N-12 N-11 N-1 N t DCOPD DCO+ DCO– Figure 3. CMOS Timing Diagram EXPLANATION OF TEST LEVELS Test Level Definitions I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. 0 | Page 7 of 40 05089-003 AD9444 ABSOLUTE MAXIMUM RATINGS Table 5. Thermal Resistance With The heat sink of the AD9444 package must be soldered to Parameter Respect to Min Max Unit ground. ELECTRICAL Table 6. AVDD1 AGND −0.3 +4 V Package Type θ θ θ Unit JA JB JC AVDD2 AGND −0.3 +6 V 100-Lead TQFP/EP 19.8 8.3 2 °C/W DRVDD DGND −0.3 +4 V AGND DGND −0.3 +0.3 V AVDD1 DRVDD −4 +4 V Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer AVDD2 DRVDD −4 +6 V board in still air. AVDD2 AVDD1 −4 +6 V D0 to D13 DGND –0.3 DRVDD + 0.3 V Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board CLK, MODE AGND –0.3 AVDD1 + 0.3 V in still air. VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V VREF AGND –0.3 AVDD1 + 0.3 V Typical θ = 2°C/W (junction to exposed heat sink) represents JC SENSE AGND –0.3 AVDD1 + 0.3 V the thermal resistance through heat-sink path. REFT, REFB AGND –0.3 AVDD1 + 0.3 V Airflow increases heat dissipation effectively reducing θ . Also, JA ENVIRONMENTAL more metal directly in contact with the package leads, from Storage Temperature –65 +125 °C metal traces, through holes, ground, and power planes, reduces Operating Temperature Range –40 +85 °C the θJA. It is required that the exposed heat sink be soldered to Lead Temperature Range 300 °C the ground plane. (Soldering 10 sec) Junction Temperature 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 40 AD9444 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) Minimum Conversion Rate The analog input frequency at which the spectral power of the The clock rate at which the SNR of the lowest analog signal fundamental frequency (as determined by the FFT analysis) is frequency drops by no more than 3 dB below the guaranteed reduced by 3 dB. limit. Aperture Delay (t ) Offset Error A The delay between the 50% point of the rising edge of the clock The major carry transition should occur for an analog value and the instant at which the analog input is sampled. ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point. Aperture Uncertainty (Jitter, t ) J The sample-to-sample variation in aperture delay. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input Clock Pulse Width and Duty Cycle after a transition from 10% above positive full scale to 10% Pulse width high is the minimum amount of time that the above negative full scale, or from 10% below negative full scale clock pulse should be left in the Logic 1 state to achieve rated to 10% below positive full scale. performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these Output Propagation Delay (t ) PD specifications define an acceptable clock duty cycle. The delay between the clock rising edge and the time when all bits are within valid logic levels. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB Power-Supply Rejection Ratio apart. DNL is the deviation from this ideal value. Guaranteed no The change in full scale from the value with the supply at the missing codes to 14-bit resolution indicates that all 16384 codes minimum limit to the value with the supply at its maximum limit. must be present over all operating ranges. Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) The ratio of the rms input signal amplitude to the rms value of The effective number of bits for a sine wave input at a given the sum of all other spectral components below the Nyquist input frequency can be calculated directly from its measured frequency, including harmonics but excluding dc. SINAD using the following formula Signal-to-Noise Ratio (SNR) () SINAD−1.76 The ratio of the rms input signal amplitude to the rms value of ENOB= the sum of all other spectral components below the Nyquist 6.02 frequency, excluding the first six harmonics and dc. Gain Error Spurious-Free Dynamic Range (SFDR) The first code transition should occur at an analog value ½ LSB The ratio of the rms signal amplitude to the rms value of the above negative full scale. The last transition should occur at an peak spurious spectral component. The peak spurious compo- analog value 1 ½ LSB below the positive full scale. Gain error is nent may or may not be a harmonic. May be reported in dBc the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code (i.e., degrades as signal level is lowered) or dBFS (always related transitions. back to converter full scale). Temperature Drift Integral Nonlinearity (INL) The temperature drift for offset error and gain error specifies The deviation of each individual code from a line drawn from the maximum change from the initial (25°C) value to the value negative full scale through positive full scale. The point used as at T or T . negative full scale occurs ½ LSB before the first code transition. MIN MAX Positive full scale is defined as a level 1 ½ LSBs beyond the last Total Harmonic Distortion (THD) code transition. The deviation is measured from the middle of The ratio of the rms input signal amplitude to the rms value of each particular code to the true straight line. the sum of the first six harmonic components. Maximum Conversion Rate Two-Tone SFDR The clock rate at which parametric testing is performed. The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Rev. 0 | Page 9 of 40 AD9444 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 75 DRVDD AVDD1 1 DNC 2 74 DRGND DNC 3 73 D10+ DNC 72 D10– 4 OUTPUT MODE 5 71 D9+ 70 D9– DFS 6 LVDSBIAS 7 69 D8+ AVDD1 68 8 D8– AVDD1 9 67 DRGND SENSE 10 66 D7+ 65 D7– VREF 11 AD9444 AGND 64 DCO+ 12 TOP VIEW 63 REFT 13 DCO– (Not to Scale) REFB 62 DRVDD 14 AGND 15 61 DRGND 60 D6+ AVDD1 16 AVDD1 17 59 D6– AVDD1 58 18 D5+ AVDD2 57 D5– 19 AGND 20 56 D4+ VIN+ 55 D4– 21 VIN– 22 54 DRVDD AGND 23 53 DRGND AVDD1 24 52 D3+ AVDD1 25 51 D3– DNC = DO NOT CONNECT Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode Rev. 0 | Page 10 of 40 AVDD1 26 100 DCS MODE AVDD1 27 AGND 99 AVDD2 28 98 AVDD1 AVDD2 29 97 AGND AVDD2 30 96 AGND AVDD2 31 95 AVDD1 AGND AVDD1 32 94 C1 33 93 AVDD1 AVDD1 34 92 AVDD1 AVDD1 35 91 AVDD1 CLK+ 36 90 AVDD1 CLK– 89 AVDD1 37 AVDD1 38 88 AGND AVDD2 39 87 AVDD1 AVDD2 86 40 AGND AVDD1 41 85 OR+ AVDD1 84 42 OR– (LSB) D0– 43 83 DRVDD D0+ 44 82 DRGND D1– 81 D13+ (MSB) 45 D1+ 46 80 D13– DRVDD 47 79 D12+ DRGND 48 D12– 78 D2– 49 77 D11+ D2+ 50 D11– 76 05089-004 AD9444 Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode Pin No. Mnemonic Description Pin No. Mnemonic Description 1, 8 to 9, AVDD1 3.3 V (±5%) Analog Supply. 44 D0+ D0 True Output Bit. 16 to 18, 45 D1− D1 Complement Output Bit. 24 to 27, 46 D1+ D1 True Output Bit. 34 to 35, 38, 47, 54, 62, DRVDD 3.3 V Digital Output Supply 41 to 42, 87, 75, 83 (3.0 V to 3.6 V). 89 to 95, 98 48, 53, 61, DRGND Digital Ground. 2 to 4 DNC Do Not Connect. These pins 67, 74, 82 should float. 49 D2− D2 Complement Output Bit. 5 OUTPUT CMOS Compatible Output Logic 50 D2+ D2 True Output Bit. MODE Mode Control Pin. OUTPUT MODE 51 D3− D3 Complement Output Bit. = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS 52 D3+ D3 True Output Bit. outputs. 55 D4− D4 Complement Output Bit. 6 DFS Data Format Select Pin. CMOS 56 D4+ D4 True Output Bit. control pin that determines the 57 D5− D5 Complement Output Bit. format of the output data. DFS = 58 D5+ D5 True Output Bit. high (AVDD1) for twos comple- 59 D6− D6 Complement Output Bit. ment, DFS = low (ground) for offset binary format. 60 D6+ D6 True Output Bit. 7 LVDSBIAS Set Pin for LVDS Output Current. 63 DCO− Data Clock Output—Complement. Place 3.7 kΩ resistor terminated to 64 DCO+ Data Clock Output—True. DRGND. 65 D7− D7 Complement Output Bit. 10 SENSE Reference Mode Selection. 66 D7+ D7 True Output Bit. Connect to AGND for internal 1 V 68 D8− D8 Complement Output Bit. reference, and connect to AVDD2 for external reference. 69 D8+ D8 True Output Bit. 11 VREF 1.0 V Reference I/O—Function 70 D9− D9 Complement Output Bit. Dependent on SENSE. Decouple 71 D9+ D9 True Output Bit. to ground with 0.1 µF and 10 µF 72 D10− D10 Complement Output Bit. capacitors. 73 D10+ D10 True Output Bit. 12, 15, 20, AGND Analog Ground. The exposed 76 D11− D11 Complement Output Bit. 23, 32, 86, heat sink on the bottom of the 77 D11+ D11 True Output Bit. 88, 96 to 97, package must be connected to 78 D12− D12 Complement Output Bit. 99, Exposed AGND. Heat Sink 79 D12+ D12 True Output Bit. 13 REFT Differential Reference Output. 80 D13− D13 Complement Output. Decoupled to ground with 0.1 µF 81 D13+ (MSB) D13 True Output Bit. capacitor and to REFB (Pin 14) with 84 OR− Out-of-Range Complement 0.1 µF and 10 µF capacitors. Output Bit. 14 REFB Differential Reference Output. 85 OR+ Out-of-Range True Output Bit. Decoupled to ground with a 0.1 µF 100 DCS MODE Clock Duty Cycle Stabilizer (DCS) capacitor and to REFT (Pin 13) with Control Pin, CMOS-Compatible. 0.1 µF and 10 µF capacitors. DCS = low (AGND) to enable DCS 19, 28 to 31, AVDD2 5.0 V Analog Supply (±5%). (recommended). DCS = high 39 to 40 (AVDD1) to disable DCS. 21 VIN+ Analog Input—True. 22 VIN− Analog Input—Complement. 33 C1 Internal Bypass Node. Connect a 0.1 µF capacitor from this pin to AGND. 36 CLK+ Clock Input—True. 37 CLK− Clock Input—Complement. 43 D0− (LSB) D0 Complement Output Bit (LVDS Levels). Rev. 0 | Page 11 of 40 AD9444 AVDD1 75 DRVDD 1 DNC 2 74 DRGND 73 DNC 3 D6 DNC 4 72 D5 OUTPUT MODE 5 71 D4 DFS 6 70 D3 69 DNC 7 D2 AVDD1 68 8 D1 AVDD1 9 67 DRGND SENSE 10 66 D0 (LSB) VREF 65 DNC 11 AD9444 AGND 12 64 DCO+ TOP VIEW 63 REFT 13 DCO– (Not to Scale) REFB 14 62 DRVDD AGND 61 15 DRGND AVDD1 60 DNC 16 59 AVDD1 17 DNC AVDD1 58 18 DNC AVDD2 19 57 DNC 56 AGND 20 DNC VIN+ 55 DNC 21 54 VIN– 22 DRVDD AGND 53 23 DRGND AVDD1 24 52 DNC 51 AVDD1 25 DNC DNC = DO NOT CONNECT Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode Rev. 0 | Page 12 of 40 AVDD1 DCS MODE 26 100 AVDD1 27 AGND 99 AVDD2 28 98 AVDD1 AVDD2 29 AGND 97 AVDD2 30 AGND 96 AVDD2 31 95 AVDD1 AGND AVDD1 32 94 C1 33 93 AVDD1 AVDD1 34 92 AVDD1 AVDD1 AVDD1 35 91 CLK+ 36 90 AVDD1 CLK– 37 89 AVDD1 AVDD1 38 88 AGND AVDD2 39 87 AVDD1 AVDD2 40 86 AGND AVDD1 41 85 OR AVDD1 42 84 D13 (MSB) DNC 83 43 DRVDD DNC 44 82 DRGND DNC 45 81 D12 DNC 46 80 D11 DRVDD 47 79 D10 DRGND 48 78 D9 DNC 49 77 D8 DNC 50 76 D7 05089-005 AD9444 Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic Description Pin No. Mnemonic Description 1, 8 to 9, 16 to 18, AVDD1 3.3 V (±5%) Analog Supply. 33 C1 Internal Bypass Node. 24 to 27, 34 to 35, Connect a 0.1 µF capacitor 38, 41 to 42, 87, from this pin to AGND. 89 to 95, 98 36 CLK+ Clock Input—True. 2 to 4, 7, DNC Do Not Connect. These 37 CLK− Clock Input—Complement. 43 to 46, 49 to 52, pins should float. 47, 54, 62, DRVDD 3.3 V Digital Output 55 to 60, 65 75, 83 Supply (2.5V to 3.6 V). 5 OUTPUT CMOS Compatible Output 48, 53, 61, DRGND Digital Ground. MODE Logic Mode Control Pin. 67, 74, 82 OUTPUT MODE = 0 for CMOS 63 DCO− Data Clock Output— mode, and OUTPUT MODE = Complement (CMOS Levels). 1 (AVDD1) for LVDS outputs. 64 DCO+ Data Clock Output— 6 DFS Data Format Select Pin. True. CMOS control pin that de- 66 D0 (LSB) D0 Output Bit (LSB) termines the format of the (CMOS Levels). output data. DFS = high 68 D1 D1 Output Bit. (AVDD1) for twos comple- ment, DFS = low (ground) for 69 D2 D2 Output Bit. offset binary format. 70 D3 D3 Output Bit. 10 SENSE Reference Mode Selection. 71 D4 D4 Output Bit. Connect to AGND for internal 72 D5 D5 Output Bit. 1 V reference, and connect to 73 D6 D6 Output Bit. AVDD2 for external reference. 76 D7 D7 Output Bit. 11 VREF 1.0 V Reference I/O— Function Dependent on 77 D8 D8 Output Bit. SENSE. Decouple to ground 78 D9 D9 Output Bit. with 0.1 µF and 10 µF 79 D10 D10 Output Bit. capacitors. 80 D11 D11 Output Bit. 12, 15, 20, 23, AGND Analog Ground. The exposed 81 D12 D12 Output Bit. 32, 86, 88, 96 to heat sink on the bottom of 84 D13 (MSB) D13 Output Bit. 97, 99, Exposed the package must be Heat Sink connected to AGND. 85 OR Out-of-Range Output. 13 REFT 100 DCS MODE Clock Duty Cycle Stabilizer Differential Reference Out- (DCS) Control Pin, CMOS- put. Decoupled to ground Compatible. DCS = low with 0.1 µF capacitor and to REFB (Pin 14) with 0.1 µF and (AGND) to enable DCS 10 µF capacitors. (recommended). DCS = high (AVDD1) to disable DCS. 14 REFB Differential Reference Out- put. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 13) with 0.1 µF and 10 µF capacitors. 19, 28 to 31, AVDD2 5.0 V Analog Supply (±5%). 39 to 40 21 VIN+ Analog Input—True. 22 VIN− Analog Input—Complement. Rev. 0 | Page 13 of 40 AD9444 EQUIVALENT CIRCUITS AVDD2 DRVDD VIN+ AVDD2 2.5pF 1kΩ DX 3.5V X1 SHA 1kΩ AVDD2 Figure 9. Equivalent CMOS Digital Output Circuit VIN– VDD 2.5pF Figure 6. Equivalent Analog Input Circuit DRVDD DRVDD DCS MODE, OUTPUT MODE, DFS 30kΩ K 1.2V LVDSBIAS 3.74kΩ I LVDSOUT Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE Figure 7. Equivalent LVDS BIAS Circuit AVDD2 DRVDD 12kΩ 12kΩ CLK+ CLK– V V 150Ω 150Ω DX– DX+ 10kΩ 10kΩ V V Figure 8. Equivalent LVDS Digital Output Circuit Figure 11. Equivalent Sample Clock Input Circuit Rev. 0 | Page 14 of 40 05089-008 05089-007 05089-006 05089-009 05089-010 05089-011 AD9444 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted. 0 0 80MSPS 80MSPS 10.1MHz @ –0.5dBFS 100.3MHz @ –0.5dBFS SNR: 73.9dB SNR: 72.3dB –20 –20 ENOB: 12.0BITS ENOB: 11.8BITS SFDR: 97dBc SFDR: 96dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. 64K Point Single-Tone FFT/80 MSPS/10.1 MHz Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz 0 0 80MSPS 80MSPS 125MHz @ –0.5dBFS 30.3MHz @ –0.5dBFS SNR: 71.2dB SNR: 74.0dB –20 –20 ENOB: 11.6BITS ENOB: 12.1BITS SFDR: 91dBc SFDR: 95dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. 64K Point Single-Tone FFT/80 MSPS/30.3 MHz Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz 0 0 80MSPS 80MSPS 70.3MHz @ –0.5dBFS 151MHz @ –0.5dBFS SNR: 73.3dB SNR: 71.1dB –20 –20 ENOB: 11.9BITS ENOB: 11.5BITS SFDR: 100dBc SFDR: 87dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. 64K Point Single-Tone FFT/80 MSPS/70 MHz Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz Rev. 0 | Page 15 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05089-014 05089-013 05089-012 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05089-017 05089-016 05089-015 AD9444 75 75 SNR dB @ –40°C 74 74 SNR dB @ –40°C 73 73 SNR dB @ +25°C 72 72 SNR dB @ +85°C SNR dB @ +25°C 71 71 SNR dB @ +85°C 70 70 69 69 68 68 67 67 66 66 65 65 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode Figure 21. SNR vs. Analog Input Frequency, 80 MSPS/CMOS Mode 105 105 SFDR dBc @ +85°C SFDR dBc @ +85°C SFDR dBc @ +25°C 100 100 SFDR dBc @ +25°C 95 95 SFDR dBc @ –40°C 90 90 SFDR dBc @ –40°C 85 85 80 80 75 75 70 70 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode Figure 22. SFDR vs. Analog Input Frequency, 80 MSPS/CMOS Mode 120 120 SECOND –dBFS THIRD –dBFS SECOND –dBFS THIRD –dBFS 110 110 100 100 90 SFDR –dBFS 90 SECOND –dBc 80 80 SFDR –dBFS THIRD –dBc 70 70 SFDR –dBFS SECOND –dBc 60 60 50 50 THIRD –dBc 40 40 SFDR –dBFS 30 30 20 20 10 10 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT AMPLITUDE (dBc) ANALOG INPUT AMPLITUDE (dBc) Figure 20. Single-Tone SFDR/Second/Third vs. Figure 23. Single-Tone SFDR/Second/Third vs. Analog Input Level, 80 MSPS, AIN = 30.3 MHz Analog Input Level 80 MSPS, AIN = 70.30 MHz Rev. 0 | Page 16 of 40 (dB) (dB) (dB) 05089-020 05089-019 05089-018 (dB) (dB) (dB) 05089-023 05089-021 05089-022 AD9444 0 0 SFDR: 102dBFS –10 90dBFS REFERENCE LINE –20 –20 –30 SFDR (dBc) –40 –40 –50 –60 –60 WORST THIRD-ORDER IMD (dBc) –70 –80 –80 –90 SFDR (dBFS) –100 –100 –110 WORST THIRD-ORDER IMD (dBFS) –120 –120 0 5 10 15 20 25 30 35 40 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 27. Two-Tone SFDR vs. Analog Input Level, AIN = 9.8 MHz/10.8 MHz Figure 24. 32K Point Two-Tone FFT 80 MSPS/9.8 MHz/10.8 MHz 0 0 SFDR: –100dBFS –10 –10 90dBFS REFERENCE LINE –20 –20 –30 –30 –40 SFDR (dBc) –40 –50 –50 –60 –60 WORST THIRD-ORDER IMD (dBc) –70 –70 –80 –80 SFDR (dBFS) –90 –90 –100 –100 –110 –110 WORST THIRD-ORDER IMD (dBFS) –120 –120 0 5 10 15 20 25 30 35 40 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 25. 32K Point Two-Tone FFT 80 MSPS/69.3 MHz/70.3 MHz Figure 28. Two-Tone SFDR vs. Analog Input Level, AIN = 69.3 MHz/70.3 MHz 100 100 95 95 90 90 85 85 80 80 75 75 70 70 20 30 40 50 60 70 80 90 100 110 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) Figure 26. SFDR vs. Sample Rate, VIN = 10.3 MHz @ −0.5 dBFS Figure 29. SFDR vs. Sample Rate, V = 70.3 MHz @ −0.5 dBFS IN Rev. 0 | Page 17 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR (dB) 05089-026 05089-025 05089-024 SFDR AND IMD3 (dB) IMD (dBFS) SFDR (dB) 05089-029 05089-028 05089-027 AD9444 0 12000 61.44MSPS –10 TOTAL INPUT SIGNAL POWER: –30dBFS –20 10000 –30 –40 8000 –50 –60 6000 –70 –80 4000 –90 –100 2000 –110 –120 0 –130 8179 8180 8181 8182 8183 8184 8185 8186 8187 0 7.68 15.36 23.04 30.72 B IN FREQUENCY (MHz) Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz Figure 33. Ground Input Histogram 80 MSPS, VIN+ = VIN−, 32K Samples 0 250 NPR: 63.1dB –10 230 –20 210 –30 190 –40 AVDD1 (3.3V) –50 170 –60 150 –70 130 –80 –90 110 –100 90 –110 DRVDD (3.3V) AVDD2 (5.0V) 70 –120 –130 50 20 30 40 50 60 70 80 90 100 110 120 130 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 31. NPR, 80 MSPS/18 MHz Notch Figure 34. I vs. Sample Rate, A = 10.3 MHz @ −0.5 dBFS SUPPLY IN 105 100 SFDR (dBc) SFDR - DCS ON (dBFS) 95 100 90 95 SFDR - DCS OFF (dBFS) 85 90 80 85 75 SNR (dB) 80 70 75 SNR - DCS ON (dB) 65 SNR - DCS OFF (dB) 60 70 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 20 30 40 50 60 70 80 CLOCK DUTY CYCLE (%) V COMMON-MODE (V) IN Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle, Figure 35. Single-Tone SNR/SFDR vs. FSAMPLE = 80 MSPS, 10.3 MHz @ −0.5 dBFS VIN Common-Mode Voltage 80 MSPS/10.3 MHz Rev. 0 | Page 18 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) dB 05089-032 05089–031 05089-030 CURRENT (mA) FREQUENCY (dB) 05089-035 05089-034 05089-033 AD9444 0.961 0.2 0.960 0.1 0.959 0 0.958 0.957 –0.1 0.956 –0.2 0.955 0.954 –0.3 0.953 –0.4 0.952 0.951 –0.5 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 36. VREF vs. Temperature Figure 38. Gain vs. Temperature 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 OUTPUT CODE OUTPUT CODE Figure 37. DNL Error vs. Output Code, 80 MSPS, A = 15 MHz IN Figure 39. INL Error vs. Output Code, 80 MSPS, AIN = 15 MHz Rev. 0 | Page 19 of 40 DNL ERROR (LSB) REFERENCE VOLTAGE (V) 05089-036 05089-037 INL ERROR (LSB) GAIN (%FS) 05089-038 05089-039 AD9444 THEORY OF OPERATION Internal Reference Trim The AD9444 architecture is optimized for high speed and ease The internal reference voltage is trimmed during the produc- of use. The analog inputs drive an integrated, high bandwidth, tion test to adjust the gain (analog input voltage range) of the track-and-hold circuit that samples the signal prior to quantiza- AD9444. Therefore, there is little advantage to the user supply- tion by the 14-bit pipeline ADC core. The device includes an ing an external voltage reference to the AD9444. The gain trim on-board reference and input logic that accepts TTL, CMOS, or is performed with the AD9444’s input range set to 2 V p-p LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the nominal (SENSE connected to AGND). Because of this trim, OUTPUT MODE pin. and because the 2 V p-p analog input range provides maximum ac performance, there is little benefit to using analog input ANALOG INPUT AND REFERENCE OVERVIEW ranges < 2 V p-p. Users are cautioned that the differential A stable and accurate 0.5 V voltage reference is built into the nonlinearity of the ADC varies with the reference voltage. AD9444. The input range can be adjusted by varying the refer- Configurations that use < 2 V p-p may exhibit missing codes ence voltage applied to the AD9444, using either the internal and, therefore, degraded noise and distortion performance. reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The VIN+ various reference modes are described in the next few sections. VIN– REFT Internal Reference Connection 0.1µF + ADC A comparator within the AD9444 detects the potential at the 0.1µF 10µF CORE SENSE pin and configures the reference into four possible REFB states, which are summarized in Table 9. If SENSE is grounded, 0.1µF VREF the reference amplifier switch is connected to the internal resis- + 10µF 0.1µF tor divider (see Figure 40), setting VREF to ~1 V. Connecting SELECT the SENSE pin to VREF switches the reference amplifier output LOGIC to the SENSE pin, completing the loop and providing a ~0.5 V SENSE reference output. If a resistor divider is connected, as shown in 0.5V Figure 41, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF AD9444 output defined as R2 ⎛ ⎞ Figure 40. Internal Reference Configuration VREF= 0.5× 1+ ⎜ ⎟ R1 ⎝ ⎠ VIN+ In all reference configurations, REFT and REFB drive the A/D VIN– REFT conversion core and establish its input span. The input range of 0.1µF the ADC always equals twice the voltage at the reference pin for ADC + 0.1µF 10µF CORE either an internal or an external reference. REFB 0.1µF VREF + 10µF 0.1µF SELECT R2 LOGIC SENSE R1 0.5V AD9444 Figure 41. Programmable Reference Configuration Rev. 0 | Page 20 of 40 05089-043 05089-042 AD9444 Table 9. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 2 × VREF R2 ⎛ ⎞ (See Figure 41) 0.5× 1+ ⎜ ⎟ R1 ⎝ ⎠ Internal Fixed Reference AGND to 0.2 V 1.0 2.0 External Reference Operation The AD9444’s internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to be VIN+ improved. Figure 36 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. 1Vp-p 3.5V When the SENSE pin is tied to AVDD, the internal reference is VIN– disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference Figure 42. Differential Analog Input Range for VREF = 1 V voltage; therefore, the external reference must be limited to a maximum of 1 V. The AD9444 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 kΩ resistor to Analog Inputs the 3.5 V bias voltage and to the input of a differential buffer. As with most new high speed, high dynamic range ADCs, the The internal bias network on the input properly biases the analog input to the AD9444 is differential. Differential inputs buffer for maximum linearity and range (see the Equivalent improve on-chip performance as signals are processed through Circuits section). Therefore, the analog source driving the attenuation and gain stages. Most of the improvement is a result AD9444 should be ac-coupled to the input pins. The recom- of differential analog stages having high rejection of even-order mended method for driving the analog input of the AD9444 is harmonics. There are also benefits at the PCB level. First, to use an RF transformer to convert single-ended signals to differential inputs have high common-mode rejection of stray differential (see Figure 44). Series resistors between the output signals, such as ground and power noise. Second, they provide of the transformer and the AD9444 analog inputs help isolate good rejection of common-mode signals, such as local oscillator the analog input source from switching transients caused by the feedthrough. The specified noise and distortion of the AD9444 internal sample-and-hold circuit. The series resistors, along with cannot be realized with a single-ended analog input, so such the 1 kΩ resisters connected to the internal 3.5 V bias, must be configurations are discouraged. Contact ADI for recommenda- considered in impedance matching the transformers input. For tions of other 14-bit ADCs that support single-ended analog example, if R were set to 51 Ω and R were set to 33 Ω, along T S input configurations. with a 1:1 impedance ratio transformer, the input would match a 50 Ω source with a full-scale drive of 10.0 dBm. The 50 Ω With the 1 V reference (nominal value, see the Internal Refer- impedance matching can also be incorporated on the secondary ence Trim section), the differential input range of the AD9444’s side of the transformer, as shown in the evaluation board sche- analog input is nominally 2 V p-p or 1 V p-p on each input matic (see Figure 47 and Figure 59). (VIN+ or VIN−). R ADT1–1WT S ANALOG AIN INPUT R T SIGNAL AD9444 R S AIN 0.1µF Figure 43. Transformer-Coupled Analog Input Circuit Rev. 0 | Page 21 of 40 05089-046 05089-045 AD9444 CLOCK INPUT CONSIDERATIONS the CLK+ and CLK− pins via a transformer or capacitors. Figure 44 shows one preferred method for clocking the AD9444. Any high speed ADC is extremely sensitive to the quality of the The clock source (low jitter) is converted from single-ended-to- sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on differential using an RF transformer. The back-to-back Schottky the clock is combined with the desired signal at the A/D output. diodes across the transformer secondary limit clock excursions For that reason, considerable care was taken in the design of the into the AD9444 to approximately 0.8 V p-p differential. This clock inputs of the AD9444, and the user is advised to give helps prevent the large voltage swings of the clock from feeding careful thought to the clock source. through to other portions of the AD9444 and limits the noise presented to the sample clock inputs. Typical high speed ADCs use both clock edges to generate a If a low jitter clock is available, another option is to ac couple a variety of internal timing signals and, as a result, may be differential ECL/PECL signal to the encode input pins, as shown sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic perform- in Figure 46. ance characteristics. The AD9444 contains a clock duty cycle ADT1–1WT CLOCK CLK+ stabilizer (DCS) that retimes the nonsampling edge, providing SOURCE 0.1µF AD9444 an internal clock signal with a nominal 50% duty cycle. As CLK– shown in Figure 32, noise and distortion performance are nearly HSMS2812 DIODES flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing Figure 44. Crystal Clock Oscillator, Differential Encode internally. This allows for a wide range of input duty cycles at VT the input without degrading performance. Jitter in the rising 0.1µF edge of the input is still of paramount concern and is not re- ENCODE duced by the internal stabilization circuit. The duty cycle con- ECL/ AD9444 PECL 0.1µF trol loop does not function for clock rates less than 30 MHz ENCODE nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can VT change dynamically, which requires a wait time of 1.5 µs to 5 µs Figure 45. Differential ECL for Encode after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time Jitter Considerations period the loop is not locked, the DCS loop is bypassed, and the High speed, high resolution ADCs are sensitive to the quality internal device timing is dependant on the duty cycle of the of the clock input. The degradation in SNR at a given input input clock signal. In such an application, it may appropriate to frequency (fINPUT) and rms amplitude due only to aperture jitter disable the duty cycle stabilizer. In all other applications, (tJ) can be calculated using the following equation. enabling the DCS circuit is recommended to maximize ac performance. SNR = 20 log[2πfINPUT × tJ] The DCS circuit is controlled by the DCS MODE pin; a CMOS In the equation, the rms aperture jitter represents the root-mean logic low (AGND) on DCS MODE enables the duty cycle stabi- square of all jitter sources, which includes the clock input, lizer, and logic high (AVDD1 = 3.3 V) disables the controller. analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, The AD9444 input sample clock signal must be a high quality, see Figure 46. extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on The clock input should be treated as an analog signal in cases the encode clock phase noise. SNR performance can easily where aperture jitter may affect the dynamic range of the degrade by 3 dB to 4 dB with 70 MHz analog input signals AD9444. Power supplies for clock drivers should be separated when using a high jitter clock source. (See AN-501, Aperture from the ADC output driver supplies to avoid modulating the Uncertainty and ADC System Performance, for complete clock signal with digital noise. Low jitter, crystal-controlled details.) For optimum performance, the AD9444 must be oscillators make the best clock sources. If the clock is generated clocked differentially. The sample clock inputs are internally from another type of source (by gating, dividing, or other meth- biased to ~2.2 V, and the input signal is usually ac-coupled into ods), it should be retimed by the original clock at the last step. Rev. 0 | Page 22 of 40 05089-048 05089-047 AD9444 75 tion resistor placed at the LVDS receiver inputs results in a 0.2ps nominal 350 mV swing at the receiver. LVDS mode facilitates 70 interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance 65 0.5ps in noisy environments. Single point-to-point net topologies are 60 recommended with a 100 Ω termination resistor as close to the 1.0ps receiver as possible. It is recommended to keep the trace length 1.5ps 55 less than 1 inch to 2 inches and to keep differential output trace 2.0ps 2.5ps lengths as equal as possible. 50 3.0ps CMOS Mode 45 In applications that can tolerate a slight degradation in dynamic performance, the AD9444 output drivers can be configured to 40 1 10 100 1000 interface with 2.5 V or 3.3 V logic families by matching DRVDD INPUT FREQUENCY (MHz) to the digital supply of the interfaced logic. CMOS outputs are Figure 46. SNR vs. Input Frequency and Jitter available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits are single- POWER CONSIDERATIONS ended CMOS, DX, as is the overrange output, OR. The output Care should be taken when selecting a power source. The use of clock is provided as a differential CMOS signal, DCO+/DCO−. linear dc supplies is highly recommended. Switching supplies Lower supply voltages are recommended to avoid coupling tend to have radiated components that may be received by the switching transients back to the sensitive analog sections of the AD9444. Each of the power supply pins should be decoupled as ADC. The capacitive load to the CMOS outputs should be closely to the package as possible using 0.1 µF chip capacitors. minimized, and each output should be connected to a single The AD9444 has separate digital and analog power supply gate through a series resistor (220 Ω) to minimize switching transients caused by the capacitive loading. pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V) and the digital supply pins are denoted DRVDD. TIMING Although the AVDD1 and DRVDD supplies may be tied The AD9444 provides latched data outputs with a pipeline delay together, best performance is achieved when the supplies are of 12 clock cycles. Data outputs are available one propagation separate. This is because the fast digital output swings can delay (t ) after the rising edge of CLK+. Refer to Figure 2 and couple switching current back into the analog supplies. Note PD Figure 3 for detailed timing diagrams. that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. OPERATIONAL MODE SELECTION Data Format Select The DRVDD supply of the AD9444 is a dedicated supply for the digital outputs, in either LVDS or CMOS output modes. When The data format select (DFS) pin of the AD9444 determines in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS the coding format of the output data. This pin is 3.3 V CMOS mode, the DRVDD supply may be connected from 2.5 V to compatible, with logic high (or AVDD1, 3.3 V) selecting twos 3.6 V to be compatible with the receiving logic. complement, and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding. DIGITAL OUTPUTS Output Mode Select LVDS Mode The OUPUT MODE pin controls the logic compatibility, The off-chip drivers on the chip can be configured to provide as well as the pinout of the digital outputs. This pin is a CMOS LVDS-compatible output levels via Pin 5 (OUTPUT MODE). compatible input. With OUTPUT MODE = 0 (AGND), the LVDS outputs are available when OUTPUT MODE is CMOS AD9444 outputs are CMOS-compatible and the pin assignment logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET for the device is defined in Table 8. With OUTPUT MODE = 1 resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic (AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and performance, including both SFDR and SNR, is maximized the pin assignment for the device is defined in Table 7. when the AD9444 is used in LVDS mode, and designers are encouraged to take advantage of this mode. The AD9444 out- Duty Cycle Stabilizer puts include complimentary LVDS outputs for each data bit The DCS circuit is controlled by the DCS MODE pin; a CMOS (DX+/DX−), the overrange output (OR+/OR−), and the output logic low (AGND) on DCS MODE enables the DCS, and logic data clock output (DCO+/DCO−). The RSET resistor current is high (AVDD1, 3.3 V) disables the controller. ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 × I ). A 100 Ω differential termina- R SET Rev. 0 | Page 23 of 40 SNR (dBc) 05089-049 AD9444 Table 10. Digital Output Coding VIN+ − VIN− VIN+ − VIN− Digital Output Digital Output Code Input Span = 2 V p-p (V) Input Span = 1 V p-p (V) Offset Binary (D9••••••D0) Twos Complement (D9••••••D0) 16383 1.000 0.500 11 1111 1111 1111 01 1111 1111 1111 8192 0 0 10 0000 0000 0000 00 0000 0000 0000 8191 −0.000122 −0.000061 01 1111 1111 1111 11 1111 1111 1111 0 −1.00 −0.5000 00 0000 0000 0000 10 0000 0000 0000 EVALUATION BOARD Both the LVDS and CMOS versions of the evaluation board are compatible with the high speed ADC FIFO evaluation kit (part Evaluation boards are offered to configure the AD9444 in number HSC-ADC-EVALA-SC). The kit includes a high speed either CMOS or LVDS mode. Each represents a recommended data capture board that provides a hardware solution for captur- configuration for using the device over a wide range of sample ing up to 32Ksamples of high speed ADC output data in a FIFO rates and analog input frequencies. These evaluation boards memory chip (user upgradeable to 256K samples). Software is provide all the support circuitry required to operate the ADC in provided to enable the user to download the captured data to a its various modes and configurations. Complete schematics and PC via the USB port. This software also includes a behavioral layout plots follow and demonstrate the proper routing and model of the AD9444 and many other high speed ADCs. grounding techniques that should be applied at the system level. Behavioral modeling of the AD9444 is also available at It is critical that signal sources with very low phase noise www.analog.com/ADIsimADC. The ADIsimADC™ software (< 1 ps rms jitter) be used to realize the ultimate performance supports virtual ADC evaluation using ADI proprietary of the converter. Proper filtering of the input signal, to remove behavioral modeling technology. This allows rapid comparison harmonics and lower the integrated noise at the input, is also between the AD9444 and other high speed ADCs, with or necessary to achieve the specified noise performance. without hardware evaluation boards. The evaluation boards are shipped with an ac to 6 V dc power The AD9444 LVDS evaluation board includes an on-board, supply. The evaluation boards include low dropout regulators to LVDS-to-CMOS translator, but the user may choose to remove generate the various dc supplies required by the AD9444 and its the translator and terminations to access the LVDS outputs support circuitry. Separate power supplies are provided to iso- directly. late the DUT from the support circuitry. Each input configura- The CMOS evaluation board includes a buffer for the output tion can be selected by proper connection of various jumpers data and the DCO output clock of the AD9444. (see Figure 47 to Figure 50 and Figure 59 to Figure 61). Rev. 0 | Page 24 of 40 AD9444 LVDS EVALUATION BOARD SCHEMATICS GND H4 8 MTHOLE6 7 VDL GND 6 H3 DRVDD 5 MTHOLE6 GND 4 H2 VCC 3 GND MTHOLE6 2 1 5V H1 MTHOLE6 GND 76 50 D11_C/D7_YN D11– D2+ D2_TN 77 49 D2– D11_T/D8_YN D11+ D2_CN 78 48 D12_C/D9_YN D12– DRGND GND 79 47 D12+ DRVDD D12_T/D10_YN DRVDD 80 46 D13_C/D11_YN D13– D1+ D1_TN 81 45 D1– D13_T/D12_YN D13+ (MSB) D1_CN 82 44 GND DRGND D0+ D0_TN 83 43 DRVDD DRVDD (LSB) D0– D0_CN 84 42 DOR_C/D13_YN OR– AVDD1 VCC 85 41 DOR_T/DOR_YN OR+ AVDD1 VCC 86 40 GND AGND AVDD2 87 39 1 VCC AVDD1 AVDD2 5V 88 38 3 GND AGND AVDD1 VCC 89 37 2 VCC AVDD1 CLK– ENCB 90 36 VCC AVDD1 CLK+ ENC 91 35 CR2 VCC AVDD1 AVDD1 VCC 92 34 VCC AVDD1 AVDD1 VCC 93 33 AVDD1 VCC C1 GND 94 32 VCC AVDD1 AGND GND C40 95 31 0.1µF VCC AVDD1 AVDD2 96 30 GND AGND AVDD2 97 29 AGND GND AVDD2 98 28 AVDD1 AVDD2 5V 99 27 AGND AVDD1 VCC 100 26 DCS MOD AVDD1 VCC R39 XX C36 EPAD 101 0.1µF C26 0.1µF 50Ω R7 50Ω R8 XTALINPUTB C2 0.1µF R28 OPTIONAL 33Ω 33Ω R35 C51 C91 10µF C3 0.1µF C9 0.1µF 0.1µF GND C24 R37 0.1µF XX R27 XX + R36 R20 XX XX R1 R2 3.8kΩ 3.8kΩ R3 3.8kΩ Figure 47. LVDS Mode Evaluation Board Schematic Rev. 0 | Page 25 of 40 ENCODE OPTIONAL ENCODE CIRCUITS GND VXTAL GND + C44 C93 C92 E47 5V P5 10µF 0.1µF 0.1µF ENC VXTAL XTALINPUT E52 E46 VCC J5 T3 GND ADT1-1WT 1 6 GND C42 U6 2 NC 5 ECLOSC J1 VXTAL 3 4 GND 0.1µF ENCODE PRI SEC 8 GND 14 XTALOUTB VXTAL VCC OUT ENCB 1 GND XTALOUT 7 GND VEE ~OUT GND R38 R40 GND VXTAL GND XX XX R12 R17 VCC FOR VECTRON XTAL 1kΩ XX XTALINPUTB JN00158 R9 GND 1 6 VCC E/D VCC VXTAL E39 1kΩ XTALINPUT 2 5 XTALOUTB E38 NC OUTPUTB 3 4 FOR VF XTAL GND XTALOUT GND OUTPUT GND E40 R18 GND XX R19 U2 XX GND R15 1 75 DRVDD VCC AVDD1 DRVDD 1kΩ 2 74 GND DNC DRGND VCC 3 73 E3 D10_T/D6_YN DNC D10+ E1 4 72 D10_C/D5_YN DNC D10– R14 5 71 GND E2 D9_T/D4_YN GND OUTPUT MODE D9+ 1kΩ 6 70 DFS D9– D9_C/D3_YN 69 7 D8_T/D2_YN LVDSBIAS/DNC D8+ 68 C86 8 VCC AVDD1 D8_C/D1_YN D8– GND GND 9 67 E26 VCC GND VCC AVDD1 DRGND 0.1µF E25 10 66 SENSE D7+ D7_T/D0_YN E27 65 11 E41 VREF D7– D7_CN AD9444 E20 64 E24 12 U1 GND AGND DCO+ DRN EXTREF EXTREF 13 63 PIN DEFINITIONS GND REFT DCO– DRBN 14 LVDS/CMOS 62 REFB DRVDD DRVDD C39 15 61 GND GND GND GND AGND DRGND 16 60 10µF VCC AVDD1 D6+ D6_TN GND 17 59 VCC AVDD1 D6– D6_CN 18 58 GND AVDD1 VCC D5+ D5_TN 19 57 5V AVDD2 D5– D5_CN 56 T5 20 GND AGND D4+ D4_TN ADT1-1WT TOUT 21 55 D4– GND VIN+ D4_CN 1 6 22 54 VIN– DRVDD DRVDD 5 2 NC GND 23 53 GND AGND DRGND GND 3 4 GND C12 R4 24 52 D3+ VCC AVDD1 D3_TN R5 0.1µF 36Ω 25 51 D3– xx VCC AVDD1 D3_CN J4 100Ω TOUTB C13 R13 TINB 20pF L1 xx C5 E15 R6 0.1µF 36Ω GND ANALOG GND 05089-050 AD9444 POWER OPTIONS ADP3338 ADP3338 U4 U15 P4 3.3V 3.3V PJ-102A 1 1 2 GND GND 2 2 2 3 4 4 OUT1 OUT1 3 OUT OUT 3 3 1 IN IN 1 + C1 + C6 + C33 10µF 10µF 10µF + C57 + C87 10µF 10µF ADP3338 ADP3338 U3 U14 3.3V 5V 1 1 GND GND 2 2 4 4 OUT1 OUT1 OUT OUT 3 3 IN IN + + C34 C4 10µF 10µF + C88 + C89 10µF 10µF Figure 48. LVDS Mode Evaluation Board Schematic (Continued) VCC + P19 C43 C35 C32 C30 C28 C27 C48 C50 C60 C61 C46 C75 C64 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF GND 10µF GND VCC C10 C11 C14 C17 C16 C15 C31 C37 C38 C29 C19 C18 C90 XX XX XX XX XX XX XX XX XX XX XX XX XX GND DRVDD DRVDD + C65 C47 C23 C22 C21 C20 C69 C70 C45 C49 C59 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF XX XX XX XX XX GND GND 5V EXTREF 5V + + C55 C71 C72 C73 C62 C56 C85 C53 C52 C58 10µF XX XX XX XX 10µF 0.1µF 0.1µF 0.1µF 0.1µF GND GND GND Figure 49. LVDS Mode Evaluation Board Schematic (Continued) Rev. 0 | Page 26 of 40 DRVDD VDL GND GND GND GND GND GND DRVDD VDL VIN VIN 5V VCC GND GND GND GND GND GND 5V VCC VIN VIN GND GND VIN 05089-051 05089-052 AD9444 U7 SN75LVDS386 1 64 DOR_T/DOR_YN A1A GND GND 2 63 RZ5 220 P6 DOR_C/D13_YN A1B VCC1 VDL RSO16ISO 3 62 C40MS D13_T/D12_YN A2A VCC2 VDL 4 61 R1 1 16 D13_C/D11_YN A2B GND1 GND ORO 5 60 39 40 D12_T/D10_YN A3A ENA VDL R2 P39 GND P40 GND 6 59 2 15 D12_C/D9_YN D13O A3B A1Y 37 38 7 58 P37 R3 P38 D11_T/D8_YN A4A A2Y 3 14 D12O 35 8 57 36 P35 D11_C/D7_YN P36 GND A4B A3Y GND R4 9 56 4 13 33 34 D10_T/D6_YN B1A A4Y D11O P33 DOR_T/DOR_YN DOR_C/D13_YN P34 10 55 R5 D10_C/D5_YN B1B ENB VDL 5 12 31 32 54 11 D10O P31 P32 D13_T/D12_YN D9_T/D4_YN D13_C/D11_YN B2A B1Y R6 12 53 29 30 6 11 D9_C/D3_YN B2B B2Y P29 D12_T/D10_YN D9O D12_C/D9_YN P30 13 52 D8_T/D2_YN B3A B3Y R7 27 28 7 10 P27 14 51 D11_C/D7_YN D11_T/D8_YN P28 D8O D8_C/D1_YN B3B B4Y 25 26 15 50 R8 P25 D10_T/D6_YN D7_T/D0_YN 8 9 D10_C/D5_YN P26 B4A GND2 GND D7O 16 49 23 24 D7_CN B4B VCC3 VDL P23 D9_T/D4_YN D9_C/D3_YN P24 17 48 DRN C1A VCC4 VDL 21 22 220 18 47 P21 D8_T/D2_YN D8_C/D1_YN P22 DRBN C1B GND3 GND RSO16ISO 19 46 19 20 D6_TN P19 D7_T/D0_YN C2A C1Y DRP D7_CN P20 R1 20 45 1 16 D6_CN C2B C2Y 17 18 D6O P17 DRN 21 44 P18 DRBN D5_TN C3A C3Y R2 2 15 16 15 22 43 D5O P15 D6_TN D5_CN D6_CN P16 C3B C4Y 23 42 R3 13 14 3 14 D4_TN C4A ENC VDL P13 D5_TN D4O P14 D5_CN 24 41 D4_CN C4B D1Y 12 R4 11 4 13 25 40 P11 D4_TN D4_CN P12 D3O D3_TN D1A D2Y 26 39 9 10 R5 D3_CN P9 D3_TN D1B D3Y 5 12 P10 D3_CN D2O 27 38 8 D2_TN 7 D2A D4Y R6 P7 P8 D2_TN 28 37 6 11 D2_CN D1O D2_CN D2B END VDL 5 6 29 36 P5 D1_TN R7 P6 D1_TN D1_CN D3A GND4 GND 7 10 D0O 30 35 4 3 D1_CN D3B VCC5 VDL P3 P4 D0_TN R8 D0_CN 31 34 8 9 D0_TN D4A VCC6 VDL 1 2 P1 32 33 GND P2 GND D0_CN D4B GND5 GND RZ4 40 39 P39 GND P40 38 37 P37 DRO P38 74VCX86 36 35 P35 GND P36 3 1 1A 34 33 P33 D13O 1Y P34 6 2 1B 32 31 P31 D12O P32 4 2A GND 2Y 30 29 00 P29 D11O 8 P30 5 2B DRO 28 27 00 R52 9 3A P27 D10O XORN 11 P28 3Y VDL E43 26 25 R53 10 3B P25 D9O 14 PWR P26 E32 VDL 12 4A 24 23 GND E34 P23 D8O GND 4Y 7 GND P24 13 4B GND 22 21 P21 D7O P22 20 19 P19 D6O P20 18 17 U10 P17 D5O P18 VDL 16 15 P15 D4O P16 + C76 C97 C82 C80 81 14 13 10µF 0.1µF 0.1µF 0.1µF 0.1µF P13 D3O P14 12 11 GND P11 D2O P12 10 9 P9 D1O P10 8 7 P7 P8 D0O 6 5 P5 P6 ORO 4 3 P3 P4 2 1 P1 GND GND P2 P3 C40MS Figure 50. LVDS Mode Evaluation Board Schematic (Continued) Rev. 0 | Page 27 of 40 05089-053 AD9444 Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2 Figure 51. LVDS Mode Evaluation Board Layout, Primary Side Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1 Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1 Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2 Rev. 0 | Page 28 of 40 05089-058 05089-059 05089-057 05089-061 05089-060 05089-062 AD9444 Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen Rev. 0 | Page 29 of 40 05089-063 05089-064 AD9444 LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 11. Item Qty. REFDES Description Manufacturer MFG_PART_NO 1 1 AD9444PCB PCB, AD9444 LVDS Engineering Evaluation Board PCSM AD9444LVDSCUSTREVC 2 16 C1, C4, C6, Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS C33, C34, C39, C44, C55 to C57, C64, C65, C76, C87 to C89 3 38 C2, C3, C5, Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K C9, C12, C20 to C24, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C80 to C82, C85, C86, C91 to C93, C97 4 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU 5 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX) 6 17 E1 to E3, E24, 40-Pin Breakable Header 3M 2340-611TN to E27, E32, E34, E38, E39, E40, E41, E43, E46, E47, E52 7 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 8 1 L1 10 nH Inductor Coilcraft 0603CJ-10NXGBU 9 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA 10 1 P4 Power Jack Swithcraft RAPC722 11 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X 12 2 R4, R6 Resistor, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X 13 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X 14 4 R9, R12, R14, Resistor, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X R15 15 2 R28, R35 Resistor, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X 16 3 R39, R52, Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X R53 17 2 RZ4, RZ5 22 Ω Resistor Array, 16 Term CTS Corp. 742163220JTR 18 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT 19 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80 20 3 U3, U4, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V 21 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V 22 1 U6 Clock Oscillator, 80 MHz CTS Reeves MX045-80 23 1 U7 LVDS-to-CMOS Translator with 100 Term Texas Instruments SN75LVDT386DGG 24 1 U10 2 Input XOR Gate Fairchild 74VCX86M 25 4 U6 Pin Sockets, Closed End AMP 5-330808-3 Rev. 0 | Page 30 of 40 AD9444 Item Qty. REFDES Description Manufacturer MFG_PART_NO 26 24 C10, C11, Capacitors, Select 10 V Ceramic X5R 0402 Panasonic C13, to C19, C29, C31, C36 to C38, C45, C49, C59, C62, C69, C70 to 1 C73, C90 1 27 1 J5 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 1 28 2 P5, P6 Power Connectors Weiland 29 1 R1, R2, R5, Resistors, Select 1/16 W 1% 0402 SMD Panasonic 1 R7, R13 30 1 R17 to R20, Resistors, Select 1/16 W 1% 0402 SMD Panasonic R27, R36 to 1 R38, R40 1 31 5 U2 XO Select Vectron 1 Parts not placed. Rev. 0 | Page 31 of 40 AD9444 CMOS EVALUATION BOARD SCHEMATICS GND 8 7 VDL GND 6 DRVDD 5 GND 4 3 VCC GND 2 1 5V H4 MTHOLE6 H3 MTHOLE6 H2 MTHOLE6 76 50 D11C/D7YN D7 DNC H1 49 77 D11T/D8YN DNC D8 MTHOLE6 78 48 D12C/D9YN GND D9 DRGND GND 79 47 D12T/D10YN D10 DRVDD DRVDD 46 80 D13C/D11YN D11 DNC 45 81 D13T/D12YN DNC D12 82 44 GND DRGND DNC 83 43 DRVDD DRVDD DNC 84 42 DORC/D13Y AVDD1 VCC (MSB) D13 85 41 DORT/DORY OR AVDD1 VCC 86 40 GND AGND AVDD2 87 39 1 VCC DRVDD AVDD2 5V 38 88 3 GND AVDD1 VCC AGND 89 37 2 VCC AVDD1 CLK– ENCB 90 36 VCC CLK+ AVDD1 ENC 91 35 CR2 VCC AVDD1 VCC AVDD1 92 34 VCC AVDD1 VCC AVDD1 33 93 VCC AVDD1 C1 GND 94 32 VCC AGND AVDD1 GND C40 95 31 0.1µF VCC AVDD2 AVDD1 96 30 GND AGND AVDD2 97 29 GND AGND AVDD2 98 28 AVDD2 5V AVDD1 99 27 AVDD1 AGND VCC 100 26 AVDD1 R39 DCS MODE VCC XX C36 EPAD 101 0.1µF C26 0.1µF 50Ω R7 50Ω R8 C78 0.1µF R28 OPTIONAL 33Ω 33Ω R35 C51 10µF C91 C3 0.1µF C9 0.1µF 0.1µF R37 GND XX C2 R27 0.1µF XX R36 R20 + XX XX R1 R2 3.8kΩ 3.8kΩ R3 3.8kΩ Figure 59. CMOS Mode Evaluation Board Schematic Rev. 0 | Page 32 of 40 GND ENCODE GND OPTIONAL ENCODE CIRCUITS P5 XTALINPUT VXTAL ENC + C44 C93 C92 C96 J5 E47 5V 10µF 0.1µF 0.1µF 0.1µF VXTAL T3 E52 ADT1-1WT E46 VCC 1 6 GND C42 5 2 NC GND J1 3 4 0.1µF U6 PRI SEC GND ENCB ECLOSC VXTAL GND GND 8 XTALOUTB 14 VXTAL VCC OUT 1 XTALOUT GND 7 GND VEE ~OUT XTALINPUTB GND R38 R40 R9 VXTAL GND XX VCC XX 1kΩ R17 FOR VECTRON XTAL XX R12 XTALINPUTB GND JN00158 VCC E39 1kΩ 1 6 E38 E/D VCC VXTAL XTALINPUT 2 5 XTALOUTB NC OUTPUTB GND E40 3 4 FOR VF XTAL GND GND XTALOUT GND OUTPUT R18 XX R19 U2 XX GND R21 1 75 DRVDD VCC DRVDD AVDD1 1kΩ 2 74 GND DRGND DNC 3 73 VCC E3 D10T/D6YN D6 DNC E1 4 72 D10C/D5YN DNC D5 R15 5 71 GND E2 D9T/D4Y GND OUTPUT MODE D4 1kΩ 6 70 D3 D9C/D3Y DFS 69 7 D8T/D2Y LVDSBIAS D2 8 68 VCC D8C/D1Y AVDD1 D1 GND 9 67 E26 VCC GND VCC DRGND EXTERNAL AVDD1 E25 10 66 REFERENCE D0 (LSB) D7T/D0Y SENSE 65 E41 E27 11 INPUT VREF AD9444 DNC E24 E20 12 64 U1 EXTREF GND COUT AGND DCO+ EXTREF 13 63 GND PIN DEFINITIONS COUTB REFT DCO– 14 LVDS/CMOS 62 DRVDD REFB DRVDD C39 61 15 GND GND GND GND AGND DRGND 60 16 10µF VCC DNC AVDD1 GND 17 59 VCC DNC AVDD1 GND 18 58 VCC AVDD1 DNC 57 19 5V AVDD2 DNC 56 T5 20 GND AGND DNC TOUT ADT1-1WT 21 55 GND VIN+ DNC 1 6 22 54 CT 5 2 VIN– DRVDD DRVDD NC GND 53 23 GND GND 3 4 AGND DRGND GND C12 52 24 PRI SEC VCC AVDD1 DNC R5 R4 0.1µF 25 51 xx 36Ω VCC AVDD1 DNC J4 100Ω C13 TOUTB R13 TINB L110NH xx 20pF C5 E15 R6 0.1µF 36Ω GND ANALOG GND 05089-054 AD9444 ADP3338 ADP3338 U8 U15 P4 3.3V 3.3V PJ-102A 1 1 2 GND GND 2 2 2 3 4 4 OUT1 OUT1 3 OUT OUT 3 3 1 IN IN 1 + C1 + C6 + C33 10µF 10µF 10µF + C57 + C87 10µF 10µF ADP3338 ADP3338 U3 U14 3.3V 5V 1 1 GND GND 2 2 4 4 OUT1 OUT1 OUT OUT 3 3 IN IN + C34 + C4 10µF 10µF C88 C89 + + 10µF 10µF Figure 60. CMOS Mode Evaluation Board Schematic (Continued) Rev. 0 | Page 33 of 40 DRVDD VDL GND GND GND GND GND GND DRVDD VDL VIN VIN 5V VCC GND GND GND GND GND GND 5V VCC VIN VIN GND GND VIN 05089-055 AD9444 40 39 P39 GND P40 RZ1 220 RZ5 220 38 37 P37 DRM RSO16ISO RSO16ISO P38 U5 36 35 SN74LVCH16373A R1 R1 1 16 P35 GND 1 16 P36 ORM DORT/DORY Q = OUTPUT 34 33 R2 R2 P33 D13M 2 15 24 P34 25 2 15 D = INPUT LE2 OE2 D13M DORC/D13Y XOR2IN GND 23 26 32 31 R3 R3 2D8 2Q8 P31 D12M 3 14 P32 3 14 22 D12M D13T/D12Y 27 2D7 2Q7 30 29 R4 R4 P29 4 13 28 21 P30 D11M 4 13 GND GND GND GND D11M D13C/D11Y 29 20 28 27 R5 R5 2D6 2Q6 5 12 P27 D10M 5 12 P28 30 19 D10M D12T/D10Y 2D5 2Q5 26 25 R6 R6 31 18 6 11 P25 D9M 6 11 P26 VDL VCC VCC VDL D12C/D9Y D9M 32 17 24 23 2D4 2Q4 R7 R7 7 10 P23 D8M 7 10 P24 33 16 D11T/D8Y D8M 2D3 2Q3 22 21 34 15 R8 R8 8 9 P21 D7M GND GND GND 8 9 P22 GND D11C/D7Y D7M 35 14 2D2 2Q2 19 20 P19 D6M 36 13 P20 2D1 2Q1 RZ2 220 RZ5 220 37 12 18 17 P17 D5M RSO16ISO 1D8 1Q8 RSO16ISO P18 38 11 1D7 1Q7 16 15 R1 39 10 R1 P15 D4M 1 16 1 16 P16 GND GND GND D6M D10T/D6Y GND 9 40 14 13 R2 1D6 1Q6 R2 P13 D3M 2 15 2 15 P14 8 41 D10C/D5Y D5M 1D5 1Q5 12 11 7 R3 42 R3 P11 D2M 3 14 3 14 P12 VDL VCC VCC VDL D9T/D4Y D4M 6 43 10 9 1D4 1Q4 R4 R4 P9 D1M 4 13 4 13 P10 44 5 D9C/D3Y D3M 1D3 1Q3 8 7 45 4 R5 R5 P7 D0M 5 12 GND GND GND P8 GND 5 12 D8T/D2Y D2M 46 3 1D2 1Q2 6 5 R6 R6 P5 ORM 6 11 47 2 P6 6 11 D1M D8C/D1Y 1D1 1Q1 48 1 4 3 R7 R7 P3 10 XOR2IN LE1 OE1 GND P4 7 7 10 D0M D7T/D0Y 2 1 R8 R8 P1 GND P2 GND 8 9 8 9 RZ4 RZ4 P3 C40MS NOT PLACED 00 COUTB R50 00 U4 XORZIN COUT 74VCX86 R16 00 3 1 1A DRM 1Y VDL E49 R14 00 2 1B 6 E42 R41 4 2A E45 GND GND 2Y 8 5 2B GATE 00 9 3A 11 3Y DRM 10 3B R42 PWR 14 VDL 12 4A GATE2 4Y 7 GND VDL E32 GND 13 4B E31 E30 GND U10 VDL + C66 C25 C41 C24 C68 C67 63 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.01µF GND Figure 61. CMOS Mode Evaluation Board Schematic (Continued) Rev. 0 | Page 34 of 40 05089-056 AD9444 Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2 Figure 62. CMOS Mode Evaluation Board Layout, Primary Side Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1 Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2 Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1 Rev. 0 | Page 35 of 40 05089-067 05089-066 05089-065 05089-070 05089-069 05089-068 AD9444 Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen Rev. 0 | Page 36 of 40 05089-071 05089-072 AD9444 CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Item Qty. REFDES Description Manufacturer MFG_PART_NO 1 1 AD9444PCB PCB, AD9444 LVDS Evaluation Board PCSM AD9444LVDSCUSTREVC 2 16 C1, C4, C6, C33, C34, Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS C39, C44, C55 to C57, C64 to C66, C87 to C89 3 32 C2, C3, C5, C9, C12, Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K C20 to C23, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C78, C85, C91, C92 4 5 C24, C25, C41, C67, Capacitors, 0.1 µF 16 V Ceramic X7R 0603 Panasonic ECJ-1VB1C104K C68 5 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU 6 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX) 7 20 E1 to E3, E24 to E27, 40-Pin Breakable Header 3M 2340-611TN E30 to E32, E38 to E42, E45 to E47, E49, E52 8 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 9 1 L1 10 nH O402 Inductor Coilcraft 0402CS-10NX_B_ 10 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA 11 1 P4 Power Jack Swithcraft RAPC722 12 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X 13 2 R4, R6 Resistors, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X 14 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X 15 4 R9, R12, R15, R21 Resistors, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X 16 2 R14, R50 Resistors, 0 Ω 1/10 W 5% 0603 SMD Panasonic ERJ-3GEY0R00V 17 2 R28, R35 Resistors, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X 18 1 R39 Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X 19 4 RZ1 to RZ3, RZ6 220 Ω Resistor Array, 16 Term CTS Corp. 742163221JTR 20 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT 21 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80 22 4 U3, U8, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V 23 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V 24 1 U5 16-Bit Flip Flop Fairchild 74LVTH162374 25 4 U6 Pin Sockets, Closed End AMP 5-330808-3 Rev. 0 | Page 37 of 40 AD9444 Item Qty. REFDES Description Manufacturer MFG_PART_NO 26 26 C10, C11, C13, C14 to Capacitors, Select 10 V Ceramic X5R 0402 Panasonic C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to 1 C73, C90, C93, C96 1 27 1 J5 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 28 15 R1,R2,R5,R7, R13, Resistors, Select 1/16 W 1% 0402 SMD Panasonic R17 to R20, R27, 1 R36 to R40 1 29 3 R16, R41, R42 Resistors, Select 1/16 W 5% 0603 SMD Panasonic 1 30 1 C63 Capacitor, Select 10 V Ceramic X5R 0603 Panasonic 1 31 1 U4 XOR 74VCX86D Fairchild 74VCX86D 1 32 2 P5, P6 Power Connectors Weiland 1 Parts not placed. Rev. 0 | Page 38 of 40 AD9444 OUTLINE DIMENSIONS 1.20 16.00 SQ 0.75 MAX 0.60 14.00 SQ 0.45 100 76 76 100 1 75 75 1 SEATING BOTTOM VIEW PLANE (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 51 25 25 26 50 50 26 0.20 1.05 6.50 0.09 NOM 1.00 7° 0.95 3.5° 0° 0.15 0.50 BSC 0.27 COPLANARITY 0.05 0.08 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. 3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP. Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Outline 1 AD9444BSVZ-80 –40°C to +85°C 100-Lead TQFP_EP SV-100-1 AD9444-CMOS/PCB CMOS Mode Evaluation Board AD9444-LVDS/PCB LVDS Mode Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 39 of 40 AD9444 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05089–0–10/04(0) Rev. 0 | Page 40 of 40