ANALOG DEVICES AD9434

12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter AD9434 FEATURES FUNCTIONAL BLOCK DIAGRAM VREF PWDN AGND AVDD SNR = 65 dBFS at f up to 250 MHz at 500 MSPS IN ENOB of 10.5 bits at f up to 250 MHz at 500 MSPS (−1.0 dBFS) IN REFERENCE AD9434 SFDR = 78 dBc at f up to 250 MHz at 500 MSPS (−1.0 dBFS) IN CML Integrated input buffer DRVDD DRGND Excellent linearity VIN+ TRACK-AND-HOLD VIN– DNL = ±0.5 LSB typical ADC 12 OUTPUT 12 CORE STAGING D11± TO D0± INL = ±0.6 LSB typical LVDS LVDS at 500 MSPS (ANSI-644 levels) CLK+ CLOCK OR+ MANAGEMENT CLK– 1 GHz full power analog bandwidth OR– On-chip reference, no external decoupling required SERIAL PORT Low power dissipation DCO+ DCO– 690 mW at 500 MSPS—LVDS SDR mode 660 mW at 500 MSPS—LVDS DDR mode SCLK/DFS SDIO CSB Programmable (nominal) input voltage range Figure 1. 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment APPLICATIONS Fabricated on an advanced BiCMOS process, the AD9434 is Wireless and wired broadband communications available in a 56-lead LFCSP, specified over the industrial Cable reverse path temperature range (−40°C to +85°C). This part is protected Communications test equipment under a U.S. patent. Radar and satellite subsystems Power amplifier linearization PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. High Performance. Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input. The AD9434 is a 12-bit monolithic sampling analog-to-digital 2. Low Power. converter (ADC) optimized for high performance, low power, Consumes only 660 mW at 500 MSPS. and ease of use. The part operates at up to a 500 MSPS 3. Ease of Use. conversion rate and is optimized for outstanding dynamic LVDS output data and output clock signal allow interface performance in wideband carrier and broadband systems. All to FPGA technology. The on-chip reference and sample- necessary functions, including a sample-and-hold and voltage and-hold provide flexibility in system design. Use of a reference, are included on the chip to provide a complete signal single 1.8 V supply simplifies system power supply design. conversion solution. The VREF pin can be used to monitor the 4. Serial Port Control. internal reference or provide an external voltage reference Standard serial port interface supports various product (external reference mode must be enabled through the SPI functions, such as data formatting, power-down, gain port). adjust, and output test pattern generation. The ADC requires a 1.8 V analog voltage supply and a differen- 5. The AD9434 is pin compatible with the AD9230, and can tial clock for full performance operation. The digital outputs are be substituted in many applications with minimal design LVDS (ANSI-644) compatible and support twos complement, changes. offset binary format, or Gray code. A data clock output is available for proper output data timing. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09383-001 AD9434 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 19  Applications ....................................................................................... 1  Analog Input and Voltage Reference ....................................... 19  General Description ......................................................................... 1  Clock Input Considerations ...................................................... 20  Functional Block Diagram .............................................................. 1  Power Dissipation and Power-Down Mode ........................... 21  Product Highlights ........................................................................... 1  Digital Outputs ........................................................................... 21  Revision History ............................................................................... 2  Timing ......................................................................................... 22  Specif ica t ions ..................................................................................... 3  VREF ............................................................................................ 22  DC Specifications ......................................................................... 3  AD9434 Configuration Using the SPI ..................................... 22  AC Specifications .......................................................................... 4  Using the AD9434 to Replace the AD9230............................. 23  Digital Specifications ................................................................... 5  Hardware Interface ..................................................................... 23  Switching Specifications .............................................................. 6  Configuration Without the SPI ................................................ 23  Timing Diagrams .......................................................................... 7  Memory Map .................................................................................. 25  Absolute Maximum Ratings ............................................................ 8  Reading the Memory Map Table .............................................. 25  Thermal Resistance ...................................................................... 8  Reserved Locations .................................................................... 25  ESD Caution .................................................................................. 8  Default Values ............................................................................. 25  Pin Configurations and Function Descriptions ........................... 9  Logic Levels ................................................................................. 25  Typical Performance Characteristics ........................................... 13  Outline Dimensions ....................................................................... 28  Equivalent Circuits ......................................................................... 18  Ordering Guide .......................................................................... 28  REVISION HISTORY 5/11—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Changes to Table 4, Aperture Time Values ................................... 6 Changes to Figure 32 ...................................................................... 17 Changes to Figure 42 ...................................................................... 19 Changes to Table 13, Register 10, Bits[7:0] Value, Register 14 Default Value, Register 15 Default Value, Register 17, Bit 7 Value and Register 18, Bit[4:0] Values .................................................... 26 3/11—Revision 0: Initial Version Rev. A | Page 2 of 28 AD9434 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, T = −40°C, T = +85°C, f = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. MIN MAX IN Table 1. AD9434-370 AD9434-500 1 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C ±0.25 ±0.25 mV Full −3.0 +1.0 −3.0 +1.0 mV Gain Error 25°C 1.0 1.0 % FS Full −5.0 +7.0 −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.4 ±0.5 LSB Full −0.9 +0.9 −0.95 +1.0 LSB Integral Nonlinearity (INL) 25°C ±0.4 ±0.6 LSB Full −0.92 +0.92 −1.3 +1.3 LSB INTERNAL REFERENCE VREF Full 0.71 0.75 0.78 0.71 0.75 0.78 V TEMPERATURE DRIFT Offset Error Full 18 18 μV/°C Gain Error Full 0.07 0.07 %/°C ANALOG INPUTS (VIN+, VIN−) 2 Differential Input Voltage Range Full 1.18 1.5 1.6 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 1.7 V Input Resistance (Differential) Full 1 1 kΩ Input Capacitance (Differential) 25°C 1.3 1.3 pF POWER SUPPLY AVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V Supply Currents 3 I Full 260 280 283 301 mA AVDD 3 4 I /SDR Mode Full 88 100 100 114 mA DRVDD 3 5 IDRVDD /DDR Mode Full 70 80 82 96 mA Power Dissipation 4 SDR Mode Full 625 685 690 747 mW 5 DDR Mode Full 595 648 657 715 mW Standby Mode Full 40 50 40 50 mW Power-Down Mode Full 2.5 7 2.5 7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 I and I are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9434. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. A | Page 3 of 28 AD9434 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 2. AD9434-370 AD9434-500 1 , 2 Parameter Temp Min Typ Max Min Typ Max Unit SNR fIN = 30.3 MHz 25°C 66.3 65.9 dBFS fIN = 70.3 MHz 25°C 66.2 65.9 dBFS fIN = 100.3 MHz 25°C 66.1 65.8 dBFS Full 65.3 64.5 dBFS fIN = 250.3 MHz 25°C 65.5 65.2 dBFS fIN = 450.3 MHz 25°C 64.0 63.5 dBFS SINAD fIN = 30.3 MHz 25°C 66.1 65.9 dBFS fIN = 70.3 MHz 25°C 66.1 65.8 dBFS fIN = 100.3 MHz 25°C 66.0 65.8 dBFS Full 65.2 64.4 dBFS fIN = 250.3 MHz 25°C 65.3 64.8 dBFS fIN = 450.3 MHz 25°C 63.7 62.9 dBFS EFFECTIVE NUMBER OF BITS (ENOB) f = 30.3 MHz 25°C 10.7 10.7 Bits IN f = 70.3 MHz 25°C 10.7 10.6 Bits IN fIN = 100.3 MHz 25°C 10.7 10.6 Bits fIN = 250.3 MHz 25°C 10.6 10.5 Bits fIN = 450.3 MHz 25°C 10.3 10.2 Bits WORST HARMONIC (SECOND or THIRD) f = 30.3 MHz 25°C −93 −93 dBc IN f = 70.3 MHz 25°C −89 −91 dBc IN f = 100.3 MHz 25°C −83 −87 dBc IN Full −75 −74 dBc f = 250.3 MHz 25°C −80 −78 dBc IN f = 450.3 MHz 25°C −78 −69 dBc IN SFDR f = 30.3 MHz 25°C 89 84 dBc IN f = 70.3 MHz 25°C 88 82 dBc IN f = 100.3 MHz 25°C 83 83 dBc IN Full 75 74 dBc f = 250.3 MHz 25°C 79 78 dBc IN f = 450.3 MHz 25°C 78 68 dBc IN WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD) fIN = 30.3 MHz 25°C −90 −85 dBc fIN = 70.3 MHz 25°C −90 −82 dBc fIN = 100.3 MHz 25°C −91 −84 dBc Full −75 −74 dBc f = 250.3 MHz 25°C −83 −85 dBc IN f = 450.3 MHz 25°C −82 −78 dBc IN TWO-TONE IMD fIN1 = 119.5 MHz, fIN2 = 122.5 MHz 25°C −85 −85 dBc ANALOG INPUT BANDWIDTH Full Power 25°C 1 1 GHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. A | Page 4 of 28 AD9434 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 3. AD9434-370 AD9434-500 1 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 −10 +10 μA Low Level Input Current (I) Full −10 +10 −10 +10 μA IL Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ Input Capacitance Full 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 0 μA Logic 0 Input Current (SDIO, CSB) Full −60 −60 μA Logic 1 Input Current (SCLK, PDWN) Full 50 50 μA Logic 0 Input Current (SCLK, PDWN) Full 0 0 μA Input Capacitance 25°C 4 4 pF 2 LOGIC OUTPUTS V Differential Output Voltage Full 247 454 247 454 mV OD V Output Offset Voltage Full 1.125 1.375 1.125 1.375 V OS Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω. Rev. A | Page 5 of 28 AD9434 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 4. AD9434-370 AD9434-500 Parameter Temp Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 370 500 MSPS Minimum Conversion Rate Full 50 50 MSPS 1, 2 CLK+ Pulse Width High (t ) Full 1.1 11 0.9 11 ns CH CLK+ Pulse Width Low (t ) Full 1.1 11 0.9 11 ns CL 1 Output (LVDS—SDR Mode) Data Propagation Delay (tPD) Full 0.85 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (t ) (20% to 80%) 25°C 0.15 0.15 ns F DCO Propagation Delay (t ) Full 0.6 0.6 ns CPD Data to DCO Skew (tSKEW) Full 0.15 0.38 0.15 0.38 ns Latency Full 15 15 Cycles 2 Output (LVDS—DDR Mode) Data Propagation Delay (t ) Full 0.6 0.6 ns PD Rise Time (t ) (20% to 80%) 25°C 0.15 0.15 ns R Fall Time (t ) (20% to 80%) 25°C 0.15 0.15 ns F DCO Propagation Delay (tCPD) Full 0.6 0.6 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 −0.07 +0.07 ns Latency Full 15 15 Cycles Aperture Time (t) 25°C 0.85 0.85 ns A Aperture Uncertainty (Jitter, t ) 25°C 80 80 fs rms J 1 See Figure 2. 2 See Figure 3. Rev. A | Page 6 of 28 AD9434 Timing Diagrams N – 1 t N + 4 A N + 5 N N + 3 VIN+, VIN– N + 1 N + 2 t t 1/f CH CL S CLK+ CLK– t CPD DCO+ DCO– t SKEW t PD Dx+ N – 15 N – 14 N – 13 N – 12 N – 11 Dx– Figure 2. Single Data Rate Mode N – 1 N + 4 t A N + 5 N N + 3 VIN+, VIN– N + 1 N + 2 t t 1/f CH CL S CLK+ CLK– t CPD DCO+ DCO– t SKEW t PD D0/D6+ D6 D0 D6 D0 D6 D0 D6 D0 D6 D0 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 N – 12 N – 11 N – 11 N – 10 D0/D6– D5/D11+ D11 D5 D11 D5 D11 D5 D11 D5 D11 D5 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 N – 12 N – 11 N – 11 N – 10 D5/D11– 6 MSBs 6 LSBs Figure 3. Double Data Rate Mode Rev. A | Page 7 of 28 09383-003 09383-002 AD9434 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− Through D11+/D11− −0.3 V to DRVDD + 0.2 V THERMAL RESISTANCE to DRGND The exposed paddle must be soldered to the ground plane for DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the PCB OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V increases the reliability of the solder joints, maximizing the CLK+ to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V Table 6. VIN− to AGND −0.3 V to AVDD + 0.2 V Package Type θJA θJC Unit CML to AGND −0.3 V to AVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W VREF to AGND −0.3 V to AVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. SDIO to DRGND −0.3 V to DRVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In PDWN to AGND −0.3 V to DRVDD + 0.2 V addition, metal in direct contact with the package leads from CSB to AGND −0.3 V to DRVDD + 0.2 V metal traces, through holes, ground, and power planes reduces SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V the θ . JA Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C ESD CAUTION Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. A | Page 8 of 28 AD9434 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D3– 1 PIN 1 42 AVDD INDICATOR D3+ 2 41 AVDD D4– 3 40 CML D4+ 4 39 AVDD D5– 5 38 AVDD D5+ 6 37 AVDD AD9434 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) D6– 9 34 AVDD D6+ 10 33 AVDD D7– 11 32 AVDD D7+ 12 31 VREF PIN 0 (EXPOSED PADDLE) = AGND D8– 13 30 AVDD D8+ 14 29 PWDN NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. AGND AND DRGND SHOULD BE TIED TO A COMMON QUIET GROUND PLANE. 3. THE EXPOSED PADDLE MUST BE SOLDERED TO A GROUND PLANE. Figure 4. Pin Configuration—Single Data Rate Mode Table 7. Pin Function Descriptions—Single Data Rate Mode Pin No. Mnemonic Description 1 0 AGND Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39, AVDD 1.8 V Analog Supply. 41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 1 8, 23, 48 DRGND Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 28 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output (LSB). 52 D0+ D0 True Output (LSB). 53 D1− D1 Complement Output. 54 D1+ D1 True Output. 55 D2− D2 Complement Output. 56 D2+ D2 True Output. 1 D3− D3 Complement Output. 2 D3+ D3 True Output. 3 D4− D4 Complement Output. Rev. A | Page 9 of 28 09383-004 D9– 15 56 D2+ D9+ 16 55 D2– D10– 17 54 D1+ D10+ 18 53 D1– D11– 19 52 D0+ D11+ 20 51 D0– OR– 21 50 DCO+ OR+ 22 49 DCO– DRGND 23 48 DRGND DRVDD 24 47 DRVDD SDIO 25 46 AVDD SCLK/DFS 26 45 CLK– CSB 27 44 CLK+ DNC 28 43 AVDD AD9434 Pin No. Mnemonic Description 4 D4+ D4 True Output. 5 D5− D5 Complement Output. 6 D5+ D5 True Output. 9 D6− D6 Complement Output. 10 D6+ D6 True Output. 11 D7− D7 Complement Output. 12 D7+ D7 True Output. 13 D8− D8 Complement Output. 14 D8+ D8 True Output. 15 D9− D9 Complement Output. 16 D9+ D9 True Output. 17 D10− D10 Complement Output. 18 D10+ D10 True Output. 19 D11− D11 Complement Output (MSB). 20 D11+ D11 True Output (MSB). 21 OR− Overrange Complement Output. 22 OR+ Overrange True Output. 1 AGND and DRGND should be tied to a common quiet ground plane. Rev. A | Page 10 of 28 AD9434 D3/D9– 1 PIN 1 42 AVDD INDICATOR D3/D9+ 2 41 AVDD D4/D10– 3 40 CML D4/D10+ 4 39 AVDD D5/D11– 5 38 AVDD D5/D11+ 6 37 AVDD AD9434 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) OR– 9 34 AVDD OR+ 10 33 AVDD DNC 11 32 AVDD DNC 12 31 VREF PIN 0 (EXPOSED PADDLE) = AGND DNC 13 30 AVDD DNC 14 29 PWDN NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. AGND AND DRGND SHOULD BE TIED TO A COMMON QUIET GROUND PLANE. 3. THE EXPOSED PADDLE MUST BE SOLDERED TO A GROUND PLANE. Figure 5. Pin Configuration—Double Data Rate Mode Table 8. Pin Function Descriptions—Double Data Rate Mode Pin No. Mnemonic Description 1 0 AGND Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39, 41 AVDD 1.8 V Analog Supply. to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 1 8, 23, 48 DRGND Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0/D6− D0/D6 Complement Output (LSB). 52 D0/D6+ D0/D6 True Output (LSB). 53 D1/D7− D1/D7 Complement Output. 54 D1/D7+ D1/D7 True Output. 55 D2/D8− D2/D8 Complement Output. 56 D2/D8+ D2/D8 True Output. 1 D3/D9− D3/D9 Complement Output. 2 D3/D9+ D3/D9 True Output. 3 D4/D10− D4/D10 Complement Output. 4 D4/D10+ D4/D10 True Output. 5 D5/D11− D5/D11 Complement Output (MSB). Rev. A | Page 11 of 28 09383-005 DNC 15 56 D2/D8+ DNC 16 55 D2/D8– DNC 17 54 D1/D7+ DNC 18 53 D1/D7– DNC 19 52 D0/D6+ DNC 20 51 D0/D6– 50 DCO+ DNC/(OR–) 21 DNC/(OR+) 22 49 DCO– DRGND 23 48 DRGND DRVDD 24 47 DRVDD SDIO 25 46 AVDD SCLK/DFS 26 45 CLK– CSB 27 44 CLK+ DNC 28 43 AVDD AD9434 Pin No. Mnemonic Description 6 D5/D11+ D5/D11 True Output (MSB). 9 OR− Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) 10 OR+ Overrange True Output. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) 11 to 20, 28 DNC Do Not Connect. Do not connect to these pins. These pins should be left floating. 21 DNC/(OR−) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange complement output through the serial port register.) 22 DNC/(OR+) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange true output through the serial port register.) 1 Tie AGND and DRGND to a common quiet ground plane. Rev. A | Page 12 of 28 AD9434 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted. 0 0 370MSPS 500MSPS 30.3MHz AT –1.0dBFS 30.3MHz AT –1.0dBFS –20 –20 SNR: 65.4dB SNR: 65.0dB ENOB: 10.7 BITS ENOB: 10.7 BITS SFDR: 90dBc SFDR: 85dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 30.3 MHz Figure 9. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz 0 0 370MSPS 500MSPS 100.3MHz AT –1.0dBFS 100.3MHz AT –1.0dBFS –20 –20 SNR: 65.3dB SNR: 64.9dB ENOB: 10.7 BITS ENOB: 10.6 BITS SFDR: 83dBc SFDR: 84dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 100.3 MHz Figure 10. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 100.3 MHz 0 0 370MSPS 500MSPS 140.3MHz AT –1.0dBFS 140.3MHz AT –1.0dBFS –20 –20 SNR: 65.2dB SNR: 64.8dB ENOB: 10.7 BITS ENOB: 10.6 BITS SFDR: 85dBc SFDR: 79dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 140.3 MHz Figure 11. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 140.3 MHz Rev. A | Page 13 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09383-108 09383-107 09383-106 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09383-111 09383-110 09383-109 AD9434 0 90 SFDR (dBc), T = –40°C A 491.52MSPS 85 368.3MHz AT –1.0dBFS SFDR (dBc), T = +25°C A –20 SNR: 64.0dB ENOB: 10.5 BITS 80 SFDR: 79dBc –40 75 SFDR (dBc), T = +85°C A –60 70 SNR (dBFS), T = –40°C A 65 –80 SNR (dBFS), T = +25°C A 60 SNR (dBFS), T = +85°C A –100 55 –120 50 0 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) ANALOG INPUT FREQUECY (MHz) Figure 12. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 368.3 MHz Figure 15. AD9434-500 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature; 500 MSPS 0 100 SFDR (dBc), 30.3MHz 491.52MSPS 450.3MHz AT –1.0dBFS –20 90 SNR: 63.5dB ENOB: 10.3 BITS SFDR: 72dBc –40 80 SFDR (dBc), 100.3MHz SNR (dBFS), 30.3MHz –60 70 –80 60 SNR (dBFS), 100.3MHz –100 50 –120 40 0 20 40 60 80 100 120 140 160 180 200 220 240 50 100 150 200 250 300 350 400 450 500 550 FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 13. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 450.3 MHz Figure 16. AD9434-370 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz 100 100 95 SFDR (dBc), 30.3MHz SFDR (dBc), T = –40°C A 90 90 SFDR (dBc), T = +25°C A 85 80 SFDR (dBc), 100.3MHz 80 SNR (dBFS), 30.3MHz 75 SFDR (dBc), T = +85°C 70 A SNR (dBFS), T = –40°C A 70 60 65 SNR (dBFS), 100.3MHz SNR (dBFS), T = +25°C A 60 SNR (dBFS), T = +85°C 50 A 55 50 40 0 50 100 150 200 250 300 350 400 450 500 50 100 150 200 250 300 350 400 450 500 550 ANALOG INPUT FREQUECY (MHz) SAMPLE RATE (MSPS) Figure 14. AD9434-370 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Figure 17. AD9434-500 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz Temperature; 370 MSPS Rev. A | Page 14 of 28 SNR/SFDR (dB) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09383-113 09383-112 09383-114 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 09383-115 09383-117 09383-116 AD9434 100 0.8 90 SFDR (dBFS) 0.6 80 0.4 SNR (dBFS) 70 0.2 60 50 0 SFDR (dBc) 40 –0.2 30 SNR (dB) –0.4 20 –0.6 10 0 –0.8 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –1 1023 2047 3071 4095 AMPLITUDE (dB) OUTPUT CODE Figure 18. AD9434-370 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz Figure 21. AD9434-500 INL; 500 MSPS 100 0.4 90 0.3 SFDR (dBFS) 80 0.2 70 SNR (dBFS) 0.1 60 50 0 SFDR (dBc) 40 –0.1 30 SNR (dB) –0.2 20 –0.3 10 0 –0.4 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –1 1023 2047 3071 4095 AMPLITUDE (dB) OUTPUT CODE Figure 19. AD9434-500 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz Figure 22. AD9434-370 DNL; 370 MSPS 0.5 0.6 0.4 0.5 0.3 0.4 0.2 0.3 0.1 0.2 0 0.1 –0.1 0 –0.2 –0.1 –0.3 –0.2 –0.4 –0.3 –0.5 –0.4 –1 1023 2047 3071 4095 –1 1023 2047 3071 4095 OUTPUT CODE OUTPUT CODE Figure 20. AD9434-370 INL; 370 MSPS Figure 23. AD9434-500 DNL, 500 MSPS Rev. A | Page 15 of 28 INL (LSB) SNR/SFDR (dB) SNR/SFDR (dB) 09383-119 09383-118 09383-120 DNL (LSB) DNL (LSB) INL (LSB) 09383-123 09383-122 09383-121 AD9434 2.5 0 1.17LSB rms 500MSPS f = 119.5MHz AT –7.0dBFS IN1 –20 2.0 f = 122.5MHz AT –7.0dBFS IN2 SFDR: 86dBc –40 1.5 –60 1.0 –80 0.5 –100 0 –120 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE 0 50 100 150 200 250 BINS FREQUENCY (MHz) Figure 24. AD9434-370 Grounded Input Histogram; 370 MSPS Figure 27. AD9434-500 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz, 122.5 MHz 2.5 120 1.24LSB rms IMD3 (dBFS) 100 2.0 SFDR (dBFS) 80 1.5 60 1.0 SFDR (dBc) 40 0.5 20 0 0 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE –90 –80 –70 –60 –50 –40 –30 –20 –10 0 BINS AMPLITUDE (dBFS) Figure 25. AD9434-500 Grounded Input Histogram; 500 MSPS Figure 28. AD9434-370 Two-Tone SFDR vs. Input Amplitude; 370 MSPS, 119.5 MHz, 122.5 MHz 120 0 IMD3 (dBFS) 370MSPS f = 119.5MHz AT –7.0dBFS IN1 100 –20 f = 122.5MHz AT –7.0dBFS IN2 SFDR: 82dBc SFDR (dBFS) 80 –40 60 –60 SFDR (dBc) 40 –80 20 –100 0 –120 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 050 100 150 AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 29. AD9434-500 Two-Tone SFDR vs. Input Amplitude; 500 MSPS, Figure 26. AD9434-370 64k Point, Two-Tone FFT; 370 MSPS, 119.5 MHz, 122.5 MHz 119.5 MHz, 122.5 MHZ Rev. A | Page 16 of 28 AMPLITUDE (dB) NUMBER OF HITS (M) NUMBER OF HITS (M) 09383-125 09383-124 09383-126 AMPLITUDE (dB) SFDR (dB) SFDR (dB) 09383-129 09383-128 09383-127 AD9434 90 80 SFDR (dBc) 85 SFDR (dBc) 75 80 70 75 AD9434, 370MSPS AD9434, 370MSPS 70 65 SNR (dBFS) 65 SNR (dBFS) 60 AD9434, 500MSPS AD9434, 500MSPS 60 55 55 50 50 1.5 1.6 1.7 1.8 1.9 2.0 500 600 700 800 900 1000 V (V) ANALOG INPUT FREQUENCY (MHz) CM Figure 30. SNR/SFDR vs. Common-Mode Voltage; 370 MSPS, 500 MSPS, Figure 32. SNR/SFDR for AD9434-370 and AD9434-500 at 370 MSPS and f = 140.3 MHz 500 MSPS; AIN Sweep at −1.0 dBFS IN 350 800 TOTAL POWER 700 300 600 250 500 I AVDD 200 400 300 150 200 I 100 DRVDD 100 50 0 SAMPLE RATE (MSPS) Figure 31. Current and Power vs. Sample Rate, f = 30.3 MHz IN Rev. A | Page 17 of 28 CURRENT (mA) SNR/SFDR (dB) 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 POWER (mW) 09383-130 09383-131 SNR/SFDR (dB) 09383-132 AD9434 EQUIVALENT CIRCUITS AVDD DRVDD AVDD AVDD 0.9V DRVDD 15kΩ 15kΩ CLK+ CLK– 30kΩ DRVDD 350Ω CSB Figure 33. Clock Inputs Figure 37. Equivalent CSB Input Circuit V BOOST AVDD DRVDD CML V+ V– D11– TO D0– D11+ TO D0+ AVDD V– V+ VIN+ A + IN 500Ω DC Figure 38. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) AVDD 500Ω SPI CONTROLLED AVDD VIN+ A – 20kΩ IN (00) (01) VREF (10) Figure 34. Analog Input DC Equivalent Circuit (VCML = ~1.7 V) NOT USED (11) DRVDD SPI CTRL V SELECT REF 00 = INTERNAL V REF 01 = IMPORT V REF 10 = EXPORT V REF DRVDD 11 = NOT USED 350Ω Figure 39. Equivalent VREF Input/Output Circuit SCLK/DFS 30kΩ DRVDD DRVDD Figure 35. Equivalent SCLK/DFS, PDWN Input Circuit 30kΩ 350Ω VIN+ SDIO 1.3pF 1000Ω CTRL VIN– Figure 36. Analog Input AC Equivalent Circuit Figure 40. Equivalent SDIO Input Circuit Rev. A | Page 18 of 28 09383-025 09383-008 09383-007 09383-006 09383-010 09383-009 09383-011 09383-012 AD9434 THEORY OF OPERATION The AD9434 architecture consists of a front-end sample-and- Differential Input Configurations hold amplifier (SHA) followed by a pipelined switched capacitor Optimum performance is achieved while driving the AD9434 ADC. The quantized outputs from each stage are combined into in a differential input configuration. For baseband applications, a final 12-bit result in the digital correction logic. The pipelined the AD8138 differential driver provides excellent performance architecture permits the first stage to operate on a new input and a flexible interface to the ADC. The output common-mode sample, whereas the remaining stages operate on preceding voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the samples. Sampling occurs on the rising edge of the clock. driver can be configured in a Sallen-Key filter topology to pro- Each stage of the pipeline, excluding the last, consists of a low vide band limiting of the input signal. resolution flash ADC connected to a switched capacitor DAC 1V p-p 49.9Ω and interstage residue amplifier (MDAC). The residue amplifier 499Ω magnifies the difference between the reconstructed DAC output AVDD 33Ω 499Ω VIN+ and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction 20pF AD8138 AD9434 523Ω of flash errors. The last stage simply consists of a flash ADC. 0.1µF VIN– 33Ω CML The input stage contains a differential SHA that can be ac- or 499Ω dc-coupled in differential or single-ended mode. The output Figure 41. Differential Input Configuration Using the AD8138 staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers At input frequencies in the second Nyquist zone and above, the are powered from a separate supply, allowing adjustment of the performance of most amplifiers may not be adequate to achieve output voltage swing. During power-down, the output buffers the true performance of the AD9434. This is especially true in enter a high impedance state. IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, ANALOG INPUT AND VOLTAGE REFERENCE differential transformer coupling is the recommended input The analog input to the AD9434 is a differential buffer. For best configuration. The signal characteristics must be considered dynamic performance, match the source impedances driving when selecting a transformer. Most RF transformers saturate at VIN+ and VIN− such that common-mode settling errors are frequencies below a few megahertz (MHz), and excessive signal symmetrical. The analog input is optimized to provide superior power can cause core saturation, which leads to distortion. wideband performance and requires that the analog inputs be In any configuration, the value of the shunt capacitor, C (see driven differentially. SNR and SINAD performance degrades Figure 43), is dependent on the input frequency and may need significantly if the analog input is driven with a single-ended to be reduced or removed. signal. A wideband transformer, such as Mini-Circuits® ADT1-1WT, 15Ω VIN+ can provide the differential analog inputs for applications that 1.5V p-p 50Ω 2pF require a single-ended-to-differential conversion. Both analog AD9434 inputs are self-biased by an on-chip reference to a nominal 1.7 V. VIN– 15Ω An internal differential voltage reference creates positive and 0.1µF negative reference voltages that define the 1.5 V p-p fixed span Figure 42. Differential Transformer—Coupled Configuration of the ADC core. This internal voltage reference can be adjusted by means of an SPI control. See the AD9434 Configuration As an alternative to using a transformer-coupled input at frequen- Using the SPI section for more details. cies in the second Nyquist zone, the AD8352 differential driver can be used (see Figure 43). Rev. A | Page 19 of 28 09383-014 09383-013 AD9434 V CC 0.1µF 0.1µF 0Ω 16 8, 13 1 0.1µF ANALOG INPUT 11 R 2 VIN+ 200Ω C R R AD8352 C AD9434 D D G 200Ω 3 0.1µF R CML VIN– 4 ANALOG INPUT 10 5 14 0Ω 0.1µF 0.1µF 0.1µF Figure 43. Differential Input Configuration Using the AD8352 AD9510/AD9511/ CLOCK INPUT CONSIDERATIONS AD9512/AD9513/ AD9514/AD9515 For optimum performance, drive the AD9434 sample clock 0.1µF 0.1µF CLOCK CLK CLK+ INPUT inputs (CLK+ and CLK−) with a differential signal. This signal ADC 100Ω is typically ac-coupled into the CLK+ and CLK− pins via a PECL DRIVER AD9434 0.1µF 0.1µF CLOCK transformer or capacitors. These pins are biased at ~0.9 V CLK– CLK INPUT 1 1 240Ω 240Ω internally and require no additional bias. If the clock signal is 50Ω 50Ω dc-coupled, then the common-mode voltage should remain 1 50Ω RESISTORS ARE OPTIONAL. within a range of 0.9 V. Figure 45. Differential PECL Sample Clock Figure 44 shows one preferred method for clocking the AD9434. AD9510/AD9511/ AD9512/AD9513/ The low jitter clock source is converted from single-ended to AD9514/AD9515 differential using an RF transformer. The back-to-back Schottky 0.1µF 0.1µF CLOCK CLK CLK+ diodes across the secondary transformer limit clock excursions INPUT ADC 100Ω into the AD9434 to approximately 0.8 V p-p differential. This LVDS DRIVER AD9434 0.1µF 0.1µF helps prevent the large voltage swings of the clock from feeding CLOCK CLK– CLK INPUT 1 1 through to other portions of the AD9434 and preserves the fast 50Ω 50Ω rise and fall times of the signal, which are critical to low jitter 1 50Ω RESISTORS ARE OPTIONAL. performance. Figure 46. Differential LVDS Sample Clock MINI-CIRCUITS In some applications, it may be acceptable to drive the sample ADT1–1WT, 1:1Z clock inputs with a single-ended 1.8 V CMOS signal. In such 0.1µF 0.1µF XFMR CLOCK CLK+ applications, drive the CLK+ pin directly from a CMOS gate, INPUT 100Ω ADC 50Ω and bypass the CLK− pin to ground with a 0.1 μF capacitor in 0.1µF AD9434 CLK– parallel with a 39 kΩ resistor (see Figure 47). 0.1µF SCHOTTKY DIODES: HSM2812 V CC OPTIONAL 0.1µF Figure 44. Transformer-Coupled Differential Clock 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER INPUT If a low jitter clock is available, another option is to ac couple a 1 1kΩ 50Ω ADC AD9434 differential PECL signal to the sample clock input pins, as CLK– shown in Figure 45. The AD9510/AD9511/AD9512/AD9513/ 0.1µF 39kΩ AD9514/AD9515 family of clock drivers offers excellent jitter performance. 1 50Ω RESISTOR IS OPTIONAL. Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. A | Page 20 of 28 09383-016 09383-015 09383-024 09383-018 09383-017 AD9434 Clock Duty Cycle Considerations POWER DISSIPATION AND POWER-DOWN MODE Typical high speed ADCs use both clock edges to generate a As shown in Figure 31, the power dissipated by the AD9434 is variety of internal timing signals. As a result, these ADCs may proportional to its sample rate. The digital power dissipation be sensitive to clock duty cycle. A 5% tolerance is commonly does not vary much because it is determined primarily by the required on the clock duty cycle to maintain dynamic performance DRVDD supply and bias current of the LVDS output drivers. characteristics. The AD9434 contains a duty cycle stabilizer (DCS) By asserting PDWN (Pin 29) high, the AD9434 is placed in that retimes the nonsampling edge, providing an internal clock standby mode or full power-down mode, as determined by the signal with a nominal 50% duty cycle. This allows a wide range contents of Serial Port Register 08. Reasserting the PDWN pin of clock input duty cycles without affecting the performance of low returns the AD9434 to its normal operational mode. the AD9434. An additional standby mode is supported by means of varying The duty cycle stabilizer uses a delay-locked loop (DLL) to the clock input. When the clock rate falls below 50 MHz, the create the nonsampling edge. As a result, any changes to the AD9434 assumes a standby state. In this case, the biasing network sampling frequency require approximately 5 μs to allow the and internal reference remain on, but digital circuitry is powered DLL to acquire and lock to the new rate. down. Upon reactivating the clock, the AD9434 resumes normal Clock Jitter Considerations operation after allowing for the pipeline latency. High speed, high resolution ADCs are sensitive to the quality of the DIGITAL OUTPUTS clock input. The degradation in SNR at a given input frequency Digital Outputs and Timing (fA) due only to aperture jitter (tJ) can be calculated by The AD9434 differential outputs conform to the ANSI-644 SNR Degradation = 20 × log (1/2 × π × f × t ) 10 A J LVDS standard on default power-up. This can be changed to a In this equation, the rms aperture jitter represents the root mean low power, reduced signal option similar to the IEEE 1596.3 square of all jitter sources, including the clock input, analog input standard using the SPI. This LVDS standard can further reduce signal, and ADC aperture jitter specifications. IF undersampling the overall power dissipation of the device, which reduces the applications are particularly sensitive to jitter (see Figure 48). power by ~39 mW. See the Memory Map section for more infor- mation. The LVDS driver current is derived on chip and sets Treat the clock input as an analog signal in cases where aperture the output current at each output equal to a nominal 3.5 mA. jitter may affect the dynamic range of the AD9434. Separate power A 100 Ω differential termination resistor placed at the LVDS supplies for clock drivers from the ADC output driver supplies receiver inputs results in a nominal 350 mV swing at the receiver. to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. The AD9434 LVDS outputs facilitate interfacing with LVDS If the clock is generated from another type of source (by gating, receivers in custom ASICs and FPGAs that have LVDS capability dividing, or other methods), it should be retimed by the for superior switching performance in noisy environments. original clock at the last step. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as Refer to the AN-501 Application Note and the AN-756 possible. No far end receiver termination or poor differential Application Note for more in-depth information about jitter trace routing may result in timing errors. It is recommended performance as it relates to ADCs (visit www.analog.com). that the trace length be no longer than 24 inches and that the 130 RMS CLOCK JITTER REQUIREMENT differential output traces be kept close together and at equal 120 lengths. 110 An example of the LVDS output using the ANSI standard (default) 100 16 BITS data eye and a time interval error (TIE) jitter histogram with 90 14 BITS trace lengths less than 24 inches on regular FR-4 material is 80 shown in Figure 49. Figure 50 shows an example of when the 12 BITS trace lengths exceed 24 inches on regular FR-4 material. Notice 70 10 BITS that the TIE jitter histogram reflects the decrease of the data eye 60 0.125ps opening as the edge deviates from the ideal position. It is up to 8 BITS 0.25ps 50 the user to determine if the waveforms meet the timing budget 0.5ps 40 1.0ps of the design when the trace lengths exceed 24 inches. 2.0ps 30 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) Figure 48. Ideal SNR vs. Input Frequency and Jitter Rev. A | Page 21 of 28 SNR (dB) 09383-019 AD9434 14 Out-of-Range (OR) 500 An out-of-range condition exists when the analog input voltage 12 400 is beyond the input range of the ADC. OR+ and OR− (OR±) 300 10 are digital outputs that are updated along with the data output 200 corresponding to the particular sampled input voltage. Thus, 100 8 OR± has the same pipeline latency as the digital data. OR± is 0 low when the analog input voltage is within the analog input 6 –100 range and high when the analog input voltage exceeds the input –200 4 range, as shown in Figure 51. OR± remains high until the analog –300 input returns to within the input range and another conversion –400 2 is completed. By logically AND’ing OR± with the MSB and its –500 complement, overrange high or underrange low conditions can 0 –3 –2 –1 0 1 2 3 –40 –20 0 20 40 be detected. TIME (ns) TIME (ps) +FS – 1 LSB OR± DATA OUTPUTS Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less 1 1111 1111 1111 OR± than 24 Inches on Standard FR-4, AD9434-500 0 1111 1111 1111 0 1111 1111 1110 600 12 –FS + 1/2 LSB 0 0000 0000 0001 400 10 0 0000 0000 0000 1 0000 0000 0000 200 8 –FS +FS –FS – 1/2 LSB +FS – 1/2 LSB 0 6 Figure 51. OR± Relation to Input Voltage and Output Data TIMING –200 4 The AD9434 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propaga- –400 2 tion delay (tPD) after the rising edge of the clock signal. –600 0 Minimize the length of the output data lines and loads placed –3 –2 –1 01 23 –100 0100 on them to reduce transients within the AD9434. These transi- TIME (ns) TIME (ps) ents can degrade the dynamic performance of the converter. Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9434-500 The AD9434 also provides a data clock output (DCO) intended for capturing the data in an external register. The data outputs are The format of the output data is offset binary by default. An valid on the rising edge of DCO. example of the output coding format can be found in Table 12. If it is desired to change the output data format to twos comple- The lowest conversion rate of the AD9434 is 50 MSPS. At clock ment, see the AD9434 Configuration Using the SPI section. rates below 1 MSPS, the AD9434 assumes the standby mode. An output clock signal is provided to assist in capturing data VREF from the AD9434. The DCO is used to clock the output data The AD9434 VREF pin (Pin 31) allows the user to monitor the and is equal to the sampling clock (CLK) rate. In single data on-board voltage reference, or provide an external reference rate mode (SDR), data is clocked out of the AD9434 and must (requires configuration through the SPI). The three optional be captured on the rising edge of the DCO. In double data rate settings are internal VREF (pin is connected to 20 kΩ to ground), mode (DDR), data is clocked out of the AD9434 and must be export V , and import V . Do not attach a bypass capacitor REF REF captured on the rising and falling edges of the DCO. See the to this pin. VREF is internally compensated and additional timing diagrams shown in Figure 2 and Figure 3 for more loading may impact performance. information. AD9434 CONFIGURATION USING THE SPI Output Data Rate and Pinout Configuration The AD9434 SPI allows the user to configure the converter for The output data of the AD9434 can be configured to drive 12 specific functions or operations through a structured register pairs of LVDS outputs at the same rate as the input clock signal space inside the ADC. This gives the user added flexibility to (SDR mode), or six pairs of LVDS outputs at 2× the rate of the customize device operation depending on the application. input clock signal (DDR mode). SDR is the default mode; the Addresses are accessed (programmed or readback) serially in device can be reconfigured for DDR by setting Bit 3 in Register 14 1-byte words. Each byte can be further divided into fields, (see Table 13). which are documented in the Memory Map section. Rev. A | Page 22 of 28 EYE DIAGRAM: VOLTAGE (mV) EYE DIAGRAM: VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) TIE JITTER HISTOGRAM (Hits) 09383-021 09383-020 09383-022 AD9434 There are three pins that define the serial port interface (SPI) to the W0 and W1 bits, which is one or more bytes of data. All this particular ADC. They are the SCLK/DFS, SDIO, and CSB data is composed of 8-bit words. The first bit of each individual pins. The SCLK/DFS (serial clock) is used to synchronize the byte of serial data indicates whether this is a read or write com- read and write data presented to the ADC. The SDIO (serial mand. This allows the serial data input/output (SDIO) pin to data input/output) is a dual-purpose pin that allows data to be change direction from an input to an output. sent to and read from the internal ADC memory map registers. Data can be sent in MSB or in LSB first mode. MSB first is The CSB is an active low control that enables or disables the default on power-up and can be changed by changing the read and write cycles (see Table 9). configuration register. For more information about this feature and others, see the AN-877 Application Note, Interfacing to USING THE AD9434 TO REPLACE THE AD9230 High Speed ADCs via SPI at www.analog.com. The AD9434 can be used to replace the AD9230 in many applications. In these designs, the user should consider these HARDWARE INTERFACE important differences: The pins described in Table 9 comprise the physical interface between the programming device of the user and the serial port • Pin 28 is a DNC (do not connect) on the AD9434, and of the AD9434. The SCLK pin and the CSB pin function as should be left floating. The reset functionality of the inputs when using the SPI interface. The SDIO pin is bidirec- AD9230 is not available through an external pin, but is available through the SPI interface. tional, functioning as an input during the write phase and as an output during readback. • Pin 31 is the interface to the AD9434 reference circuit. It can be used to monitor the internal reference or provide an This interface is flexible enough to be controlled by either external reference voltage (nominally 0.5 V). If the internal PROMs or PIC® mirocontrollers as well. This provides the user reference is used, then this pin can float. The RBIAS func- with an alternate method to program the ADC other than a SPI tion of the AD9230 is not necessary with the AD9434. controller. • The input voltage range of the AD9434 is nominally If the user chooses not to use the SPI interface, some pins serve 1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p. a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power- Table 9. Serial Port Pins on. The Configuration Without the SPI section describes the Mnemonic Function strappable functions supported on the AD9434. SCLK SCLK (serial clock) is the serial shift clock in. SCLK is used to synchronize serial interface CONFIGURATION WITHOUT THE SPI reads and writes. In applications that do not interface to the SPI control registers, SDIO SDIO (serial data input/output) is a dual-purpose pin. The typical role for this pin is an input and the SCLK/DFS pin can alternately serve as a standalone CMOS- output depending on the instruction being sent compatible control pin. In this mode, connect the CSB pin to and the relative position in the timing frame. AVDD, which disables the serial port interface. CSB CSB (chip select) is an active low control that gates the read and write cycles. Table 10. Mode Selection External The falling edge of the CSB, in conjunction with the rising edge Mnemonic Voltage Configuration of the SCLK, determines the start of the framing. An example of SCLK/DFS AVDD Twos complement enabled the serial timing and its definitions can be found in Figure 52 AGND Offset binary enabled and Table 11. During an instruction phase, a 16-bit instruction is transmitted. Data then follows the instruction phase and is determined by Rev. A | Page 23 of 28 AD9434 t t t t DS HIGH CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SDIO DON’T CARE R/W DON’T CARE Figure 52. Serial Port Interface Timing Diagram Table 11. Serial Timing Definitions Parameter Min (ns) Description t 5 Setup time between the data and the rising edge of SCLK DS t 2 Hold time between the data and the rising edge of SCLK DH tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK t 16 Minimum period that SCLK should be in a logic high state HIGH t 16 Minimum period that SCLK should be in a logic low state LOW t 1 EN_SDIO Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 52) tDIS_SDIO 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 52) Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode, D11 to D0 Twos Complement Mode, D11 to D0 OR± VIN+ − VIN− < −0.75 − 0.5 LSB 0000 0000 0000 1000 0000 0000 1 VIN+ − VIN− = −0.75 0000 0000 0000 1000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = 0.75 1111 1111 1111 0111 1111 1111 0 VIN+ − VIN− > 0.75 + 0.5 LSB 1111 1111 1111 0111 1111 1111 1 Rev. A | Page 24 of 28 09383-023 AD9434 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map table (see Table 13) has eight Undefined memory locations should not be written to other address locations. The memory map is roughly divided into than with the default values suggested in this data sheet. Addresses three sections: chip configuration register map (Address 0x00 to that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. Address 0x02), transfer register map (Address 0xFF), and ADC functions register map (Address 0x08 to Address 0x2A). DEFAULT VALUES The Addr. (Hex) column of the memory map indicates the Exiting out of reset, critical registers are preloaded with default register address in hexadecimal, and the Default Value (Hex) values. These values are indicated in Table 13. Other registers column shows the default hexadecimal value that is already do not have default values and retain the previous value when written into the register. The Bit 7 (MSB) column is the start of exiting reset. the default hexadecimal value given. For example, Hexadecimal LOGIC LEVELS Address 0x2A, OVR_CONFIG, has a hexadecimal default value of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, An explanation of various registers follows: “Bit is set” is Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in synonymous with “bit is set to Logic 1” or “writing Logic 1 for binary. The default value enables the OR± output. Overwriting the bit.” Similarly, “clear a bit” is synonymous with “bit is set to this default so that Bit 0 = 0 disables the OR± output. For more Logic 0” or “writing Logic 0 for the bit.” information on this and other functions, consult the AN-877 Application Note, Interfacing to High-Speed ADCs via SPI® at www.analog.com. Table 13. Memory Map Register Default Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 00 CHIP_PORT_CONFIG 0 LSB Soft 1 1 Soft LSB 0 0x18 The nibbles first reset reset first should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. 01 CHIP_ID 8-bit chip ID, Bits[7:0] = 0x6A Read Default is a only unique chip ID, different for each device. This is a read- only register. 1 1 1 02 CHIP_GRADE 0 0 0 Speed grade: X XX X Read Child ID used to only differentiate 00 = 500 MSPS graded devices. 01 = 370 MSPS Transfer Register FF DEVICE_UPDATE 0 0 0 0 0 0 0 SW 0x00 Synchronously transfer transfers data from the master shift register to the slave. ADC Functions Registers 08 Modes 0 0 PDWN: 0 0 Internal power-down mode: 0x00 Determines 0 = full 000 = normal (power-up, various generic (default) default) modes of chip 1 = 001 = full power-down operation. standby 010 = standby 011 = normal (power-up) Note that external PDWN pin overrides this setting Rev. A | Page 25 of 28 AD9434 Default Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 10 Offset 8-bit device offset adjustment [7:0] 0x00 Device offset trim: codes are 0111 1111 = +127 codes relative to the 0000 0000 = 0 codes output 1000 0000 = −128 codes resolution. 0D TEST_IO (For user-defined Reset Reset Output test mode: 0x00 When set, the mode only, set PN23 PN9 test data is 0000 = off (default) Bits[3:0] = 1000) gen: gen: placed on the 0001 = midscale short 00 = Pattern 1 only 1 = on 1 = on output pins in 0010 = +FS short 01 = toggle P1/P2 0 = off 0 = off place of normal 0011 = −FS short 10 = toggle (default) (default) data. 0100 = checkerboard output P1/0000 0101 = PN23 sequence Set pattern 11 = toggle P1/P2/ 0110 = PN9 values: 0000 0111 = one/zero word toggle P1 = Reg 0x19, 1000 = user defined Reg 0x1A 1001 = unused P2 = Reg 0x1B, 1010 = unused Reg 0x1C. 1011 = unused 1100 = unused (Format determined by OUTPUT_MODE) 0F AIN_CONFIG 0 0 0 0 0 Analog 0 0 0x00 input disable: 1 = on 0 = off (default) 14 OUTPUT_MODE 0 0 0 Output DDR: Output Data format select: 0x00 enable: 1 = invert: 00 = offset binary enabled 1 = on (default) 0 = 0 = 0 = off 01 = twos enable disabled (default) complement (default) (default) 10 = Gray code 1 = disable 15 OUTPUT_ADJUST 0 0 0 0 LVDS LVDS fine adjust: 0x00 course 001 = 3.50 mA adjust: 010 = 3.25 mA 0 = 011 = 3.00 mA 3.5 mA 100 = 2.75 mA (default) 101 = 2.50 mA 1 = 110 = 2.25 mA 2.0 mA 111 = 2.00 mA 16 OUTPUT_PHASE Output 0 0 0 0 0 0 0 0x00 clock polarity 1 = inverted 0 = normal (default) 17 FLEX_OUTPUT_DELAY 0 0 0 0 Output clock delay: 0x00 Shown as fractional value 0000 = 0 of sampling 0001 = −1/10 clock period 0010 = −2/10 that is 0011 = −3/10 subtracted or 0100 = reserved added to initial 0101 = +5/10 tSKEW, see 0110 = +4/10 Figure 2 0111 = +3/10 1000 = +2/10 1001 = +1/10 Rev. A | Page 26 of 28 AD9434 Default Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 18 FLEX_VREF VREF select 0 Input voltage range setting: 0x00 00 = internal VREF 11100 = 1.60 00101 = 1.36 (20 kΩ pull-down) 11101 = 1.58 00110 = 1.34 01 = import V REF 11110 = 1.55 00111 = 1.31 (0.59 V to 0.8 V on 11111 = 1.52 01000 = 1.28 VREF pin) 00000 = 1.50 01001 = 1.26 10 = export V REF (from internal 00001 = 1.47 01010 = 1.23 reference) 00010 = 1.44 01011 = 1.20 11 = not used 00011 = 1.42 01100 = 1.18 00100 = 1.39 19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A USER_PATT1_MSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 MSB. 1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSBs. 1C USER_PATT2_MSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 MSBs. 2A OVR_CONFIG 0 0 0 0 0 0 OR± OR± 0x01 position enable: (DDR 1 = on mode (default) only): 0 = off 0 = Pin 9, Pin 10 1 = Pin 21, Pin 22 2C Input coupling 0 0 0 0 0 DC 0 0 0x00 Default is coupling ac coupling. enable 1 X = don’t care. Rev. A | Page 27 of 28 AD9434 OUTLINE DIMENSIONS 0.30 8.10 0.60MAX 0.23 8.00SQ 0.18 7.90 0.60 MAX 43 56 42 1 0.50 PIN1 BSC INDICATOR 7.85 EXPOSED 7.75SQ 5.25 PAD 7.65 5.10SQ 4.95 14 29 28 15 0.50 0.25MIN BOTTOMVIEW TOPVIEW 0.40 6.50REF 0.30 0.80MAX 1.00 12°MAX 0.65TYP FORPROPERCONNECTIONOF 0.85 THEEXPOSEDPAD,REFERTO 0.05MAX 0.80 THEPINCONFIGURATIONAND 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.20REF 0.08 PLANE COMPLIANTTOJEDECSTANDARDSMO-220-VLLD-2 Figure 53. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-5) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9434BCPZ-370 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5 AD9434BCPZRL7-370 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5 AD9434BCPZ-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5 AD9434BCPZRL7-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5 AD9434-370EBZ LVDS Evaluation Board with AD9434BCPZ-370 AD9434-500EBZ LVDS Evaluation Board with AD9434BCPZ-500 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09383-0-5/11(A) Rev. A | Page 28 of 28 PIN1 INDICATOR 081809-B