ANALOG DEVICES AD9410

10-Bit, 210 MSPS ADC AD9410 FEATURES FUNCTIONAL BLOCK DIAGRAM REF REF V V V IN OUT AGND DGND D DD CC SNR = 54 dB with 99 MHz analog input 500 MHz analog bandwidth AD9410 On-chip reference and track and hold REFERENCE OR A 10 1.5 V p-p differential analog input range PORT D –D A9 A0 A 5.0 V and 3.3 V supply operation A ADC 10 IN 3.3 V CMOS/TTL outputs T/H 10-BIT A IN CORE Power: 2.1 W typical at 210 MSPS OR B 10 PORT Demultiplexed outputs each at 105 MSPS D –D B9 B0 B DS Output data format option DS TIMING AND CLK+ SYNCHRONIZATION Data sync input and data clock output provided CLK– DCO Interleaved or parallel data output option DCO DFS I/P APPLICATIONS Figure 1. Communications and radars Local multipoint distribution services (LMDS) High-end imaging systems and projectors Cable reverse paths Point-to-point radio links GENERAL DESCRIPTION The AD9410 is a 10-bit monolithic sampling analog-to-digital Fabricated on an advanced BiCMOS process, the AD9410 is converter (ADC) with an on-chip track-and-hold circuit and is available in an 80-lead thin quad flat package, exposed pad optimized for high speed conversion and ease of use. The product specified over the industrial temperature range (−40°C to +85°C). operates at a 210 MSPS conversion rate, with outstanding PRODUCT HIGHLIGHTS dynamic performance over its full operating range. 1. High Resolution at High Speed—The architecture is spe- The ADC requires a 5.0 V and 3.3 V power supply and up to a cifically designed to support conversion up to 210 MSPS 210 MHz differential clock input for full performance operation. with outstanding dynamic performance. No external reference or driver components are required for many 2. Demultiplexed Output—Output data is decimated by two applications. The digital outputs are TTL-/CMOS-compatible and and provided on two data ports for ease of data transport. separate output power supply pins also support interfacing with 3.3 V logic. 3. Output Data Clock—The AD9410 provides an output data clock synchronous with the output data, simplifying the The clock input is differential and TTL-/CMOS-compatible. timing between data and other logic. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data 4. Data Synchronization—A DS input is provided to allow for up to 105 MSPS rates and binary or twos complement output synchronization of two or more AD9410s in a system, or to coding format is available. A data sync function is provided for synchronize data to a specific output port in a single timing-dependent applications. An output clock simplifies AD9410 system. interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01679-001 AD9410 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications....................................................................................... 1 Terminology.................................................................................... 10 Functional Block Diagram .............................................................. 1 Equivalent Circuits..................................................................... 12 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 13 Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 16 Revision History ............................................................................... 2 Using the AD9410 ...................................................................... 16 Specifications..................................................................................... 3 Analog Input ............................................................................... 16 DC Specifications ......................................................................... 3 Digital Outputs ........................................................................... 16 Switching Specifications .............................................................. 4 Clock Outputs (DCO, DCO).................................................... 16 Digital Specifications ................................................................... 4 Voltage Reference ....................................................................... 17 AC Specifications.......................................................................... 5 Timing ......................................................................................... 17 Absolute Maximum Ratings............................................................ 7 Data Sync (DS) ........................................................................... 17 Explaination of Test Levels.......................................................... 7 Outline Dimensions ....................................................................... 19 ESD Caution.................................................................................. 7 Ordering Guide .......................................................................... 19 REVISION HISTORY 7/07—Rev. 0 to Rev. A 10/00—Revision 0: Initial Version Updated Format..................................................................Universal Deleted 80-Lead LQFP_EP ...............................................Universal Added 80-Lead TQFP_EP.................................................Universal Changes to Figure 1 and General Description ............................. 1 Changes to Table 2 and Table 3....................................................... 4 Changes to Figure 2.......................................................................... 6 Changes to Note 1............................................................................. 7 Changes to Figure 3 and Table 6..................................................... 8 Changes to Terminology Section.................................................. 10 Changes to Figure 6........................................................................ 12 Deleted Evaluation Board Section................................................ 14 Renamed Encode Input Section, Clock Input Section and DCO Changes to Clock Input Section, Clock Outputs (DCO, ) Section, Figure 26, and Figure 27 ................................................. 16 Changes to Data Sync (DS) Section ............................................. 17 Changes to Figure 29...................................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 Rev. A | Page 2 of 20 AD9410 SPECIFICATIONS DC SPECIFICATIONS V = 3.3 V, V = 3.3 V, V = 5.0 V; 2.5 V external reference; A = −0.5 dBFS; clock input = 210 MSPS; T = 25°C; unless otherwise noted. DD D CC IN A Table 1. Parameter Temp Test Level Min Typ Max Unit RESOLUTION 10 Bits DC ACCURACY No Missing Codes Full IV Guaranteed Differential Nonlinearity 25°C I −1.0 ±0.5 +1.25 LSB Full VI −1.0 +1.5 LSB Integral Nonlinearity 25°C I −2.5 ±1.65 +2.5 LSB Full VI −3.0 +3.0 LSB Gain Error 25°C I −6.0 0 +6.0 % FS Gain Temperature Coefficient Full V 130 ppm/°C ANALOG INPUT Input Voltage Range (With Respect to A ) Full V ±768 mV p-p IN Common-Mode Voltage Full V 3.0 V Input Offset Voltage 25°C I −15 +3 +15 mV Full VI −20 +20 mV Reference Voltage Full VI 2.4 2.5 2.6 V Reference Temperature Coefficient Full V 50 ppm/°C Input Resistance Full VI 610 875 1250 Ω Input Capacitance 25°C V 3 pF Analog Bandwidth, Full Power 25°C V 500 MHz POWER SUPPLY 1 Power Dissipation AC 25°C V 2.1 W 2 Power Dissipation DC Full VI 2.0 2.4 W 2 I Full VI 128 145 mA VCC 2 I Full VI 401 480 mA VD Power Supply Rejection Ratio, PSRR 25°C I −7.5 +0.5 +7.5 mV/V 1 Clock input = 210 MSPS, AIN = –0.5 dBFS, 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF. 2 Clock input = 210 MSPS, A = dc, outputs not switching. IN Rev. A | Page 3 of 20 AD9410 SWITCHING SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted. Table 2. Parameter Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Clock Pulse Width High, tEH 25°C IV 1.2 2.4 ns Clock Pulse Width Low, t 25°C IV 1.2 2.4 ns EL Aperture Delay, t 25°C V 1.0 ns A Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms Output Valid Time, tV Full VI 3.0 ns Output Propagation Delay, tPD Full VI 7.4 ns Output Rise Time, t 25°C V 1.8 ns R Output Fall Time, t 25°C V 1.4 ns F 1 CLKOUT Propagation Delay, tCPD Full VI 2.6 4.8 6.4 ns Data to DCO Skew, (tPD – tCPD) Full IV 0 1 2 ns DS Setup Time, tSDS Full IV 0.5 ns DS Hold Time, tHDS Full IV 0 ns Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles 1 CLOAD = 5 pF. DIGITAL SPECIFICATIONS V = 3.3 V, V = 3.3 V, V = 5.0 V; 2.5 V external reference; A = −0.5 dBFS; clock input = 210 MSPS; T = 25°C; unless otherwise noted. DD D CC IN A Table 3. Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS DFS, Input Logic 1 Voltage Full IV 4 V DFS, Input Logic 0 Voltage Full IV 1 V DFS, Input Logic 1 Current Full V 50 μA DFS, Input Logic 0 Current Full V 50 μA 1 I/P Input Logic 1 Current Full V 400 μA 1 I/P Input Logic 0 Current Full V 1 μA CLK+, CLK− Differential Input Voltage Full IV 0.4 V CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ 2 CLK+, CLK− Common-Mode Input Voltage Full V 1.5 V DS, DS Differential Input Voltage Full IV 0.4 V DS, DS Common-Mode Input Voltage Full V 1.5 V Digital Input Pin Capacitance 25°C V 3 pF DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3.3 V) Full VI VDD – 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 V Output Coding Binary or Twos Complement 1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to V when setting to Logic 1 to limit input current. DD 2 See Clock Input section. Rev. A | Page 4 of 20 AD9410 AC SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted. Table 4. Parameter Temp Test Level Min Typ Max Unit DYNAMIC PERFORMANCE Transient Response 25°C V 2 ns Overvoltage Recovery Time 25°C V 2 ns Signal-to-Noise Ratio, SNR (Without Harmonics) f = 10.3 MHz 25°C I 52.5 55 dB IN f = 82 MHz 25°C I 52 54 dB IN fIN = 160 MHz 25°C V 53 dB Signal-to-Noise Ratio, SINAD (With Harmonics) fIN = 10.3 MHz 25°C I 51 54 dB f = 82 MHz 25°C I 50 53 dB IN f = 160 MHz 25°C V 52 dB IN Effective Number of Bits, ENOB fIN = 10.3 MHz 25°C I 8.3 8.8 Bits fIN = 82 MHz 25°C I 8.1 8.6 Bits fIN = 160 MHz 25°C V 8.4 Bits Second Harmonic Distortion f = 10.3 MHz 25°C I −56 −65 dBc IN f = 82 MHz 25°C I −55 −63 dBc IN fIN = 160 MHz 25°C V −65 dBc Third Harmonic Distortion fIN = 10.3 MHz 25°C I −58 −69 dBc f = 82 MHz 25°C I −57 −67 dBc IN f = 160 MHz 25°C V −62 dBc IN Spurious-Free Dynamic Range, SFDR fIN = 10.3 MHz 25°C I 56 61 dBc fIN = 82 MHz 25°C I 54 60 dBc f = 160 MHz 25°C V 58 dBc IN 1 Two-Tone Intermod Distortion, IMD f = 80.3 MHz, f = 81.3 MHz 25°C V 58 dBFS IN1 IN2 1 IN1, IN2 level = −7 dBFS. Rev. A | Page 5 of 20 AD9410 SAMPLE N+3 SAMPLE N+4 SAMPLE N SAMPLE N–1 SAMPLE N+5 A IN t A SAMPLE N+1 SAMPLE N+2 SAMPLE N+6 SAMPLE N–2 t t EH EL 1/f S CLK+ CLK– t SDS t HDS DS DS t t PD V INTERLEAVED DATA OUT PORT A STATIC INVALID INVALID INVALID DATA N+1 DATA N+3 D7 TO D0 PORT B STATIC INVALID INVALID INVALID DATA N DATA N+2 D7 TO D0 PARALLEL DATA OUT PORT A STATIC INVALID INVALID INVALID INVALID DATA N+1 D7 TO D0 PORT B STATIC INVALID INVALID INVALID DATA N DATA N+2 D7 TO D0 t CPD DCO STATIC DCO Figure 2. Timing Diagram Rev. A | Page 6 of 20 01679-002 AD9410 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V , V , V 6 V D CC DD other conditions above those indicated in the operational Analog Inputs 0 V to V + 0.5 V CC section of this specification is not implied. Exposure to absolute Digital Inputs 0 V to VDD + 0.5 V maximum rating conditions for extended periods may affect VREFIN 0 V to VD + 0.5 V device reliability. Digital Output Current 20 mA Operating Temperature Range −55°C to +125°C Storage Temperature Range −65°C to +150°C EXPLAINATION OF TEST LEVELS 1 Maximum Junction Temperature 150°C Test Level 1 Adequate dissipation of power from the AD9410 relies on all power and I. 100% production tested. ground pins of the device being soldered directly to a copper plane on a PCB. In addition, the thermally enhanced package of the AD9410BSVZ has an II. 100% production tested at 25°C and sample tested at exposed paddle on the bottom that must be soldered to a large copper plane, which, for convenience, can be the ground plane. Sockets for package specified temperatures. style of the AD9410 device are not recommended. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. ESD CAUTION Rev. A | Page 7 of 20 AD9410 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AGND 1 60 V DD PIN 1 2 59 AGND DGND IDENTIFIER 3 58 V D CC A4 4 57 REF D OUT A3 5 56 REF D IN A2 DNC 6 55 D A1 V 7 54 D (LSB) CC A0 AGND 8 53 V DD AGND 9 52 DGND AD9410 TOP VIEW 10 51 A DCO IN 80-LEAD THIN QUAD FLAT PACKAGE 11 50 A DCO IN (Not to Scale) 12 49 AGND DGND AGND 13 48 V DD V 14 47 OR CC B V 15 46 D (MSB) CC B9 AGND 16 45 D B8 AGND 17 44 D B7 CLK+ 18 43 D B6 CLK– 19 42 D B5 20 41 AGND V DD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DNC = DO NOT CONNECT. Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Function 1, 2, 8, 9, 12, 13, 16, AGND Analog Ground. 17, 20, 21, 24, 27, 28, 29, 30, 71, 72, 73, 74, 77, 78 3, 7, 14, 15 VCC 5 V Supply. (Regulate to within ±5%.) 4 REFOUT Internal Reference Output. 5 REFIN Internal Reference Input. 6 DNC Do Not Connect. 10 AIN Analog Input—True. 11 A Analog Input—Complement. IN 18 CLK+ Clock Input—True. 19 CLK− Clock Input—Complement. 22 DS Data Sync (Input)—True. Tie low if not used. 23 DS Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used. 25, 26, 31, 32, 69, 70, VD 3.3 V Analog Supply. (Regulate to within ±5%.) 75, 76 33, 40, 49, 52, 59, 68 DGND Digital Ground. 34, 41, 48, 53, 60, 67 V 3.3 V Digital Output Supply. (2.5 V to 3.6 V) DD 35 to 39 D to D Digital Data Output for Channel B. (LSB = D .) B0 B4 B0 42 to 46 D to D Digital Data Output for Channel B. (MSB = D .) B5 B9 B9 47 OR Data Overrange for Channel B. B 50 DCO Clock Output—Complement. Rev. A | Page 8 of 20 AGND I/P DS DFS DS AGND AGND AGND V V D D V V D D AGND AGND AGND AGND AGND AGND AGND AGND V V D D V V D D DGND DGND V V DD DD (LSB) D OR B0 A D D (MSB) B1 A9 D D B2 A8 D D B3 A7 D D B4 A6 DGND D A5 01679-003 AD9410 Pin No. Mnemonic Function 51 DCO Clock Output—True. 54 to 58 DA0 to DA4 Digital Data Output for Channel A (LSB = DA0). 61 to 65 DA5 to DA9 Digital Data Output for Channel A (MSB = DA9). 66 ORA Data Overrange for Channel A. 79 DFS Data Format Select. High = twos complement, and low = binary. 80 I/P Interleaved or Parallel Output Mode. Low = parallel mode, and high = interleaved mode. If tying high, use a current limiting series resistor (2.5 kΩ) to the 5 V supply. Rev. A | Page 9 of 20 AD9410 TERMINOLOGY Full-Scale Input Power Analog Bandwidth Expressed in dBm. Computed using the equation The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is ⎡ ⎤ ⎢ 2 ⎥ reduced by 3 dB. V FULLSCALE rms ⎢ ⎥ POWER = 10 log FULLSCALE Aperture Delay Z ⎢ ⎥ INPUT ⎢ ⎥ The delay between the 50% point of the rising edge of the clock ⎣ 0.001 ⎦ command and the instant at which the analog input is sampled. Harmonic Distortion, Second Aperture Uncertainty (Jitter) The ratio of the rms signal amplitude to the rms value of the The sample-to-sample variation in aperture delay. second harmonic component, reported in dBc. Differential Analog Input Resistance, Differential Analog Harmonic Distortion, Third Input Capacitance, and Differential Analog Input Impedance The ratio of the rms signal amplitude to the rms value of the The real and complex impedances measured at each analog third harmonic component, reported in dBc. input port. The resistance is measured statically and the Integral Nonlinearity capacitance and differential input impedances are measured The deviation of the transfer function from a reference line with a network analyzer. measured in fractions of 1 LSB using a best straight line Differential Analog Input Voltage Range determined by a least-square curve fit. The peak-to-peak differential voltage that must be applied to Minimum Conversion Rate the converter to generate a full-scale response. Peak differential The clock rate at which the SNR of the lowest analog voltage is computed by observing the voltage on a single pin signal frequency drops by no more than 3 dB below the and subtracting the voltage from the other pin, which is 180° guaranteed limit. out of phase. Peak-to-peak differential is computed by rotating Maximum Conversion Rate the inputs phase 180° and taking the peak measurement again. The clock rate at which parametric testing is performed. The difference is then computed between both peak measurements. Output Propagation Delay The delay between a differential crossing of CLK+ and Differential Nonlinearity CLK− and the time when all output data bits are within valid The deviation of any code width from an ideal 1 LSB step. logic levels. Effective Number of Bits (ENOB) Out-of-Range Recovery Time ENOB is calculated from the measured SINAD based on the Out-of-range recovery time is the time it takes for the ADC to equation reacquire the analog input after a transient from 10% above ENOB= positive full scale to 10% above negative full scale, or from 10% ⎛ Full Scale Amplitude⎞ below negative full scale to 10% below positive full scale. ⎜ ⎟ SINAD − 1.76 dB+ 20 log MEASURED ⎜ ⎟ Input Amplitude Noise (For Any Range Within the ADC) ⎝ ⎠ 6.02 FS − SIGNAL ⎛ ⎞ dBm dBFS V = | Z |× 0.001×10⎜ ⎟ NOISE Clock Pulse Width/Duty Cycle 10 ⎝ ⎠ Pulse width high is the minimum amount of time that the clock where: pulse should be left in Logic 1 state to achieve rated performance; Z is the input impedance. pulse width low is the minimum time the clock pulse should be FS is the full scale of the device for the frequency in question. left in low state. At a given clock rate, these specifications define SIGNAL is the signal level within the ADC reported in dB an acceptable clock duty cycle. below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. Rev. A | Page 10 of 20 AD9410 Signal-to-Noise-and-Distortion (SINAD) Two-Tone Intermodulation Distortion Rejection The ratio of the rms signal amplitude (set 0.5 dB below full The ratio of the rms value of either input tone to the rms scale) to the rms value of the sum of all other spectral value of the worst third-order intermodulation product; components, including harmonics, but excluding dc. reported in dBc. Signal-to-Noise Ratio (Without Harmonics) Two-Tone SFDR The ratio of the rms signal amplitude (set at 0.5 dB below full The ratio of the rms value of either input tone to the rms value scale) to the rms value of the sum of all other spectral of the peak spurious component. The peak spurious component components, excluding the first five harmonics and dc. may or may not be an IMD product. May be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always Spurious-Free Dynamic Range (SFDR) related back to converter full scale). The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious Worst Other Spur component may or may not be a harmonic. It may be reported The ratio of the rms signal amplitude to the rms value of the in dBc (that is, degrades as signal level is lowered) or dBFS worst spurious component (excluding the second and third (always related back to converter full scale). harmonic) reported in dBc. Transient Response Time Transient response time is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Table 7. Output Coding (VREF = 2.5 V) Step AIN − AIN Digital Outputs Offset Binary Digital Outputs Twos Complement ORA, ORB >+0.768 11 1111 1111 01 1111 1111 1 1023 +0.768 11 1111 1111 01 1111 1111 0 · · · · · · · · · · 513 +0.0015 10 0000 0001 00 0000 0001 0 512 0.0 10 0000 0000 00 0000 0000 0 511 –0.0015 01 1111 1111 11 1111 1111 0 · · · · · · · · · · 0 –0.768 00 0000 0000 10 0000 0000 0 < –0.768 00 0000 0000 10 0000 0000 1 Rev. A | Page 11 of 20 AD9410 EQUIVALENT CIRCUITS V CC 1.5kΩ 1.5kΩ V CC A IN A IN 2.25kΩ 2.25kΩ VREF OUT Figure 4. Equivalent Analog Input Circuit Figure 8. Equivalent Reference Output Circuit V CC V CC VREF IN DFS 100kΩ Figure 5. Equivalent Reference Input Circuit Figure 9. Equivalent DFS Input Circuit V CC V CC 450Ω 450Ω 17.5kΩ 17kΩ 17kΩ 300Ω 300Ω DS DS CLK– CLK+ 100Ω 100Ω 8kΩ 8kΩ 7.5kΩ Figure 6. Equivalent Clock Input Circuit Figure 10. Equivalent DS Input Circuit V CC 17.5kΩ V 300Ω DD I/P 7.5kΩ DIGITAL OUTPUT Figure 7. Equivalent Digital Output Circuit Figure 11. Equivalent I/P Input Circuit Rev. A | Page 12 of 20 01679-007 01679-005 01679-004 01679-006 01679-008 01679-009 01679-011 01679-010 AD9410 TYPICAL PERFORMANCE CHARACTERISTICS 0 55 ENCODE = 210MSPS A = 40MHz @ –0.5dBFS 54 IN SNR = 54.5dB –20 53 SINAD = 53.5dB SNR 52 –40 51 –60 50 49 –80 48 SINAD 47 –100 46 –120 45 0 105 0 50 100 150 200 250 FREQUENCY (MHz) A (MHz) IN Figure 12. Single Tone at 40 MHz; 210 MSPS Figure 15. SNR/SINAD vs. A ; 210 MSPS IN 0 55.0 ENCODE = 210MSPS A = 100MHz @ –0.5dBFS IN 54.5 SNR = 53.5dB SNR –20 SINAD = 52.5dB 54.0 53.5 –40 53.0 –60 52.5 SINAD 52.0 –80 51.5 51.0 –100 50.5 –120 50.0 0 105 100 120 140 160 180 200 220 240 FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 13. Single Tone at 100 MHz; 210 MSPS Figure 16. SNR/SINAD vs. Sample Rate; AIN = 70 MHz 0 60 ENCODE = 210MSPS A = 160MHz @ –0.5dBFS IN SNR = 53dB –20 55 SINAD = 52dB SNR SINAD –40 50 –60 45 –80 40 –100 35 –120 30 0 105 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (MHz) PULSE WIDTH (ns) Figure 14. Single Tone at 160 MHz; 210 MSPS Figure 17. SNR/SINAD vs. Clock Positive Pulse Width (f = 210 MSPS, A = 70 MHz) S IN Rev. A | Page 13 of 20 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 01679-014 01679-013 01679-012 SNR/SINAD (dB) SNR/SINAD (dB) SNR/SINAD (dB) 01679-015 01679-017 01679-016 AD9410 0 2.52 ENCODE = 210MSPS A 1, A 2 = –7dBFS IN IN SFDR = 62dBFS –20 2.51 –40 2.50 –60 2.49 –80 2.48 –100 2.47 –120 2.46 0 105 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 FREQUENCY (MHz) ANALOG SUPPLY (V) Figure 18. Two Tone Test A 1 = 80.3 MHz, A 2 = 81.3 MHz IN IN Figure 21. VREFOUT vs. Analog 5 V Supply 55.5 460 IAhi3 410 55.0 360 54.5 310 54.0 SNR 260 53.5 210 53.0 160 IAhi5 52.5 110 SINAD 52.0 60 Ivdd 10 51.5 –40 –20 0 20 40 60 80 100 120 100 120 140 160 180 200 220 TEMPERATURE (°C) SAMPLE RATE (MSPS) Figure 19. SNR/SINAD vs. Temperature, 210 MSPS, AIN = 70 MHz Figure 22. Power Supply Currents vs. Sample Rate 74 2.55 72 2.50 H2 70 2.45 68 66 2.40 H3 64 2.35 62 2.30 60 2.25 58 –40 –20 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (mA) TEMPERATURE (°C) Figure 23. VREFOUT vs. ILOAD Figure 20. Second and Third Harmonics vs. Temperature; AIN = 70 MHz, 210 MSPS Rev. A | Page 14 of 20 SNR/SINAD (dB) SECOND AND THIRD HARMONIC AMPLITUDE (dB) AMPLITUDE (dB) 01679-018 01679-020 01679-019 VREF (V) SUPPLY CURRENT (mA) VREF (V) 01679-023 01679-022 01679-021 AD9410 2.503 5.1 2.502 4.9 t PD 2.501 4.7 2.500 t V 4.5 2.499 4.3 2.498 t CPD 4.1 2.497 2.496 3.9 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 24. VREFOUT vs. Temperature Figure 25. tPD, tV, tCPD vs. Temperature Rev. A | Page 15 of 20 VREF (V) 01679-024 TIMING SPECIFICATIONS (ns) 01679-025 AD9410 THEORY OF OPERATION The AD9410 architecture is optimized for high speed and ease ANALOG INPUT of use. The analog inputs drive an integrated high bandwidth The analog input to the AD9410 is a differential buffer. For best track-and-hold circuit that samples the signal prior to A dynamic performance, impedances at AIN and IN should quantization by the flash 10-bit core. For ease of use, the part match. The analog input has been optimized to provide includes an on-board reference and input logic that accepts superior wideband performance and requires that the analog TTL, CMOS, or PECL levels. inputs be driven differentially. SNR and SINAD performance USING THE AD9410 degrades significantly if the analog input is driven with a single- ended signal. A wideband transformer, such as Mini-Circuits Clock Input ADT1-1WT, can be used to provide the differential analog Any high speed ADC is extremely sensitive to the quality of the inputs for applications that require a single-ended-to- sampling clock provided by the user. A track-and-hold circuit is differential conversion. Both analog inputs are self-biased by an essentially a mixer, and any noise, distortion, or timing jitter on on-chip resistor divider to nominal 3 V (see the Equivalent the clock combines with the desired signal at the ADC output. Circuits section). For that reason, considerable care has been taken in the design Special care was taken in the design of the Analog Input section of the clock input of the AD9410, and the user is advised to give of the AD9410 to prevent damage and corruption of data when commensurate thought to the clock source. To limit SNR the input is overdriven. The nominal input range is 1.5 V diff p-p. degradation to less than 1 dB, a clock source with less than 1.25 ps rms jitter is required for sampling at Nyquist (for The nominal differential input range is 768 mV p-p × 2. example, the Valpey Fisher VF561). Note that required jitter accuracy is a function of input frequency and amplitude. Refer to the Analog Devices, Inc. AN-501 application note, Aperture A IN 3.384 Uncertainty and ADC System Performance, for more information. The clock input is fully TTL/CMOS compatible. The clock 3.000 input can be driven differentially or with a single-ended signal. Best performance is obtained when driving the clock differentially. A Both clock inputs are self-biased to 1/3 × VCC by a high impedance IN 2.616 resistor divider (see the Equivalent Circuits section). Single- ended clocking, which can be appropriate for lower frequency or nondemanding applications, is accomplished by driving the clock input directly and placing a 0.1 μF capacitor at CLOCK. Figure 28. Typical Analog Input Levels DIGITAL OUTPUTS TTL/ AD9410 CMOS CLK+ The digital outputs are TTL/CMOS compatible for lower power GATE CLK– consumption. The outputs are biased from a separate supply 0.1µF (V ), allowing easy interface to external logic. The outputs are DD CMOS devices that swing from ground to V (with no dc DD Figure 26. Driving Single-Ended Clock Input at TTL/CMOS Levels load). It is recommended to minimize the capacitive load the An example where the clock is obtained from a PECL driver is ADC drives by keeping the output traces short (<1 inch, for a shown in Figure 27. Note that the PECL driver is ac-coupled to total CLOAD < 5 pF). It is also recommended to place low value the clock inputs to minimize input current loading. The (20 Ω) series damping resistors on the data lines to reduce AD9410 can be dc-coupled to PECL logic levels, resulting in the switching transient effects on performance. clock input currents increasing to approximately 8 mA typical, CLOCK OUTPUTS (DCO, DCO) which is due to the difference in dc bias between the clock inputs and a PECL driver (see the Equivalent Circuits section). The input clock is divided by two and available off-chip at DCO and DCO. These clocks can facilitate latching off-chip, 0.1µF AD9410 CLK+ providing a low skew clocking solution (see Figure 2). These PECL 0.1µF GATE clocks can also be used in multiple AD9410 systems to CLK– synchronize the ADCs. Depending on application, DCO or 510Ω 510Ω DCO can be buffered and used to drive the DS inputs on a second AD9410, ensuring synchronization. The on-chip clock GND buffers should not drive more than 5 pF to 7 pF of capacitance Figure 27. Driving the Clock Inputs Differentially to limit switching transient effects on performance. Rev. A | Page 16 of 20 01679-026 01679-027 INPUT SPAN (V) 01679-028 AD9410 VOLTAGE REFERENCE DATA SYNC (DS) A stable and accurate 2.5 V voltage reference is built into the The data sync input, DS, can be used in applications requiring AD9410 (VREFOUT). The input range can be adjusted by varying that a given sample appear at a specific output Port A or Port B. the reference voltage. No appreciable degradation in When DS is held high, the ADC data outputs and clock do not performance occurs when the reference is adjusted ±5%. The switch and are held static. Synchronization is accomplished by full-scale range of the ADC tracks reference voltage changes the assertion (falling edge) of DS, within the timing constraints linearly within the ±5% tolerance. t and t relative to an clock rising edge. (On initial SDS HDS synchronization, tHDS is not relevant.) If DS falls within the TIMING required setup time (tSDS) before a given clock rising edge N, the The AD9410 provides latched data outputs, with six pipeline analog value at that point is digitized and available at Port B six delays in interleaved mode (see Figure 2). In parallel mode, the cycles later (interleaved mode). The next sample, N+1, is Port A has one additional cycle of latency added on-chip to line sampled by the next rising clock edge and available at Port A six up transitions at the data ports, resulting in a latency of seven cycles after that clock edge (interleaved mode). In dual parallel cycles for the Port A. The length of the output data lines and mode, Port A has a seven cycle latency, and Port B has a six loads placed on them should be minimized to reduce transients cycle latency, but data is available at the same time. within the AD9410; these transients can detract from the dynamic performance of the converter. The minimum guaranteed conversion rate of the AD9410 is 100 MSPS. At internal clock rates below 100 MSPS, dynamic performance may degrade. Note that lower effective sampling rates can be obtained simply by sampling just one output port— decimating the output by two. Lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulse width is a maximum of 5 ns. Rev. A | Page 17 of 20 AD9410 GND GND GND C1 C2 C3 C5 C4 5V 5V C40 MC10EL16 10µF 10µF 10µF 10µF 10µF 0.1µF R19 R14 R11 C7 1 NC VCC 8 5V 330Ω J1 8.2kΩ 8.2kΩ 0.1µF 3.3VA VDD EXT REF VDAC 5V 2 7 D Q ENCT U1 C6 3 6 R8 D Q ENCC 0.1µF 1 VDAC GND 50Ω R18 R9 C8 R15 4 VBB VEE 5 GND 24kΩ 24kΩ 330Ω 0.1µF 2 GND GND P4 3 EXT REF GND GND GND 4 GND GND VDD 5V 1 GND C14 3.3VA 0.1µF 2 GND C10 R6 R4 3.3VA P1 0.1µF 100Ω 2.5kΩ GND NOTE: 3 VDD/3.3V R3, R6, R7, R24 OPTIONAL GND GND 4 DA9 (CAN BE ZERO Ω ) GND C11 E10 E16 R7 0.1µF DA8 1 3.3VA R24 100Ω GND DA7 100Ω E12 2 3.3VA GND 3.3VA 5V GND DA6 E7 P5 3 5V GND GND DAOR DA5 E11 R3 100Ω 4 GND GND GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 E14 C12 0.1µF GND V DD 60 GND 1 AGND VDD C27 2 AGND DGND 59 GND GND 0.1µF 3 V GND 5V CC D 58 A4 DA4 C28 REF 4 OUT D A3 57 E6 DA3 0.1 F EXT REF 5 IN D 56 DA2 A2 REF E3 E1 DNC 6 D 55 DA1 A1 7 V 5V CC D 54 A0 DA0 C26 AGND 8 0.1µF V 53 DD VDD 9 GND AGND C21 GND DGND 52 GND T1 0.1µF 1 6 A 10 IN GND DCO 51 DCOT C7 AD9410 2 R27 GND 5 11 A J8 0.1µF IN 50Ω U3 50 DCO DCOC 3 4 12 AGND GND GND 1:1 AIN DGND 49 GND C24 AGND R23 C25 13 V 48 VDD DD 0.1µF GND 50Ω 0.1µF 14 V C22 GND CC OR B 47 DBOR 0.1µF GND 5V 15 V CC D B9 46 DB9 GND GND GND 16 AGND D 45 B8 DB8 17 AGND D B7 44 DB7 D ENCT 18 CLK+ B6 43 DB6 D 42 ENCC 19 CLK– B5 DB5 V DD 41 VDD 20 AGND GND C18 0.1µF 21 23 25 27 29 31 33 34 36 22 24 26 28 30 32 35 37 38 39 40 GND J9X GND DB0 3.3VA GND GND GND DB1 DB2 R26 C15 3.3VA 50Ω DB3 0.1µF C19 DB4 J10X GND GND 0.1µF GND R25X 3.3VA VDD 50Ω GND GND C16 3.3VA 0.1µF Figure 29. PCB Schematic Example Rev. A | Page 18 of 20 I/P AGND DFS DS AGND DS AGND AGND V D V D V D V D AGND AGND AGND AGND AGND AGND AGND AGND V D V D V D V D DGND DGND V DD V DD OR A D B0 D A9 D B1 D A8 D B2 D A7 D B3 D A6 D B4 D A5 DGND 01679-029 AD9410 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 14.20 1.20 14.00 SQ 0.75 MAX 13.80 0.60 0.45 80 61 61 80 1 60 60 1 PIN 1 EXPOSED 9.50 SQ TOP VIEW PAD (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 (PINS UP) 0.09 20 41 41 20 0.95 7° 21 21 40 40 3.5° VIEW A 0.15 SEATING 0° 0.65 BSC 0.27 PLANE 0.05 0.08 MAX LEAD PITCH 0.22 COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD Figure 30. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Option 1 AD9410BSVZ −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-4 1 Z = RoHS Compliant Part. Rev. A | Page 19 of 20 091506-A AD9410 NOTES ©2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01679-0-7/07(A) Rev. A | Page 20 of 20