ANALOG DEVICES AD9289

Quad 8-Bit, 65 MSPS, Serial LVDS 3 V A/D Converter AD9289 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DFS PDWN DTP DRVDD DRGND Four ADCs in one package Serial LVDS digital output data rates to 520 Mbps (ANSI-644) AD9289 Data and frame clock outputs VIN+A 8 D1+A SERIAL PIPELINE SNR = 48 dBc (to Nyquist) SHA LVDS VIN–A ADC D1–A Excellent linearity VIN+B 8 D1+B DNL = ±0.2 LSB (typical) SERIAL PIPELINE SHA LVDS VIN–B ADC D1–B INL = ±0.25 LSB (typical) 300 MHz full power analog bandwidth VIN+C 8 D1+C SERIAL PIPELINE SHA LVDS VIN–C D1–C ADC Power dissipation = 112 mW/channel at 65 MSPS 1 Vp-p to 2 Vp-p input voltage range VIN+D 8 D1+D SERIAL PIPELINE SHA 3.0 V supply operation LVDS VIN–D ADC D1–D Power-down mode LOCK VREF Digital test pattern enable for timing alignments SENSE FCO+ 0.5V FCO– REFT_A APPLICATIONS REF REFB_A SELECT DCO+ Tape drives DATA RATE REFT_B MULTIPLIER DCO– Medical imaging REFB_B SHARED_REF AGND LVDSBIAS CML CLK+ CLK– Figure 1. PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital conver- 1. Four ADCs are contained in a small, space-saving package. ter (ADC) with an on-chip sample-and-hold circuit that is 2. A data clock out (DCO) is provided, which operates up to designed for low cost, low power, small size, and ease of use. 260 MHz and supports double-data rate operation (DDR). The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small 3. The outputs of each ADC are serialized LVDS with data package size is critical. rates up to 520 Mbps (8 bits × 65 MSPS). The ADC requires a single, 3 V power supply and an LVDS- 4. The AD9289 operates from a single 3.0 V power supply. compatible sample rate clock for full performance operation. No external reference or driver components are required for 5. The internal clock duty cycle stabilizer maintains many applications. performance over a wide range of input clock duty cycles. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported. The ADC typically consumes 7 mW when enabled. Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64-BGA). It is specified over the industrial temperature range of –40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03682-001 AD9289 TABLE OF CONTENTS Specifications..................................................................................... 3 Typical Performance Characteristics ..............................................9 AC Specifications.......................................................................... 4 Terminology.................................................................................... 12 Digital Specifications ................................................................... 4 Theory of Operation ...................................................................... 14 Switching Specifications .............................................................. 5 Analog Input and Reference Overview ................................... 14 Timing Diagrams.......................................................................... 5 Clock Input and Considerations .............................................. 15 Absolute Maximum Ratings............................................................ 6 Evaluation Board ............................................................................ 20 Explanation of Test Levels........................................................... 6 Outline Dimensions ....................................................................... 30 ESD Caution.................................................................................. 6 Ordering Guide .......................................................................... 30 Pin Configuration and Function Descriptions............................. 7 Equivalent Circuits ........................................................................... 8 REVISION HISTORY 10/04—Initial Version: Revision 0 Rev. 0 | Page 2 of 32 AD9289 SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 1. Parameter Temperature Test Level Min Typ Max Unit RESOLUTION 8 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI ±5 ±57 mV Offset Matching Full VI ±12 ±68 mV 1 Gain Error Full VI ±0.5 ±2.5 % FS 1 Gain Matching Full VI ±0.2 ±0.9 % FS Differential Nonlinearity (DNL) 25°C V ±0.2 LSB Full VI ±0.2 ±0.6 LSB Integral Nonlinearity (INL) 25°C V ±0.25 LSB Full VI ±0.25 ±0.6 LSB TEMPERATURE DRIFT Offset Error Full V ±16 ppm/°C Gain Error1 Full V ±40 ppm/°C Reference Voltage (VREF = 1 V) Full V ±10 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full VI ±10 ±35 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full V 0.7 mV Output Voltage Error (VREF = 0.5 V) Full VI ±8 ±26 mV Load Regulation @ 0.5 mA (VREF = 0.5 V) Full V 0.2 mV Input Resistance Full V 7 kΩ COMMON MODE Common-Mode Level Output Full VI ±1.5 ±50 mV ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Full VI 2 V p-p Differential Input Voltage Range (VREF = 0.5 V) Full VI 1 V p-p Common-Mode Voltage Full V 1.5 V Input Capacitance Full V 5 pF Analog Bandwidth, Full Power Full V 300 MHz POWER SUPPLY AVDD Full IV 2.7 3.0 3.3 V DRVDD Full IV 2.7 3.0 3.3 V IAVDD2 Full VI 150 168 mA DRVDD2 Full VI 33 40 mA 2 Power Dissipation Full VI 550 625 mW Power-Down Dissipation Full VI 7 12 mW CROSSTALK Full V –75 dB 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference and a 2 V p-p differential analog input). 2 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. Rev. 0 | Page 3 of 32 AD9289 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. Parameter Temperature Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full IV 47.7 49.0 dB f = 10.3 MHz 25°C V 48.5 dB IN fIN = 35 MHz Full VI 46.7 48.0 dB SIGNAL-TO-NOISE RATIO (SINAD) fIN = 2.4 MHz Full IV 47.6 48.9 dB fIN = 10.3 MHz 25°C V 48.4 dB f = 35 MHz Full VI 46.2 47.5 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz Full IV 7.6 7.8 Bits IN fIN = 10.3 MHz 25°C V 7.7 Bits fIN = 35 MHz Full VI 7.4 7.6 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full IV 61.0 70.0 dBc f = 10.3 MHz 25°C V 68.0 dBc IN fIN = 35 MHz Full VI 54.0 65.0 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full IV –75.0 –61.0 dBc fIN = 10.3 MHz 25°C V –70.0 dBc f = 35 MHz Full VI –65.0 –54.0 dBc IN WORST OTHER (Excluding Second or Third) f = 2.4 MHz Full IV –70.0 –61.0 dBc IN fIN = 10.3 MHz 25°C V –68.0 dBc fIN = 35 MHz Full VI –65.0 –57.5 dBc TWO TONE INTERMOD DISTORTION (IMD) fIN1 = 15 MHz 25°C V –72.0 dBc AIN1 and AIN2 = –7.0 dBFS f = 16 MHz IN2 DIGITAL SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 3. Parameter Temperature Test Level Min Typ Max Unit 1 CLOCK INPUTS (CLK+, CLK–) Logic Compliance LVDS Differential Input Voltage Full IV 250 350 450 mV p-p High Level Input Current Full VI 30 75 µA Low Level Input Current Full VI 30 75 µA Input Common-Mode Voltage Full IV 1.125 1.25 1.375 V Input Resistance 25°C V 100 kΩ Input Capacitance 25°C V 2 pF LOGIC INPUTS (DFS, PDWN, SHARED_REF) Logic 1 Voltage Full IV 2.0 V Logic 0 Voltage Full IV 0.8 V Input Resistance 25°C V 30 kΩ Input Capacitance 25°C V 4 pF LOGIC OUTPUTS (LOCK) Logic 1 Voltage Full IV 2.45 V Logic 0 Voltage Full IV 0.05 V DIGITAL OUTPUTS (D1+, D1–) Logic Compliance LVDS Differential Output Voltage Full VI 260 350 440 mV Output Offset Voltage Full VI 1.15 1.25 1.35 V Output Coding Full VI Twos complement or binary 1 Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled. Rev. 0 | Page 4 of 32 AD9289 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Clock Rate Full VI 65 MSPS Minimum Clock Rate Full IV 12 MSPS Clock Pulse Width High (t) Full VI 6.9 7.7 ns EH Clock Pulse Width Low (t) Full VI 6.9 7.7 ns EL OUTPUT PARAMETERS 1 Valid Time (t ) Full IV 0.5 <1.5 CLK cycles V Propagation Delay (t ) Full VI 6.9 9.0 11.6 ns PD Rise Time (tR) (20% to 80%) Full V 250 ps Fall Time (tF) (20% to 80%) Full V 250 ps FCO Propagation Delay (tFCO) Full V 9.0 ns DCO Propagation Delay (t) Full V 9.0 ns CPD DCO-to-Data Delay (t) Full VI ±100 ±550 ps DATA DCO-to-FCO Delay (t) Full VI ±100 ±500 ps FRAME Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Full IV ±100 ±250 ps PLL Lock Time (tLOCK) 25°C V 1.8 µs Wake-Up Time 25°C V 7 ms Pipeline Latency Full IV 6 CLK cycles APERTURE Aperture Delay (tA) 25°C V 4.5 ns Aperture Uncertainty (Jitter) 25°C V <1 ps rms OUT-OF-RANGE RECOVERY TIME 25°C V 1 CLK cycles 1 LOCK Actual valid time is dependent on the moment when goes low. TIMING DIAGRAMS N-1 AIN t A N t t EH EL CLK– CLK+ t CPD DCO– STATIC STATIC DCO+ t t FCO FRAME FCO– STATIC STATIC FCO+ t t PD DATA D1– MSB D6 D5 D4 D3 D2 D1 LSB MSB STATIC INVALID STATIC (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-6) D1+ LOCK t V Figure 2. Timing Diagram Rev. 0 | Page 5 of 32 03682-003 AD9289 ABSOLUTE MAXIMUM RATINGS Table 5. EXPLANATION OF TEST LEVELS With I. 100% production tested. Respect Parameter To Min Max Unit II. 100% production tested at 25°C and guaranteed by design ELECTRICAL and characterization at specified temperatures. AVDD AGND –0.3 +3.9 V DRVDD DRGND –0.3 +3.9 V III. Sample tested only . AGND DRGND –0.3 +0.3 V IV. Parameter is guaranteed by design and characterization AVDD DRVDD –3.9 +3.9 V testing. Digital Outputs (D1+, DRVDD DRGND –0.3 V D1–, DCO+, DCO–, V. Parameter is a typical value only. FCO+, FCO–) DRVDD LOCK, LVDSBIAS DRGND –0.3 V VI. 100% production tested at 25°C and guaranteed by design CLK+, CLK– AGND –0.3 AVDD V and characterization for industrial temperature range. VIN+, VIN– AGND –0.3 AVDD V PDWN, DFS, DTP AGND –0.3 AVDD V REFT, REFB, AGND –0.3 AVDD V SHARED_REF, CML VREF, SENSE AGND –0.3 AVDD V Stresses above those listed under Absolute Maximum Ratings ENVIRONMENTAL may cause permanent damage to the device. This is a stress Operating –40 +85 °C rating only; functional operation of the device at these or any Temperature Range other conditions above those listed in the operational sections (Ambient) of this specification is not implied. Exposure to absolute Maximum Junction 150 °C Temperature maximum rating conditions for extended periods may affect 300 °C device reliability. Lead Temperature (Soldering, 10 sec) Storage –65 +150 °C Temperature Range (Ambient) Thermal 40 °C/W 1 Impedance 1 θ for a 4-layer PCB with solid ground plane in still air. JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 32 AD9289 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 234 567 8 A B C D E F G H Figure 3. BGA Top View (Looking Through) Table 6. Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description A1 D1–A ADC A Complement Digital Output D5 AGND Analog Ground B1 D1+A ADC A True Digital Output E5 AGND Analog Ground C1 FCO+ Frame Clock Output (MSB Indicator) F5 REFT_B Reference Buffer Decoupling (Positive) True Output G5 REFB_B Reference Buffer Decoupling (Negative) D1 DNC Do Not Connect H5 VREF Voltage Reference Input/Output E1 AGND Analog Ground A6 DNC Do Not Connect F1 VIN–A ADC A Analog Input—Complement B6 DNC Do Not Connect G1 VIN+A ADC A Analog Input—True C6 DRVDD Digital Supply 1 H1 LVDSBIAS LVDS Output Bias Pin D6 DRGND Digital Ground A2 DNC Do Not Connect E6 AVDD Analog Supply B2 DNC Do Not Connect F6 AGND Analog Ground C2 FCO– Frame Clock Output (MSB Indicator) G6 AGND Analog Ground Complement Output H6 VIN–C ADC C Analog Input—Complement D2 DNC Do Not Connect A7 D1–D ADC D Complement Digital Output E2 AGND Analog Ground B7 D1+D ADC D True Digital Output F2 AVDD Analog Supply 2 C7 DFS Data Format Select G2 AGND Analog Ground D7 AGND Analog Ground H2 VIN+B ADC B Analog Input—True E7 AGND Analog Ground A3 D1–B ADC B Complement Digital Output F7 AVDD Analog Supply B3 D1+B ADC B True Digital Output G7 AGND Analog Ground C3 DRVDD Digital Supply H7 VIN+C ADC C Analog Input—True D3 DRGND Digital Ground A8 DNC Do Not Connect E3 AGND Analog Ground B8 DNC Do Not Connect F3 CML Common Mode Level Output ( = AVDD/2) C8 CLK+ Input Clock—True 3 G3 SHARED_REF Shared Reference Control Bit D8 CLK– Input Clock—Complement H3 VIN–B ADC B Analog Input—Complement 3 E8 PDWN Power Down Selection A4 DNC Do Not Connect F8 VIN–D ADC D Analog Input—Complement B4 DNC Do Not Connect G8 VIN+D ADC D Analog Input—True C4 DCO+ Data Clock Output—True 3, 4 H8 DTP Digital Test Pattern D4 PLL Lock Output LOCK E4 AVDD Analog Supply 1 LVDSBIAS use a 3.9 kΩ resistor-to-analog ground to set the LVDS output F4 REFT_A Reference Buffer Decoupling (Positive) differential swing of 350 mV p-p. G4 REFB_A Reference Buffer Decoupling (Negative) 2 DFS has an internal on-chip pull-down resistor and defaults to offset binary H4 SENSE Reference Mode Selection output coding if untied. If twos complement output coding is desired then tie this pin to AVDD. A5 D1–C ADC C Complement Digital Output 3 To enable, tie this pin to AVDD. To disable, tie this pin to AGND. 4 B5 D1+C ADC C True Digital Output DTP has an internal on-chip pull-down resistor. C5 DCO– Data Clock Output—Complement Rev. 0 | Page 7 of 32 03682-005 AD9289 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– V V D1– D1+ V V AGND DRGND Figure 4. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit AVDD DRVDD CLK+, CLK– LOCK 375Ω 25Ω AGND DRGND Figure 5. Equivalent Clock Input Circuit Figure 8. Equivalent LOCK Output Circuit DRVDD DFS, PDWN, SHARED_REF 375Ω DRGND Figure 6. Equivalent Digital Input Circuit Rev. 0 | Page 8 of 32 03682-007 03682-006 03682-008 03682-009 03682-010 AD9289 TYPICAL PERFORMANCE CHARACTERISTICS 0 75 AIN = –0.5dBFS AIN = –0.5dBFS 2V p-p, SFDR (dBc) SNR = 49.08dB ENOB = 7.86 BITS 70 –20 SFDR = 70.55dBc 1V p-p, SFDR (dBc) 65 –40 60 –60 55 –80 2V p-p, SNR (dB) 50 1V p-p, SNR (dB) –100 45 0.0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 10 20 30 40 50 60 70 FREQUENCY (MHz) ENCODE (MSPS) Figure 9. Single-Tone 32k FFT With f = 2.4 MHz, f = 65 MSPS Figure 12. SNR/SFDR vs. f , f = 2.4 MHz IN SAMPLE SAMPLE IN 0 75 AIN = –0.5dBFS SNR = 48.93dB ENOB = 7.83 BITS 2V p-p, SFDR (dBc) 70 –20 SFDR = 71.45dBc AIN = –0.5dBFS 1V p-p, SFDR (dBc) 65 –40 60 –60 55 –80 2V p-p, SNR (dB) 50 1V p-p, SNR (dB) –100 45 0.0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 10 20 30 40 50 60 70 FREQUENCY (MHz) ENCODE (MSPS) Figure 10. Single-Tone 32k FFT With fIN = 10.3 MHz, fSAMPLE = 65 MSPS Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz 0 75 2V p-p, SFDR (dBc) AIN = –0.5dBFS AIN = –0.5dBFS SNR = 48.8dB ENOB = 7.8 BITS 70 –20 SFDR = 68.5dBc 1V p-p, SFDR (dBc) 65 –40 60 –60 55 –80 2V p-p, SNR (dB) 50 1V p-p, SNR (dB) –100 45 0.0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 10 20 30 40 50 60 70 FREQUENCY (MHz) ENCODE (MSPS) Figure 11. Single-Tone 32k FFT With f = 35 MHz, f = 65 MSP Figure 14. SNR/SFDR vs. f , f = 35 MHz IN SAMPLE SAMPLE IN Rev. 0 | Page 9 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03682-016 03682-015 03682-014 dB dB dB 03682-019 03682-017 03682-018 AD9289 75 75 60 70dB REFERENCE LINE 70 SFDR (dBc) 2V p-p, SNR (dB) 50 1V p-p, SFDR (dBc) 65 40 60 30 1V p-p, SNR (dB) 55 20 50 10 2V p-p, SFDR (dBc) SNR (dB) 0 45 –40 –35 –30 –25 –20 –15 –10 –5 0 0.1 1 10 100 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS, Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz fIN = 2.4 MHz 75 0 AIN1 AND AIN2 = –7.0dBFS SFDR = 69.9dBc 60 70dB REFERENCE LINE IMD2 = 74.9dBc IMD3 = 72.9dBc –20 2V p-p, SNR (dB) 50 1V p-p, SFDR (dBc) –40 40 30 1V p-p, SNR (dB) –60 20 –80 10 2V p-p, SFDR (dBc) –100 0 0.0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 –40 –35 –30 –25 –20 –15 –10 –5 0 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 16. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS, Figure 19. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fIN = 10.3 MHz fSAMPLE = 65 MSPS 75 80 70 60 70dB REFERENCE LINE 60 2V p-p, SNR (dB) 50 1V p-p, SFDR (dBc) 70dB REFERENCE LINE 50 40 40 30 1V p-p, SNR (dB) SFDR (dBc) 30 20 20 2V p-p, SFDR (dBc) 10 10 0 0 –40 –35 –30 –25 –20 –15 –10 –5 0 –40 –35 –30 –25 –20 –15 –10 –5 0 ANALOG INPUT LEVEL (dBFS) ANALOG INPUT LEVEL (dBFS) Figure 17. SNR/SFDR vs. Analog Input Level, f = 65 MSPS, Figure 20. Two-Tone SFDR vs. Analog Input Level with f = 15 MHz and SAMPLE IN1 f = 35 MHz f = 16 MHz, f = 65 MSPS IN IN2 SAMPLE Rev. 0 | Page 10 of 32 dB dB dB 03682-022 03682-021 03682-020 dB AMPLITUDE (dBFS) dB 03682-025 03682-024 03682-023 AD9289 0.5 75 2V p-p, SFDR (dBc) 0.4 70 0.3 1V p-p, SFDR (dBc) 0.2 65 0.1 0 60 –0.1 55 –0.2 –0.3 2V p-p, SINAD (dB) 50 –0.4 1V p-p, SINAD (dB) –0.5 45 0 32 64 96 128 160 192 224 256 –40 –2006 20 490 80 CODE TEMPERATURE (°C) Figure 21. SINAD/SFDR vs. Temperature, fSAMPLE = 65 MSPS, fIN 10.3 MHz Figure 23. Typical DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS 0.5 15 0.4 10 0.3 0.2 5 0.1 SHARED REF MODE (PIN TIED HIGH) 0 0 –0.1 –5 –0.2 SHARED REF MODE (PIN TIED LOW) –0.3 –10 –0.4 –0.5 –15 0 32 64 96 128 160 192 224 256 –40 –2006 20 490 80 CODE TEMPERATURE (°C) Figure 24. Typical INL, f = 2.4 MHz, f = 65 MSPS IN SAMPLE Figure 22. Gain vs. Temperature Rev. 0 | Page 11 of 32 GAIN ERROR (ppm/°C) dB 03682-027 03682-026 INL (LSB) DNL (LSB) 03682-029 03682-028 AD9289 TERMINOLOGY Analog Bandwidth Effective Number of Bits (ENOB) Analog Bandwidth is the analog input frequency at which the For a sine wave, SINAD can be expressed in terms of the spectral power of the fundamental frequency (as determined by number of bits. Using the following formula, it is possible to the FFT analysis) is reduced by 3 dB from full scale. obtain a measure of performance expressed as N, the effective number of bits: Aperture Delay N = (SINAD – 1.76)/6.02 Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising Thus, the effective number of bits for a device for sine wave edge of the clock input to the time at which the input signal is inputs at a given input frequency can be calculated directly held for conversion. from its measured SINAD. Aperture Uncertainty (Jitter) Gain Error Aperture jitter is the variation in aperture delay for successive The largest gain error is specified and is considered the samples and can be manifested as frequency-dependent noise difference between the measured and ideal full-scale input on the ADC input. voltage range. Clock Pulse Width and Duty Cycle Gain Matching Pulse width high is the minimum amount of time that the clock Expressed in %FSR. Computed using the following equation: pulse should be left in the Logic 1 state to achieve a rated FSR max− FSR min performance. Pulse width low is the minimum time the clock GainMatching= ×100% FSR max+ FSR min ⎛ ⎞ pulse should be left in the low state. At a given clock rate, these ⎜ ⎟ 2 ⎝ ⎠ specifications define an acceptable clock duty cycle. where FSRMAX is the most positive gain error of the ADCs, and Crosstalk FSR is the most negative gain error of the ADCs. MIN Crosstalk is defined as the coupling of a channel when all Second and Third Harmonic Distortion channels are driven by a full-scale signal. The ratio of the rms signal amplitude to the rms value of the Differential Analog Input Capacitance second or third harmonic component, reported in dBc. The complex impedance simulated at each analog input port. Integral Nonlinearity (INL) Differential Analog Input Voltage Range INL refers to the deviation of each individual code from a line The peak-to-peak differential voltage that must be applied to drawn from negative full scale through positive full scale The the converter to generate a full-scale response. Peak differential point used as negative full scale occurs 1/2 LSB before the first voltage is computed by observing the voltage on a pin and code transition. Positive full scale is defined as a level 1 1/2 LSB subtracting the voltage from a second pin that is 180° out of beyond the last code transition. The deviation is measured from phase. Peak-to-peak differential is computed by rotating the the middle of each particular code to the true straight line. input phase 180° and taking the peak measurement again. The Offset Error difference is computed between both peak measurements. The largest offset error is specified and is considered the Differential Nonlinearity (DNL, No Missing Codes) difference between the measured and ideal voltage at the analog An ideal ADC exhibits code transitions that are exactly 1 LSB input that produces the midscale code at the outputs. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to an 8-bit resolution indicates that all 256 codes, respectively, must be present over all operating ranges. Rev. 0 | Page 12 of 32 AD9289 Signal-to Noise and Distortion (SINAD) Ratio Offset Matching SINAD is the ratio of the rms value of the measured input Expressed in mV. Computed using the following equation: signal to the rms sum of all other spectral components below OffsetMatching = OFF − OFF MAX MIN the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. where OFFMAX is the most positive offset error and OFFMIN is the most negative offset error. Signal-to-Noise Ratio (SNR) Out-of-Range Recovery Time SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist Out-of-range recovery time is the time it takes for the ADC to frequency, excluding the first six harmonics and dc. The value reacquire the analog input after a transient from 10% above for SNR is expressed in decibels. positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Spurious-Free Dynamic Range (SFDR) Output Propagation Delay SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. The delay between the clock logic threshold and the time when all bits are within valid logic levels. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at T or T . MIN MAX Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. 0 | Page 13 of 32 AD9289 THEORY OF OPERATION of a clock cycle. A small resistor in series with each input can Each A/D converter in the AD9289 architecture consists of a help reduce the peak transient current required from the output front send sample-and-hold amplifier (SHA) followed by a stage of the driving source. Also, a small shunt capacitor can pipe-lined, switched capacitor ADC. The pipelined ADC is be placed across the inputs to provide dynamic charging divided into two sections, consisting of six 1.5-bit stages and a currents. This passive network creates a low-pass filter at the final 2-bit flash. Each stage provides sufficient overlap to correct ADC’s input; therefore, the precise values are dependent on for flash errors in the preceding stages. The quantized outputs the application. from each stage are combined into a final 8-bit result in the digital correc-tion logic. The pipelined architecture permits the The analog inputs of the AD9289 are not internally dc biased. In first stage to operate on a new input sample, while the ac-coupled applications, the user must provide this bias exter- remaining stages operate on preceding samples. Sampling nally. Setting the device so that VCM = AVDD/2 is recommended occurs on the rising edge of the clock. for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 26 and Each stage of the pipeline, excluding the last, consists of a low Figure 27). resolution flash ADC connected to a switched capacitor digital- to-analog converter (DAC) and interstage residue amplifier 75 2V p-p, SFDR (dBc) (MDAC). The MDAC magnifies the difference between the 70 reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the 65 1V p-p, SFDR (dBc) stages to facilitate digital correction of flash errors. The last 60 stage simply consists of a flash ADC. 55 The input stage contains a differential SHA that can be config- 2V p-p, SNR (dB) 50 ured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data and carries out the 1V p-p, SNR (dB) 45 error correction. The data is serialized and aligned to the frame, 40 output clock, and lock detection circuitry. 35 ANALOG INPUT AND REFERENCE OVERVIEW 0 0.5 1.0 1.5 2.0 2.5 3.0 ANALOG INPUT COMMON-MODE VOLTAGE (V) The analog input to the AD9289 is a differential-switched Figure 26. SNR, SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, capacitor SHA that has been designed for optimum perfor- fSAMPLE = 65 MSPS mance while processing a differential input signal. The SHA 75 input can support a wide common-mode range and maintain 2V p-p, SFDR (dBc) excellent performance, as shown in Figure 26 sand Figure 27. 70 An input common-mode voltage of midsupply minimizes 65 signal dependent errors and provides optimum performance. 60 H 1V p-p, SFDR (dBc) 55 S S 2V p-p, SNR (dB) 50 VIN+ C PAR 1V p-p, SNR (dB) 45 40 S 35 VIN– 0 0.5 1.0 1.5 2.0 2.5 3.0 C PAR ANALOG INPUT COMMON-MODE VOLTAGE (V) S Figure 27. SNR, SFDR vs. Common-Mode Voltage, f = 35 MHz, IN f = 65 MSPS SAMPLE H For best dynamic performance, the source impedances driving Figure 25. Switched-Capacitor SHA Input UPDATE VIN+ and VIN− should be matched such that common-mode The clock signal alternately switches the SHA between sample settling errors are symmetrical. These errors are reduced by the mode and hold mode (see Figure 25). When the SHA is common-mode rejection of the ADC. switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half Rev. 0 | Page 14 of 32 03682-051 dB dB 03682-030 03682-031 AD9289 An internal reference buffer creates the positive and negative AVDD R reference voltages, REFT and REFB, respectively, that defines VIN+ the span of the ADC core. The output common-mode of the 2Vp-p 49.9Ω AD9289 C reference buffer is set to midsupply, and the REFT and REFB R AVDD VIN– voltages and span are defined as AGND 1kΩ REFT = 1/2 (AVDD + VREF) 1kΩ REFB = 1/2 (AVDD − VREF) 0.1µF Span = 2 × (REFT − REFB) = 2 × VREF Figure 29. Differential Transformer-Coupled Configuration It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage Single-Ended Input Configuration and, by definition, the input span is twice the value of the VREF voltage. A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a The internal voltage reference can be pin-strapped to fixed degradation in SFDR and distortion performance due to the values of 0.5 V or 1.0 V or adjusted within the same range, as large input common-mode swing. However, if the source discussed in the Internal Reference Connection section. impedances on each input are matched, there should be little Maximum SNR performance is achieved by setting the AD9289 effect on SNR performance. Figure 30 details a typical single- to the largest input span of 2 V p-p. ended input configuration. The SHA should be driven from a source that keeps the signal 10µF peaks within the allowable range for the selected reference AVDD 1kΩ voltage. The minimum and maximum common-mode input R VIN+ levels are defined in Figure 26 and Figure 27. 0.1µF 2V p-p 49.9Ω 1kΩ AD9289 C Differential Input Configurations AVDD Optimum performance is achieved by driving the AD9289 in a R 1kΩ VIN– differential input configuration. For baseband applications, the AGND 10µF 0.1µF 1kΩ AD8351 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 28). Figure 30. Single-Ended Input Configuration 1kΩ 10kΩ 0.1µF 1kΩ 1kΩ 1kΩ CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a AVDD 0.1µF V 0.1µF 10Ω CM R variety of internal timing signals, and as a result may be VIN– PWUP GP1 25Ω sensitive to clock duty cycle. Typically, a 5% tolerance is 25Ω AD8351 C AD9289 required on the clock duty cycle to maintain dynamic perfor- GP2 0.1µF R 1V p-p VIN+ mance characteristics. The AD9289 has a self-contained clock 10Ω 0.1µF AGND 50Ω duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty 1.2kΩ AVDD 1kΩ 1kΩ cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9289. Figure 28. Differential Input Configuration Using the AD8351 An on-board phase-locked loop (PLL) multiplies the input However, the noise performance of most amplifiers is not clock rate for the purpose of shifting the serial data out. As a adequate to achieve the true performance of the AD9289. For result, any change to the sampling frequency requires a applications where SNR is a key parameter, differential transfor- minimum of 100 clock periods to allow the PLL to reacquire mer coupling is the recommended input configuration. An and lock to the new rate. example of this is shown in Figure 29. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. Rev. 0 | Page 15 of 32 03682-054 03682-052 03682-053 AD9289 By asserting the PDWN pin high, the AD9289 is placed in High speed, high resolution ADCs are sensitive to the quality of standby mode. In this state, the ADC typically dissipates 7 mW. the clock input. The degradation in SNR at a given full-scale During standby the LVDS output drivers are placed in a high input frequency (f ) due only to aperture jitter (t ) can be A A impedance state. Reasserting the PDWN pin low returns the calculated with the following equation: AD9289 into its normal operational mode. SNR degradation = 20 × log10 [1/2 × π × fA × tA] In standby mode, low power dissipation is achieved by shutting In the equation, the rms aperture jitter, tA, represents the root down the reference, reference buffer, and biasing networks. The sum square of all jitter sources, which include the clock input, decoupling capacitors on REFT and REFB are discharged when analog input signal, and ADC aperture jitter specification. entering standby mode and then must be recharged when Applications that require undersampling are particularly returning to normal operation. As a result, the wake-up time is sensitive to jitter. related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the The LVDS clock input should be treated as an analog signal in recommended 0.1 µF and 10 µF decoupling capacitors on REFT cases where aperture jitter may affect the dynamic range of the and REFB, it takes approximately 1 s to fully discharge the AD9289. Power supplies for clock drivers should be separated reference buffer decoupling capacitors and 7 ms to restore full from the ADC output driver supplies to avoid modulating the operation. clock signal with digital noise. Low jitter, crystal-controlled Digital Outputs oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other The AD9289’s differential outputs conform to the ANSI-644 methods), it should be retimed by the original clock at the LVDS standard. To set the LVDS bias current place a resistor (RSET is nominally equal to 3.9 kΩ) to ground at the last step. LVDSBIAS pin. The RSET resistor current is derived on-chip The AD9289 can also support a single-ended CMOS clock. and sets the output current at each output equal to a nominal Refer to the evaluation board schematics to enable this feature. 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal ±350 mV swing at Power Dissipation and Standby Mode the receiver. To adjust the differential signal swing, simply As shown in Figure 31, the power dissipated by the AD9289 is change the resistor to a different value, as shown in Table 7. proportional to its sample rate. The digital power dissipation does not vary because it is determined primarily by the strength Table 7. LVDSBIAS Pin Configuration of the digital drivers and the load on each output bit. RSET Differential Output Swing 3.6k 375 mV p-p Digital power consumption can be minimized by reducing the 3.9k (Default) 350 mV p-p capacitive load presented to the output drivers. The data in 4.3k 325mV p-p Figure 31 was collected while a 5 pF load was placed on each The AD9289’s LVDS outputs facilitate interfacing with LVDS output driver. receivers in custom ASICs and FPGAs that have LVDS capa- The analog circuitry of the AD9289 is optimally biased to bility for superior switching performance in noisy environ- achieve excellent performance while affording reduced ments. Single point-to-point net topologies are recommended power consumption. with a 100 Ω termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length no 600 180 longer than 12 inches and to keep differential output traces 160 close together and at equal lengths. 550 140 I AVDD The format of the output data can be selected as offset binary or 120 twos complement. A quick example of each output coding 500 100 format can be found in Table 8. The DFS pin is used to set the format (see Table 9). POWER 80 450 Table 8. Digital Output Coding 60 VIN+ − VIN+ − Digital Digital 40 VIN− Input VIN− Input Output Offset Output Twos 400 I Span = 2 V Span = 1 V Binary Complement DRVDD 20 Code p-p (V) p-p (V) (D7...D0) (D7...D0) 350 0 255 1.000 0.500 1111 1111 0111 1111 10 20 30 40 50 60 70 128 0 0 1000 0000 0000 0000 ENCODE (MSPS) 127 −0.00781 −0.00391 0111 1111 1111 1111 Figure 31. Supply Current vs. f for f = 10.3 MHz SAMPLE IN 0 −1.00 −0.5000 0000 0000 1000 0000 Rev. 0 | Page 16 of 32 POWER (mW) 03682-032 CURRENT (mA) AD9289 Table 9. Data Format Configuration Voltage Reference DFS Mode Data Format A stable and accurate 0.5 V voltage reference is built into the AVDD Twos complement AD9289. The input range can be adjusted by varying the refer- AGND Offset binary ence voltage applied to the AD9289, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. Timing Data from each ADC is serialized and provided on a separate The shared reference mode (see Figure 32) allows the user to channel. The data rate for each serial stream is equal to eight externally connect the reference buffers from the quad ADC for bits times the sample clock rate, with a maximum of 520 MHz better gain and offset matching performance. If the ADCs are to (8 bits x 65 MSPS = 520 MHz). The lowest typical conversion function independently, the reference decoupling can be treated rate is 12 MSPS. independently and can provide better isolation between the four channels. To enable shared reference mode, the SHARED_REF Two output clocks are provided to assist in capturing data from pin must be tied high and external reference buffer decoupling the AD9289. The DCO is used to clock the output data and is pins must be externally shorted. (REFT_A must be externally equal to four times the sampling clock (CLK) rate. Data is shorted to REFT_B and REFB_A must be shorted to REFB_B.) clocked out of the AD9289 and can be captured on the rising Note that Channels A and B are referenced to REFT_A and and falling edges of the DCO that supports double-data rate REFB_A and Channels C and D are referenced to REFT_B operation (DDR). The frame clock out (FCO) signals the start and REFB_B. of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Table 10. Reference Settings Resulting LOCK Pin SENSE Resulting Differential Span Selected Mode Voltage V (V) (V p-p) REF The AD9289 contains an internal PLL that is used to generate External AVDD N/A 2 × External the DCO. When the PLL is locked, the signal will be low, LOCK Reference Reference indicating valid data on the outputs. Internal, VREF 0.5 1.0 1 V p-p FSR If for any reason the PLL loses lock, the LOCK signal goes high Programmable 0.2 V to 0.5 × 2 × VREF VREF (1 + R2/R1) as soon as the lock circuitry detects an unlocked condition. Internal, AGND to 1.0 2.0 While the PLL is unlocked, the data outputs and DCO remains 2 V p-p FSR 0.2 V in the last known state. If the LOCK signal goes high in the middle of a byte, no data or DCO signals will be available for Internal Reference Connection the rest of the byte. It takes at least 1.8 µs at 65 MSPS to regain A comparator within the AD9289 detects the potential at the lock once it is lost. Note that regaining lock is sample rate- SENSE pin and configures the reference into four possible dependent and takes at least 100 input periods after the PLL states, which are summarized in Table 10. If SENSE is grounded, acquires the input clock. the reference amplifier switch is connected to the internal resis- Once the PLL regains lock the DCO starts. The first valid data tor divider (see Figure 33), setting VREF to 1 V. Connecting the byte is indicated by the FCO signal. The FCO rising edge occurs SENSE pin to the VREF pin switches the amplifier output to the 0.5 to <1.5 input clock periods after goes low. LOCK SENSE pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 V reference output. If an external CML Pin resistor divider is connected as shown in Figure 34 the switch is A common-mode level output is available at Pin F3. This output again set to the SENSE pin. This puts the reference amplifier in self biases to AVDD/2. This is a relatively high impedance a noninverting mode with the VREF output defined as output (2.5k nominal), which may need to be considered when used as a reference. R2 ⎛ ⎞ VREF= 0.5× 1+ ⎜ ⎟ R1 ⎝ ⎠ DTP Pin In all reference configurations, REFT_A and REFT_B and When the digital test pattern (DTP) pin is enabled (pulled to REFB_A and REFB_B establish their input span of the ADC AVDD), all of the ADC channel outputs shift out the following core. The input range of the ADC always equals twice the pattern: 11000000. The FCO and DCO outputs still work as voltage at the reference pin for either an internal or an external usual while all channels shift out the test pattern. This pattern reference. allows the user to perform timing alignment adjustments between the DCO and the output data. Rev. 0 | Page 17 of 32 AD9289 VIN+A (+B) VIN+A (+B) VIN–A (–B) VIN–A (–B) REFT_A REFT_A 0.1µF 0.1µF + + A CORE A CORE 0.1µF 10µF 0.1µF 10µF B CORE B CORE REFB_A REFB_A V V REF REF 0.1µF 0.1µF V V REF REF 10µF 0.1µF 10µF 0.1µF SELECT SELECT R2 LOGIC LOGIC SENSE SENSE R1 0.5V 0.5V VIN+C (+D) VIN+C (+D) VIN–C (–D) VIN–C (–D) REFT_B REFT_B V V REF REF 0.1µF 0.1µF + + C CORE C CORE 0.1µF 10µF 0.1µF 10µF D CORE D CORE REFB_B REFB_B AVDD CONTROL SHARED_REF CONTROL SHARED_REF Figure 32. Shared Reference Mode Enabled Figure 34. Programmable Reference Configuration VIN+A (+B) If the internal reference of the AD9289 is used to drive multiple VIN–A (–B) REFT_A converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 35 0.1µF + A CORE 0.1µF 10µF depicts how the internal reference voltage is affected by loading. B CORE REFB_A V REF 0.05 0.1µF V REF 0 10µF 0.1µF –0.05 SELECT LOGIC V = 0.5V REF –0.10 SENSE –0.15 0.5V –0.20 V = 1.0V –0.25 REF VIN+C (+D) –0.30 VIN–C (–D) REFT_B V REF –0.35 0.1µF + C CORE –0.40 0.1µF 10µF D CORE 0 0.5 1.0 1.5 2.0 2.5 REFB_B I (mA) LOAD SHARED_REF CONTROL Figure 35. VREF Accuracy vs. Load Figure 33. Internal Reference Configuration Rev. 0 | Page 18 of 32 03682-012 03682-011 V ERROR (%) REF 03682-033 03682-013 AD9289 External Reference Operation When the SENSE pin is tied to AVDD, the internal reference is The use of an external reference may be necessary to enhance disabled, allowing the use of an external reference. An internal the gain accuracy of the ADC or improve thermal drift reference buffer loads the external reference with an equivalent characteristics. Figure 36 shows the typical drift characteristics 7 kΩ load. The internal buffer still generates the positive and of the internal shared reference in both 1 V and 0.5 V modes. negative full-scale references, REFT_A and REFT_B and REFB_A and REFB_B , for the ADC core. The input span is 0.15 always twice the value of the reference voltage; therefore, the V = 0.5V 0.10 REF external reference must be limited to a maximum of 1 V. 0.05 Power and Ground Recommendations V = 1.0V REF When connecting power to the AD9289, it is recommended that 0 two separate 3.0 V supplies be used. One for analog (AVDD) –0.05 and one for digital (DRVDD). If only one supply is available then it should be routed to the AVDD first and tapped off and –0.10 isolated with a ferrite bead or filter choke with decoupling –0.15 capacitors proceeding. One may want to use several different decoupling capacitors to cover both high and low frequencies. –0.20 These should be located close the point of entry at the pc board –0.25 –40 –20 0 20 40 60 80 level as well as close to the parts with minimal trace length. TEMPERATURE (°C) A single pc board ground plane should be sufficient when using Figure 36. Typical VREF Drift the AD9289. With proper decoupling and smart partitioning of the pc board’s analog, digital, and clock sections, optimum performance is easily achieved. Rev. 0 | Page 19 of 32 V ERROR (%) REF 03682-034 AD9289 EVALUATION BOARD the signal sources that are used have very low phase noise The AD9289 evaluation board provides all of the support cir- (< 1 ps rms jitter) to realize the ultimate performance of the cuitry required to operate the ADC in its various modes and converter. Proper filtering of the analog input signal to configurations. The converter can be driven differentially remove harmonics and lower the integrated or broadband through a transformer (default) or the AD8351 driver. Provi- noise at the input is also necessary to achieve the specified sions have also been made to drive the ADC single-ended. noise performance. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by See Figure 37 to Figure 47 for complete schematics and layout proper connection of various jumpers (refer to the schematics). plots, which demonstrate the routing and grounding techniques Figure 37 shows the typical bench characterization setup used that should be applied at the system level. to evaluate the ac performance of the AD9289. It is critical that 3.0V 3.0V 3.3V –+ –+ – + HSC-ADC-FPGA HSC-ADC-EVAL-DC PC HIGH-SPEED FIFO DATA RUNNING DE-SERIALIZATION CAPTURE ADC ROHDE AND SCHWARZ, BOARD BOARD ANALYZER SMHU, BAND-PASS XFMR 2V p-p SIGNAL CHA–CHD FILTER INPUT 2 CH SYNTHESIZER AD9289 8-BIT USB 8-BIT EVALUATION BOARD SERIAL CONNECTION PARALLEL ROHDE AND SCHWARZ, LVDS CMOS CLK SMHU, 2V p-p SIGNAL SYNTHESIZER Figure 37. Evaluation Board Connections Rev. 0 | Page 20 of 32 DUT_AVDD GND DUT_DRVDD GND BRD_AVDD 03682-002 AD9289 U7 Figure 38. Evaluation Board Schematic, DUT, VREF, and Clock Inputs Rev. 0 | Page 21 of 32 DIGITAL LVDS OUTPUTS U5 1 50 2 49 VOLTAGE REFERENCE CIRCUITRY AD9289 EXTERNAL 3 48 REFERENCE OPTION 4 47 BRD_AVDD 5 46 6 45 U6 R26 R1 7 44 VREF DNP U17 1kΩ ADR510 JP2 V = 0.5V 3 1 8 43 1 8 REF DCO DCO NC TRIM/NC V+ R25 V = EXTERNAL 9 DNP 42 2 7 REF RA C53 BRD_AVDD V– DNP 10 41 0.1µF V = 0.5V (1 + RA/RB) 3 6 REF C47 CX FCO R67 FCO 2 0.1µF 10µF 11 40 DNP V = 1V 4 5 REF RB 12 39 DNP CHA CHA R2 13 38 DNP REMOVE CX 14 37 CHB CHB WHEN USING R3 15 36 DNP EXTERNAL V U6 REF 16 35 CHC CHC R4 17 34 DNP 18 33 CHD CHD 19 32 R76 20 31 3.9kΩ H1 C3 LVDSBIAS DRVDD DUT_DRVDD 21 30 C120 C35 F3 D6 CML DRGND 22 29 10µF 0.1µF C1 G3 B3 23 28 0.1µF SHARED_REF SHARED_REF D1+B CHB C44 24 27 H4 A3 0.1µF SENSE D1–B CHB 25 26 JP3 JP5 H5 B4 VREF VREF DNC F7 A4 DUT_AVDD AVDD DNC G7 D4 C100 C600 AGND LOCK TP9 10µF 0.1µF G4 C4 C250 REFB_A DCO+ DCO AD9289 0.1µF C80 F4 C5 REFT_A DCO – DCO 0.1µF G5 D5 REFB_B AGND F5 B5 REFT_B D1+C CHC E3 A5 AGND D1–C CHC BRD_AVDD G6 B6 AGND DNC DUT_AVDD BRD_AVDD R66 F6 A6 U2 0Ω TP3 AGND DNC R40 1 8 E6 C6 1kΩ VCC DOUT – P5 R73 TP1 AVDD DRVDD DUT_DRVDD CLOCK 2 7 100Ω DIN DOUT+ H8 D3 DUT_AVDD INPUT DTP DRGND 3 6 R41 C6 R43 DNC DNC R71 50Ω 0.1µF 1kΩ 4 5 0Ω R37 TP4 GND DNC 10kΩ FIN1017M TP2 BRD_AVDD JP1 R29 1kΩ JP9 C36 R70 0.1µF 1kΩ BRD_AVDD BRD_AVDD R110 J6 R102 1kΩ U1 U1 JP35 1 6 22Ω 12 13 12 2 5 R109 C7 3 4 0.1µF 1kΩ SINGLE-ENDED SHARED_REF ** PLACE ONLY WHEN USING THE AD8351 CLOCK DRIVER OPTION AS INPUT. SEE DATASHEET FOR DETAILS. R75 R72 R32 10kΩ 10kΩ 10kΩ DNP = DO NOT POPULATE = GND 03682-048 E5 G2 AGND AGND E4 F2 DUT_AVDD AVDD AVDD DUT_AVDD H6 H3 VIN_C VIN–C VIN–B VIN_B H7 H2 VIN_C VIN+C VIN_B VIN+B E7 E2 AGND AGND D7 E1 AGND AGND G8 G1 VIN+D VIN_D VIN+A VIN_A F8 F1 VIN–D VIN_D VIN–A VIN_A C7 D1 DFS DNC D8 D2 CLK – DNC C8 C1 CLK+ FCO+ FCO E8 C2 PDWN FCO – FCO A8 B1 DNC D1+A CHA B8 A1 DNC D1–A CHA A7 B2 CHD D1–D DNC B7 A2 D1+D CHD DNC AD9289 Figure 39. Evaluation Board Schematic, DUT Analog Input Rev. 0 | Page 22 of 32 AMP_IN1 C19 L3 DNP 120nH C2 R62** R31 CH_A P1 0.1µF ANALOG DNP 33Ω 3 4 INPUT VIN_A L2 CHANNEL A R68** R15 T1 120nH DNP 50Ω 2 5 C30 C31 CM1 CM1 20pF DNP 1 6 R59** L1 R34 DNP 120nH 33Ω VIN_A AVDD CH_A C23 R12 R20 C16 L4 DNP 1kΩ 1kΩ 0.1µF 120nH AMP_IN2 C24 L6 DNP 120nH C3 R63** R27 CH_B P2 0.1µF DNP ANALOG 33Ω 1 6 INPUT VIN_B L19 R69** CHANNEL B R30 T2 120nH DNP 50Ω 2 5 C17 C21 CM2 CM2 DNP 20pF 3 4 R74** L20 R23 DNP 120nH 33Ω VIN_B AVDD CH_B C22 R13 R16 C15 L9 DNP 1kΩ 1kΩ 0.1µF 120nH AMP_IN3 C25 L12 DNP 120nH C4 R64** R47 0.1µF CH_C P3 DNP ANALOG 33Ω 3 4 VIN_C INPUT L21 R80** CHANNELC R83 T3 120nH DNP 50Ω 2 5 C41 C42 CM3 CM3 20pF DNP 1 6 R77** L22 R44 DNP 120nH 33Ω VIN_C AVDD CH_C C43 R18 R19 C18 L11 DNP 1kΩ 1kΩ 0.1µF 120nH AMP_IN4 C28 L10 DNP 120nH C5 R65** R14 P4 0.1µF CH_D DNP 1 6 33Ω ANALOG VIN_D INPUT L27 R82** R42 CHANNEL D T4 120nH DNP 50Ω 2 5 C9 C10 CM4 CM4 DNP 20pF 3 4 R84** L28 R11 DNP 120nH 33Ω VIN_D AVDD ** PLACE ONLY WHEN USING THE AD8351 AS INPUT. SEE CH_D C13 R21 R24 C20 L13 DATASHEET FOR DETAILS. DNP 1kΩ 1kΩ 0.1µF 120nH DNP = DO NOT POPULATE = GND 03682-047 JP28 JP27 JP25 JP24 JP21 JP18 JP29 JP19 JP26 JP20 AD9289 Figure 40. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. 0 | Page 23 of 32 AD8351 ANALOG INPUT DRIVER OPTION BRD_AVDD R36 C48 R45 10kΩ 0.1µF 1kΩ FOR PWDN PLACE R6 R50 C49 R6* 1kΩ 0.1µF DNP BRD_AVDD U7 1 10 PWUP VOCM C54 C52 2 9 R5 R48 R54 C55 R58 RGP1 VPOS 0.1µF 0.1µF 10Ω 0Ω 10kΩ 0.1µF 1kΩ 3 8 AMP_IN1 INHI OPHI CH_A FOR PWDN 4 7 PLACE R51 INLO OPLO CH_A R57 C57 R7 5 6 R48 C50 C51 R51* RGP2 COMM 1kΩ 0.1µF 10Ω 0Ω 0.1µF 0.1µF DNP R38 R49 R22 R35 50Ω 25Ω 25Ω U8 1.2kΩ 1 10 PWUP VOCM C59 C60 2 9 R10 R60 RGP1 VPOS 0.1µF 0.1µF 10Ω 0Ω 3 8 INHI OPHI CH_B 4 7 AMP_IN2 INLO OPLO CH_B 5 6 R17 R61 C58 C61 RGP2 COMM 10Ω 0Ω 0.1µF 0.1µF R55 R56 R52 R53 BRD_AVDD 25Ω 50Ω 25Ω 1.2kΩ R90 C62 R94 10kΩ 0.1µF 1kΩ FOR PWDN PLACE R78 R93 C63 R78* 1kΩ 0.1µF DNP BRD_AVDD U9 1 10 PWUP VOCM C65 C66 2 9 R8 R98 RGP1 VPOS R104 C68 R111 0.1µF 0.1µF 10Ω 0Ω 3 8 10kΩ 0.1µF 1kΩ AMP_IN3 INHI OPHI CH_C FOR PWDN 4 7 INLO OPLO PLACE R100 CH_C 5 6 R9 R99 R108 C69 C64 C67 RGP2 COMM R100* 10Ω 0Ω 1kΩ 0.1µF 0.1µF 0.1µF DNP R91 R92 R79 R81 50Ω 25Ω 25Ω 1.2kΩ U10 1 10 PWUP VOCM C71 C72 2 9 R33 R113 RGP1 VPOS 0.1µF 0.1µF 10Ω 0Ω 3 8 INHI OPHI CH_D 4 7 AMP_IN4 INLO OPLO CH_D R39 5 6 R114 C70 C73 RGP2 COMM 10Ω 0Ω 0.1µF 0.1µF R106 R107 R101 R103 * TO ENABLE THE POWER DOWN OPTION ON THE 25Ω 50Ω 25Ω 1.2kΩ AD8351, PLACE A 0Ω RESISTOR IN THIS PLACE HOLDER. 03682-049 AD8351 AD8351 AD8351 AD8351 AD9289 Figure 41. Evaluation Board Schematic, Power, and Decoupling Rev. 0 | Page 24 of 32 POWER CONNECTIONS UNUSED GATES L5 U1 10µH 34 BRD_AVDD + C170 C108 10µF 0.1µF U1 P6 56 1 +3.3V P1 2 P2 L7 10µH U1 3 98 +3.0V P3 DUT_AVDD + C176 C183 4 P4 10µF 0.1µF 5 U1 +3.0V P5 11 10 6 P6 L8 10µH DUT_DRVDD + C171 C110 10µF 0.1µF DECOUPLING CAPS GROUND TEST POINTS DUT_AVDD BRD_AVDD DUT_DRVDD C14 C12 C37 C29 C25 C40 C11 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF ** PLACE ONLY WHEN USING THE AD8351 AS INPUT. SEE DATASHEET FOR DETAILS. DNP = DO NOT POPULATE = GND 03682-050 JP2 JP4 JP1 TP14 TP15 TP16 TP18 AD9289 Figure 42. Evaluation Board Layout, Primary Side Figure 43. Evaluation Board Layout, Primary Side (With Ground Copper Pour) Rev. 0 | Page 25 of 32 03682-038 03682-036 AD9289 Figure 44. Evaluation Board Layout, Ground Plane Figure 45. Evaluation Board Layout, Power Plane Rev. 0 | Page 26 of 32 03682-040 03682-039 AD9289 Figure 46. Evaluation Board Layout, Secondary Side Figure 47. Evaluation Board Layout, Secondary Side (With Ground Copper Pour) Rev. 0 | Page 27 of 32 03682-041 03682-045 AD9289 Table 11. Evaluation Board Bill of Materials (BOM) Qnty. per Item Board REFDES Device Package Value Manufacturing Mfg. Part Number 1 1 AD9289 BGA PCB PCB PCB PCSM PCSM REVA/PCB 2 1 Assembly Protronics Protronics 3 8 R46, R48, R60, R61, RES_402 402 0 Yageo America 9C04021A0R00JLHF3 R98, R99, R113, R114 4 8 R5, R7, R8, R9, R10, RES_402 402 10 Susumu Co Ltd RR0510R-100-D R17, R33, R39 5 8 R22,R49, R52, R55, RES_402 402 25 Susumu Co Ltd RR0510R-240-D R79, R92, R101, R106 6 8 R11,R14, R23, R27, RES_402 402 33 Susumu Co Ltd RR0510R-330-D R31, R34, R44, R47 7 4 R38, R56, R91, R107 RES_402 402 50 Panasonic-ECG ERJ-L14KF50MU 8 1 R73 RES_402 402 100 Yageo America 9C04021A1000FLHF3 9 8 R45, R50, R57, R58, RES_402 402 1K Panasonic-ECG ERJ-2GEJ102X R93, R94, R108, R111 10 4 R35, R53, R81, R103 RES_402 402 1.2K Panasonic-ECG ERJ-2GEJ122X 11 13 R6, R32, R36, R51, RES_402 402 10K Susumu Co Ltd RR0510P-103-D R54, R72, R75, R78, R90, R100, R104, R37, R76 12 6 R62, R63, R64, R65, BRES603 603 0 Panasonic-ECG ERJ-3GEY0R00V R66, R71 13 1 R102 BRES603 603 22 Susumu Co Ltd RR0816Q-220-D 14 5 BRES603 603 50 Susumu Co Ltd RR0816Q-49R9-D-68R R15, R30, R41, R42, R83 15 23 R1, R12, R13, R16, BRES603 603 1K Susumu Co Ltd RR0816P-102-D R18, R19, R20, R21, R24, R29, R40, R43, R59, R68, R69, R70, R74, R77, R80, R82, R84, R109, R110 16 2 R96, R97 BRES603 603 XXX 17 4 C10, C21, C30, C41 CAP402 402 20PF Kemet C0402C220J5GACTU 18 36 C1, C35, C44, C47, CAP402 402 1UF Panasonic-ECG ECJ-0EF1C104Z C80, C250, C600, C11, C12, C14, C37, C40, C48, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C73 19 17 C2, C3, C4, BYPASSCAP 603 0.1UF Kemet C0603C104Z3VACTU C5, C6, C7, C15, C16, C18, C20, C25, C29, C36, C53, C108, C110, C183 20 3 C100, C120, C163 TANTALUMB 805 10UF Panasonic-ECG ECJ-2FB0J106M 21 3 C170, C171, C176 TANTALUMB T491B06K01 10UF Kemet T491B106K016AS 22 16 L1, L2 ,L3, L4, L6, L9, INDUCTOR_6 603 120NH Murata BLM18BB750SN1D L10, L11, L12, L13, L19, L20, L21, L22, L27, L28 23 3 L5,L7,L8 IND1210 1210 10UH Panasonic-ECG ELJ-SA100KF 24 1 P6 PTMICRO6 PTMICRO6 6-Pole PCB Wieland Z5.531.3625.0 Header Rev. 0 | Page 28 of 32 AD9289 Qnty. per Item Board REFDES Device Package Value Manufacturing Mfg. Part Number 1 6-Pole PCB Wieland 25.600.5653.0 Connector 25 5 P1, P2, P3, P4, P5 SMBMST SMB SMBMST Amphenol-RF 901-144-8RFX Division 26 4 T1, T2, T3, T4 ADT1-1WT CD542_X65 ADT1-1WT Minicircuits ADT1-1WT 27 1 U17 HEADER 2MMSMT-872 WM18158- Molex/Waldom 87267-0850 ND Electronics Corp 28 1 U5 DIFF_CONN FCN_268M01 DIFF_CONN Fujitsu FCN-268M012-G/1D 29 1 J6 MINIJMPR3 2MMSMT-872 MINIJMPR3 Molex/Waldom 87267-0850 Electronics Corp 30 2 JP1, JP2 SGLJMPR SGLJMPR 87267-0850 Samtec TSW-120-07-G-S 31 2 11/4" NYLON 1/4" 6-32 RAF 4040-632-N STANDOFF 32 2 6-32NUTS NYLON 6-32 RAF 3058-N 33 1 U1 74VHC04MTC TSSOP-14 74VHC04 Fairchild 74VHC04MTC Semiconductor 34 1 U2 FIN1017M MO8A_(SOIC) FIN1017M Fairchild FIN1017M Semiconductor 35 1 U4 9289BGA 9289BGA ADI AD9289BBC-65 AD9289BBC- 65 36 1 U6 ADR510 SOT23 ADR510 ADI ADR510 37 4 U7, U8, U9, U10 AD8351ARM MSOP010 AD8351 ADI AD8351ARM Rev. 0 | Page 29 of 32 AD9289 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 8.00 BSC SQ 87 65 4 3 21 A BALL A1 B INDICATOR C 5.60 BSC SQ D TOP VIEW 0.80 E BSC F G H BOTTOM VIEW DETAIL A 1.70 1.31 1.55 DETAIL A 1.21 1.35 0.34 NOM 1.10 0.25 MIN COPLANARITY 0.55 0.12 SEATING 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-BA Figure 48. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-64-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9289BBC –40°C to +85°C 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] BC-64-1 AD9289-65EB Evaluation Board Rev. 0 | Page 30 of 32 AD9289 NOTES Rev. 0 | Page 31 of 32 AD9289 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03682-0-10/04(0) Rev. 0 | Page 32 of 32