ANALOG DEVICES AD9286

8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9286 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation The AD9286 is an 8-bit, monolithic sampling, analog-to-digital SNR: 49.3 dBFS at 200 MHz input at 500 MSPS converter (ADC) that supports interleaved operation and is SFDR: 65 dBc at 200 MHz input at 500 MSPS optimized for low cost, low power, and ease of use. Each ADC Low power: 315 mW at 500 MSPS operates at up to a 250 MSPS conversion rate with outstanding On-chip interleaved clocking dynamic performance. On-chip reference and track-and-hold The AD9286 takes a single sample clock and, with an on-chip 1.2 V p-p analog input range for each channel clock divider, time interleaves the two ADC cores (each running Differential input with 500 MHz bandwidth at one-half the clock frequency) to achieve the rated 500 MSPS. LVDS-compliant digital output By using the SPI, the user can accurately adjust the timing of the On-chip voltage reference and sample-and-hold circuit sampling edge per ADC to minimize the image spur energy. DNL: ±0.2 LSB The ADC requires a single 1.8 V supply and an encode clock for Serial port control options full performance operation. No external reference components Interleaved clock timing adjustment are required for many applications. The digital outputs are LVDS Offset binary, Gray code, or twos complement data format compatible. Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation The AD9286 is available in a Pb-free, 48-lead LFCSP that is Pin-programmable power-down function specified over the industrial temperature range of −40°C to +85°C. Available in 48-lead LFCSP PRODUCT HIGHLIGHTS APPLICATIONS 1. Integrated 8-Bit, 500 MSPS ADC. Battery-powered instruments 2. Single 1.8 V Supply Operation with LVDS Outputs. Handheld scope meters 3. Power-Down Option Controlled via a Pin-Programmable Low cost digital oscilloscopes Setting. OTS: video over fiber FUNCTIONAL BLOCK DIAGRAM SDIO/ PWDN CSB SCLK OE CLK+ SPI CLK– VIN1+ ADC VIN1– VCM D7+ (MSB), D7– (MSB) REF VREF ×1.5 SELECT CLOCK D0+ (LSB), D0– (LSB) 1.0V MANAGEMENT V REF VIN2– DCO+ DCO ADC GENERATION VIN2+ DCO– AUXCLK– AUXCLK+ AD9286 RBIAS AUXCLKEN AGND AVDD DRVDD DRGND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. 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OUTPUT INTERLEAVE LVDS OUTPUT BUFFER 09338-001 AD9286 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 15 Applications ....................................................................................... 1 RBIAS ........................................................................................... 15 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 16 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 18 Functional Block Diagram .............................................................. 1 Built-In Self-Test (BIST) and Output Test .................................. 19 Revision History ............................................................................... 2 Built-In Self-Test (BIST) ............................................................ 19 Specifications ..................................................................................... 3 Output Test Modes ..................................................................... 19 DC Specifications ......................................................................... 3 Serial Port Interface (SPI) .............................................................. 20 AC Specifications .......................................................................... 4 Configuration Using the SPI ..................................................... 20 Digital Specifications ................................................................... 5 Hardware Interface ..................................................................... 21 Switching Specifications .............................................................. 6 Configuration Without the SPI ................................................ 21 SPI Timing Specifications ........................................................... 6 SPI Accessible Features .............................................................. 21 Absolute Maximum Ratings ............................................................ 9 Memory Map .................................................................................. 22 Thermal Resistance ...................................................................... 9 Reading the Memory Map Register Table ............................... 22 ESD Caution .................................................................................. 9 Memory Map Register Table ..................................................... 23 Pin Configuration and Function Descriptions ........................... 10 Memory Map Register Descriptions ........................................ 25 Typical Performance Characteristics ........................................... 12 Applications Information .............................................................. 26 Equivalent Circuits ......................................................................... 14 Design Guidelines ...................................................................... 26 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 27 ADC Architecture ...................................................................... 15 Ordering Guide .......................................................................... 27 Analog Input Considerations .................................................... 15 REVISION HISTORY 3/11—Rev. 0 to Rev. A Changes to General Description, ADC Conversion Rate ........... 1 1/11—Revision 0: Initial Version Rev. A | Page 2 of 28 AD9286 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted. Table 1. 1 Parameter Temperature Min Typ Max Unit RESOLUTION Full 8 Bits DC ACCURACY Differential Nonlinearity Full ±0.2 ±0.4 LSB Integral Nonlinearity Full ±0.1 ±0.3 LSB No Missing Codes Full Guaranteed Offset Error Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±2 ±2.8 % FS MATCHING CHARACTERISTICS 2 Offset Error Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±0.05 ±0.2 % FS TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±20 ppm/°C ANALOG INPUT Input Span Full 1.2 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 16 kΩ Input Capacitance (Differential) Full 250 fF Full Power Bandwidth Full 700 MHz VOLTAGE REFERENCE Internal Reference Full 0.97 1 1.03 V Input Resistance Full 3 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current IAVDD Full 125 130 mA IDRVDD Full 51 54 mA POWER CONSUMPTION 3 Sine Wave Input Full 315 330 mW Power-Down Power Full 0.3 1.7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 See the Interleave Performance section. 3 Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. A | Page 3 of 28 AD9286 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, VIN = −1.0 dBFS differential input, optimum timing value set, unless otherwise noted. Table 2. Parameter Temperature Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz 25°C 49.3 dBFS fIN = 70 MHz 25°C 49.3 dBFS f = 96.6 MHz Full 48.8 49.3 dBFS IN f = 220 MHz 25°C 49.3 dBFS IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) f = 10.3 MHz 25°C 49.2 dBFS IN f = 70 MHz 25°C 49.2 dBFS IN fIN = 96.6 MHz Full 48.7 49.2 dBFS fIN = 220 MHz 25°C 49.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz 25°C 7.9 Bits fIN = 70 MHz 25°C 7.9 Bits fIN = 96.6 MHz Full 7.8 7.9 Bits f = 220 MHz 25°C 7.9 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz 25°C −70 dBc f = 70 MHz 25°C −70 dBc IN f = 96.6 MHz Full −69 −61 dBc IN f = 220 MHz 25°C −65 dBc IN 1 SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 10.3 MHz 25°C 70 dBc IN fIN = 70 MHz 25°C 70 dBc fIN = 96.6 MHz Full 61 68 dBc fIN = 220 MHz 25°C 65 dBc WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz 25°C −71 dBc fIN = 70 MHz 25°C −71 dBc f = 96.6 MHz Full −71 −64 dBc IN f = 220 MHz 25°C −67 dBc IN CROSSTALK Full −80 dBc 1 Excludes offset and alias spur (see the Interleave Performance section). Rev. A | Page 4 of 28 AD9286 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, AIN = 5 MHz, full temperature, unless otherwise noted. Table 3. 1 Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−, AUXCLK+, AUXCLK−) Logic Compliance LVDS/PECL Internal Common-Mode Bias Full 1.2 V 2 Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS CSB High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −5 −0.4 +5 μA Low Level Input Current Full −80 −63 −50 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF SCLK, SDIO/PWDN, AUXCLKEN, OE High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full 50 57 70 μA Low Level Input Current Full −5 −0.4 +5 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS DRVDD = 1.8 V Differential Output Voltage (V ) Full 290 345 400 mV OD Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 Specified for LVDS and LVPECL only. Rev. A | Page 5 of 28 AD9286 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 60 500 MHz CLK Period (tCLK) Full 4 ns CLK Pulse Width High (tCH) Full 2 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3.7 ns DCO Propagation Delay (tDCO) Full 3.7 ns DCO to Data Skew (t ) Full −280 −60 100 ps SKEW Pipeline Delay (Latency) Full 11 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms 1 Wake-Up Time Full 500 µs OUT-OF-RANGE RECOVERY TIME Full 4 Cycles 1 Wake-up time is dependent on the value of the decoupling capacitors. SPI TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input 10 ns EN_SDIO to an output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output 10 ns to an input relative to the SCLK rising edge Timing Diagrams M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t A M + 1 M + 2 N + 4 N – 1 N – 2 N + 3 VIN2+, VIN2– N N + 2 N + 1 t A t CLK t CH CLK+ CLK– t DCO DCO+, DCO– t SKEW DATA M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 t PD Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default) Rev. A | Page 6 of 28 09338-002 AD9286 M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t A N – 1 N + 4 M + 1 M + 2 N + 5 N N + 3 VIN2+, VIN2– N + 1 N + 2 t t CH CLK CLK+ CLK– t DCO DCO+, DCO– t SKEW DATA N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7 t PD Figure 3. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 0 M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t A N – 1 N + 4 M + 1 N + 5 M + 2 N N + 3 VIN2+, VIN2– N + 1 N + 2 t t CH CLK CLK+ CLK– AUXCLK+ AUXCLK– t DCO DCO+, DCO– t SKEW DATA M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 t PD Figure 4. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK in Phase Rev. A | Page 7 of 28 09338-005 09338-006 AD9286 M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t A M + 1 N + 4 M + 2 N – 1 N – 2 N + 3 VIN2+, VIN2– N N + 2 N + 1 t A t t CH CLK CLK+ CLK– AUXCLK– AUXCLK+ t DCO DCO+, DCO– t SKEW M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 DATA t PD Figure 5. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK Out of Phase Rev. A | Page 8 of 28 09338-007 AD9286 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 6. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V THERMAL RESISTANCE D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.3 V to DRGND θ is specified for the worst-case conditions, that is, a device JA DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V soldered in a circuit board for surface-mount packages. CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance AUXCLK+, AUXCLK− to AGND −0.3 V to AVDD + 0.2 V VIN1±, VIN2± to AGND −0.3 V to AVDD + 0.2 V Package Type θ θ Unit JA JC SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V 48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V ESD CAUTION Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. A | Page 9 of 28 AD9286 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD 1 36 AVDD PIN 1 AVDD 2 35 AVDD INDICATOR AUXCLK+ 3 34 CLK+ AUXCLK– 4 33 CLK– RBIAS 5 32 CSB AD9286 AUXCLKEN 6 31 SDIO/PWDN TOP VIEW DRGND 7 30 SCLK (Not to Scale) DRVDD 8 29 OE 28 DRGND D0– (LSB) 9 D0+ (LSB) 10 27 DRVDD D1– 11 26 D7+ (MSB) D1+ 12 25 D7– (MSB) NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 6. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Pins 1, 2, 35, 36, 37, 40, 42, AVDD Supply Analog Power Supply (1.8 V Nominal). 44, 45, 48 8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 7, 28 DRGND Ground Digital Output Ground. 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ADC Analog Pins 39 VIN1+ Input Differential Analog Input Pin (+) for Channel 1. 38 VIN1− Input Differential Analog Input Pin (−) for Channel 1. 46 VIN2+ Input Differential Analog Input Pin (+) for Channel 2. 47 VIN2− Input Differential Analog Input Pin (−) for Channel 2. 43 VREF Input/output Voltage Reference Input/Output. 5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. 41 VCM Output Common-Mode Level Bias Output for Analog Inputs. 34 CLK+ Input ADC Clock Input—True. 33 CLK− Input ADC Clock Input—Complement. 3 AUXCLK+ Input Auxiliary ADC Clock Input—True. 4 AUXCLK− Input Auxiliary ADC Clock Input—Complement. Digital Inputs 6 AUXCLKEN Input Auxiliary Clock Input Enable. 29 OE Input Digital Enable (Active Low) to Tristate Output Data Pins. Digital Outputs 26 D7+ (MSB) Output Output Data 7—True. 25 D7− (MSB) Output Output Data 7—Complement. 24 D6+ Output Output Data 6—True. 23 D6− Output Output Data 6—Complement. Rev. A | Page 10 of 28 D2– 13 48 AVDD D2+ 14 47 VIN2– D3– 15 46 VIN2+ D3+ 16 45 AVDD DCO– 17 44 AVDD DCO+ 18 43 VREF D4– 19 42 AVDD D4+ 20 41 VCM D5– 21 40 AVDD D5+ 22 39 VIN1+ 38 VIN1– D6– 23 D6+ 24 37 AVDD 09338-003 AD9286 Pin No. Mnemonic Type Description 22 D5+ Output Output Data 5—True. 21 D5− Output Output Data 5—Complement. 20 D4+ Output Output Data 4—True. 19 D4− Output Output Data 4—Complement. 16 D3+ Output Output Data 3—True. 15 D3− Output Output Data 3—Complement. 14 D2+ Output Output Data 2—True. 13 D2− Output Output Data 2—Complement. 12 D1+ Output Output Data 1—True. 11 D1− Output Output Data 1—Complement. 10 D0+ (LSB) Output Output Data 0—True. 9 D0− (LSB) Output Output Data 0—Complement. 18 DCO+ Output Data Clock Output—True. 17 DCO− Output Data Clock Output—Complement. SPI Control Pins 30 SCLK Input SPI Serial Clock. 31 SDIO/PWDN Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). 32 CSB Input SPI Chip Select (Active Low). Rev. A | Page 11 of 28 AD9286 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 500 MSPS, DCS enable, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, unless otherwise noted. 0 0 500MSPS 500MSPS 4.3MHz @ –1dBFS 96.6MHz @ –1dBFS SNR = 48.4dB (49.4dBFS) SNR = 48.2dB (49.2dBFS) –20 –20 ENOB = 7.7 ENOB = 7.7 SFDR = 70.0dBc SFDR = 68.4dBc –40 –40 SECOND HARMONIC –60 –60 THIRD HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Single-Tone FFT with fIN = 4.3 MHz = 96.6 MHz Figure 10. Single-Tone FFT with fIN 0 0 500MSPS 500MSPS 220.3MHz @ –1dBFS 29.1MHz @ –7dBFS SNR = 48.2dB (49.2dBFS) 32.1MHz @ –7dBFS –20 –20 ENOB = 7.7 SFDR = 70.3dBc (77.3dBFS) SFDR = 66.4dBc –40 –40 SECOND HARMONIC THIRD HARMONIC –60 –60 –80 –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Single-Tone FFT with fIN = 220.3 MHz Figure 11. Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz 80 100 IMD3 (dBFS) 90 70 SFDR (dBFS) 80 60 70 SFDR (dBFS) SNR (dBFS) 50 60 IMD3 (dBc) REFERENCE LINE 40 50 SFDR (dBc) SFDR (dBc) 40 30 SNR (dBc) 30 20 20 10 10 0 0 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 AIN POWER (dBFS) AIN POWER (dBFS) Figure 9. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Rev. A | Page 12 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/SNR (dB) 09338-109 09338-108 09338-107 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/IMD3 (dB) 09338-112 09338-111 09338-110 AD9286 75 100 95 SFDR +25°C +85°C 70 90 SFDR –40°C SFDR +85°C 85 65 80 75 60 +25°C 70 55 65 SNRFS –40°C SNRFS +25°C –40°C 60 SNRFS +85°C 50 55 50 45 –3 –2 –1 0 1 2 3 0 50 100 150 200 250 300 350 400 450 500 INPUT FREQUENCY (MHz) COARSE TIMING ADJUSTMENT (Bits) Figure 13. SNRFS/SFDR vs. Input Frequency (f ) and Temperature Figure 16. Alias Spur vs. Coarse Timing Adjustment and Temperature IN 0.15 0.200 0.40 0.175 0.35 0.10 TOTAL POWER 0.150 0.30 0.05 0.125 0.25 0 0.100 0.20 I_AVDD 0.075 0.15 –0.05 0.050 0.10 I_DVDD –0.10 0.025 0.05 –0.15 0 0 0 32 64 96 128 160 192 224 256 100 150 200 250 300 350 400 450 500 OUTPUT CODE ENCODE FREQUENCY (MHz) Figure 14. Supply Current and Power vs. Encode Figure 17. INL Error with f = 4.3 MHz IN 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 0 32 64 96 128 160 192 224 256 OUTPUT CODE Figure 15. DNL Error with f = 4.3 MHz IN Rev. A | Page 13 of 28 SUPPLY CURRENT (A) DNL ERROR (LSB) SNRFS/SFDR (dBFS/dBc) 09338-113 TOTAL POWER (W) 09338-115 09338-114 INL ERROR (LSB) ALIAS SPUR (dBFS) 09338-116 09338-118 AD9286 EQUIVALENT CIRCUITS DRVDD AVDD AVDD AVDD DRVDD 1.2V 10kΩ 10kΩ 350Ω CLK+ CLK– SCLK, OE, AUXCLKEN 30kΩ Figure 18. Clock Inputs Figure 21. SCLK, OE, AUXCLKEN AVDD AVDD DRVDD BUF VIN+ 350Ω 8kΩ V CML BUF 30kΩ ~1.4V AVDD 8kΩ SDIO VIN– BUF CTRL Figure 19. Analog Inputs (VCML = ~1.4 V) Figure 22. SDIO DRVDD DRVDD DRVDD V+ V– DRVDD 30kΩ D7– TO D0– D7+ TO D0+ 350Ω CSB V– V+ Figure 20. CSB Figure 23. LVDS Output Driver Rev. A | Page 14 of 28 09338-020 09338-021 09338-019 09338-024 09338-023 09338-022 AD9286 THEORY OF OPERATION The AD9286 is a pipeline-type converter. The input buffers are Differential Input Configurations differential, and both sets of inputs are internally biased. This Optimum performance is achieved when driving the AD9286 allows the use of ac or dc input modes. A sample-and-hold in a differential input configuration. For baseband applications, amplifier is incorporated into the first stage of the multistage the ADA4937-1 differential driver provides excellent performance pipeline converter core. The output staging block aligns the data, and a flexible interface to the ADC (see Figure 24). The output carries out error correction for the pipeline stages, and feeds common-mode voltage of the AD9286 is easily set to 1.4 V, and that data to the output interleave block and, finally, to the output the driver can be configured in a Sallen-Key filter topology to buffers. All user-selected options are programmed through provide band limiting of the input signal. dedicated digital input pins or a serial port interface (SPI). 200Ω ADC ARCHITECTURE 1.2V p-p 61.9Ω 33Ω + 200Ω VIN1 – – Each interleaving channel of the AD9286 consists of a differential 4.7pF ADA4937-1 input buffer followed by a sample-and-hold amplifier (SHA). AD9286 227.4Ω 0.1µF This SHA is followed by a pipeline switched-capacitor ADC. + 33Ω + The quantized outputs from each stage are combined into a final VIN2 200Ω – 8-bit result in the digital correction logic. The pipelined archi- VCM tecture permits the first stage to operate on a new input sample, whereas the remaining stages operate on preceding samples. Figure 24. Differential Input Configuration Using the ADA4937-1 Each stage of the pipeline, excluding the last, consists of a low The AD9286 can also be driven passively with a differential resolution flash ADC connected to a switched-capacitor DAC transformer-coupled input (see Figure 25). To bias the analog and interstage residue amplifier (MDAC). The residue amplifier input, the VCM voltage can be connected to the center tap of magnifies the difference between the reconstructed DAC output the secondary winding of the transformer. and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction 33Ω + of flash errors. The last stage consists of a flash ADC. VIN1 – 1.2V p-p 49.9Ω The input stage contains a differential SHA that can be ac- or 4.7pF AD9286 dc-coupled in differential or single-ended mode. The output 33Ω + staging block aligns the data, carries out the error correction, VIN2 – and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the VCM output voltage swing. During power-down, the output buffers 0.1µF go into a high impedance state. The outputs from both interleaving channels are time interleaved Figure 25. Differential Transformer-Coupled Configuration to achieve an effective 500 MSPS. The signal characteristics must be considered when selecting a ANALOG INPUT CONSIDERATIONS transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause The analog inputs of the AD9286 are differentially buffered. core saturation, which leads to distortion. For best dynamic performance, the source impedances driving VIN1+, VIN1−, VIN2+, and VIN2− should be matched such VOLTAGE REFERENCE that common-mode settling errors are symmetrical. Because An internal differential voltage reference creates positive and the AD9286 interleaves two ADC cores, special attention should negative reference voltages that define the 1.2 V p-p fixed span be given, during board layout, to the symmetry of the two analog of the ADC core. This internal voltage reference can be adjusted paths. Mismatch introduces undesired distortion. The analog by means of SPI control. It can also be driven externally with inputs are optimized to provide superior wideband performance an off-chip stable reference. See the Memory Map Register and must be driven differentially. SNR and SINAD performance Descriptions section for more details. degrades significantly if the analog inputs are driven with RBIAS a single-ended signal. The AD9286 requires the user to place a 10 kΩ resistor between A wideband transformer, such as Mini-Circuits® ADT1-1WT, can the RBIAS pin and ground. This resistor, which is used to set provide the differential analog inputs for applications that require the master current reference of the ADC core, should have a 1% a single-ended-to-differential conversion. Both analog inputs tolerance. are self-biased by an on-chip resistor divider to a nominal 1.4 V. Rev. A | Page 15 of 28 09338-026 09338-025 AD9286 CLOCK INPUT CONSIDERATIONS 0.1µF 0.1µF CLOCK CLK+ For optimum performance, clock the AD9286 sample clock inputs, INPUT CLK+ and CLK− (and, optionally, AUXCLK+ and AUXCLK−), AD951x 100Ω ADC PECL DRIVER 0.1µF 0.1µF with a differential signal. The signal is typically ac-coupled into CLOCK CLK– INPUT the CLK+ and CLK− pins via a transformer or capacitors. 50kΩ 50kΩ 240Ω 240Ω Clock Input Options Figure 28. Differential PECL Sample Clock The AD9286 has a very flexible clock input structure. The clock input can be an LVDS, LVPECL, or sine wave signal. Each con- A third option is to ac couple a differential LVDS signal to the figuration that is described in this section applies to both CLK+ sample clock input pins, as shown in Figure 29. The AD9510/ and CLK− and AUXCLK+ and AUXCLK −, when necessary. AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. Figure 26 and Figure 27 show two preferred methods for clocking the AD9286. A low jitter clock source is converted from a single- 0.1µF 0.1µF ended signal to a differential signal using either an RF transformer CLOCK CLK+ INPUT or an RF balun. The back-to-back Schottky diodes across the AD951x 100Ω ADC transformer/balun secondary limit clock excursions into the LVDS DRIVER 0.1µF 0.1µF CLOCK AD9286 to approximately 0.8 V p-p differential. CLK– INPUT 50kΩ 50kΩ This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9286, while Figure 29. Differential LVDS Sample Clock preserving the fast rise and fall times of the signal that are Clocking Modes critical to low jitter performance. The AD9286 powers up as a single-channel converter with inter- ® Mini-Circuits leaving enabled. In this mode, a single high speed clock, driving ADT1-1WT, 1:1 Z 0.1µF XFMR CLK+ and CLK−, is divided down into two half-speed clocks CLOCK CLK+ INPUT 100Ω 0.1µF running 180° out of phase with each other, each driving their 50Ω ADC respective ADC core. By strapping the two analog inputs together CLK– 0.1µF SCHOTTKY externally, the AD9286 operates as a single 500 MSPS ADC. 0.1µF DIODES: HSM2822 Because the high sample rate is achieved by interleaving two ADC cores, mismatch between the cores, board layout, and Figure 26. Transformer-Coupled Differential Clock clock timing can cause unwanted distortion. The AD9286 has been designed with two well-matched ADC cores to minimize mismatch. To aid the user in removing timing errors, the AD9286 1nF provides both fine and coarse timing adjustments, per channel, CLOCK CLK+ INPUT through SPI. These features are available at Register 0x37 (fine) 0.1µF 50Ω ADC 1nF and Register 0x38 (coarse). CLK– 0.1µF SCHOTTKY The AD9286 supports a mode that allows the user to provide DIODES: HSM2822 two separate half-speed clocks, bypassing the internal clock timing circuits and permitting external control of the clock Figure 27. Balun-Coupled Differential Clock timing relationship for each interleave channel. When the sample If a low jitter clock source is not available, another option is to mode is set to simultaneous (Address 0x09, Bit 3 = 0) and the ac couple a differential PECL signal to the sample clock input AUXCLKEN pin is tied to DRVDD, the AD9286 expects a second pins, as shown in Figure 28. The AD9510/AD9511/AD9512/ clock on its auxiliary clock input (AUXCLK+, AUXCLK−). AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. Rev. A | Page 16 of 28 09338-028 09338-027 09338-030 09338-029 AD9286 AS , as a function of gain mismatch, is shown in Figure 30. GAIN In this mode, the AD9286 can also function as a dual 8-bit, 85 250 MSPS converter. This may be useful in applications where both a single 8-bit, 500 MSPS and a dual 8-bit, 250 MSPS converter 80 are needed. The clock management block requires that CLK± 75 and AUXCLK± be either 0° or 180°, relative to each other. If this requirement is satisfied, the circuit correctly time aligns the 70 data coming out of each ADC core. 65 If the user desires to operate the AD9286 as a dual 8-bit, 250 MSPS 60 converter and supply only a single clock, this is achieved by setting sample mode to simultaneous, with the AUXCLKEN 55 pin tied to AGND. In this mode, the two ADC cores sample 50 simultaneously. For a summary of all supported clocking modes, see Table 9. 45 0 0.1 0.2 0.3 0.4 0.5 The AD9286 supports the clocking of each internal ADC with GAIN MISMATCH (% FS) separate clocks. By setting AUXCLKEN to DRVDD, the user Figure 30. ASGAIN as a Function of Gain Mismatch can supply a differential auxiliary clock to AUXCLK+ and The magnitude of the alias spur (AS) contributed by a timing AUXCLK−. In this mode, each internal ADC core has a maximum error is shown in Equation 4. sample rate of 250 MSPS. This mode bypasses the internal timing adjustment blocks. ASTIMING (dBc) = 20 × log(ASTIMING) = 20 × log(θEP/2) (4) where θEP = ωA × ∆tE(Radians), with ωA as the analog input Interleave Performance frequency and ∆t as the clock skew error. E The AD9286 achieves 500 MSPS conversion by time interleaving two 250 MSPS ADC channels. Although this technique is sufficient AS , as a function of timing error, is shown in Figure 31. TIMING in achieving 8-bit performance, quantifiable errors are introduced. 85 These errors come from three sources: gain mismatch, imperfect 80 out-of-phase sampling, and offset mismatch between the two 75 channels. Distortion appears spectrally in two distinct ways: gain and timing mismatch appear as an alias spur (see Equation 1), and 70 offset mismatch appears as a spur located at the Nyquist rate of the 65 converter (see Equation 2). f = f /2 − f (1) ALIAS_SPUR S IN 60 where: 55 f is the interleaved sample rate. S 50 fIN is the analog input frequency. 45 fOFFSET_SPUR = fS/2 (2) 0 2 4 6 8 10 12 TIMING ERROR (ps) where fS is the interleaved sample rate. Figure 31. ASTIMING as a Function of Timing Error The magnitude of the alias spur (AS) contributed by a gain error The total magnitude of the alias spur (AS) is shown in Equation 5. is shown in Equation 3. 2 2 AS (dBc) = 20 × log(AS ) = 20 × log(G /2) (3) ASTOTAL (dB) = 20 × log√((ASGAIN) + (ASTIMING) ) (5) GAIN GAIN E where: GE = Gain_Error_Ratio = 1 − VFS1/VFS2. VFSn is the full-scale voltage of Core n. Table 9. Supported Clocking Modes Effective Number Maximum CLK AUXCLK AUXCLK Phase SPI Register, of Channels Frequency Frequency Relative to CLK AUXCLKEN Address 0x09, Bit 3 Clock Timing Adjust One 500 MSPS N/A N/A Low 1 Internal Two 250 MSPS N/A N/A Low 0 N/A Two 250 MSPS CLK 0° High 0 N/A One 250 MSPS CLK 180° High 0 External Rev. A | Page 17 of 28 ALIAS SPUR (dBc) ALIAS SPUR (dBc) 09338-032 09338-033 AD9286 The magnitude of the offset spur (OS) is shown in Equation 6. Due to the orthogonal relationship between the gain and timing errors, it is impossible to correct for one with the other. To mini- RESOLUTION OS (dBFS) = 20 × log(OFFSET × 2/2 ) (6) OFFSET mize channel-to-channel gain error, the AD9286 is designed where: to have very close gain matching between the two channels. OFFSET is the channel-to-channel offset in codes. Address 0x37 and Address 0x38 of the SPI provide the ability to RESOLUTION is the resolution of the converter (eight bits). add delay to either clock path to realize a minimum clock skew OSOFFSET, as a function of offset mismatch, is shown in Figure 32. error. Also provided via the SPI, in Address 0x10, is the ability 60 to minimize the channel-to-channel offset error. DIGITAL OUTPUTS 55 Digital Output Enable Function (OE) 50 The AD9286 has a flexible three-state ability for the digital output 45 OE OE pins. The three-state mode is enabled using the pin. When 40 is set to logic level high, the output drivers for both data buses are placed into a high impedance state. 35 30 25 20 0 0.5 1.0 1.5 2.0 2.5 OFFSET MISMATCH (% FS) Figure 32. OSOFFSET as a Function of Offset Mismatch Rev. A | Page 18 of 28 OFFSET SPUR (dBFS) 09338-034 AD9286 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9286 includes a built-in self-test feature that is designed Writing a value of 0x05 to Register 0x0E runs the BIST. This to enable verification of the integrity of each channel, as well as enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN facilitate board level debugging. A built-in self-test (BIST) feature sequence generator, Bit 2 (BIST init) of Register 0x0E. At the that verifies the integrity of the digital datapath of the AD9286 completion of the BIST, Bit 0 of Register 0x0E is automatically is included. Various output test options are also provided to cleared. The PN sequence can be continued from its last value place predictable values on the outputs of the AD9286. by writing a 0 to Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal BUILT-IN SELF-TEST (BIST) the predetermined value at the end of the test. At that point, the The BIST is a thorough test of the digital portion of the selected user must rely on verifying the output data. AD9286 signal path. Perform the BIST test after a reset to ensure OUTPUT TEST MODES that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through The output test options are described in Table 13 at Address 0x0D. the digital datapath of both channels, starting at the ADC block When an output test mode is enabled, the analog section of the output. At the datapath output, CRC logic calculates a signature ADC is disconnected from the digital back-end blocks and the from the data. The BIST sequence runs for 512 cycles and then test pattern is run through the output formatting block. Some stops. When the test is completed, the BIST compares the signature test patterns are subject to output formatting, and some are not. results with a predetermined value. If the signatures match, the The PN generators from the PN sequence tests can be reset by BIST sets Bit 0 of Register 0x0E, signifying that the test passed. setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs with or without an analog signal (if present, the analog signal is are connected during this test, so the PN sequence can be observed ignored), but they do require an encode clock. For more as it runs. information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. A | Page 19 of 28 AD9286 SERIAL PORT INTERFACE (SPI) The AD9286 serial port interface (SPI) allows the user to configure The falling edge of CSB, in conjunction with the rising edge of the converter for specific functions or operations through a SCLK, determines the start of the framing. An example of the structured register space provided inside the ADC. The SPI serial timing and its definitions can be found in Figure 33. gives the user added flexibility and customization, depending Other modes involving CSB are available. The CSB pin can be held on the application. Addresses are accessed via the serial port low indefinitely, which permanently enables the device; this is and can be written to or read from via the port. Memory is called streaming. CSB can stall high between bytes to allow for organized into bytes that can be further divided into fields, additional external timing. When the CSB pin is tied high, SPI which are documented in the Memory Map section. For detailed functions are placed in high impedance mode. This mode turns operational information, see the AN-877 Application Note, on any SPI pin secondary functions. Interfacing to High Speed ADCs via SPI. During the instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: SCLK, SDIO, and CSB by the W0 and W1 bits, as shown in Figure 33. (see Table 10). SCLK (a serial clock) is used to synchronize the All data is composed of 8-bit words. The first bit of the first byte read and write data presented from and to the ADC. SDIO in a multibyte serial data transfer frame indicates whether a read (serial data input/output) is a dual-purpose pin that allows data command or a write command is issued. This allows the serial to be sent to and read from the internal ADC memory map data input/output (SDIO) pin to change direction, from an input registers. CSB (chip select bar) is an active low control that to an output, at the appropriate point in the serial frame. enables or disables the read and write cycles. In addition to word length, the instruction phase determines Table 10. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read Pin Function the contents of the on-chip memory. If the instruction is a readback SCLK Serial clock. A serial shift clock input that is used to synchronize serial interface reads and writes. operation, the serial data input/output (SDIO) pin changes SDIO Serial data input/output. A dual-purpose pin that direction, from an input to an output, at the appropriate point typically serves as an input or an output, depending in the serial frame. on the instruction being sent and the relative position Data can be sent in MSB-first mode or in LSB-first mode. MSB in the timing frame. first is the default on power-up and can be changed via the SPI CSB Chip select bar. An active low control that gates the read and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 33. Serial Port Interface Timing Diagram Rev. A | Page 20 of 28 09338-004 AD9286 HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 10 constitute the physical interface In applications that do not interface to the SPI control registers, between the programming device of the user and the serial port the SDIO/PWDN pin serves as a standalone, CMOS-compatible of the AD9286. The SCLK and CSB pins function as inputs control pin. When the device is powered up, it is assumed that when using the SPI interface. The SDIO pin is bidirectional, the user intends to use the SDIO, SCLK, and CSB pins as static functioning as an input during write phases and as an output control lines for the output enable and power-down feature control. during readback. In this mode, connecting the CSB chip select to AVDD disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration SPI ACCESSIBLE FEATURES is described in detail in the AN-812 Application Note, Micro- Table 12 provides a brief description of the general features that controller-Based Serial Port Interface (SPI) Boot Circuit. are accessible via the SPI. These features are described in detail The SPI port should not be active during periods when the full in the AN-877 Application Note, Interfacing to High Speed ADCs dynamic performance of the converter is required. Because the via SPI. The AD9286 part-specific features are described in SCLK, CSB, and SDIO signals are typically asynchronous to the detail in Table 13. ADC clock, noise from these signals can degrade converter Table 12. Features Accessible Using the SPI performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the Feature Description AD9286 to prevent these signals from transitioning at the Mode Allows the user to set either power-down mode or standby mode converter inputs during critical sampling periods. Clock Allows the user to access the DCS via the SPI SDIO/PWDN serves a dual function when the SPI interface is Offset Allows the user to digitally adjust the converter not being used. When the pin is strapped to AVDD or ground offset during device power-on, it is associated with a specific function. Test I/O Allows the user to set test modes to have known The mode selection table (see Table 11) describes the strappable data on output bits functions that are supported on the AD9286. Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Table 11. Mode Selection Output Delay Allows the user to vary the DCO delay External Voltage Allows the user to set the voltage reference Pin Voltage Configuration Reference SDIO/PWDN AVDD (default) Chip in full power-down AGND Normal operation OE AVDD Outputs in high impedance AGND (default) Outputs enabled Rev. A | Page 21 of 28 AD9286 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table (see Table 13) has eight bit locations. The memory map is roughly divided into • “Bit is set” is synonymous with “bit is set to Logic 1” or three sections: the chip configuration registers (Address 0x00 “writing Logic 1 for the bit.” to Address 0x02), the device index and transfer registers • “Bit is cleared” is synonymous with “bit is set to Logic 0” or (Address 0x05 and Address 0xFF), and the program registers “writing Logic 0 for the bit.” (Address 0x08 to Address 0x38). Transfer Register Map Table 13 documents the default hexadecimal value for each Address 0x08 to Address 0x38 are shadowed. Writes to these hexadecimal address shown. The column with the heading Bit 7 addresses do not affect part operation until a transfer command (MSB) is the start of the default hexadecimal value given. For is issued by writing 0x01 to Address 0xFF, setting the transfer bit. more information on this function and others, see the AN-877 Setting the transfer bit allows these registers to be updated Application Note, Interfacing to High Speed ADCs via SPI. This internally and simultaneously. The internal update takes place document details the functions controlled by Register 0x00 to when the transfer bit is set, and then the bit autoclears. Register 0xFF. Channel-Specific Registers Open Locations Some channel setup functions can be programmed differently All address and bit locations that are not included in the SPI for each channel. In these cases, channel address locations are map are not currently supported for this device. Unused bits of internally duplicated for each channel. These registers and bits a valid address location should be written with 0s. Writing to these are designated in the memory map register table as local. These locations is required only when part of an address location is local registers and bits can be accessed by setting the appropriate open. If the entire address location is open, it is omitted from the Channel 1 (Bit 0) or Channel 2 (Bit 1) bits in Register 0x05. SPI map (for example, Address 0x13) and should not be written. If both bits are set, the subsequent write affects the registers of Default Values both channels. In a read cycle, set only Channel 1 or Channel 2 After the AD9286 is reset, critical registers are loaded with to read one of the two registers. If both bits are set during an default values. The default values for the registers are given SPI read cycle, the part returns the value for Channel 1. in the memory map register table (see Table 13). Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. A | Page 22 of 28 AD9286 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are configuration mirrored so that LSB- first or MSB- first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID 0x0A Unique chip (global) ID used to differentiate devices; read only 0x02 Chip grade Open Speed grade ID Open 0x40 Unique (global) speed grade 100 = 500 MSPS ID used to differentiate devices; read only Device Index and Transfer Registers 0x05 Device Open ADC 2 ADC 1 0xFF Bits are set to Index A default default determine which on- chip device receives the next write command; default is all devices on the chip 0xFF Transfer Open Transfer 0xFF Synchronous transfer of data from the master shift register to the slave Program Registers (May or may not be indexed by device index) 0x08 Modes Open Internal power-down mode 0x00 Determines (global) various 00: chip run generic 01: full power-down modes 10: reserved of chip 11: reserved operation 0x09 Clock Open Sample Open Clock Duty cycle 0x09 (global) mode boost stabilizer 0: simul- taneous 1: inter- leaved 0x0D Test mode Open Reset Reset Open Output test mode 0x00 When test (local) PN23 gen PN9 gen mode is set, 000: off test data is 001: midscale short placed on 010: +FS short the output 011: −FS short pins in place 100: checkerboard output of normal 101: PN23 sequence data 110: PN9 sequence 111: one-/zero-word toggle 0x0E BIST (local) Open BIST init Open BIST enable 0x00 BIST mode config Rev. A | Page 23 of 28 AD9286 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0F ADC input Open Analog Common- Open 0x00 (global/local) disconnect mode (local) input enable (global) 0x10 Offset (local) Open Offset adjust (twos complement format) 0x00 Device offset trim 0111: +7 0110: +6 … 0001: +1 0000: 0 1111: −1 … 1001: −7 1000: −8 0x14 Output Open Output Open Output Data format select 0x00 Configures mode (local) enable invert the outputs 00: offset binary and the 01: twos complement format of 10: Gray code the data 11: reserved 0x16 Output DCO invert Open 0x00 phase (global) 0x18 Voltage Open Voltage reference and input full-scale adjustment (see Table 14) 0x00 Selects/ reference adjusts V REF (global) 0x24 MISR LSB LSBs of multiple input shift register (MISR) 0x00 MISR least (local) significant byte; read only 0x25 MISR MSB MSBs of multiple input shift register (MISR) 0x00 MISR most (local) significant byte; read only 0x37 Timing Open Fine timing skew 0x00 Determines adjust (local) the clock 0000: 0.0 ps delay that is 0001: 0.075 ps introduced … into the 1111: 1.125 ps sampling path 0x38 Open Coarse timing skew 0x00 Determines the clock 0000: 0.0 ps delay that is 0001: 1.2 ps introduced … into the 1111: 18 ps sampling path Rev. A | Page 24 of 28 AD9286 MEMORY MAP REGISTER DESCRIPTIONS Table 14. V and Input Full Scale (Register 0x18) REF For more information about functions controlled in Register 0x00 V (V) Value REF Full Scale (V) to Register 0xFF, see the AN-877 Application Note, Interfacing 0x14 0.844 1.013 to High Speed ADCs via SPI. 0x15 0.857 1.028 0x16 0.87 1.044 Voltage Reference (Register 0x18) 0x17 0.883 1.060 Bits[7:5]—Reserved 0x18 0.896 1.075 Bits[4:0]—Voltage Reference 0x19 0.909 1.091 0x1A 0.922 1.106 Bits[4:0] scale the internally generated voltage reference and, consequently, the full scale of the analog input. Within this register, 0x1B 0.935 1.122 the reference driver can be configured to be more easily driven 0x1C 0.948 1.138 externally by reducing the capacitive loading. 0x1D 0.961 1.153 0x1E 0.974 1.169 The relationship between the VREF voltage and the input full 0x1F 0.987 1.184 scale is described by Equation 7. See Table 14 for a complete list 0x00 1 1.200 of register settings. 0x01 1.013 1.216 Input_Full_Scale = VREF × 1.2 (7) 0x02 1.026 1.231 0x03 1.039 1.247 0x04 1.052 1.262 0x05 1.065 1.278 0x06 1.078 1.294 0x07 1.091 1.309 0x08 1.104 1.325 0x09 1.117 1.340 0x0A 1.13 1.356 0x0B 1.143 1.372 0x0C 1.156 1.387 0x0D 1.169 1.403 0x0E 1.182 1.418 0x0F 1.195 1.434 0x10 1.208 1.450 0x11 1.221 1.465 0x12 1.234 1.481 0x13 External External × 1.2 Rev. A | Page 25 of 28 AD9286 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting design and layout of the AD9286 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements that are needed for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9286, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V supply (LFCSP), at www.analog.com. for analog (AVDD); use a separate 1.8 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD VCM supply must be used, the AVDD and DRVDD domains must be The VCM pin should be decoupled to ground with a 0.1 μF isolated with a ferrite bead or filter choke and separate decoupling capacitor. capacitors. Several different decoupling capacitors can be used RBIAS to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board (PCB) The AD9286 requires that a 10 kΩ resistor be placed between level and close to the pins of the part, with minimal trace length. the RBIAS pin and ground. This resistor, which sets the master current reference of the ADC core, should have at least a 1% A single PCB ground plane should be sufficient when using the tolerance. AD9286. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance Reference Decoupling is easily achieved. Decouple the VREF pin externally to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic Exposed Paddle Thermal Heat Sink Recommendations capacitor. The exposed paddle (Pin 0) is the only ground connection for the AD9286; therefore, it must be connected to analog SPI Port ground (AGND) on the customer PCB. To achieve the best The SPI port should not be active during periods when the full electrical and thermal performance, mate an exposed (no dynamic performance of the converter is required. Because the solder mask), continuous copper plane on the PCB to the SCLK, CSB, and SDIO signals are typically asynchronous to the AD9286 exposed paddle, Pin 0. ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, The copper plane should have several vias to achieve the it may be necessary to provide buffers between this bus and the lowest possible resistive thermal path for heat dissipation AD9286 to prevent these signals from transitioning at the converter to flow through the bottom of the PCB. Fill or plug these inputs during critical sampling periods. vias with nonconductive epoxy. Rev. A | Page 26 of 28 AD9286 OUTLINE DIMENSIONS 7.10 0.30 0.60 MAX 7.00 SQ 0.23 6.90 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 1 36 PIN 1 INDICATOR 0.50 6.85 REF * 4.70 6.75 SQ EXPOSED 4.60 SQ PAD 6.65 4.50 (BOTTOM VIEW) 25 12 24 13 0.50 0.25 MIN TOP VIEW 0.40 5.50 REF 0.30 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-12) Dimensions shown in millimeters ORDERING GUIDE Package 1 Model Temperature Range Package Description Option AD9286BCPZ-500 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-12 AD9286BCPZRL7-500 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-12 AD9286-500EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 27 of 28 04-22-2010-A AD9286 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09338-0-3/11(A) Rev. A | Page 28 of 28