ANALOG DEVICES AD9284

8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9284 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital SNR: 49.3 dBFS at 200 MHz input at 250 MSPS converter (ADC) that supports simultaneous operation and is SFDR: 65 dBc at 200 MHz input at 250 MSPS optimized for low cost, low power, and ease of use. Each ADC Low power: 314 mW at 250 MSPS operates at up to a 250 MSPS conversion rate with outstanding On-chip reference and track-and-hold dynamic performance. 1.2 V p-p analog input range for each channel The ADC requires a single 1.8 V supply and an encode clock for Differential input with 500 MHz bandwidth full performance operation. No external reference components LVDS-compliant digital output are required for many applications. The digital outputs are LVDS DNL: ±0.2 LSB compatible. Serial port control options The AD9284 is available in a Pb-free, 48-lead LFCSP that is Offset binary, Gray code, or twos complement data format specified over the industrial temperature range of −40°C to +85°C. Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation PRODUCT HIGHLIGHTS Pin-programmable power-down function 1. Integrated Dual 8-Bit, 250 MSPS ADC. Available in 48-lead LFCSP 2. Single 1.8 V Supply Operation with LVDS Outputs. APPLICATIONS 3. Power-Down Option Controlled via a Pin-Programmable Setting. Communications Diversity radio systems I/Q demodulation systems Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber FUNCTIONAL BLOCK DIAGRAM SDIO/ PWDN CSB SCLK OE CLK+ SPI CLK– VIN+A D7+ (MSB), D7– (MSB) ADC D0+ (LSB), D0– (LSB) VIN–A (CHANNEL A) VCM REF DCO+ VREF ×1.5 DCO SELECT CLOCK GENERATION 1.0V DCO– MANAGEMENT V REF VIN–B D7+ (MSB), D7– (MSB) ADC D0+ (LSB), D0– (LSB) (CHANNEL B) VIN+B AD9284 RBIAS AGND AVDD DRVDD DRGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. LVDS LVDS OUTPUT BUFFER OUTPUT BUFFER 09085-001 AD9284 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 13  Applications....................................................................................... 1  RBIAS........................................................................................... 13  General Description ......................................................................... 1  Clock Input Considerations...................................................... 14  Product Highlights ........................................................................... 1  Digital Outputs ........................................................................... 14  Functional Block Diagram .............................................................. 1  Built-In Self-Test (BIST) and Output Test .................................. 15  Revision History ............................................................................... 2  Built-In Self-Test (BIST)............................................................ 15  Specifications..................................................................................... 3  Output Test Modes..................................................................... 15  DC Specifications ......................................................................... 3  Serial Port Interface (SPI).............................................................. 16  AC Specifications.......................................................................... 4  Configuration Using the SPI..................................................... 16  Digital Specifications ................................................................... 5  Hardware Interface..................................................................... 17  Switching Specifications .............................................................. 6  Configuration Without the SPI ................................................ 17  SPI Timing Specifications ........................................................... 6  SPI Accessible Features.............................................................. 17  Absolute Maximum Ratings............................................................ 7  Memory Map .................................................................................. 18  Thermal Resistance ...................................................................... 7  Reading the Memory Map Register Table............................... 18  ESD Caution.................................................................................. 7  Memory Map Register Table..................................................... 19  Pin Configuration and Function Descriptions............................. 8  Memory Map Register Descriptions........................................ 21  Typical Performance Characteristics ........................................... 10  Applications Information .............................................................. 22  Equivalent Circuits ......................................................................... 12  Design Guidelines ...................................................................... 22  Theory of Operation ...................................................................... 13  Outline Dimensions....................................................................... 23  ADC Architecture ...................................................................... 13  Ordering Guide .......................................................................... 23  Analog Input Considerations.................................................... 13  REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD9284 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted. Table 1. 1 Parameter Temperature Min Typ Max Unit RESOLUTION Full 8 Bits DC ACCURACY Differential Nonlinearity Full ±0.2 ±0.4 LSB Integral Nonlinearity Full ±0.1 ±0.3 LSB No Missing Codes Full Guaranteed Offset Error Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±2.5 ±2.8 % FS MATCHING CHARACTERISTICS Offset Error Full 0 ±0.5 ±2.6 % FS Gain Error Full 0 ±0.1 ±0.7 % FS TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±20 ppm/°C ANALOG INPUT Input Span Full 1.2 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 16 kΩ Input Capacitance (Differential) Full 250 fF Full Power Bandwidth Full 700 MHz VOLTAGE REFERENCE Internal Reference Full 0.97 0.98 0.99 V Input Resistance Full 3 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current IAVDD Full 124 128 mA IDRVDD Full 51 54 mA POWER CONSUMPTION 2 Sine Wave Input Full 314 330 mW Power-Down Power Full 0.3 1.7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. 0 | Page 3 of 24 AD9284 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = −1.0 dBFS differential input, unless otherwise noted. Table 2. Parameter Temperature Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz 25°C 49.3 dBFS fIN = 70 MHz 25°C 49.3 dBFS f = 96.6 MHz Full 48.7 49.3 dBFS IN f = 220 MHz 25°C 49.3 dBFS IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) f = 10.3 MHz 25°C 49.2 dBFS IN f = 70 MHz 25°C 49.2 dBFS IN fIN = 96.6 MHz Full 48.5 49.2 dBFS fIN = 220 MHz 25°C 49.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz 25°C 7.9 Bits fIN = 70 MHz 25°C 7.9 Bits fIN = 96.6 MHz Full 7.8 7.9 Bits f = 220 MHz 25°C 7.9 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz 25°C −70 dBc f = 70 MHz 25°C −70 dBc IN f = 96.6 MHz Full −70 −61 dBc IN f = 220 MHz 25°C −65 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 10.3 MHz 25°C 70 dBc IN fIN = 70 MHz 25°C 70 dBc fIN = 96.6 MHz Full 61 69 dBc fIN = 220 MHz 25°C 65 dBc WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz 25°C −71 dBc fIN = 70 MHz 25°C −71 dBc f = 96.6 MHz Full −70 −64 dBc IN f = 220 MHz 25°C −67 dBc IN CROSSTALK Full −80 dBc Rev. 0 | Page 4 of 24 AD9284 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted. Table 3. 1 Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/PECL Internal Common-Mode Bias Full 1.2 V 2 Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS CSB High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −5 −0.4 +5 μA Low Level Input Current Full −80 −63 −50 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF SCLK, SDIO/PWDN, OE High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full 50 57 70 μA Low Level Input Current Full −5 −0.4 +5 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS DRVDD = 1.8 V Differential Output Voltage (V) Full 290 345 400 mV OD Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 Specified for LVDS and LVPECL only. Rev. 0 | Page 5 of 24 AD9284 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 30 250 MHz CLK Period (tCLK) Full 7.4 ns CLK Pulse Width High (tCH) Full 3.7 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3.7 ns DCO Propagation Delay (t) Full 3.7 ns DCO DCO to Data Skew (t) Full −280 −60 +100 ps SKEW Pipeline Delay (Latency) Full 10.5 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms 1 Wake-Up Time Full 500 μs OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Wake-up time is dependent on the value of the decoupling capacitors. SPI TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns t Setup time between CSB and SCLK 2 ns S t Hold time between CSB and SCLK 2 ns H tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input 10 ns to an output relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output 10 ns DIS_SDIO to an input relative to the SCLK rising edge Timing Diagram M – 1 M + 4 M + 5 M M + 3 VIN±A t A M + 1 N – 1 N + 4 M + 2 N + 5 N VIN±B N + 3 N + 1 N + 2 t t CH CLK CLK+ CLK– t DCO DCO+, DCO– CH A, CH B t SKEW DATA CH A, CH B N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7 t PD Figure 2. Output Data Timing Rev. 0 | Page 6 of 24 09085-002 AD9284 ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.3 V THERMAL RESISTANCE to DRGND DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V θJA is specified for the worst-case conditions, that is, a device CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V soldered in a circuit board for surface-mount packages. VIN±A, VIN±B to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V Package Type θ θ Unit JA JC CSB to AGND −0.3 V to DRVDD + 0.3 V 48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W SCLK to AGND −0.3 V to DRVDD + 0.3 V Environmental Storage Temperature Range −65°C to +125°C ESD CAUTION Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. 0 | Page 7 of 24 AD9284 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD 1 36 AVDD PIN 1 AVDD 2 35 AVDD INDICATOR DNC 3 34 CLK+ 33 CLK– DNC 4 RBIAS 5 32 CSB AD9284 DNC 6 31 SDIO/PWDN TOP VIEW DRGND 7 30 SCLK (Not to Scale) DRVDD 8 29 OE D0– (LSB) 9 28 DRGND D0+ (LSB) 10 27 DRVDD D1– 11 26 D7+ (MSB) D1+ 12 25 D7– (MSB) NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Pins 1, 2, 35, 36, 37, 40, 42, AVDD Supply Analog Power Supply (1.8 V Nominal). 44, 45, 48 8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 7, 28 DRGND Ground Digital Output Ground. 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ADC Analog Pins 39 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 46 VIN+B Input Differential Analog Input Pin (+) for Channel B. 47 VIN−B Input Differential Analog Input Pin (−) for Channel B. 43 VREF Input/output Voltage Reference Input/Output. 5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. 41 VCM Output Common-Mode Level Bias Output for Analog Inputs. 34 CLK+ Input ADC Clock Input—True. 33 CLK− Input ADC Clock Input—Complement. Digital Input 29 OE Input Digital Enable (Active Low) to Tristate Output Data Pins. Digital Outputs 26 D7+ (MSB) Output Channel A/Channel B LVDS Output Data 7—True. 25 D7− (MSB) Output Channel A/Channel B LVDS Output Data 7—Complement. 24 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 23 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 22 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 21 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 20 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 19 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. Rev. 0 | Page 8 of 24 D2– 13 48 AVDD D2+ 14 47 VIN–B D3– 15 46 VIN+B D3+ 16 45 AVDD DCO– 17 44 AVDD DCO+ 18 43 VREF 42 AVDD D4– 19 D4+ 20 41 VCM D5– 21 40 AVDD D5+ 22 39 VIN+A D6– 23 38 VIN–A D6+ 24 37 AVDD 09085-003 AD9284 Pin No. Mnemonic Type Description 16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 10 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 9 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 18 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 17 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control Pins 30 SCLK Input SPI Serial Clock. 31 SDIO/PWDN Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). 32 CSB Input SPI Chip Select (Active Low). Do Not Connect 3, 4, 6 DNC N/A Do Not Connect. Do not connect to this pin. Rev. 0 | Page 9 of 24 AD9284 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, unless otherwise noted. 0 0 250MSPS 250MSPS 4.3MHz @ –1dBFS 96.6MHz @ –1dBFS SNR = 48.3dB (49.3dBFS) SNR = 48.3dB (49.3dBFS) –20 –20 ENOB = 7.7 ENOB = 7.7 SFDR = 70.3dBc SFDR = 70.0dBc –40 –40 SECOND HARMONIC SECOND HARMONIC –60 –60 THIRD HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 0 25 50 75 100 125 0 25 50 75 100 125 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Single-Tone FFT with fIN = 4.3 MHz Figure 7. Single-Tone FFT with fIN = 96.6 MHz 0 0 250MSPS 250MSPS 29.2MHz @ –7dBFS 330.3MHz @ –1dBFS 32.2MHz @ –7dBFS SNR = 48.2dB (49.2dBFS) –20 –20 SFDR = 69.6dBc (76.6dBFS) ENOB = 7.6 SFDR = 60.9dBc –40 –40 –60 THIRD HARMONIC SECOND HARMONIC –60 –80 –80 –100 –100 –120 0 25 50 75 100 125 –120 FREQUENCY (MHz) 0 25 50 75 100 125 FREQUENCY (MHz) Figure 5. Single-Tone FFT with f = 220.3 MHz Figure 8. Two-Tone FFT with f = 29.1 MHz and f = 32.1 MHz IN IN1 IN2 80 80 IMD3 (dBFS) 70 70 SFDR (dBFS) 60 60 SFDR (dBFS) SNR (dBFS) 50 50 REFERENCE LINE 40 40 SFDR (dBc) IMD3 (dBc) 30 30 SFDR (dBc) 20 20 SNR (dBc) 10 10 0 0 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 AIN POWER (dBFS) AIN POWER (dBFS) Figure 6. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Rev. 0 | Page 10 of 24 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/SNR (dB) 09085-109 09085-107 09085-108 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/IMD3 (dB) 09085-112 09085-111 09085-110 AD9284 75 50.0 0.15 0.10 70 49.8 0.05 SFDR: SIDE A SFDR: SIDE B 65 49.6 SNRFS: SIDE A 0 60 49.4 SNRFS: SIDE B –0.05 55 49.2 –0.10 50 49.0 –0.15 50 75 100 125 150 175 200 225 250 0 32 64 96 128 160 192 224 256 ENCODE (MSPS) OUTPUT CODE Figure 10. SNRFS/SFDR vs Encode with f = 2.4 MHz IN Figure 12. INL Error with fIN = 4.3 MHz 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 0 32 64 96 128 160 192 224 256 OUTPUT CODE Figure 11. DNL Error with fIN = 4.3 MHz Rev. 0 | Page 11 of 24 SFDR (dBc) DNL ERROR (LSB) SNRFS (dBFS) 09085-115 09085-113 INL ERROR (LSB) 09085-117 AD9284 EQUIVALENT CIRCUITS AVDD DRVDD AVDD AVDD 1.2V DRVDD 10kΩ 10kΩ CLK+ CLK– 350Ω SCLK, OE, AUXCLKEN 30kΩ Figure 13. Clock Inputs Figure 16. SCLK, OE AVDD AVDD VIN+ BUF DRVDD 350Ω 8kΩ V CML BUF 30kΩ ~1.4V AVDD 8kΩ SDIO BUF VIN– CTRL Figure 14. Analog Inputs (V = ~1.4 V) Figure 17. SDIO CML DRVDD DRVDD DRVDD V+ V– DRVDD 30kΩ D7– TO D0– D7+ TO D0+ 350Ω CSB V– V+ Figure 15. CSB Figure 18. LVDS Output Driver Rev. 0 | Page 12 of 24 09085-020 09085-021 09085-019 09085-024 09085-023 09085-022 AD9284 THEORY OF OPERATION The AD9284 is a pipeline-type converter. The input buffers are Differential Input Configurations differential, and both sets of inputs are internally biased. This Optimum performance is achieved when driving the AD9284 allows the use of ac or dc input modes. A sample-and-hold in a differential input configuration. For baseband applications, amplifier is incorporated into the first stage of the multistage the ADA4937-1 differential driver provides excellent performance pipeline converter core. The output staging block aligns the and a flexible interface to the ADC (see Figure 19). The output data, carries out error correction for the pipeline stages, and common-mode voltage of the AD9284 is easily set to 1.4 V, and feeds that data to the output buffers. The two ADC channels the driver can be configured in a Sallen-Key filter topology to are sampled simultaneously through a single encoding clock. provide band limiting of the input signal. All user-selected options are programmed through dedicated 200Ω digital input pins or a serial port interface (SPI). 1.2V p-p 61.9Ω 33Ω 200Ω AD9284 – ADC ARCHITECTURE 4.7pF + ADA4937-1 Each channel of the AD9284 consists of a differential input VIN 227.4Ω 0.1µF – buffer followed by a sample-and-hold amplifier (SHA). The + 33Ω SHA is followed by a pipeline switched-capacitor ADC. The 200Ω VCM quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. The pipelined Figure 19. Differential Input Configuration Using the ADA4937-1 architecture permits the first stage to operate on a new input The AD9284 can also be driven passively with a differential sample, whereas the remaining stages operate on preceding transformer-coupled input (see Figure 20). To bias the analog samples. input, the VCM voltage can be connected to the center tap of Each stage of the pipeline, excluding the last, consists of a low the secondary winding of the transformer. resolution flash ADC connected to a switched-capacitor DAC 33Ω and interstage residue amplifier (MDAC). The residue amplifier AD9284 1.2V p-p 49.9Ω magnifies the difference between the reconstructed DAC output + 4.7pF and the flash input for the next stage in the pipeline. One bit of VIN – redundancy is used in each stage to facilitate digital correction 33Ω of flash errors. The last stage consists of a flash ADC. VCM The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended mode. The output 0.1µF staging block aligns the data, carries out error correction, and passes the data to the output buffers. The output buffers are Figure 20. Differential Transformer-Coupled Configuration powered from a separate supply, allowing adjustment of the The signal characteristics must be considered when selecting a output voltage swing. During power-down, the output buffers transformer. Most RF transformers saturate at frequencies below enter a high impedance state. a few megahertz (MHz). Excessive signal power can also cause ANALOG INPUT CONSIDERATIONS core saturation, which leads to distortion. The analog inputs of the AD9284 are differentially buffered. VOLTAGE REFERENCE For best dynamic performance, the source impedances driving An internal differential voltage reference creates positive and VIN+A, VIN+B, VIN−A, and VIN−B should be matched such negative reference voltages that define the 1.2 V p-p fixed span that common-mode settling errors are symmetrical. The analog of the ADC core. This internal voltage reference can be adjusted inputs are optimized to provide superior wideband performance by means of SPI control. It can also be driven externally with and must be driven differentially. SNR and SINAD performance an off-chip stable reference. See the Memory Map Register degrades significantly if the analog inputs are driven with a single- Descriptions section for more details. ended signal. RBIAS A wideband transformer, such as Mini-Circuits® ADT1-1WT, The AD9284 requires the user to place a 10 kΩ resistor between can provide the differential analog inputs for applications that the RBIAS pin and ground. This resistor, which is used to set require a single-ended-to-differential conversion. Both analog the master current reference of the ADC core, should have a 1% inputs are self-biased by an on-chip resistor divider to tolerance. a nominal 1.4 V. Rev. 0 | Page 13 of 24 09085-026 09085-025 AD9284 If a low jitter clock source is not available, another option is to CLOCK INPUT CONSIDERATIONS ac couple a differential PECL signal to the sample clock input For optimum performance, clock the AD9284 sample clock inputs, pins, as shown in Figure 23. The AD9510/AD9511/AD9512/ CLK+ and CLK− with a differential signal. The signal is typically AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer ac-coupled into the CLK+ and CLK− pins via a transformer or excellent jitter performance. capacitors. Clock Input Options 0.1µF 0.1µF CLOCK CLK+ The AD9284 has a very flexible clock input structure. The clock INPUT input can be an LVDS, LVPECL, or sine wave signal. Each configu- AD951x 100Ω ADC PECL DRIVER 0.1µF ration that is described in this section applies to CLK+ and CLK−. 0.1µF CLOCK CLK– INPUT Figure 21 and Figure 22 show the two preferred methods for 50kΩ 50kΩ 240Ω 240Ω clocking the AD9284. A low jitter clock source is converted from a single-ended signal to a differential signal using either Figure 23. Differential PECL Sample Clock an RF transformer or an RF balun. The back-to-back Schottky A third option is to ac couple a differential LVDS signal to the diodes across the transformer/balun secondary limit clock sample clock input pins, as shown in Figure 24. The AD9510/ excursions into the AD9284 to approximately 0.8 V p-p AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 differential. clock drivers offer excellent jitter performance. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9284, while 0.1µF 0.1µF CLOCK preserving the fast rise and fall times of the signal that are CLK+ INPUT critical to low jitter performance. AD951x 100Ω ADC LVDS DRIVER 0.1µF 0.1µF ® CLOCK Mini-Circuits CLK– ADT1-1WT, 1:1 Z INPUT 50kΩ 50kΩ 0.1µF XFMR CLOCK CLK+ INPUT 100Ω 0.1µF 50Ω ADC Figure 24. Differential LVDS Sample Clock CLK– 0.1µF DIGITAL OUTPUTS SCHOTTKY 0.1µF DIODES: HSM2822 Digital Output Enable Function (OE) Figure 21. Transformer-Coupled Differential Clock The AD9284 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OE pin. When OE is set to logic level high, the output drivers for both data buses are placed into a high impedance state. 1nF CLOCK CLK+ INPUT 0.1µF 50Ω ADC 1nF CLK– 0.1µF SCHOTTKY DIODES: HSM2822 Figure 22. Balun-Coupled Differential Clock Rev. 0 | Page 14 of 24 09085-028 09085-027 09085-030 09085-029 AD9284 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9284 includes a built-in self-test feature that is designed Writing a value of 0x05 to Register 0x0E runs the BIST. This to enable verification of the integrity of each channel, as well as enables Bit 0 (BIST enable) of Register 0x0E and resets the PN facilitate board level debugging. A built-in self-test (BIST) feature sequence generator, Bit 2 (BIST init) of Register 0x0E. At the that verifies the integrity of the digital datapath of the AD9284 completion of the BIST, Bit 0 of Register 0x0E is automatically is included. Various output test options are also provided to cleared. The PN sequence can be continued from its last value place predictable values on the outputs of the AD9284. by writing a 0 to Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal BUILT-IN SELF-TEST (BIST) the predetermined value at the end of the test. At that point, the The BIST is a thorough test of the digital portion of the selected user must rely on verifying the output data. AD9284 signal path. Perform the BIST test after a reset to ensure OUTPUT TEST MODES that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through The output test options are described in Table 12 at Address 0x0D. the digital datapath of both channels, starting at the ADC block When an output test mode is enabled, the analog section of the output. At the datapath output, CRC logic calculates a signature ADC is disconnected from the digital back-end blocks, and the from the data. The BIST sequence runs for 512 cycles and then test pattern is run through the output formatting block. Some stops. When the test is completed, the BIST compares the signature test patterns are subject to output formatting, and some are not. results with a predetermined value. If the signatures match, the The PN generators from the PN sequence tests can be reset by BIST sets Bit 0 of Register 0x0E, signifying that the test passed. setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs with or without an analog signal (if present, the analog signal are connected during this test, so the PN sequence can be observed is ignored), but they do require an encode clock. For more as it runs. information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 15 of 24 AD9284 SERIAL PORT INTERFACE (SPI) The AD9284 serial port interface (SPI) allows the user to configure The falling edge of CSB, in conjunction with the rising edge of the converter for specific functions or operations through a SCLK, determines the start of the framing. An example of the structured register space provided inside the ADC. The SPI serial timing and its definitions can be found in Figure 25. gives the user added flexibility and customization, depending Other modes involving CSB are available. The CSB pin can be on the application. Addresses are accessed via the serial port held low indefinitely, which permanently enables the device; and can be written to or read from via the port. Memory is this is called streaming. CSB can stall high between bytes to organized into bytes that can be further divided into fields, allow for additional external timing. When the CSB pin is tied which are documented in the Memory Map section. For detailed high, SPI functions are placed in high impedance mode. This operational information, see the AN-877 Application Note, mode turns on any SPI pin secondary functions. Interfacing to High Speed ADCs via SPI. During the instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: SCLK, SDIO, and CSB by the W0 and W1 bits, as shown in Figure 25. (see Table 9). SCLK (a serial clock) is used to synchronize the All data is composed of 8-bit words. The first bit of the first byte read and write data presented from and to the ADC. SDIO in a multibyte serial data transfer frame indicates whether a read (serial data input/output) is a dual-purpose pin that allows data command or a write command is issued. This allows the serial to be sent to and read from the internal ADC memory map data input/output (SDIO) pin to change direction from an input registers. CSB (chip select bar) is an active low control that to an output at the appropriate point in the serial frame. enables or disables the read and write cycles. In addition to word length, the instruction phase determines Table 9. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read Pin Function the contents of the on-chip memory. If the instruction is a readback SCLK Serial clock. A serial shift clock input that is used to synchronize serial interface reads and writes. operation, the serial data input/output (SDIO) pin changes SDIO Serial data input/output. A dual-purpose pin that direction, from an input to an output, at the appropriate point in typically serves as an input or an output, depending the serial frame. on the instruction being sent and the relative position Data can be sent in MSB-first mode or in LSB-first mode. MSB in the timing frame. first is the default on power-up and can be changed via the SPI CSB Chip select bar. An active low control that gates the read and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 25. Serial Port Interface Timing Diagram Rev. 0 | Page 16 of 24 09085-004 AD9284 HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 9 constitute the physical interface In applications that do not interface to the SPI control registers, between the programming device of the user and the serial port the SDIO/PWDN pin serves as a standalone, CMOS-compatible of the AD9284. The SCLK and CSB pins function as inputs control pin. When the device is powered up, it is assumed that when using the SPI interface. The SDIO pin is bidirectional, the user intends to use the SDIO, SCLK, and CSB pins as static functioning as an input during write phases and as an output control lines for the output enable and power-down feature control. during readback. In this mode, connecting the CSB chip select to AVDD disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration SPI ACCESSIBLE FEATURES is described in detail in the AN-812 Application Note, Micro- Table 11 provides a brief description of the general features that controller-Based Serial Port Interface (SPI) Boot Circuit. are accessible via the SPI. These features are described in detail The SPI port should not be active during periods when the full in the AN-877 Application Note, Interfacing to High Speed ADCs dynamic performance of the converter is required. Because the via SPI. The AD9284 part-specific features are described in SCLK, CSB, and SDIO signals are typically asynchronous to the detail in Table 12. ADC clock, noise from these signals can degrade converter Table 11. Features Accessible Using the SPI performance. If the on-board SPI bus is used for other devices, Feature Description it may be necessary to provide buffers between this bus and the Mode Allows the user to set either power-down mode AD9284 to prevent these signals from transitioning at the converter or standby mode inputs during critical sampling periods. Clock Allows the user to access the DCS via the SPI SDIO/PWDN serves a dual function when the SPI interface is Offset Allows the user to digitally adjust the converter not being used. When the pin is strapped to AVDD or ground offset during device power-on, it is associated with a specific function. Test I/O Allows the user to set test modes to have known The mode selection table (see Table 10) describes the strappable data on output bits functions that are supported on the AD9284. Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Table 10. Mode Selection Output Delay Allows the user to vary the DCO delay Pin External Voltage Configuration Voltage Allows the user to set the voltage reference SDIO/PWDN AVDD (default) Chip in full power-down Reference AGND Normal operation OE AVDD Outputs in high impedance AGND (default) Outputs enabled Rev. 0 | Page 17 of 24 AD9284 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table (see Table 12) has eight bit locations. The memory map is roughly divided into • “Bit is set” is synonymous with “bit is set to Logic 1” or three sections: the chip configuration registers (Address 0x00 “writing Logic 1 for the bit.” to Address 0x02), the device index and transfer registers • “Bit is cleared” is synonymous with “bit is set to Logic 0” or (Address 0x05 and Address 0xFF), and the program registers “writing Logic 0 for the bit.” (Address 0x08 to Address 0x25). Transfer Register Map Table 12 documents the default hexadecimal value for each Address 0x08 to Address 0x38 are shadowed. Writes to these hexadecimal address shown. The column with the heading Bit 7 addresses do not affect part operation until a transfer command (MSB) is the start of the default hexadecimal value given. For is issued by writing 0x01 to Address 0xFF, setting the transfer bit. more information on this function and others, see the AN-877 Setting the transfer bit allows these registers to be updated Application Note, Interfacing to High Speed ADCs via SPI. This internally and simultaneously. The internal update takes place document details the functions controlled by Register 0x00 to when the transfer bit is set, and then the bit autoclears. Register 0xFF. Channel-Specific Registers Open Locations Some channel setup functions can be programmed differently All address and bit locations that are not included in the SPI for each channel. In these cases, channel address locations are map are not currently supported for this device. Unused bits of internally duplicated for each channel. These registers and bits a valid address location should be written with 0s. Writing to these are designated in the memory map register table as local. These locations is required only when part of an address location is local registers and bits can be accessed by setting the appropriate open. If the entire address location is open, it is omitted from the Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. SPI map (for example, Address 0x13) and should not be written. If both bits are set, the subsequent write affects the registers of Default Values both channels. In a read cycle, set only Channel A or Channel B After the AD9284 is reset, critical registers are loaded with to read one of the two registers. If both bits are set during a SPI default values. The default values for the registers are given read cycle, the part returns the value for Channel A. Registers in the memory map register table (see Table 12). and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 18 of 24 AD9284 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 12 are not currently supported for this device. Table 12. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are configuration mirrored so that LSB-first or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID 0x0A Unique chip (global) ID used to differentiate devices; read only 0x02 Chip grade Open Speed grade ID Open 0x00 Unique speed (global) grade ID is 000 = 250 MSPS used to differentiate devices; read only Device Index and Transfer Registers 0x05 Device Open ADC B ADC A 0xFF Bits are set to Index A default default determine which on-chip device receives the next write command; default is all devices on the chip 0xFF Transfer Open Transfer 0xFF Synchronous transfer of data from the master shift register to the slave Program Registers (May or may not be indexed by device index) 0x08 Modes Open Internal power-down mode 0x00 Determines (global) various 00: chip run generic 01: full power-down modes 10: reserved of chip 11: reserved operation 0x09 Clock Open Clock Duty cycle 0x01 (global) boost stabilizer 0x0D Test mode Open Reset Reset Open Output test mode 0x00 When test (local) PN23 gen PN9 gen mode is set, 000: off test data is 001: midscale short placed on the 010: +FS short output pins 011: −FS short in place of 100: checkerboard output normal data 101: PN23 sequence 110: PN9 sequence 111: one-/zero-word toggle 0x0E BIST (local) Open BIST init Open BIST enable 0x00 BIST mode config Rev. 0 | Page 19 of 24 AD9284 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0F ADC input Open Analog Common-Open 0x00 (global/local) disconnect mode (local) input enable (global) 0x10 Offset (local) Open Offset adjust (twos complement format) 0x00 Device offset trim 0111: +7 0110: +6 … 0001: +1 0000: 0 1111: −1 … 1001: −7 1000: −8 0x14 Output Open Output Open Output Data format select 0x00 Configures mode (local) enable invert the outputs 00: offset binary and the 01: twos complement format of 10: Gray code the data 11: reserved 0x16 Output DCO invert Open 0x00 phase (global) 0x18 Voltage Open Voltage reference and input full-scale adjustment (see Table 13) 0x00 Selects/ reference adjusts V REF (global) 0x24 MISR LSB LSBs of multiple input shift register (MISR) 0x00 MISR least (local) significant byte; read only 0x25 MISR MSB MSBs of multiple input shift register (MISR) 0x00 MISR most (local) significant byte; read only Rev. 0 | Page 20 of 24 AD9284 MEMORY MAP REGISTER DESCRIPTIONS Table 13. V and Input Full Scale (Register 0x18) REF For more information about functions controlled in Register 0x00 Value V (V) Full Scale (V) REF to Register 0xFF, see the AN-877 Application Note, Interfacing 0x14 0.844 1.013 to High Speed ADCs via SPI. 0x15 0.857 1.028 0x16 0.87 1.044 Voltage Reference (Register 0x18) 0x17 0.883 1.060 Bits[7:5]—Reserved 0x18 0.896 1.075 Bits[4:0]—Voltage Reference 0x19 0.909 1.091 0x1A 0.922 1.106 Bits[4:0] scale the internally generated voltage reference and, 0x1B 0.935 1.122 consequently, the full scale of the analog input. Within this register, 0x1C 0.948 1.138 the reference driver can be configured to be more easily driven 0x1D 0.961 1.153 externally by reducing the capacitive loading. 0x1E 0.974 1.169 The relationship between the VREF voltage and the input full scale 0x1F 0.987 1.184 is described by Equation 1. See Table 13 for a complete list of 0x00 1 1.200 register settings. 0x01 1.013 1.216 Input_Full_Scale = VREF × 1.2 (1) 0x02 1.026 1.231 0x03 1.039 1.247 0x04 1.052 1.262 0x05 1.065 1.278 0x06 1.078 1.294 0x07 1.091 1.309 0x08 1.104 1.325 0x09 1.117 1.340 0x0A 1.13 1.356 0x0B 1.143 1.372 0x0C 1.156 1.387 0x0D 1.169 1.403 0x0E 1.182 1.418 0x0F 1.195 1.434 0x10 1.208 1.450 0x11 1.221 1.465 0x12 1.234 1.481 0x13 External External x 1.2 Rev. 0 | Page 21 of 24 AD9284 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting design and layout of the AD9284 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements that are needed for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9284, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V (LFCSP), at www.analog.com. supply for analog (AVDD); use a separate 1.8 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and VCM DRVDD supply must be used, the AVDD and DRVDD domains The VCM pin should be decoupled to ground with a 0.1 μF must be isolated with a ferrite bead or filter choke and separate capacitor. decoupling capacitors. Several different decoupling capacitors RBIAS can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board The AD9284 requires that a 10 kΩ resistor be placed between (PCB) level and close to the pins of the part, with minimal the RBIAS pin and ground. This resistor, which sets the master trace length. current reference of the ADC core, should have at least a 1% tolerance. A single PCB ground plane should be sufficient when using the AD9284. With proper decoupling and smart partitioning of the Reference Decoupling PCB analog, digital, and clock sections, optimum performance Decouple the VREF pin externally to ground with a low ESR, is easily achieved. 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection SPI Port for the AD9284; therefore, it must be connected to analog The SPI port should not be active during periods when the full ground (AGND) on the customer PCB. To achieve the best dynamic performance of the converter is required. Because the electrical and thermal performance, mate an exposed (no SCLK, CSB, and SDIO signals are typically asynchronous to the solder mask), continuous copper plane on the PCB to the ADC clock, noise from these signals can degrade converter AD9284 exposed paddle, Pin 0. performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the The copper plane should have several vias to achieve the AD9284 to prevent these signals from transitioning at the converter lowest possible resistive thermal path for heat dissipation to inputs during critical sampling periods. flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. Rev. 0 | Page 22 of 24 AD9284 OUTLINE DIMENSIONS 7.10 0.30 7.00 SQ 0.60 MAX 0.23 6.90 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 1 36 PIN 1 INDICATOR 0.50 6.85 REF * 4.70 6.75 SQ EXPOSED 4.60 SQ PAD 6.65 4.50 (BOTTOM VIEW) 25 12 24 13 0.50 0.25 MIN TOP VIEW 0.40 5.50 REF 0.30 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-12) Dimensions shown in millimeters ORDERING GUIDE Temperature Package 1 Model Range Package Description Option AD9284BCPZ-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-12 AD9284BCPZRL7-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-12 AD9284-250EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 04-22-2010-A AD9284 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09085-0-1/11(0) Rev. 0 | Page 24 of 24