ANALOG DEVICES AD9281

Dual Channel 8-Bit a Resolution CMOS ADC AD9281 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual Matching ADC AVDD AVSS CLOCK DVDD DVSS Low Power Dissipation: 225 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V IINA I SLEEP Differential Nonlinearity Error: 0.1 LSB "I" ADC AD9281 REGISTER IINB On-Chip Analog Input Buffers SELECT REFERENCE IREFB On-Chip Reference BUFFER IREFT Signal-to-Noise Ratio: 49.2 dB THREE- QREFB ASYNCHRONOUS STATE DATA Over Seven Effective Bits QREFT MULTIPLEXER OUTPUT 8 BITS Spurious-Free Dynamic Range: –65 dB BUFFER VREF 1V No Missing Codes Guaranteed REFSENSE CHIP 28-Lead SSOP SELECT QINB Q "Q" ADC REGISTER QINA PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9281 is a complete dual channel, 28 MSPS, 8-bit 1. Dual 8-Bit, 28 MSPS ADC CMOS ADC. The AD9281 is optimized specifically for applica- A pair of high performance 28 MSPS ADCs that are opti- tions where close matching between two ADCs is required (e.g., mized for spurious free dynamic performance are provided for I/Q channels in communications applications). The 28 MHz encoding of I and Q or diversity channel information. sampling rate and wide input bandwidth will cover both narrow- 2. Low Power band and spread-spectrum channels. The AD9281 integrates Complete CMOS Dual ADC function consumes a low two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal 225 mW on a single supply (on 3 V supply). The AD9281 voltage reference and multiplexed digital output buffers. operates on supply voltages from 2.7 V to 5.5 V. Each ADC incorporates a simultaneous sampling sample-and- 3. On-Chip Voltage Reference hold amplifier at its input. The analog inputs are buffered; no The AD9281 includes an on-chip compensated bandgap external input buffer op amp will be required in most applica- voltage reference pin programmable for 1 V or 2 V. tions. The ADCs are implemented using a multistage pipeline 4. On-chip analog input buffers eliminate the need for external architecture that offers accurate performance and guarantees no op amps in most applications. missing codes. The outputs of the ADCs are ported to a multi- plexed digital output buffer. 5. Single 8-Bit Digital Output Bus The AD9281 ADC outputs are interleaved onto a single The AD9281 is manufactured on an advanced low cost CMOS output bus saving board space and digital pin count. process, operates from a single supply from 2.7 V to 5.5 V, and consumes 225 mW of power (on 3 V supply). The AD9281 6. Small Package input structure accepts either single-ended or differential signals, The AD9281 offers the complete integrated function in a providing excellent dynamic performance up to and beyond compact 28-lead SSOP package. 14 MHz Nyquist input frequencies. 7. Product Family The AD9281 dual ADC is pin compatible with a dual 10-bit ADC (AD9201). REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: (AVDD = +3 V, DVDD = +3 V, F = 28 MSPS, VREF = 2 V, INB = 0.5 V, T to T SAMPLE MIN MAX AD9281–SPECIFICATIONS unless otherwise noted) Parameter Symbol Min Typ Max Units Condition RESOLUTION 8 Bits CONVERSION RATE F 28 MHz (32 MHz at +25°C) S DC ACCURACY Differential Nonlinearity DNL ±0.1 LSB REFT = 1.0 V, REFB = 0.0 V Integral Nonlinearity INL ±0.25 LSB 1 Differential Nonlinearity (SE) DNL ±0.2 ±1.0 LSB REFT = 1.0 V, REFB = 0.0 V 1 Integral Nonlinearity (SE) INL ±0.3 ±1.5 LSB Zero-Scale Error, Offset Error E ±1 ±3.2 % FS ZS Full-Scale Error, Gain Error E ±1.2 ±5.4 % FS FS Gain Match ±0.2 LSB Offset Match ±1.2 LSB ANALOG INPUT Input Voltage Range AIN –0.5 AVDD/2 V Input Capacitance C 2pF IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Aperture Delay Match 2 ps Input Bandwidth (–3 dB) BW Small Signal (–20 dB) 240 MHz Full Power (0 dB) 245 MHz INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) ±10 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Output Voltage Tolerance (2 V Mode) ±15 mV Load Regulation (1 V Mode) VREF ±10 ±35 mV 1 mA Load Current Load Regulation (2 V Mode) ±15 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DVDD 2.7 3 5.5 V Supply Current I 75 mA AVDD I 0.1 mA DVDD Power Consumption P 225 260 mW D Power-Down 16 mW STBY = AVDD, Clock Low Power Supply Rejection PSR 0.15 0.75 % FS 2 DYNAMIC PERFORMANCE Signal-to-Noise and Distortion SINAD f = 3.58 MHz 46.4 49.1 dB f = 14 MHz 48 dB Signal-to-Noise SNR f = 3.58 MHz 47.8 49.2 dB f = 14 MHz 48.5 dB Total Harmonic Distortion THD f = 3.58 MHz –67.5 –49.5 dB f = 14 MHz –60 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 49.6 65 dB f = 14 MHz 56 dB 3 Two-Tone Intermodulation Distortion IMD –58 dB f = 44.9 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.08 % F = 14.3 MHz S Crosstalk Rejection –62 dB REV. F –2– AD9281 Parameter Symbol Min Typ Max Units Condition 1 DYNAMIC PERFORMANCE (SE) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 47.2 dB Signal-to-Noise SNR f = 3.58 MHz 48 dB Total Harmonic Distortion THD f = 3.58 MHz –55 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –58 dB DIGITAL INPUTS High Input Voltage V 2.4 V IH Low Input Voltage V 0.3 V IL DC Leakage Current I ±6mA IN Input Capacitance C 2pF IN LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (I = 50 mA) V 2.88 V OH OH Low Level Output Voltage (I = 1.5 mA) V 0.095 V OL OL LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (I = 50 mA) V 4.5 V OH OH Low Level Output Voltage (I = 1.5 mA) V 0.4 V OL OL Data Valid Delay t 11 ns OD MUX Select Delay t 7ns MD Data Enable Delay t 13 ns C = 20 pF. Output Level to ED L 90% of Final Value Data High-Z Delay t 13 ns DHZ CLOCKING Clock Pulsewidth High t 16.9 ns CH Clock Pulsewidth Low t 16.9 ns CL Pipeline Latency 3.0 Cycles NOTES 1 SE is single ended input, REFT = 1.5 V, REFB = –0.5 V. 2 AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V. 3 IMD referred to larger of two input signals. Specifications subject to change without notice. t OD CLOCK INPUT ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE #1 #2 #3 #4 #5 SELECT I CHANNEL Q CHANNEL t MD INPUT OUTPUT ENABLED OUTPUT ENABLED SAMPLE #1-1 SAMPLE #1 SAMPLE #2 Q CHANNEL Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-3 SAMPLE #1-2 DATA Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-1 SAMPLE #1 I CHANNEL I CHANNEL OUTPUT OUTPUT Figure 1. ADC Timing REV. F –3– AD9281 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS With Pin Respect No. Name Description Parameter to Min Max Units 1 DVSS Digital Ground AVDD AVSS –0.3 +6.5 V 2 DVDD Digital Supply DVDD DVSS –0.3 +6.5 V 3 AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V 4 CLK AVSS –0.3 AVDD + 0.3 V 5 D0 Bit 0 (LSB) Digital Outputs DVSS –0.3 DVDD + 0.3 V 6 D1 Bit 1 AINA, AINB AVSS –1.0 AVDD + 0.3 V 7 D2 Bit 2 VREF AVSS –0.3 AVDD + 0.3 V 8 D3 Bit 3 REFSENSE AVSS –0.3 AVDD + 0.3 V 9 D4 Bit 4 REFT, REFB AVSS –0.3 AVDD + 0.3 V Junction Temperature +150 °C 10 D5 Bit 5 Storage Temperature –65 +150 °C 11 D6 Bit 6 Lead Temperature 12 D7 Bit 7 (MSB) 10 sec +300 °C 13 SELECT Hi I Channel Out, Lo Q Channel Out *Stresses above those listed under Absolute Maximum Ratings may cause perma- 14 CLOCK Clock nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 15 SLEEP Hi Power Down, Lo Normal Operation sections of this specification is not implied. Exposure to absolute maximum ratings 16 INA-I I Channel, A Input for extended periods may effect device reliability. 17 INB-I I Channel, B Input 18 REFT-I Top Reference Decoupling, I Channel 19 REFB-I Bottom Reference Decoupling, I Channel 20 AVSS Analog Ground 21 REFSENSE Reference Select 22 VREF Internal Reference Output 23 AVDD Analog Supply 24 REFB-Q Bottom Reference Decoupling, Q Channel 25 REFT-Q Top Reference Decoupling, Q Channel PIN CONFIGURATION 26 INB-Q Q Channel B Input 27 INA-Q Q Channel A Input 28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation DVSS CHIP-SELECT DVDD INA-Q INB-Q REFT-Q DEFINITIONS OF SPECIFICATIONS REFB-Q (LSB) D0 AD9281 INTEGRAL NONLINEARITY (INL) D1 AVDD TOP VIEW Integral nonlinearity refers to the deviation of each individual (Not to Scale) D2 VREF code from a line drawn from “zero” through “full scale.” The REFSENSE D3 point used as “zero” occurs 1/2 LSB before the first code transi- D4 AVSS tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last D5 REFB-I code transition. The deviation is measured from the center of REFT-I D6 each particular code to the true straight line. (MSB) D7 INB-I SELECT INA-I DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CLOCK SLEEP CODES) NC = NO CONNECT An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9281 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. F –4– AD9281 AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS AVSS a. D0–D9 b. Three-State Standby c. CLK AVDD AVDD AVDD AVDD AVDD REFBS IN AVSS AVDD AVSS AVSS REFBF AVSS AVSS AVSS d. INA, INB e. Reference f. REFSENSE g. VREF Figure 2. Equivalent Circuits scale. Gain error is the deviation of the actual difference be- OFFSET ERROR tween first and last code transitions and the ideal difference The first transition should occur at a level 1 LSB above “zero.” between the first and last code transitions. Offset is defined as the deviation of the actual first code transi- tion from that point. GAIN MATCH The change in gain error between I and Q channels. OFFSET MATCH The change in offset error between I and Q channels. PIPELINE DELAY (LATENCY) The number of clock cycles between conversion initiation and EFFECTIVE NUMBER OF BITS (ENOB) the associated output data being made available. New output For a sine wave, SINAD can be expressed in terms of the num- data is provided every rising clock edge. ber of bits. Using the following formula, N = (SINAD – 1.76)/6.02 MUX SELECT DELAY It is possible to get a measure of performance expressed as N, The delay between the change in SELECT pin data level and the effective number of bits. valid data on output pins. Thus, effective number of bits for a device for sine wave inputs POWER SUPPLY REJECTION at a given input frequency can be calculated directly from its The specification shows the maximum change in full scale from measured SINAD. the value with the supply at the minimum limit to the value with the supply at its maximum limit. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- APERTURE JITTER ponents to the rms value of the measured input signal and Aperture jitter is the variation in aperture delay for successive is expressed as a percentage or in decibels. samples and is manifested as noise on the input to the A/D. SIGNAL-TO-NOISE RATIO (SNR) APERTURE DELAY SNR is the ratio of the rms value of the measured input signal Aperture delay is a measure of the Sample-and-Hold Amplifier to the rms sum of all other spectral components below the (SHA) performance and is measured from the rising edge of the Nyquist frequency, excluding the first six harmonics and dc. clock input to when the input signal is held for conversion. The value for SNR is expressed in decibels. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) SPURIOUS FREE DYNAMIC RANGE (SFDR) RATIO The difference in dB between the rms amplitude of the input S/N+D is the ratio of the rms value of the measured input sig- signal and the peak spurious signal. nal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. GAIN ERROR The value for S/N+D is expressed in decibels. The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full REV. F –5– AD9281–Typical Characteristic Curves (AVDD = +3 V, DVDD = +3 V, F = 28 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted) S 1 55 –0.5dB 50 45 –6dB 0 40 35 –20dB 30 –1 25 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 1.0E+05 1.0E+06 1.0E+07 1.0E+08 CODE OFFSET INPUT FREQUENCY – Hz Figure 3. Typical INL Figure 6. SNR vs. Input Frequency 1 55 –0.5dB 50 45 –6dB 0 40 35 –20dB 30 –1 25 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 1.0E+05 1.0E+06 1.0E+07 1.0E+08 CODE OFFSET INPUT FREQUENCY – Hz Figure 4. Typical DNL Figure 7. SINAD vs. Input Frequency 1.00 –30 0.80 –35 0.60 –20dB –40 0.40 –45 0.20 0.00 –50 –0.20 –55 –6dB –0.40 –60 –0.60 –65 –0.80 –0.5dB –1.00 –70 –1.0 –0.5 0 0.5 1.0 1.5 2.0 1.0E+05 1.0E+06 1.0E+07 1.0E+08 INPUT VOLTAGE – Volts INPUT FREQUENCY – Hz Figure 5. Input Bias Current vs. Input Voltage Figure 8. THD vs. Input Frequency REV. F –6– I – nA B LSB LSB THD – dB SNR – dB SNR – dB AD9281 1.20E+07 70 65 10000000 1.00E+07 60 55 8.00E+06 50 6.00E+06 45 40 4.00E+06 35 30 2.00E+06 25 12050 800 0.00E+00 20 N–1 N N+1 1.00E+06 1.00E+07 1.00E+08 CODE CLOCK FREQUENCY – Hz Figure 9. THD vs. Clock Frequency Figure 12. Grounded Input Histogram 1.013 0 –3 1.012 –6 –9 1.011 –12 –15 1.010 –18 –21 1.009 –24 1.008 –27 –40 –20 020 40 60 80 100 1.00E+06 1.00E+07 1.00E+08 1.00E+09 TEMPERATURE – 8C INPUT FREQUENCY – Hz Figure 10. Voltage Reference Error vs. Temperature Figure 13. Full Power Bandwidth 240 50 235 –0.5dB 230 45 225 –6dB 220 40 215 210 35 205 200 30 195 –20dB 190 185 25 034 8 1216 20 24282 1.00E+05 1.00E+06 1.00E+07 1.00E+08 CLOCK FREQUENCY – MHz INPUT FREQUENCY – Hz Figure 11. Power Consumption vs. Clock Frequency Figure 14. SNR vs. Input Frequency (Single-Ended) REV. F –7– V – Volts REF POWER CONSUMPTION – mW THD – dB HITS AMPLITUDE – dB SNR – dB AD9281 10.0 converter to readily accommodate either single-ended or differ- FUND 0.0 ential input signals. This differential structure makes the part capable of accommodating a wide range of input signals. –10.0 –20.0 The AD9281 also includes an on-chip bandgap reference and –30.0 reference buffer. The reference buffer shifts the ground-referred –40.0 reference to levels more suitable for use by the internal circuits of the converter. Both converters share the same reference and –50.0 reference buffer. This scheme provides for the best possible gain –60.0 5TH match between the converters while simultaneously minimizing 6TH 2ND 3RD –70.0 7TH 9TH 4TH the channel-to-channel crosstalk. 8TH –80.0 Each A/D converter has its own output latch, which updates on –90.0 the rising edge of the input clock. A logic multiplexer, con- –100.0 trolled through the SELECT pin, determines which channel is –110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6 passed to the digital output pins. The output drivers have their own supply, allowing the part to be interfaced to a variety of Figure 15a. Simultaneous Operation of I and Q Channels logic families. The outputs can be placed in a high impedance state using the CHIP SELECT pin. 10.0 FUND 0.0 The AD9281 has great flexibility in its supply voltage. The –10.0 analog and digital supplies may be operated from 2.7 V to 5.5 V, independently of one another. –20.0 –30.0 ANALOG INPUT –40.0 Figure 16 shows an equivalent circuit structure for the analog –50.0 input of one of the A/D converters. PMOS source-followers –60.0 buffer the analog input pins from the charge kickback problems 5TH 2ND 3RD –70.0 8TH 6TH 7TH normally associated with switched capacitor ADC input struc- 4TH –80.0 tures. This produces a very high input impedance on the part, –90.0 allowing it to be effectively driven from high impedance sources. –100.0 This means that the AD9281 could even be driven directly by a –110.0 passive antialias filter. 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6 Figure 15b. Simultaneous Operation of I and Q Channels IINA BUFFER OUTPUT WORD THEORY OF OPERATION ADC CORE The AD9281 integrates two A/D converters, two analog input SHA +FS –FS buffers, an internal reference and reference buffer, and an out- LIMIT LIMIT put multiplexer. For clarity, this data sheet refers to the two IINB BUFFER converters as “I” and “Q.” The two A/D converters simulta- +FS LIMIT = –FS LIMIT = V +V V –V neously sample their respective inputs on the rising edge of the REF REF/2 REF REF/2 input clock. The two converters distribute the conversion opera- tion over several smaller A/D sub-blocks, refining the conversion V REF with progressively higher accuracy as it passes the result from stage to stage. As a consequence of the distributed conversion, Figure 16. Equivalent Circuit for AD9281 Analog Inputs each converter requires a small fraction of the 256 comparators The source followers inside the buffers also provide a level-shift used in a traditional flash-type 8-bit ADC. A sample-and-hold function of approximately 1 V, allowing the AD9281 to accept function within each of the stages permits the first stage to oper- inputs at or below ground. One consequence of this structure is ate on a new input sample while the following stages continue to that distortion will result if the analog input comes within 1.4 V process previous samples. This results in a “pipeline processing” of the positive supply. For optimum high frequency distortion latency of three clock periods between when an input sample is performance, the analog input signal should be centered accord- taken and when the corresponding ADC output is updated into ing to Figure 27. the output registers. The capacitance load of the analog input pin is 4 pF to the The AD9281 integrates input buffer amplifiers to drive the analog supplies (AVSS, AVDD). analog inputs of the converters. In most applications, these Full-scale setpoints may be calculated according to the following input amplifiers eliminate the need for external op amps for the algorithm (V may be internally or externally generated): REF input signals. The input structure is fully differential, but the SHA common-mode response has been designed to allow the –F = V – (V /2) S REF REF +F = V + (V /2) S REF REF V = V SPAN REF REV. F –8– SNR – dB SNR – dB AD9281 The AD9281 can accommodate a variety of input spans be- 1.5V 0.1mF tween 1 V and 2 V. For spans of less than 1 V, expect a propor- 0.5V I OR QREFT ANALOG tionate degradation in SNR. Use of a 2 V span will provide the IINA 0.1mF 10mF INPUT best noise performance. 1 V spans will provide lower distortion 1kV I OR QREFB when using a 3 V analog supply. Users wishing to run with larger 0.1mF IINB 1.0mF 0.1mF full-scales are encouraged to use a 5 V analog supply (AVDD). AD9281 VREF Single-Ended Inputs: For single-ended input signals, the REFSENSE signal is applied to one input pin and the other input pin is tied to a midscale voltage. This midscale voltage defines the center Figure 18. Example Configuration for 0.5 V–1.5 V ac of the full-scale span for the input signal. Coupled Single-Ended Inputs EXAMPLE: For a single-ended input range from 0 V to 1 V Transformer Coupled Inputs applied to IINA, we would configure the converter for a 1 V Another option for input ac coupling is to use a transformer. reference (see Figure 17) and apply 0.5 V to IINB. This not only provides dc rejection, but also allows truly differ- 1V ential drive of the AD9281’s analog inputs, which will provide the optimal distortion performance. Figure 19 shows a recom- 0V 0.1mF mended transformer input drive configuration. Resistors R1 and INPUT IINA I OR QREFT R2 define the termination impedance of the transformer cou- 10mF 0.1mF MIDSCALE pling. The center tap of the transformer secondary is tied to the VOLTAGE IINB I OR QREFB = 0.5V (1V) common-mode voltage, establishing the dc bias point for the 10mF 0.1mF 0.1mF analog inputs. AD9281 5kV 5kV VREF REF SENSE IINA QINA R1 R2 10mF 0.1mF IINB QINB AD9281 0.1mF COMMON Figure 17. Example Configuration for 0 V–1 V Single- MODE I OR QREFT VOLTAGE Ended Input Signal 0.1mF10mF VREF I OR QREFB 0.1mF 10mF Note that since the inputs are high impedance, this reference 0.1mF REFSENSE level can easily be generated with an external resistive divider with large resistance values (to minimize power dissipation). A decoupling capacitor is recommended on this input to minimize Figure 19. Example Configuration for Transformer the high frequency noise-coupling onto this pin. Decoupling Coupled Inputs should occur close to the ADC. Crosstalk: The internal layout of the AD9281, as well as its Differential Inputs pinout, was configured to minimize the crosstalk between the Use of differential input signals can provide greater flexibility in two input signals. Users wishing to minimize high frequency input ranges and bias points, as well as offering improvements in crosstalk should take care to provide the best possible decoupling distortion performance, particularly for high frequency input for input pins (see Figure 20). R and C values will make a pole signals. Users with differential input signals will probably want dependant on antialiasing requirements. Decoupling is also to take advantage of the differential input structure of the AD9281. required on reference pins and power supplies (see Figure 21). Performance is still very good for single-ended inputs. Convert- ing a single-ended input to a differential signal for application to IINA QINA the converter is probably only worth considering for very high frequency input signals. AD9281 IINB QINB AC-Coupled Inputs If the signal of interest has no dc component, ac coupling can be easily used to define an optimum bias point. Figure 18 illustrates Figure 20. Input Loading one recommended configuration. The voltage chosen for the dc bias point (in this case the 1 V reference) is applied to both V ANALOG V DIGITAL IINA and IINB pins through 1 kW resistors (R1 and R2). IINA AVDD DVDD is coupled to the input signal through Capacitor C1, while IINB is 0.1mF 10mF 0.1mF 10mF decoupled to ground through Capacitor C2. AD9281 I OR QREFT 0.1mF 0.1mF10mF I OR QREFB 0.1mF Figure 21. Reference and Power Supply Decoupling REV. F –9– AD9281 REFERENCE AND REFERENCE BUFFER Externally Set Voltage Mode (Figure 24)—this mode uses The reference and buffer circuitry on the AD9281 is configured the on-chip reference, but scales the exact reference level though for maximum convenience and flexibility. An illustration of the the use of an external resistor divider network. VREF is wired to equivalent reference circuit is show in Figure 26. The user can the top of the network, with the REFSENSE wired to the tap select from five different reference modes through appropriate point in the resistor divider. The reference level (and input full pin-strapping (see Table I below). These pin strapping options scale) will be equal to 1 V · (R1 + R2)/R1. This method can be cause the internal circuitry to reconfigure itself for the appropri- used for voltage levels from 0.7 V to 2.5 V. ate operating mode. 1mF Table I. Table of Modes 0.1mF 1V + VREF + – Mode Input Span REFSENSE Pin Figure – R2 1 V 1 V VREF 22 REFSENSE 2 V 2 V AGND 23 AD9281 R1 0.1mF Programmable 1 + (R1/R2) See Figure 24 AVSS I OR QREFT External = External Ref AVDD 25 R2 0.1mF10mF VREF = 1 + R1 I OR QREFB 1 V Mode (Figure 22)—provides a 1 V reference and 1 V input 0.1mF full scale. Recommended for applications wishing to optimize high frequency performance, or any circuit on a supply voltage Figure 24. Programmable Reference of less than 4 V. The part is placed in this mode by shorting the External Reference Mode (Figure 25)—in this mode, the on- REFSENSE pin to the VREF pin. chip reference is disabled, and an external reference applied to the VREF pin. This mode is achieved by tying the REFSENSE 1V 1V pin to AVDD. 0V 0V IINA QINA 1V 1V 5kV QINB IINB 0V 0V IINA QINA 10mF 0.1mF 5kV 5kV AD9281 IINB QINB 1V 0.1mF 10mF VREF AD9281 REFSENSE 5kV 0.1mF 1V EXT VREF I OR QREFT 0.1mF REFERENCE 10mF 0.1mF I OR QREFT 0.1mF10mF 10mF 0.1mF 0.1mF10mF I OR QREFB 0.1mF I OR QREFB 0.1mF AVDD REFSENSE Figure 22. 0 V to 1 V Input 2 V Mode (Figure 23)—provides a 2 V reference and 2 V input Figure 25. External Reference full scale. Recommended for noise sensitive applications on 5 V Reference Buffer—The reference buffer structure takes the supplies. The part is placed in 2 V reference mode by ground- voltage on the VREF pin and level-shifts and buffers it for use ing (shorting to AVSS) the REFSENSE pin. by various sub-blocks within the two A/D converters. The two converters share the same reference buffer amplifier to maintain 2V 2V the best possible gain match between the two converters. In the 0V 0V interests of minimizing high frequency crosstalk, the buffered IINA QINA references for the two converters are separately decoupled on 5kV IINB QINB the IREFB, IREFT, QREFB and QREFT pins, as illustrated in 10mF 0.1mF Figure 26. AD9281 5kV VREF 0.1mF I OR QREFT 10mF 0.1mF 0.1mF10mF I OR QREFB 0.1mF REFSENSE Figure 23. 0 V to 2 V Input REV. F –10– AD9281 feature chip capacitors located close to the converter IC. The capacitors are connected to either IREFT/IREFB or QREFT/ ADC QREFB. A connection to both sides is not required. CORE 0.1mF 0.1mF IREFT QREFT COMMON-MODE PERFORMANCE 10mF 0.1mF 0.1mF10mF Attention to the common-mode point of the analog input volt- age can improve the performance of the AD9281. Figure 27 1V IREFB QREFB 0.1mF 0.1mF illustrates THD as a function of common-mode voltage (center VREF point of the analog input span) and power supply. 1.0mF 0.1mF 10kV Inspection of the curves will yield the following conclusions: REFSENSE 1. An AD9281 running with AVDD = 5 V is the easiest to INTERNAL drive. CONTROL 10kV LOGIC AVSS 2. Differential inputs are the most insensitive to common-mode AD9281 voltage. 3. An AD9281 powered by AVDD = 3 V and a single ended Figure 26. Reference Buffer Equivalent Circuit and input, should have a 1 V span with a common-mode voltage External Decoupling Recommendation of 0.75 V. For best results in both noise suppression and robustness against crosstalk, the 4-capacitor buffer decoupling arrangement shown in Figure 26 is recommended. This decoupling should –3 –15 –13 2V –25 –23 –33 –35 2V –43 –45 1V –53 1V –55 –63 –73 –65 –0.5 0 0.5 1 1.5 –0.5 0 0.5 1 1.5 CML – V CML – V a. Differential Input, 3 V Supplies c. Single-Ended Input, 3 V Supplies –35 –15 –40 –25 –45 –50 2V –35 2V –55 1V 1V –45 –60 –55 –65 –70 –65 –0.5 0 0.5 1 1.5 2 2.5 –0.5 0 0.5 1 1.5 2 2.5 CML – V CML – V b. Differential Input, 5 V Supplies d. Single-Ended Input, 5 V Supplies Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz) REV. F –11– THD – dB THD – dB THD – dB THD – dB AD9281 SELECT DIGITAL INPUTS AND OUTPUTS When the select pin is held LOW, the output word will present Each of the AD9281 digital control inputs, CHIP SELECT, the “Q” level. When the select pin is held HIGH, the “I” level CLOCK, SELECT and SLEEP are referenced to AVDD and will be presented to the output word (see Figure 1). AVSS. Switching thresholds will be AVDD/2. The AD9281’s select and clock pins may be driven by a com- The format of the digital output is straight binary. A low power mon signal source. The data will change in 5 ns to 11 ns after mode feature is provided such that for STBY = HIGH and the the edges of the input pulse. The user must make sure the inter- clock disabled, the static power of the AD9281 will drop below face latches have sufficient hold time for the AD9281’s delays 22 mW. (see Figure 28). CLOCK INPUT The AD9281 clock input is internally buffered with an inverter CLOCK powered from the AVDD pin. This feature allows the AD9281 CLOCK I LATCH I to accommodate either +5 V or +3.3 V CMOS logic input sig- PROCESSING SOURCE SELECT DATA nal swings with the input threshold for the CLK pin nominally DATA CLK at AVDD/2. OUT DATA The pipelined architecture of the AD9281 operates on both Q Q LATCH rising and falling edges of the input clock. To minimize duty PROCESSING cycle variations the logic family recommended to drive the clock CLOCK input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 28 MSPS Figure 28. Typical De-Mux Connection operation. Running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, APPLICATIONS some slight performance improvements might be realized by USING THE AD9281 FOR QAM DEMODULATION clocking the AD9281 at slower clock rates. QAM is one of the most widely used digital modulation schemes in The power dissipated by the output buffers is largely propor- digital communication systems. This modulation technique tional to the clock frequency; running at reduced clock rates can be found in both FDMA as well as spread spectrum (i.e., provides a reduction in power consumption. CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) DIGITAL OUTPUTS and in phase (i.e., PM modulation). At the transmitter, it can Each of the on-chip buffers for the AD9281 output bits (D0–D9) be generated by independently modulating two carriers of iden- is powered from the DVDD supply pin, separate from AVDD. tical frequency but with a 90° phase difference. This results in The output drivers are sized to handle a variety of logic families an inphase (I) carrier component and a quadrature (Q) carrier while minimizing the amount of glitch energy generated. In all component at a 90° phase shift with respect to the I component. cases, a fan-out of one is recommended to keep the capacitive The I and Q components are then summed to provide a QAM load on the output data bits below the specified 20 pF level. signal at the specified carrier or IF frequency. Figure 29 shows a typical analog implementation of a QAM modulator using a For DVDD = 5 V, the AD9281 output signal swing is compat- dual 10-bit DAC with 2· interpolation, the AD9761. A QAM ible with both high speed CMOS and TTL logic families. For signal can also be synthesized in the digital domain thus requir- TTL, the AD9281 on-chip, output drivers were designed to ing a single DAC to reconstruct the QAM signal. The AD9853 support several of the high speed TTL families (F, AS, S). For is an example of a complete (i.e., DAC included) digital QAM applications where the clock rate is below 28 MSPS, other TTL modulator. families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9281 sustains 28 MSPS operation with DVDD = 3 V. In all cases, check your logic family data sheets IOUT for compatibility with the AD9281’s Specification table. DSP 10 TO CARRIER 0 OR AD9761 A 2 ns reduction in output delays can be achieved by limiting MIXER FREQUENCY 90 ASIC the logic load to 5 pF per output line. QOUT NYQUIST THREE-STATE OUTPUTS QUADRATURE FILTERS MODULATOR The digital outputs of the AD9281 can be placed in a high impedance state by setting the CHIP SELECT pin to HIGH. Figure 29. Typical Analog QAM Modulator Architecture This feature is provided to facilitate in-circuit testing or evaluation. REV. F –12– AD9281 At the receiver, the demodulation of a QAM signal back into its LOGIC AVDD SUPPLY separate I and Q components is essentially the modulation DVDD process explain above but in the reverse order. A common and A A D traditional implementation of a QAM demodulator is shown in Figure 30. In this example, the demodulation is performed in the analog domain using a dual, matched ADC and a quadra- ADC DIGITAL IC LOGIC C STRAY ture demodulator to recover and digitize the I and Q baseband ICs signals. The quadrature demodulator is typically a single IC ANALOG DIGITAL containing two mixers and the appropriate circuitry to generate CIRCUITS CIRCUITS V IN the necessary 90° phase shift between the I and Q mixers’ local B A C A STRAY oscillators. Before being digitized by the ADCs, the mixed I I A D down baseband I and Q signals are filtered using matched ana- log filters. These filters, often referred to as Nyquist or Pulse- GND AVSS DVSS Shaping filters, remove images-from the mixing process and any out-of-band. The characteristics of the matching Nyquist filters = ANALOG A DV A A D are well defined to provide optimum signal-to-noise (SNR) = DIGITAL D performance while minimizing intersymbol interference. The Figure 31. Ground and Power Consideration ADC’s are typically simultaneously sampling their respective inputs at the QAM symbol rate or, most often, at a multiple of it These characteristics result in both a reduction of electro- if a digital filter follows the ADC. Oversampling and the use of magnetic interference (EMI) and an overall improvement in digital filtering eases the implementation and complexity of the performance. analog filter. It also allows for enhanced digital processing for It is important to design a layout that prevents noise from cou- both carrier and symbol recovery and tuning purposes. The use pling onto the input signal. Digital signals should not be run in of a dual ADC such as the AD9281 ensures excellent gain, parallel with the input signal traces and should be routed offset, and phase matching between the I and Q channels. away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9281 in a solid ground plane. The power and ground return currents I ADC must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital cir- FROM DSP CARRIER LO PREVIOUS cuitry should not pass through critical analog circuitry. OR FREQUENCY 90°C STAGE ASIC Transients between AVSS and DVSS will seriously degrade Q performance of the ADC. ADC NYQUIST If the user cannot tie analog ground and digital ground together QUADRATURE FILTERS DUAL MATCHED DEMODULATOR at the ADC, he should consider the configuration in Figure 32. ADC Another input and ground technique is shown in Figure 32. A Figure 30. Typical Analog QAM Demodulator separate ground plane has been split for RF or hard to manage signals. These signals can be routed to the ADC differentially or GROUNDING AND LAYOUT RULES single ended (i.e., both can either be connected to the driver or As is the case for any high performance device, proper ground- RF ground). The ADC will perform well with several hundred ing and layout techniques are essential in achieving optimal mV of noise or signals between the RF and ADC analog ground. performance. The analog and digital grounds on the AD9281 have been separated to optimize the management of return currents in a system. Grounds should be connected near the RF ANALOG DIGITAL ADC. It is recommended that a printed circuit board (PCB) of GROUND GROUND GROUND at least four layers, employing a ground plane and power planes, be used with the AD9281. The use of ground and power planes ADC LOGIC offers distinct advantages: DATA AIN 1. The minimization of the loop area encompassed by a signal BIN and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. Figure 32. RF Ground Scheme REV. F –13– AD9281 REVISION HISTORY 1/11—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Pin Configuration Diagram ........................................ 4 Changes to Pin Function Descriptions Table ................................ 4 Removed Evaluation Boards; Renumbered Sequentially ............................................................................ 14 to 18 Changes to Ordering Guide ........................................................... 15 8/99—Rev. D to Rev. E Rev. F | Page 14 of 15 AD9281 OUTLINE DIMENSIONS 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 33. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option AD9281ARS −40°C to +85°C 28-Lead SSOP RS-28 AD9281ARSRL −40°C to +85°C 28-Lead SSOP RS-28 AD9281ARSZ −40°C to +85°C 28-Lead SSOP RS-28 AD9281ARSZRL −40°C to +85°C 28-Lead SSOP RS-28 1 Z = RoHS Compliant Part. 2 RS = Shrink Small Outline. ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00583-0-1/11(F) Rev. F | Page 060106-A