ANALOG DEVICES AD9280

Complete 8-Bit, 32 MSPS, 95 mW a CMOS A/D Converter AD9280 FEATURES A single clock input is used to control all internal conversion CMOS 8-Bit 32 MSPS Sampling A/D Converter cycles. The digital output data is presented in straight binary Pin-Compatible with AD876-8 output format. An out-of-range signal (OTR) indicates an over- Power Dissipation: 95 mW (3 V Supply) flow condition which can be used with the most significant bit Operation Between +2.7 V and +5.5 V Supply to determine low or high overflow. Differential Nonlinearity: 0.2 LSB The AD9280 can operate with a supply range from +2.7 V to Power-Down (Sleep) Mode +5.5 V, ideally suiting it for low power operation in high speed Three-State Outputs applications. Out-of-Range Indicator The AD9280 is specified over the industrial (–40°C to +85°C) Built-In Clamp Function (DC Restore) temperature range. Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION Low Power The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS The AD9280 consumes 95 mW on a 3 V supply (excluding the analog-to-digital converter with an on-chip sample-and-hold reference power). In sleep mode, power is reduced to below amplifier and voltage reference. The AD9280 uses a multistage 5 mW. differential pipeline architecture at 32 MSPS data rates and Very Small Package guarantees no missing codes over the full operating temperature The AD9280 is available in a 28-lead SSOP package. range. Pin Compatible with AD876-8 The input of the AD9280 has been designed to ease the devel- The AD9280 is pin compatible with the AD876-8, allowing opment of both imaging and communications systems. The user older designs to migrate to lower supply voltages. can select a variety of input ranges and offsets and can drive the 300 MHz Onboard Sample-and-Hold input either single-ended or differentially. The versatile SHA input can be configured for either single- The sample-and-hold amplifier (SHA) is equally suited for both ended or differential inputs. multiplexed systems that switch full-scale voltage levels in suc- Out-of-Range Indicator cessive channels and sampling single-channel inputs at frequen- The OTR output bit indicates when the input signal is beyond cies up to and beyond the Nyquist rate. AC-coupled input the AD9280’s input range. signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent. Built-In Clamp Function Allows dc restoration of video signals. The AD9280 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP CLK AVDD DRVDD IN STBY SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN MODE VINA A/D REFTF THREE- A/D D/A A/D D/A A/D D/A A/D D/A REFTS STATE CORRECTION LOGIC REFBS REFBF OUTPUT BUFFERS OTR VREF D7 (MSB) AD9280 1V REFSENSE D0 (LSB) AVSS DRVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2010 (AVDD = +3 V, DRVDD = +3 V, F = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S AD9280–SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T to T unless otherwise noted) MIN MAX Parameter Symbol Min Typ Max Units Condition RESOLUTION 8 Bits CONVERSION RATE F 32 MHz S DC ACCURACY Differential Nonlinearity DNL ±0.2 ±1.0 LSB REFTS = 2.5 V, REFBS = 0.5 V Integral Nonlinearity INL ±0.3 ±1.5 LSB Offset Error E ±0.2 ±1.8 % FSR ZS Gain Error E ±1.2 ±3.9 % FSR FS REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD V Bottom Reference Voltage REFBS GND AVDD – 1 V Differential Reference Voltage 2 V p-p 1 Reference Input Resistance 10 kΩ REFTS, REFBS: MODE = AVDD 4.2 kΩ Between REFTF & REFBF: MODE = AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD Input Capacitance C 1 pF Switched IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Input Bandwidth (–3 dB) BW Full Power (0 dB) 300 MHz DC Leakage Current 43 μA Input = ±FS INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) ±10 ±25 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DRVDD 2.7 3 5.5 V Supply Current IAVDD 31.7 36.7 mA AVDD = 3 V, MODE = AVSS Power Consumption P 95 110 mW AVDD = DRVDD = 3 V, MODE = AVSS D Power-Down 4 mW STBY = AVDD, MODE and CLOCK = AVSS Gain Error Power Supply Rejection PSRR 1 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 46.4 49 dB f = 16 MHz 48 dB Effective Bits f = 3.58 MHz 7.8 Bits f = 16 MHz 7.7 Bits Signal-to-Noise SNR f = 3.58 MHz 47.8 49 dB f = 16 MHz 48 dB Total Harmonic Distortion THD f = 3.58 MHz –62 –49.5 dB f = 16 MHz –58 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 66 51.4 dB f = 16 MHz 61 dB Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.08 % REV. E –2– AD9280 Parameter Symbol Min Typ Max Units Condition DIGITAL INPUTS High Input Voltage V 2.4 V IH Low Input Voltage V 0.3 V IL DIGITAL OUTPUTS High-Z Leakage I –10 +10 μA Output = GND to VDD OZ Data Valid Delay t 25 ns C = 20 pF OD L Data Enable Delay t 25 ns DEN Data High-Z Delay t 13 ns DHZ LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (I = 50 μA) V +2.95 V OH OH High Level Output Voltage (I = 0.5 mA) V +2.80 V OH OH Low Level Output Voltage (I = 1.6 mA) V +0.4 V OL OL Low Level Output Voltage (I = 50 μA) V +0.05 V OL OL LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (I = 50 μA) V +4.5 V OH OH High Level Output Voltage (I = 0.5 mA) V +2.4 V OH OH Low Level Output Voltage (I = 1.6 mA) V +0.4 V OL OL Low Level Output Voltage (I = 50 μA) V +0.1 V OL OL CLOCKING Clock Pulsewidth High t 14.7 ns CH Clock Pulsewidth Low t 14.7 ns CL Pipeline Latency 3 Cycles CLAMP Clamp Error Voltage E ±60 ±80 mV CLAMPIN = +0.5 V to +2.0 V, OC R = 10 Ω IN Clamp Pulsewidth t 2 μsC = 1 μF (Period = 63.5 μs) CPW IN NOTES 1 See Figures 1a and 1b. Specifications subject to change without notice. REFTS 10kV AD9280 AD9280 REFTS REFTF 4.2kV 10kV REFBF REFBS 0.4 3 V DD REFBS MODE MODE AV DD a. b. Figure 1. Equivalent Input Load REV. E –3– AD9280 *Stresses above those listed under Absolute Maximum Ratings may cause perma- ABSOLUTE MAXIMUM RATINGS* nent damage to the device. This is a stress rating only; functional operation of the With device at these or any other conditions above those indicated in the operational Respect sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. Parameter to Min Max Units AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –6.5 +6.5 V MODE AVSS –0.3 AVDD + 0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AIN AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V REFSENSE AVSS –0.3 AVDD + 0.3 V REFTF, REFTB AVSS –0.3 AVDD + 0.3 V REFTS, REFBS AVSS –0.3 AVDD + 0.3 V Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature 10 sec +300 °C AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS a. D0–D7, OTR b. Three-State, Standby, Clamp c. CLK AVDD AVDD 22 REFTF 25 REFBS AVDD AVSS AVSS AVDD AVDD 24 21 REFBF REFTS AVSS AVSS AVSS d. AIN e. Reference AVDD AVDD AVDD AVDD AVSS AVSS AVSS AVSS f. CLAMPIN g. MODE h. REFSENSE i. VREF Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. E –4– AD9280 PIN CONFIGURATION 28-Lead Wide Body (SSOP) 1 28 AVDD AVSS DRVDD 2 27 AIN 3 26 VREF 4 25 REFBS D0 5 24 REFBF AD9280 D1 6 23 MODE TOP VIEW (Not to Scale) D2 7 22 REFTF 8 21 D3 REFTS 9 20 CLAMPIN D4 10 19 D5 CLAMP D6 11 18 REFSENSE 12 STBY D7 17 13 16 OTR THREE-STATE DRVSS 14 15 CLK 'NC = DO NOT CONNECT PIN FUNCTION DESCRIPTIONS SSOP Pin No. Name Description 1 AVSS Analog Ground 2 DRVDD Digital Driver Supply 3 4 5 D0 Bit 0 6 D1 Bit 1 7 D2 Bit 2 8 D3 Bit 3 9 D4 Bit 4 10 D5 Bit 5 11 D6 Bit 6 12 D7 Bit 7, Most Significant Bit 13 OTR Out-of-Range Indicator 14 DRVSS Digital Ground 15 CLK Clock Input 16 THREE-STATE HI: High Impedance State. LO: Normal Operation 17 STBY HI: Power-Down Mode. LO: Normal Operation 18 REFSENSE Reference Select 19 CLAMP HI: Enable Clamp Mode. LO: No Clamp 20 CLAMPIN Clamp Reference Input 21 REFTS Top Reference 22 REFTF Top Reference Decoupling 23 MODE Mode Select 24 REFBF Bottom Reference Decoupling 25 REFBS Bottom Reference 26 VREF Internal Reference Output 27 AIN Analog Input 28 AVDD Analog Supply REV. E –5– AD9280 DEFINITIONS OF SPECIFICATIONS Offset Error Integral Nonlinearity (INL) The first transition should occur at a level 1 LSB above “zero.” Integral nonlinearity refers to the deviation of each individual Offset is defined as the deviation of the actual first code transi- code from a line drawn from “zero” through “full scale.” The tion from that point. point used as “zero” occurs 1/2 LSB before the first code transi- Gain Error tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last The first code transition should occur for an analog value 1 LSB code transition. The deviation is measured from the center of above nominal negative full scale. The last transition should each particular code to the true straight line. occur for an analog value 1 LSB below the nominal positive full Differential Nonlinearity (DNL, No Missing Codes) scale. Gain error is the deviation of the actual difference be- An ideal ADC exhibits code transitions that are exactly 1 LSB tween first and last code transitions and the ideal difference apart. DNL is the deviation from this ideal value. It is often between the first and last code transitions. specified in terms of the resolution for which no missing codes Pipeline Delay (Latency) (NMC) are guaranteed. The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising edge. (AVDD = +3 V, DRVDD = +3 V, F = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted) Typical Characterization Curves 1.0 60 55 0.5 50 –0.5 AMPLITUDE 45 –6.0 AMPLITUDE 0 40 35 –0.5 30 –20.0 AMPLITUDE 25 20 –1.0 0 32 64 96 128 160 192 224 240 1.00E+05 1.00E+06 1.00E+07 1.00E+08 INPUT FREQUENCY – Hz CODE OFFSET Figure 3. Typical DNL Figure 5. SNR vs. Input Frequency 1.0 60 55 0.5 50 –0.5 AMPLITUDE 45 –6.0 AMPLITUDE 0 40 35 –0.5 30 –20.0 AMPLITUDE 25 20 –1.0 0 32 64 96 128 160 192 224 240 1.00E+05 1.00E+06 1.00E+07 1.00E+08 CODE OFFSET INPUT FREQUENCY – Hz Figure 6. SINAD vs. Input Frequency Figure 4. Typical INL REV. E –6– INL DNL SNR– dB SINAD – dB AD9280 –30 105 –35 100 –40 95 –45 –20.0 AMPLITUDE –50 90 –55 –6.0 AMPLITUDE 85 –60 80 –65 –0.5 AMPLITUDE –70 75 045 10 15 20 25 30 350 1.00E+05 1.00E+06 1.00E+07 1.00E+08 CLOCK FREQUENCY – MHz INPUT FREQUENCY – Hz Figure 10. Power Consumption vs. Clock Frequency Figure 7. THD vs. Input Frequency (MODE = AVSS) –80 1M 1M 900k –70 AIN = –0.5dBFS 800k –60 700k –50 600k –40 500k 400k –30 300k –20 200k –10 100k 0 0 0 0 N–1 N N+1 1.00E+06 1.00E+07 1.00E+08 CODE CLOCK FREQUENCY – Hz Figure 8. THD vs. Clock Frequency Figure 11. Grounded Input Histogram 30 1.01 20 F = 1MHz CLOCK = 32MHz IN 10 FUND F = 32MHz S 1.009 0 –10 –20 1.008 –30 –40 –50 2nd –60 1.007 3rd 9th 5th 7th –70 8th 6th –80 4th –90 1.006 –100 –110 –120 1.005 –50 –30 –10 10 30 50 70 90 0E+0 4E+6 8E+6 12E+6 16E+6 TEMPERATURE – °C SINGLE-TONE FREQUENCY DOMAIN Figure 12. Single-Tone Frequency Domain Figure 9. Voltage Reference Error vs. Temperature REV. E –7– V – V REF THD – dB THD – dB HITS POWER CONSUMPTION – mW AD9280 0 APPLYING THE AD9280 THEORY OF OPERATION –3 The AD9280 implements a pipelined multistage architecture to –6 achieve high sample rate with low power. The AD9280 distrib- utes the conversion over several smaller A/D subblocks, refining –9 the conversion with progressively higher accuracy as it passes –12 the results from stage to stage. As a consequence of the distrib- uted conversion, the AD9280 requires a small fraction of the –15 256 comparators used in a traditional flash type A/D. A sample- and-hold function within each of the stages permits the first –18 stage to operate on a new input sample while the second, third –21 and fourth stages operate on the three preceding samples. –24 1.0E+6 1.0E+7 1.0E+8 1.0E+9 OPERATIONAL MODES FREQUENCY – Hz The AD9280 is designed to allow optimal performance in a Figure 13. Full Power Bandwidth wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876-8 A/D. 50 To realize this flexibility, internal switches on the AD9280 are used to reconfigure the circuit into different modes. These modes 40 are selected by appropriate pin strapping. There are three parts 30 of the circuit affected by this modality: the voltage reference, the 20 reference buffer, and the analog input. The nature of the appli- REFBS = 0.5V 10 REFTS = 2.5V cation will determine which mode is appropriate: the descrip- CLOCK = 32MHz tions in the following sections, as well as Table I should assist in 0 selecting the desired mode. –10 –20 –30 –40 –50 0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE – V Figure 14. Input Bias Current vs. Input Voltage Table I. Mode Selection Input Input MODE REFSENSE Modes Connect Span Pin Pin REF REFTS REFBS Figure TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18 AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19 CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20 AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29 REFTS and REFBS Are Shorted Together for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22 – REFBS (2 V max) AGND Short to Short to 23 VREFTF VREFBF AD876-8 AIN 2 V Float or AVDD No Connect Short to Short to 30 AVSS VREFTF VREFBF REV. E –8– SIGNAL AMPLITUDE – dB I – mA B AD9280 SUMMARY OF MODES VOLTAGE REFERENCE AIN A/D 1 V Mode the internal reference may be set to 1 V by connect- SHA CORE REFTS ing REFSENSE and VREF together. 2 V Mode the internal reference my be set to 2 V by connecting REFSENSE to analog ground AD9280 External Divider Mode the internal reference may be set to a REFBS point between 1 V and 2 V by adding external resistors. See Figure 16f. Figure 15. AD9280 Equivalent Functional Input Circuit External Reference Mode enables the user to apply an exter- nal reference to REFTS, REFBS and VREF pins. This mode In single-ended operation, the input spans the range, is attained by tying REFSENSE to VDD. REFBS ≤ AIN ≤ REFTS where REFBS can be connected to GND and REFTS con- REFERENCE BUFFER nected to VREF. If the user requires a different reference range, Center Span Mode midscale is set by shorting REFTS and REFBS and REFTS can be driven to any voltage within the REFBS together and applying the midscale voltage to that point power supply rails, so long as the difference between the two is The MODE pin is set to AVDD/2. The analog input will swing between 1 V and 2 V. about that midscale point. In differential operation, REFTS and REFBS are shorted to- Top/Bottom Mode sets the input range between two points. gether, and the input span is set by VREF, The two points are between 1 V and 2 V apart. The Top/Bottom Mode is enabled by tying the MODE pin to AVDD. (REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2) where VREF is determined by the internal reference or brought ANALOG INPUT in externally by the user. Differential Mode is attained by driving the AIN pin as one The best noise performance may be obtained by operating the differential input, shorting REFTS and REFBS together and AD9280 with a 2 V input range. The best distortion perfor- driving them as the second differential input. The MODE pin mance may be obtained by operating the AD9280 with a 1 V is tied to AVDD/2. Preferred mode for optimal distortion input range. performance. Single-Ended is attained by driving the AIN pin while the REFERENCE OPERATION REFTS and REFBS pins are held at dc points. The MODE pin is The AD9280 can be configured in a variety of reference topolo- tied to AVDD. gies. The simplest configuration is to use the AD9280’s onboard Single-Ended/Clamped (AC Coupled) the input may be bandgap reference, which provides a pin-strappable option to clamped to some dc level by ac coupling the input. This is done generate either a 1 V or 2 V output. If the user desires a refer- by tying the CLAMPIN to some dc point and applying a pulse ence voltage other than those two, an external resistor divider to the CLAMP pin. MODE pin is tied to AVDD. can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V. SPECIAL Another alternative is to use an external reference for designs AD876-8 Mode enables users of the AD876-8 to drop the requiring enhanced accuracy and/or drift performance. A AD9280 into their socket. This mode is attained by floating or third alternative is to bring in top and bottom references, grounding the MODE pin. bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input ar- INPUT AND REFERENCE OVERVIEW chitecture of the AD9280. In tailoring a desired arrangement, Figure 16, a simplified model of the AD9280, highlights the the user can select an input configuration to match drive circuit. relationship between the analog input, AIN, and the reference Then, moving to the reference modes at the bottom of the voltages, REFTS, REFBS and VREF. Like the voltages applied figure, select a reference circuit to accommodate the offset and to the resistor ladder in a flash A/D converter, REFTS and amplitude of a full-scale signal. REFBS define the maximum and minimum input voltages to Table I outlines pin configurations to match user requirements. the A/D. The input stage is normally configured for single-ended opera- tion, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. E –9– AD9280 V* MIDSCALE AD9280 MODE AIN +FS AVDD/2 SHA AD9280 AIN –FS MODE SHA (AVDD) 0.1mF +F/S RANGE 10kV REFTF OBTAINED FROM 0.1mF VREF PIN OR 10kV REFTF 10kV EXTERNAL REF REFTS A2 0.1mF 10mF 10kV REFTS REFBS A/D 4.2kV CORE TOTAL 10kV A2 REFBS 0.1mF 4.2kV A/D 10mF 10kV CORE TOTAL INTERNAL 0.1mF 10kV REF –F/S RANGE OBTAINED FROM 0.1mF REFBF 10kV VREF PIN OR MIDSCALE OFFSET EXTERNAL REF REFBF * MAXIMUM MAGNITUDE OF V IS DETERMINED VOLTAGE IS DERIVED BY INTERNAL REFERENCE FROM INTERNAL OR EXTERNAL REF a. Top/Bottom Mode b. Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AD9280 MODE AIN AVDD/2 SHA AVDD/2 0.1mF 10kV REFTF 10kV REFTS A2 0.1mF 10mF 4.2kV REFBS A/D 10kV CORE TOTAL INTERNAL 0.1mF 10kV REF REFBF c. Differential Mode VREF (2V) VREF A1 (1V) 1.0mF 1V 0.1mF A1 1V 10kV REFSENSE 0.1mF 1.0mF REFSENSE AD9280 AVSS 10kV AD9280 AVSS d. 1 V Reference e. 2 V Reference VREF (= 1 + R /R ) A B A1 1V A1 VREF 1.0mF 0.1mF R A 1V REFSENSE REFSENSE AVDD R B AD9280 AD9280 AVSS INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF R AND R . A B g. Internal Reference Disable f. Variable Reference (Power Reduction) (Between 1 V and 2 V) Figure 16. REV. E –10– AD9280 The actual reference voltages used by the internal circuitry of Figure 19 shows the single-ended configuration for 2 V p-p the AD9280 appear on REFTF and REFBF. For proper opera- operation. REFSENSE is connected to GND, resulting in a 2 V tion, it is necessary to add a capacitor network to decouple these reference output. pins. The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17. 2V AIN AD9280 MODE SHA AVDD 0V 0.1mF REFTF 10kV REFTF 10mF 0.1mF AD9280 10kV REFTS A2 REFBF REFBS 10mF 0.1mF A/D 4.2kV 0.1mF 0.1mF 10kV CORE TOTAL 0.1mF 10kV Figure 17. Reference Decoupling Network REFBF VREF A1 1V Note: REFTF = reference top, force 1.0mF 0.1mF REF SENSE REFBF = reference bottom, force REFTS = reference top, sense REFBS = reference bottom, sense INTERNAL REFERENCE OPERATION Figure 19. Internal Reference, 2 V p-p Input Span Figures 18, 19 and 20 show sample connections of the AD9280 (Top/Bottom Mode) internal reference in its most common configurations. (Figures Figure 20 shows the single-ended configuration that gives the 18 and 19 illustrate top/bottom mode while Figure 20 illustrates good high frequency dynamic performance (SINAD, SFDR). center span mode). Figure 29 shows how to connect the AD9280 To optimize dynamic performance, center the common-mode for 1 V p-p differential operation. Shorting the VREF pin voltage of the analog input at approximately 1.5 V. Connect the directly to the REFSENSE pin places the internal reference shorted REFTS and REFBS inputs to a low impedance 1.5 V amplifier, A1, in unity-gain mode and the resultant reference source. In this configuration, the MODE pin is driven to a volt- output is 1 V. In Figure 18 REFBS is grounded to give an input age at midsupply (AVDD/2). range from 0 V to 1 V. These modes can be chosen when the Maximum reference drive is 1 mA. An external buffer is re- supply is either +3 V or +5 V. The VREF pin must be bypassed to quired for heavier loads. AVSS (analog ground) with a 1.0 μF tantalum capacitor in parallel with a low inductance, low ESR, 0.1 μF ceramic capacitor. 2V AIN AD9280 MODE SHA AVDD/2 1V 1V AIN AD9280 MODE SHA AVDD 0V 0.1mF 10kV REFTF 0.1mF 10kV REFTF 10kV REFTS A2 +1.5V REFBS 10mF 0.1mF 10kV REFTS A/D 4.2kV CORE TOTAL A2 REFBS 0.1mF 10mF A/D 4.2kV 10kV CORE TOTAL 0.1mF 10kV 10kV REFBF 0.1mF 10kV VREF A1 REFBF 1V REF 1.0mF 0.1mF VREF SENSE A1 1V 1.0mF 0.1mF REF SENSE Figure 20. Internal Reference 1 V p-p Input Span (Center Span Mode) Figure 18. Internal Reference—1 V p-p Input Span (Top/Bottom Mode) REV. E –11– AD9280 EXTERNAL REFERENCE OPERATION Figure 23a shows an example of the external references driving Using an external reference may provide more flexibility and the REFTF and REFBF pins that is compatible with the improve drift and accuracy. Figures 21 through 23 show ex- AD876. REFTS is shorted to REFTF and driven by an external amples of how to use an external reference with the AD9280. 4 V low impedance source. REFBS is shorted to REFBF and To use an external reference, the user must disable the internal driven by a 2 V source. The MODE pin is connected to GND reference amplifier by connecting the REFSENSE pin to VDD. in this configuration. The user then has the option of driving the VREF pin, or driv- ing the REFTS and REFBS pins. 4V VIN The AD9280 contains an internal reference buffer (A2), that 2V REFTS simplifies the drive requirements of an external reference. The 4V REFTF external reference must simply be able to drive a 10 kΩ load. 10mF 0.1mF AD9280 Figure 21 shows an example of the user driving the top and bottom REFBF 2V references. REFTS is connected to a low impedance 2 V source 0.1mF 0.1mF REFBS and REFBS is connected to a low impedance 1 V source. REFTS and REFBS may be driven to any voltage within the supply as long VREF as the difference between them is between 1 V and 2 V. REFSENSE AVDD MODE 2V AIN AD9280 SHA 1V Figure 23a. External Reference—2 V p-p Input Span 0.1mF 10kV REFTF 10kV REFTS REFTS 2V +5V A2 REFBS 0.1mF 10mF C4 4.2kV 1V A/D 6 0.1mF 8 10kV TOTAL CORE 7 REFTF 5 REF REFT C3 C6 SENSE 0.1mF 10kV 0.1mF 0.1mF AD9280 AVDD C2 MODE 10mF REFBF REFBS C5 2 0.1mF 6 Figure 21. External Reference Mode—1 V p-p Input Span REFBF 3 REFB C1 4 Figure 22 shows an example of an external reference generating 0.1mF 2.5 V at the shorted REFTS and REFBS inputs. In this in- stance, a REF43 2.5 V reference drives REFTS and REFBS. A Figure 23b. Kelvin Connected Reference Using the AD9280 resistive divider generates a 1 V VREF signal that is buffered by A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose STANDBY OPERATION this op amp based on noise and accuracy requirements. The ADC may be placed into a powered down (sleep) mode by driving the STBY (standby) pin to logic high potential and holding the clock at logic low. In this mode the typical power AD9280 3.0V drain is approximately 4 mW. 2.5V AIN AVDD AVDD 2.0V The ADC will “wake up” in 400 ns (typ) after the standby pulse REFTS goes low. 0.1mF REFBS REFTF 10mF 0.1mF 1.5kV CLAMP OPERATION 0.1mF 10mF A3 VREF The AD9280ARS features an optional clamp circuit for dc 1.0mF 0.1mF restoration of video or ac coupled signals. Figure 24 shows the 0.1mF 0.1mF 1kV REFBF internal clamp circuitry and the external control signals needed AVDD/2 MODE for clamp operation. To enable the clamp, apply a logic high to +5V AVDD REFSENSE the CLAMP pin. This will close the switch SW1. The clamp REF43 amplifier will then servo the voltage at the AIN pin to be equal 0.1mF to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, SW1 is opened by taking CLAMP back to a logic low. Ignoring the droop caused by the Figure 22. External Reference Mode—1 V p-p Input input bias current, the input capacitor CIN will hold the dc Span 2.5 V CM voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 Ω, to maintain the closed-loop stability of the clamp amplifier. REV. E –12– AD9280 The allowable voltage range that can be applied to CLAMPIN back porch to truncate the SYNC below the AD9280’s mini- depends on the operational limits of the internal clamp ampli- mum input voltage. With a C = 1 μF, and R = 20 Ω, the IN IN fier. The recommended clamp range is between 0.5 volts and acquisition time needed to set the input dc level to one volt 2.0 volts. with 1 mV accuracy is about 140 μs, assuming a full 1 volt V . C The input capacitor should be sized to allow sufficient acquisi- With a 1 μF input coupling capacitor, the droop across one tion time of the clamp voltage at AIN within the CLAMP inter- horizontal can be calculated: val, but also be sized to minimize droop between clamping I = 22 μA, and t = 63.5 μs, so dV = 1.397 mV, which is less BIAS intervals. Specifically, the acquisition time when the switch is than one LSB. closed will equal: After the input capacitor is initially charged, the clamp pulse   V width only needs to be wide enough to correct small voltage C T = R C ln ACQ IN IN   errors such as the droop. The fine scale settling characteristics V  E  of the clamp circuitry are shown in Table II. where V is the voltage change required across C , and V is C IN E Depending on the required accuracy, a CLAMP pulse width of the error voltage. V is calculated by taking the difference be- C 1 μs–3 μs should work in most applications. The OFFSET val- tween the initial input dc level at the start of the clamp interval ues ignore the contribution of offset from the clamp amplifier; and the clamp voltage supplied at CLAMPIN. V is a system E they simply compare the output code with a “final value” mea- dependent parameter, and equals the maximum tolerable devia- sured with a much longer CLAMP pulse duration. tion from V . For example, if a 2-volt input level needs to be C clamped to 1 volt at the AD9280’s input within 10 millivolts, Table II. then V equals 2 – 1 or 1 volt, and V equals 10 mV. Note that C E once the proper clamp level is attained at the input, only a very CLAMP OFFSET small voltage change will be required to correct for droop. 8 μs <1 LSB The voltage droop is calculated with the following equation: 4 μs <2 LSBs 3 μs 2 LSBs I BIAS dV = t () 2 μs 5 LSBs C IN 1 μs 9 LSBs where t = time between clamping intervals. The bias current of the AD9280 will depend on the sampling rate, F , and the difference between the reference midpoint, S AD9280 (REFTS–REFBS)/2 and the input voltage. For a fixed sampling CLAMP IN rate of 32 MHz, Figure 14 shows the input bias current for a given input. For a 1 V input range, the maximum input bias CLAMP current from Figure 14 is 22 μA. For lower sampling rates the SW1 input bias current will scale proportionally. CIN RIN AIN TO If droop is a critical parameter, then the minimum value of C IN SHA should be calculated first based on the droop requirement. Acquisition time—the width of the CLAMP pulse—can be Figure 24a. Clamp Operation adjusted accordingly once the minimum capacitor value is cho- sen. A tradeoff will often need to be made between droop and acquisition time, or error voltage V . E AIN Clamp Circuit Example 0.1mF REFTF A single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: REFTS 10mF 0.1mF AD9280 horizontal period = 63.56 μs, 0.1mF REFBF horizontal sync interval = 10.9 μs, REFBS horizontal sync pulse = 4.7 μs, AVDD sync amplitude = 0.3 volts, MODE 2 video amplitude of 0.7 volts, CLAMP reference black level = 2.3 volts SHORT TO REFBS CLAMPIN The video signal must be dc restored from a 2- to 3-volt range OR EXTERNAL DC down to a 1- to 2-volt range. Configuring the AD9280 for a one volt input span with an input range from 1 to 2 volts (see Figure 24b. Video Clamp Circuit Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS. The CLAMP pulse may be applied during the SYNC pulse, or during the REV. E –13– AD9280 DRIVING THE ANALOG INPUT In many cases, particularly in single-supply operation, ac cou- Figure 25 shows the equivalent analog input of the AD9280, a pling offers a convenient way of biasing the analog input signal sample-and-hold amplifier (switched capacitor input SHA). at the proper signal range. Figure 27 shows a typical configura- Bringing CLK to a logic low level closes Switches 1 and 2 and tion for ac-coupling the analog input signal to the AD9280. opens Switch 3. The input source connected to AIN must Maintaining the specifications outlined in the data sheet charge capacitor CH during this time. When CLK transitions requires careful selection of the component values. The most from logic “low” to logic “high,” Switches 1 and 2 open, placing important is the f high-pass corner frequency. It is a function of –3 dB the SHA in hold mode. Switch 3 then closes, forcing the output R2 and the parallel combination of C1 and C2. The f point –3 dB of the op amp to equal the voltage stored on CH. When CLK can be approximated by the equation: transitions from logic “high” to logic “low,” Switch 3 opens f = 1/(2 · pi · [R2] C ) –3 dB EQ first. Switches 1 and 2 close, placing the SHA in track mode. where C is the parallel combination of C1 and C2. Note that EQ The structure of the input SHA places certain requirements on C1 is typically a large electrolytic or tantalum capacitor that the input drive source. The combination of the pin capacitance, becomes inductive at high frequencies. Adding a small ceramic CP, and the hold capacitance, CH, is typically less than 5 pF. or polystyrene capacitor (on the order of 0.01 μF) that does not The input source must be able to charge or discharge this ca- become inductive until negligibly higher frequencies, maintains pacitance to 8-bit accuracy in one half of a clock cycle. When a low impedance over a wide frequency range. the SHA goes into track mode, the input source must charge or NOTE: AC coupled input signals may also be shifted to a desired discharge capacitor CH from the voltage already stored on CH level with the AD9280’s internal clamp. See Clamp Operation. to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the R (50 Ω) of Switch 1 and quickly (within 1/2 CLK ON C1 R1 V AIN period) settle. This situation corresponds to driving a low input IN R2 I impedance. On the other hand, when the source voltage equals B AD9280 C2 the value previously stored on CH, the hold capacitor requires V BIAS no input current and the equivalent input impedance is ex- tremely high. Adding series resistance between the output of the source and Figure 27. AC Coupled Input the AIN pin reduces the drive requirements placed on the There are additional considerations when choosing the resistor source. Figure 26 shows this configuration. The bandwidth of values. The ac-coupling capacitors integrate the switching tran- the particular application limits the size of this resistor. To sients present at the input of the AD9280 and cause a net dc maintain the performance outlined in the data sheet specifica- bias current, I , to flow into the input. The magnitude of the B tions, the resistor should be limited to 20 Ω or less. For applica- bias current increases as the signal magnitude deviates from tions with signal bandwidths less than 16 MHz, the user may V midscale and the clock frequency increases; i.e., minimum proportionally increase the size of the series resistor. Alterna- bias current flow when AIN = V midscale. This bias current tively, adding a shunt capacitance between the AIN pin and will result in an offset error of (R1 + R2) · I . If it is necessary B analog ground can lower the ac load impedance. The value of to compensate this error, consider making R2 negligibly small or this capacitance will depend on the source resistance and the modifying VBIAS to account for the resultant offset. required signal bandwidth. In systems that must use dc coupling, use an op amp to level- The input span of the AD9280 is a function of the reference shift a ground-referenced signal to comply with the input re- voltages. For more information regarding the input range, see quirements of the AD9280. Figure 28 shows an AD8041 config- the Internal and External Reference sections of the data sheet. ured in noninverting mode. CH +V CC AIN 0.1mF S1 CP SHA S3 NC AD9280 0V 1V p-p 7 DC S2 2 (REFTS CH 1 REFBS) 20V AD8041 6 AIN CP 5 3 AD9280 4 MIDSCALE NC OFFSET VOLTAGE Figure 25. AD9280 Equivalent Input Structure Figure 28. Bipolar Level Shift < 20V AIN V S AD9280 Figure 26. Simple AD9280 Drive Configuration REV. E –14– AD9280 DIFFERENTIAL INPUT OPERATION The pipelined architecture of the AD9280 operates on both The AD9280 will accept differential input signals. This function rising and falling edges of the input clock. To minimize duty may be used by shorting REFTS and REFBS and driving them cycle variations the recommended logic family to drive the clock as one leg of the differential signal (the top leg is driven into input is high speed or advanced CMOS (HC/HCT, AC/ACT) AIN). In the configuration below, the AD9280 is accepting a logic. CMOS logic provides both symmetrical voltage threshold 1 V p-p signal. See Figure 29. levels and sufficient rise and fall times to support 32 MSPS operation. The AD9280 is designed to support a conversion rate of 32 MSPS; running the part at slightly faster clock rates may AD9280 2V be possible, although at reduced performance levels. Conversely, AIN 0.1mF 1V some slight performance improvements might be realized by AVDD/2 REFTF REFTS clocking the AD9280 at slower clock rates. 0.1mF 10mF REFBS 0.1mF S1 S2 VREF REFBF ANALOG S4 t C 1.0mF 0.1mF INPUT S3 REFSENSE t t CH CL INPUT AVDD/2 MODE CLOCK 25ns Figure 29. Differential Input DATA DATA 1 OUTPUT AD876-8 MODE OF OPERATION Figure 31. Timing Diagram The AD9280 may be dropped into the AD876-8 socket. This will allow AD876-8 users to take advantage of the reduced The power dissipated by the output buffers is largely propor- power consumption realized when running the AD9280 on a tional to the clock frequency; running at reduced clock rates 3.0 V analog supply. provides a reduction in power consumption. Figure 30 shows the pin functions of the AD876-8 and AD9280. DIGITAL INPUTS AND OUTPUTS The grounded REFSENSE pin and floating MODE pin effec- Each of the AD9280 digital control inputs, THREE-STATE tively put the AD9280 in the external reference mode. The and STBY are reference to analog ground. The clock is also external reference input for the AD876-8 will now be placed referenced to analog ground. on the reference pins of the AD9280. The format of the digital output is straight binary (see Figure The clamp controls will be grounded by the AD876-8 socket. 32). A low power mode feature is provided such that for STBY The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle = HIGH and the clock disabled, the static power of the AD9280 delay of the AD876-8. will drop below 5 mW. 4V OTR AIN AD9280 2V REFTS 4V REFTF 10mF 0.1mF REFBF 2V 0.1mF 0.1mF REFBS NC MODE AVDD REFSENSE –FS+1LSB +FS CLAMP –FS +FS–1LSB CLAMPIN Figure 32. Output Data Format OTR VREF 0.1mF THREE- STATE Figure 30. AD876 Mode t t DHZ DEN DATA (D0–D9) CLOCK INPUT HIGH The AD9280 clock input is buffered internally with an inverter IMPEDANCE powered from the AVDD pin. This feature allows the AD9280 Figure 33. Three-State Timing Diagram to accommodate either +5 V or +3.3 V CMOS logic input sig- nal swings with the input threshold for the CLK pin nominally at AVDD/2. REV. E –15– AD9280 that the bandlimited IF signal aliases back into the center of the APPLICATIONS ADC’s baseband region (i.e., F /4). For example, if an IF sig- S DIRECT IF DOWN CONVERSION USING THE AD9280 nal centered at 45 MHz is sampled at 20 MSPS, an image of Sampling IF signals above an ADC’s baseband region (i.e., dc this IF signal will be aliased back to 5.0 MHz which corre- to F /2) is becoming increasingly popular in communication S sponds to one quarter of the sample rate (i.e., F /4). This S applications. This process is often referred to as Direct IF Down demodulation technique typically reduces the complexity of the Conversion or Undersampling. There are several potential ben- post digital demodulator ASIC which follows the ADC. efits in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a To maximize its distortion performance, the AD9280 is config- complete mixer stage with its associated amplifiers and filters, ured in the differential mode with a 1 V span using a transformer. reducing cost and power dissipation. Second is the ability to The center tap of the transformer is biased at midsupply via a apply various DSP techniques to perform such functions as resistor divider. Preceding the AD9280 is a bandpass filter as filtering, channel selection, quadrature demodulation, data well as a 32 dB gain stage. A large gain stage may be required reduction, detection, etc. A detailed discussion on using this to compensate for the high insertion losses of a SAW filter used technique in digital receivers can be found in Analog Devices for image rejection. The gain stage will also provide adequate Application Notes AN-301 and AN-302. isolation for the SAW filter from the charge “kick back” currents associated with AD9280’s input stage. In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal The gain stage can be realized using one or two cascaded lying outside the baseband region can be aliased back into the AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz, baseband region in a similar manner that a mixer will down- current-feedback op amp having a 3rd order intercept character- convert an IF signal. Similar to the mixer topology, an image ized up to 250 MHz. A passive bandpass filter following the rejection filter is required to limit other potential interfering AD8009 attenuates its dominant 2nd order distortion products signals from also aliasing back into the ADC’s baseband region. which would otherwise be aliased back into the AD9280’s A tradeoff exists between the complexity of this image rejection baseband region. Also, it reduces any out-of-band noise which filter and the sample rate as well as dynamic range of the ADC. would also be aliased back due to the AD9280’s noise band- width of 220+ MHz. Note, the bandpass filters specifications The AD9280 is well suited for various narrowband IF sampling are application dependent and will affect both the total distor- applications. The AD9280’s low distortion input SHA has a tion and noise performance of this circuit. full-power bandwidth extending to 300 MHz thus encompassing many popular IF frequencies. The AD9280 will typically yield The distortion and noise performance of an ADC at the given an improvement in SNR when configured for the 2 V span, the IF frequency is of particular concern when evaluating an ADC 1 V span provides the optimum full-scale distortion perfor- for a narrowband IF sampling application. Both single-tone and mance. Furthermore, the 1 V span reduces the performance dual-tone SFDR vs. amplitude are very useful in assessing an requirements of the input driver circuitry and thus may be ADC’s noise performance and noise contribution due to aper- more practical for system implementation purposes. ture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the Figure 34 shows a simplified schematic of the AD9280 config- given applications sensitivity to that particular device. ured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation ap- plications, the IF frequency and/or sample rate are selected such G = 20dB G = 12dB L-C 1 2 SAW MINI CIRCUITS BANDPASS AD9280 FILTER 50V T4 - 6T FILTER OUTPUT 50V 1:4 AIN 50V 200V 200V REFTS 280V REFBS 22.1V 93.1V VREF 1.0mF 0.1mF REFSENSE 1kV AVDD 1kV 0.1mF Figure 34. Simplified AD9280 IF Sampling Circuit REV. E –16– AD9280 Figures 35–38 combine the dual-tone SFDR as well as single is referenced to dBc. The AD9280 was operated in the differen- tone SFDR and SNR performance at IF frequencies of 45 MHz, tial mode (via transformer) with a 1 V span. The analog sup- 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli- ply (AVDD) and the digital supply (DRVDD) were set to +5 V tude data is referenced to dBFS while the single tone SNR data and 3.3 V, respectively. 70 80 DUAL TONE SFDR 70 SINGLE TONE SFDR 60 SINGLE TONE SFDR 60 50 DUAL TONE SFDR 50 40 40 30 30 SNR SNR 20 CLK = 25.7MHz CLK = 30.9MHz 20 SINGLE TONE = 45.5MHz SINGLE TONE = 85.5MHz DUAL TONE F1 = 44.5MHz DUAL TONE F1 = 84.5MHz 10 F2 = 45.5MHz 10 F2 = 85.5MHz 0 0 –0.5 –5 –10 –15 –20 –25 –30 –35 –40 –0.5 –5 –10 –15 –20 –25 –30 –35 –40 INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS Figure 35. SNR/SFDR for IF @ 45 MHz Figure 37. SNR/SFDR for IF @ 85 MHz 70 70 SINGLE TONE SFDR DUAL TONE SFDR 60 60 DUAL TONE SFDR SINGLE TONE SFDR 50 50 40 40 30 30 SNR SNR 20 20 FS = 32MHz SINGLE TONE = 135.5MHz CLK = 31.1MHz F1 = 134.5MHz SINGLE TONE = 70.5MHz 10 10 F2 = 135.5MHz DUAL TONE F1 = 69.5MHz F2 = 70.5MHz 0 0 –0.5 –5 –10 –15 –20 –25 –30 –35 –40 –0.5 –5 –10 –15 –20 –25 –30 –35 –40 INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS Figure 36. SNR/SFDR for IF @ 70 MHz Figure 38. SNR/SFDR for IF @ 135 MHz REV. E –17– WORST CASE SFDR – dBFS WORST CASE SPURIOUS – dBFS SNR – dBc SNR – dBc WORST CASE SPURIOUS – dBFS WORST CASE SPURIOUS – dBFS SNR – dBc SNR – dBc AD9280 R10 R11 +3–5A 15kV 5kV R17 +3–5A TP14 AD822 R15 5 316V AD822 0.626V TO 4.8V R7 1kV 7 Q1 2 TP16 5.49kV 4 XXXX U2 2N3906 1 6 U2 ADJ. 3 R8 C7 8 EXTT D1 10kV 0.1mF CW C11 C8 C13 AD1580 C12 0.1mF 10/10V R19 0.1mF 10/10V 178V R9 +3–5A 1.5kV CM R13 11kV R20 TP17 R12 178V C29 AD822 10kV 0.1mF XXXX 2 4 AD822 EXTB ADJ. 1 6 U3 3 C14 C15 7 Q2 8 U3 0.1mF 10/10V 5 2N3904 CW C10 R16 C9 0.1mF 1kV R18 10/10V 316kV TP11 +3–5A J7 JP5 CLAMP R37 1kV DRVDD R53 49.9V JP17 B 1 S3 2 THREE-STATE R38 3 A 1kV B 1 GND S4 2 STBY JP18 3 A R39 1kV 710 13 J8 RN1 AVDD DRVDD 22V 27 J8 611 C16 C19 11 J8 25 0.1mF J8 0.1mF RN1 3 J8 22V C18 C17 2 5 12 J8 10/10V 9 J8 10/10V 4 J8 RN1 22V 28 2 6 J8 OTR 16 8 413 B U4 A AVDD DRVDD 8 J8 TP19 7 15 9 J8 B A U4 WHITE 21 3 RN1 D5 10 J8 B U4 A AD9280 22V D6 20 4 B U4 A 13 12 J8 D7 19 5 U1 OTR 2 15 BU4 A D8 18 6 5 14 J8 J8 B U4 A D9 17 7 RN1 15 3 D0 B U4 A 16 NC J8 DUTCLK CLK 14 B 1 10 16 4 D1 22V B S2 U4 A THREE-STATE THREE-STATE NC 2 24 1 17 18 J8 5 D2 DRVDD VCCB +3–5D VCCA BIT0 116 STBY STBY 23 2 3 18 6 D3 NC1 1 J8 T/R C20 BIT1 C40 20 J8 REFSENSE REFSENSE 22 11 19 7 D4 GD2 0.1mF A RN1 0.1mF OE CLAMP CLAMP BIT2 13 20 8 D5 12 22 J8 22V GD1 GD3 CLAMPIN CLAMPIN BIT3 GND U4 21 9 D6 GND REFTS REFTS BIT4 24 J8 GND GND JP21 22 10 D7 CLK 74LVXC4245WM REFTF REFTF BIT5 23 11 D8 3 1 26 WHITE J8 MODE MODE BIT6 +3–5D 24 12 D9 2 611 REFBF REFBF BIT7 19 5 NC 39 25 J8 CLK B U5 A 33 J8 REFBS REFBS 20 4 26 C42 B U5 RN2 A 28 J8 VREF VREF 21 3 CLK_OUT 27 0.1mF U5 B A 22V AIN AIN 5 12 D0 18 6 29 J8 B U5 A 23 J8 D1 17 7 + AVSS DRVSS B U5 A RN2 30 J8 C33 16 D2 8 U5 B A 22V 10/10V 1 14 D3 15 9 31 J8 B U5 A D4 14 10 4 13 U5 B A 32 21 J8 24 J8 1 +3–5D VCCB VCCA RN2 23 2 34 J8 NC1 T/R C21 DRVDD 22 11 22V NOTE: GD2 0.1mF OE NC 35 J8 13 12 3 14 THE AD9280 IS EXERCISED IN C41 GD1 GD3 U5 19 J8 36 J8 0.1mF AN AD9200 EVALUATION BOARD GND RN2 74LVXC4245WM NC 37 J8 GND 22V GND 38 J8 2 15 32 1 17 J8 40 J8 RN2 JP20 C43 22V 0.1mF GND 1 16 15 J8 GND RN2 22V Figure 39a. Evaluation Board Schematic REV. E –18– AD9280 REFSENSE JP1 JP10 JP14 EXTB AVDD AVDD TP3 C3 JP2 0.1mF TP1 R5 MODE REFBF 10kV C5 TP4 C4 JP15 10/10V 0.1mF + JP9 JP3 REFTF R6 C6 JP4 10kV 0.1mF VREF JP16 B TP5 GND EXTT 1 S5 2 CLAMPIN 3 JP11 GND TP6 A EXTT JP6 REFTS GND JP22 JP12 AVDDCLK AVDD C35 C36 C37 C38 10/10V 0.1mF 0.1mF 0.1mF TP7 R35 REFBS 4.99kV GND JP7 JP13 EXTB R34 2kV CW U6 T1–1T U6 AIN 12 56 J1 3 R36 A 2 4.99kV 3 4 2 S8 TP12 B 1 R1 B 1 TP8 49.9V 6 S6 2 B C30 P 1 3 1 0.1mF S7 JP8 S 2 REFBS T1 A R51 TP9 3 R2 JP26 J5 49.9V 100V C1 A ADC_CLK CM 0.1mF CLK TP10 R4 A R3 TP13 2 DCIN 49.9V 100V R52 3 U6 49.9V 34 S1 C2 1 DUTCLK 47/10V B TP29 L4 +3–5D J9 C32 C31 0.1mF 10/10V TP20 U6 DECOUPLING U6 L1 AVDDCLK 9 8 J2 DRVDD C22 C23 0.1mF U6 10/10V 14 11 10 TP21 74AHC14 PWR L2 C28 U6 U6 0.1mF 12 13 J3 AVDD GND C24 C25 7 0.1mF 33/16V TP22 L3 +3–5A J4 C26 C27 0.1mF 10/10V TP23 TP24 TP25 TP26 TP27 TP28 GND J6 GND J10 Figure 39b. Evaluation Board Schematic REV. E –19– AD9280 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) REV. E –20– AD9280 Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9280 Figure 40e. Evaluation Board Component Silk (Not to Scale) C33 C6 C18 C19 C4 C5 C3 C16 C17 Figure 40f. Evaluation Board Solder Silk (Not to Scale) REV. E –22– AD9280 DIGITAL OUTPUTS GROUNDING AND LAYOUT RULES Each of the on-chip buffers for the AD9280 output bits As is the case for any high performance device, proper ground- (D0–D7) is powered from the DRVDD supply pins, separate ing and layout techniques are essential in achieving optimal from AVDD. The output drivers are sized to handle a variety performance. The analog and digital grounds on the AD9280 of logic families while minimizing the amount of glitch energy have been separated to optimize the management of return generated. In all cases, a fan-out of one is recommended to currents in a system. Grounds should be connected near the keep the capacitive load on the output data bits below the speci- ADC. It is recommended that a printed circuit board (PCB) of fied 20 pF level. at least four layers, employing a ground plane and power planes, be used with the AD9280. The use of ground and power planes For DRVDD = 5 V, the AD9280 output signal swing is com- offers distinct advantages: patible with both high speed CMOS and TTL logic families. For TTL, the AD9280 on-chip, output drivers were designed to 1. The minimization of the loop area encompassed by a signal support several of the high speed TTL families (F, AS, S). For and its return path. applications where the clock rate is below 32 MSPS, other TTL 2. The minimization of the impedance associated with ground families may be appropriate. For interfacing with lower voltage and power paths. CMOS logic, the AD9280 sustains 32 MSPS operation with 3. The inherent distributed capacitor formed by the power plane, DRVDD = 3 V. In all cases, check your logic family data sheets PCB insulation and ground plane. for compatibility with the AD9280 Digital Specification table. These characteristics result in both a reduction of electro- THREE-STATE OUTPUTS magnetic interference (EMI) and an overall improvement in The digital outputs of the AD9280 can be placed in a high performance. impedance state by setting the THREE-STATE pin to HIGH. It is important to design a layout that prevents noise from cou- This feature is provided to facilitate in-circuit testing or evaluation. pling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9280 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. REV. E –23– AD9280 OUTLINE DIMENSIONS 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 1. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE 1 2 Model Temperature Range Package Description Package Option AD9280ARS −40°C to +85°C 28-Lead SSOP RS-28 AD9280ARSRL −40°C to +85°C 28-Lead SSOP RS-28 AD9280ARSZ −40°C to +85°C 28-Lead SSOP RS-28 AD9280ARSZRL −40°C to +85°C 28-Lead SSOP RS-28 AD9280-EB Evaluation Board 1 Z = RoHS Compliant Part. 2 RS = Shrink Small Outline. REVISION HISTORY 8/10—Rev. D to Rev. E Changes to Pin Configuration and Pin Function Descriptions .. 5 Updated Outline Dimensions ........................................................ 24 Changes to Ordering Guide ........................................................... 24 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00582-0-8/10(E) -24- REV. E 060106-A