ANALOG DEVICES AD9273

Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9273 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 1.26 nV/√Hz LOSW-A AD9273 (gain = 21.3 dB) @ 5 MHz typical LO-A SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB LI-A 12-BIT DOUTA+ SERIAL LNA VGA ADC LG-A LVDS DOUTA– Single-ended input; V maximum = 733 mV p-p/ IN AAF LOSW-B 550 mV p-p/367 mV p-p LO-B Dual-mode active input impedance matching LI-B 12-BIT DOUTB+ SERIAL LNA VGA ADC LVDS Bandwidth (BW) > 100 MHz LG-B DOUTB– AAF LOSW-C Full-scale (FS) output = 4.4 V p-p differential LO-C Variable gain amplifier (VGA) LI-C 12-BIT DOUTC+ SERIAL LNA VGA Attenuator range = −42 dB to 0 dB ADC LG-C LVDS DOUTC– AAF LOSW-D SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB LO-D Linear-in-dB gain control LI-D 12-BIT SERIAL DOUTD+ LNA VGA Antialiasing filter (AAF) ADC LG-D LVDS DOUTD– AAF Programmable 2nd-order low-pass filter (LPF) from LOSW-E LO-E 8 MHz to 18 MHz LI-E 12-BIT DOUTE+ SERIAL Programmable high-pass filter (HPF) LNA VGA ADC LG-E LVDS DOUTE– AAF Analog-to-digital converter (ADC) LOSW-F 12 bits at 10 MSPS to 50 MSPS LO-F LI-F DOUTF+ SNR = 70 dB 12-BIT SERIAL LNA VGA ADC LVDS LG-F DOUTF– SFDR = 75 dB AAF LOSW-G Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) LO-G Data and frame clock outputs LI-G DOUTG+ 12-BIT SERIAL LNA VGA LG-G ADC LVDS DOUTG– Includes an 8 × 8 differential crosspoint switch to support AAF LOSW-H continuous wave (CW) Doppler LO-H Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) LI-H 12-BIT SERIAL DOUTH+ LNA VGA ADC 70 mW per channel in CW Doppler LG-H LVDS DOUTH– AAF Flexible power-down modes Overload recovery in <10 ns FCO+ FCO– Fast recovery from low power standby mode, <2 μs REFERENCE DCO+ 100-lead TQFP and 144-ball BGA SWITCH DCO– ARRAY APPLICATIONS Medical imaging/ultrasound Automotive radar GENERAL DESCRIPTION Figure 1. The AD9273 is designed for low cost, low power, small size, and The LNA has a single-ended-to-differential gain that is selectable ease of use. It contains eight channels of a low noise preamplifier through the SPI. The LNA input-referred noise voltage is typically (LNA) with a variable gain amplifier (VGA); an antialiasing 1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to- noise voltage of the entire channel is 1.42 nV/√Hz at typical digital converter (ADC). gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB Each channel features a variable gain range of 42 dB, a fully LNA gain, the input SNR is about 91 dB. In CW Doppler mode, differential signal path, an active input preamplifier termination, a the LNA output drives a transconductance amp that is switched maximum gain of up to 52 dB, and an ADC with a conversion through an 8 × 8 differential crosspoint switch. The switch is rate of up to 50 MSPS. The channel is optimized for dynamic programmable through the SPI. performance and low power in applications where a small package size is critical. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CWD[7:0]+ AND CWD[7:0]– GAIN+ AVDD1 GAIN– AVDD2 PDWN VREF STBY RBIAS CSB SERIAL SCLK PORT INTERFACE SDIO DRVDD DATA CLK+ RATE CLK– MULTIPLIER 07030-001 AD9273 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 21  Applications ....................................................................................... 1  Ultrasound .................................................................................. 21  General Description ......................................................................... 1  Channel Overview ..................................................................... 22  Functional Block Diagram .............................................................. 1  Input Overdrive .......................................................................... 25  Revision History ............................................................................... 2  CW Doppler Operation ............................................................. 25  Product Highlights ........................................................................... 3  TGC Operation ........................................................................... 27  Specif ica t ions ..................................................................................... 4  ADC ............................................................................................. 31  AC Specifications .......................................................................... 4  Clock Input Considerations ...................................................... 31  Digital Specifications ................................................................... 8  Serial Port Interface (SPI) .............................................................. 38  Switching Specifications .............................................................. 9  Hardware Interface ..................................................................... 38  ADC Timing Diagrams ................................................................. 10  Memory Map .................................................................................. 40  Absolute Maximum Ratings .......................................................... 11  Reading the Memory Map Table .............................................. 40  Thermal Impedance ................................................................... 11  Reserved Locations .................................................................... 40  ESD Caution ................................................................................ 11  Default Values ............................................................................. 40  Pin Configuration and Function Descriptions ........................... 12  Logic Levels ................................................................................. 40  Typical Performance Characteristics ........................................... 15  Outline Dimensions ....................................................................... 44  Equivalent Circuits ......................................................................... 19  Ordering Guide .......................................................................... 45  REVISION HISTORY 7/09—Rev. A to Rev. B Changes to Ultrasound Section .................................................... 21 Changes to Low Noise Amplifier (LNA) Section ....................... 22 Added BGA Package .......................................................... Universal Changes to Active Impedance Matching Section and Changes to Features and General Description Sections .............. 1 Figure 40 ...................................................................................... 23 Changes to Product Highlights Section ......................................... 3 Changes to LNA Noise Section .................................................... 24 Changes to Full-Channel (TGC) Characteristics Parameter, Changes to Input Overload Protection Section and Figure 44 ....... 25 Table 1 ............................................................................................ 4 Changes to Figure 48 ...................................................................... 28 Changes to Gain Control Interface Parameter and to CW Changes to Figure 49 and Figure 50............................................. 29 Doppler Mode Parameter, Table 1 .............................................. 6 Changes to Clock Input Considerations Section and to Change to Wake-Up Time (Standby), GAIN+ = 0.8 V Figure 56 to Figure 59 ................................................................ 31 Parameter ....................................................................................... 9 Changes to Digital Outputs and Timing Section ....................... 33 Changes to Figure 2 and Figure 3 ................................................. 10 Changes to CSB Pin Section ......................................................... 36 Changes to Table 4 .......................................................................... 11 Changes to Reading the Memory Map Table Section ............... 40 Addded Figure 5; Renumbered Sequentially .............................. 12 Updated Outline Dimensions ....................................................... 44 Changes to Table 6 .......................................................................... 13 Changes to Ordering Guide .......................................................... 45 Changes to Figure 34 and Figure 35 ............................................. 20 4/09—Revision A: Initial Version Rev. B | Page 2 of 48 AD9273 The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible Fabricated in an advanced CMOS process, the AD9273 is sample rate clock for full performance operation. No external available in a 16 mm × 16 mm, RoHS compliant, 100-lead reference or driver components are required for many TQFP or a 144-ball BGA. It is specified over the industrial applications. temperature range of −40°C to +85°C. The ADC automatically multiplies the sample rate clock for PRODUCT HIGHLIGHTS the appropriate LVDS serial data rate. A data clock (DCO±) for 1. Small Footprint. Eight channels are contained in a small, capturing data on the output and a frame clock (FCO±) trigger space-saving package. A full TGC path, ADC, and crosspoint for signaling a new output byte are provided. switch contained within a 100-lead, 16 mm × 16 mm TQFP or Powering down individual channels is supported to increase a 144-ball BGA. battery life for portable applications. There is also a standby 2. Low Power of 109 mW per Channel at 40 MSPS. mode option that allows quick power-up for power cycling. In 3. Integrated Crosspoint Switch. This switch allows numerous CW Doppler operation, the VGA, AAF, and ADC are powered multichannel configuration options to enable the CW down. The power of the time gain control (TGC) path scales Doppler mode. with selectable speed grades. 4. Ease of Use. A data clock output (DCO±) operates up to 300 MHz and supports double data rate (DDR) operation. The ADC contains several features designed to maximize flexibility 5. User Flexibility. Serial port interface (SPI) control offers a wide and minimize system cost, such as a programmable clock, data range of flexible features to meet specific system requirements. alignment, and programmable digital test pattern generation. The 6. Integrated Second-Order Antialiasing Filter. This filter is digital test patterns include built-in fixed patterns, built-in placed between the VGA and the ADC and is programmable pseudorandom patterns, and custom user-defined test patterns from 8 MHz to 18 MHz. entered via the serial port interface. Rev. B | Page 3 of 48 AD9273 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f = 5 MHz, R = 50 Ω, LNA gain = 21.3 dB, LNA bias =mid- IN S high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f /3 (default), HPF = LPF cutoff/20.7 (default), full temperature, SAMPLE ANSI-644 LVDS mode, unless otherwise noted. Table 1. AD9273-25 AD9273-40 AD9273-50 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit LNA CHARACTERISTICS Gain Single-ended 15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB input to differential output Single-ended 9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB input to single-ended output Input Voltage Range LNA gain = 733/550/367 733/550/367 733/550/367 mV p-p 2 15.6 dB/ SE 17.9 dB/ 21.3 dB, LNA output limited to 4.4 V p-p differential output Input Common 0.9 0.9 0.9 V Mode Input Resistance R = 250 Ω 50 50 50 Ω FB R = 500 Ω 100 100 100 Ω FB R = ∞ 15 15 15 kΩ FB Input Capacitance LI-x 22 22 22 pF −3 dB Bandwidth 70 70 70 MHz Input-Referred LNA gain = 1.6/1.42/1.26 1.6/1.42/1.26 1.6/1.42/1.26 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ Input Noise Current RFB = ∞ 1 1 1 pA/√Hz 1 dB Input Com- LNA gain = 1.0/0.8/0.5 1.0/0.8/0.5 1.0/0.8/0.5 mV p-p pression Point 15.6 dB/ 17.9 dB/ 21.3 dB, GAIN+ = 0 V Noise Figure LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Active Termina- R = 50 Ω, 5.8/5.1/4.3 5.8/5.1/4.3 5.8/5.1/4.3 dB S tion Matched R = 200 Ω/ FB 250 Ω/350 Ω Unterminated R = ∞ 6.3/5.3/4.4 6.3/5.3/4.4 6.3/5.3/4.4 dB FB FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Filter In range, −3 dB, 8 to 18 8 to 18 8 to 18 MHz Cutoff programmable 3 Out of range, 5 to 8, 18 to 35 5 to 8, 18 to 35 5 to 8, 18 to 35 MHz −3 dB, pro- grammable, >>AAF band- width tolerance Rev. B | Page 4 of 48 AD9273 AD9273-25 AD9273-40 AD9273-50 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit AAF Bandwidth In range ±10 ±10 ±10 % Tolerance Group Delay f = 1 MHz to ±2 ±2 ±2 ns Variation 18 MHz, GAIN+ = 0 V to 1.6 V Input-Referred LNA gain = 1.94/1.64/1.38 1.94/1.64/1.38 1.94/1.64/1.38 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, R = ∞ FB Noise Figure LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Active Termina- RS = 50 Ω, 10.3/8.7/6.8 10.3/8.6/6.7 10.3/8.6/6.7 dB tion Matched RFB = 200 Ω/ 250 Ω/350 Ω Unterminated RFB = ∞ 7.1/6.0/4.8 7.1/5.9/4.8 7.1/5.9/4.8 dB Correlated Noise No signal, −30 −30 −30 dB Ratio correlated/ uncorrelated Output Offset −35 +35 −35 +35 −35 +35 LSB Signal-to-Noise fIN = 5 MHz at 65.5 64 63.5 dBFS Ratio (SNR) −10 dBFS, GAIN+ = 0 V f = 5 MHz at 58.5 57 56.5 dBFS IN −1 dBFS, GAIN+ = 1.6 V Harmonic Distortion Second f = 5 MHz at −55 −52 −52 dBc IN Harmonic −10 dBFS, GAIN+ = 0 V f = 5 MHz at −67 −62 −58 dBc IN −1 dBFS, GAIN+ = 1.6 V Third Harmonic f = 5 MHz at −56 −50 −47 dBc IN −10 dBFS, GAIN+ = 0 V fIN = 5 MHz at −61 −56 −55 dBc −1 dBFS, GAIN+ = 1.6 V Two-Tone IMD3 fIN1 = 5.0 MHz at −75 −75 −75 dBc (2 × F1 − F2) −1 dBFS, Distortion fIN2 = 5.01 MHz at −21 dBFS, GAIN+ = 1.6 V, LNA gain = 21.3 dB Channel-to-Channel f = 5.0 MHz at −70 −70 −70 dB IN1 Crosstalk −1 dBFS Overrange −65 −65 −65 dB 4 condition Channel-to-Channel Full TGC path, 0.3 0.3 0.3 Degrees Delay Variation f = 5 MHz, IN GAIN+ = 0 V to 1.6 V PGA GAIN Differential 21/24/27/30 21/24/27/30 21/24/27/30 dB input to differential output Rev. B | Page 5 of 48 AD9273 AD9273-25 AD9273-40 AD9273-50 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit GAIN ACCURACY 25°C Gain Law Confor- 0 V < GAIN+ 1.5 1.5 1.5 dB mance Error < 0.16 V 0.16 V < GAIN+ −1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB < 1.44 V 1.44 V < GAIN+ −2.5 −2.5 −2.5 dB < 1.6 V Linear Gain Error GAIN+ = 0.8 V, −1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB normalized for ideal AAF loss Channel-to-Channel 0.16 V < GAIN+ 0.1 0.1 0.1 dB Matching < 1.44 V GAIN CONTROL INTERFACE Normal Operating 0 1.6 0 1.6 0 1.6 V Range Gain Range GAIN+ = 42 42 42 dB 0 V to 1.6 V Scale Factor 28 28 28 dB/V Response Time 42 dB change 750 750 750 ns Gain+ Impedance Single ended 10 10 10 MΩ Gain− Impedance Single ended 70 70 70 kΩ CW DOPPLER MODE Transconductance Differential, 5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Output Level Range Differential, 1.5 3.6 1.5 3.6 1.5 3.6 V CW Doppler output pins Input-Referred LNA gain = 2.6/2.1/1.6 2.6/2.1/1.6 2.6/2.1/1.6 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞, RL = 675 Ω Input-Referred LNA gain = 160/159/158 160/159/158 160/159/158 dBFS/√Hz Dynamic Range 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ Two-Tone IMD3 fIN1 = 5.0 MHz at −70 −70 −70 dBc (2 × F1 − F2) −1 dBFS (FS at Distortion LNA input), fIN2 = 5.01 MHz at −21 dBFS (FS at LNA input), LNA gain = 21.3 dB Output DC Bias Single ended, 2.4 2.4 2.4 mA per channel Maximum Output Single ended, ±2 ±2 ±2 mA p-p Swing per channel POWER SUPPLY AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V I Full-channel 158 186 223 mA AVDD1 mode CW Doppler 32 32 32 mA mode with four channels enabled Rev. B | Page 6 of 48 AD9273 AD9273-25 AD9273-40 AD9273-50 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit IAVDD2 Full-channel 150 150 150 mA mode CW Doppler 70 70 70 mA mode with four channels enabled I 47 49 50 mA DRVDD Total Power Includes output 819 940 873 996 943 1072 mW Dissipation drivers, full- channel mode, no signal CW Doppler 275 275 275 mW mode with four channels enabled Power-Down 5 5 5 mW Dissipation Standby Power 148 158 170 mW Dissipation Power Supply 1.6 1.6 1.6 mV/V Rejection Ratio (PSRR) ADC RESOLUTION 12 12 12 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV Load Regulation At 1.0 mA, 2 2 2 mV VREF = 1 V Input Resistance 6 6 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 SE = single ended. 3 AAF settings < 5 MHz are out of range and are not supported. 4 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. B | Page 7 of 48 AD9273 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 2. 1 Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF 3 LOGIC OUTPUT (SDIO) Logic 1 Voltage (I = 800 μA) Full 1.79 V OH Logic 0 Voltage (IOL = 50 μA) Full 0.05 V 1 DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH 1 LOW POWER, REDUCED-SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (V) Full 150 250 mV OD Output Offset Voltage (V) Full 1.10 1.30 V OS Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. B | Page 8 of 48 AD9273 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 3. 1 Parameter Temp Min Typ Max Unit 2 CLOCK Clock Rate Full 10 50 MSPS Clock Pulse Width High (tEH) Full 10 ns Clock Pulse Width Low (tEL) Full 10 ns 2, 3 OUTPUT PARAMETERS Propagation Delay (tPD) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns 300 Rise Time (t ) (20% to 80%) Full ps R 300 Fall Time (t ) (20% to 80%) Full ps F FCO± Propagation Delay (t ) Full (t /2) + 1.5 (t /2) + 2.3 (t /2) + 3.1 ns FCO SAMPLE SAMPLE SAMPLE 4 DCO± Propagation Delay (tCPD) Full tFCO + (tSAMPLE/24) ns 4 DCO± to Data Delay (tDATA) Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps 4 DCO± to FCO± Delay (tFRAME) Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps ±100 ±350 Data-to-Data Skew Full ps (t − t ) DATA-MAX DATA-MIN Wake-Up Time (Standby), GAIN+ = 0.8 V 25°C <2 μs 1 Wake-Up Time (Power-Down) 25°C ms 8 Pipeline Latency Full Clock cycles APERTURE <1 Aperture Uncertainty (Jitter) 25°C ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 t /24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. SAMPLE Rev. B | Page 9 of 48 AD9273 ADC TIMING DIAGRAMS N – 1 AIN N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA DOUTx– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7 DOUTx+ Figure 2. 12-Bit Data Serial Stream (Default) N – 1 AIN N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA DOUTx– D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 (LSB) N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 (MSB) DOUTx+ Figure 3. 12-Bit Data Serial Stream, LSB First Rev. B | Page 10 of 48 07030-002 07030-004 AD9273 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD1 GND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AVDD2 GND −0.3 V to +3.9 V maximum rating conditions for extended periods may affect DRVDD GND −0.3 V to +2.0 V device reliability. GND GND −0.3 V to +0.3 V AVDD2 AVDD1 −2.0 V to +3.9 V THERMAL IMPEDANCE AVDD2 DRVDD −2.0 V to +3.9 V Table 5. AVDD1 DRVDD −2.0 V to +2.0 V 1 Airflow Velocity (m/sec) θ θ θ Unit Digital Outputs GND −0.3 V to +2.0 V JA JB JC (DOUTx+, DOUTx−, 0.0 20.3 N/A N/A °C/W DCO+, DCO−, 1.0 14.4 7.6 4.7 °C/W FCO+, FCO−) 2.5 12.9 N/A N/A °C/W CLK+, CLK−, GAIN+, GND −0.3 V to +3.9 V GAIN− 1 θ is for a 4-layer PCB with a solid ground plane (simulated). The exposed JA pad is soldered to the PCB. LI-x, LO-x, LOSW-x LG-x −0.3 V to +2.0 V CWDx−, CWDx+ GND −0.3 V to +3.9 V PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V ESD CAUTION RBIAS, VREF, SDIO GND −0.3 V to +2.0 V Environmental Operating Temperature −40°C to +85°C Range (Ambient) Storage Temperature −65°C to +150°C Range (Ambient) Maximum Junction 150°C Temperature Lead Temperature 300°C (Soldering, 10 sec) Rev. B | Page 11 of 48 AD9273 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 75 LI-D INDICATOR LG-E 2 74 LG-D AVDD2 3 73 AVDD2 AVDD1 4 72 AVDD1 EXPOSED PADDLE, PIN 0 LO-F 5 71 LO-C (BOTTOM OF PACKAGE) LOSW-F 6 70 LOSW-C LI-F 7 69 LI-C AD9273 LG-F 8 68 LG-C TOP VIEW AVDD2 9 (Not to Scale) 67 AVDD2 AVDD1 10 66 AVDD1 LO-G 11 LO-B 65 12 64 LOSW-G LOSW-B LI-G 13 63 LI-B LG-G 14 62 LG-B AVDD2 AVDD2 15 61 AVDD1 16 60 AVDD1 LO-H 17 59 LO-A LOSW-H 18 58 LOSW-A LI-H 19 57 LI-A LG-H 20 56 LG-A AVDD2 21 55 AVDD2 22 54 AVDD1 AVDD1 CLK– 23 53 CSB CLK+ 24 52 SDIO AVDD1 25 51 SCLK NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. Figure 4. TQFP Pin Configuration 2 4 6 8 10 12 1357 9 11 A B C D E F G H J K L M TOP VIEW (Not to Scale) Figure 5. BGA Pin Configuration Rev. B | Page 12 of 48 DRVDD 26 100 LOSW-E DOUTH– 27 99 LO-E DOUTH+ 28 98 CWD7+ DOUTG– 29 97 CWD7– DOUTG+ 30 96 CWD6+ DOUTF– 31 95 CWD6– DOUTF+ 32 94 CWD5+ DOUTE– 33 93 CWD5– DOUTE+ 34 92 CWD4+ DCO– 35 91 CWD4– DCO+ 36 90 VREF FCO– 37 89 RBIAS FCO+ 38 88 GAIN+ DOUTD– 39 87 GAIN– 40 DOUTD+ 86 AVDD2 DOUTC– 41 85 CWD3+ DOUTC+ 42 84 CWD3– DOUTB– 43 83 CWD2+ DOUTB+ 44 82 CWD2– DOUTA– 45 81 CWD1+ 07030-300 DOUTA+ 46 80 CWD1– 47 DRVDD 79 CWD0+ STBY 48 78 CWD0– PDWN 49 77 LO-D AVDD1 50 76 LOSW-D 07030-005 AD9273 Table 6. Pin Function Descriptions Pin No. TQFP BGA Name Description 0 N/A GND Ground (the exposed paddle should be tied to a quiet analog ground) N/A B5, B6, B8, C5, GND Ground C6, C7, C8, D5, D6, D7, D8, E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9, F11, G1, G3, G5, G6, G7, G8, G10, G12, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, J2, K1, K2, M1, M12 4, 10, 16, 22, F1, F3, F5, F8, AVDD1 1.8 V Analog Supply 25, 50, 54, 60, F10, F12, G2, 66, 72 G4, G9, G11 3, 9, 15, 21, 55, B7, E2, E3, E4, AVDD2 3.0 V Analog Supply 61, 67, 73, 86 E9, E10, E11 26, 47 L1, L12 DRVDD 1.8 V Digital Output Driver Supply 1 A1 LI-E LNA Analog Input for Channel E 2 B1 LG-E LNA Ground for Channel E 5 C2 LO-F LNA Analog Inverted Output for Channel F 6 D2 LOSW-F LNA Analog Switched Output for Channel F 7 A2 LI-F LNA Analog Input for Channel F 8 B2 LG-F LNA Ground for Channel F 11 C3 LO-G LNA Analog Inverted Output for Channel G 12 D3 LOSW-G LNA Analog Switched Output for Channel G 13 A3 LI-G LNA Analog Input for Channel G 14 B3 LG-G LNA Ground for Channel G 17 C4 LO-H LNA Analog Inverted Output for Channel H 18 D4 LOSW-H LNA Analog Switched Output for Channel H 19 A4 LI-H LNA Analog Input for Channel H 20 B4 LG-H LNA Ground for Channel H 23 H1 CLK− Clock Input Complement 24 J1 CLK+ Clock Input True 27 M2 DOUTH− ADC H Digital Output Complement 28 L2 DOUTH+ ADC H Digital Output True 29 M3 DOUTG− ADC G Digital Output Complement 30 L3 DOUTG+ ADC G Digital Output True 31 M4 DOUTF− ADC F Digital Output Complement 32 L4 DOUTF+ ADC F Digital Output True 33 M5 DOUTE− ADC E Digital Output Complement 34 L5 DOUTE+ ADC E Digital Output True 35 M6 DCO− Digital Clock Output Complement 36 L6 DCO+ Digital Clock Output True 37 M7 FCO− Frame Clock Digital Output Complement 38 L7 FCO+ Frame Clock Digital Output True 39 M8 DOUTD− ADC D Digital Output Complement 40 L8 DOUTD+ ADC D Digital Output True 41 M9 DOUTC− ADC C Digital Output Complement 42 L9 DOUTC+ ADC C Digital Output True 43 M10 DOUTB− ADC B Digital Output Complement 44 L10 DOUTB+ ADC B Digital Output True Rev. B | Page 13 of 48 AD9273 Pin No. TQFP BGA Name Description 45 M11 DOUTA− ADC A Digital Output Complement 46 L11 DOUTA+ ADC A Digital Output True 48 K11 STBY Standby Power-Down 49 J11 PDWN Full Power-Down 51 K12 SCLK Serial Clock 52 J12 SDIO Serial Data Input/Output 53 H12 CSB Chip Select Bar 56 B9 LG-A LNA Ground for Channel A 57 A9 LI-A LNA Analog Input for Channel A 58 D9 LOSW-A LNA Analog Switched Output for Channel A 59 C9 LO-A LNA Analog Inverted Output for Channel A 62 B10 LG-B LNA Ground for Channel B 63 A10 LI-B LNA Analog Input for Channel B 64 D10 LOSW-B LNA Analog Switched Output for Channel B 65 C10 LO-B LNA Analog Inverted Output for Channel B 68 B11 LG-C LNA Ground for Channel C 69 A11 LI-C LNA Analog Input for Channel C 70 D11 LOSW-C LNA Analog Switched Output for Channel C 71 C11 LO-C LNA Analog Inverted Output for Channel C 74 B12 LG-D LNA Ground for Channel D 75 A12 LI-D LNA Analog Input for Channel D 76 D12 LOSW-D LNA Analog Switched Output for Channel D 77 C12 LO-D LNA Analog Inverted Output for Channel D 78 K10 CWD0− CW Doppler Output Complement for Channel 0 79 J10 CWD0+ CW Doppler Output True for Channel 0 80 K9 CWD1− CW Doppler Output Complement for Channel 1 81 J9 CWD1+ CW Doppler Output True for Channel 1 82 K8 CWD2− CW Doppler Output Complement for Channel 2 83 J8 CWD2+ CW Doppler Output True for Channel 2 84 K7 CWD3− CW Doppler Output Complement for Channel 3 85 J7 CWD3+ CW Doppler Output True for Channel 3 87 A8 GAIN− Gain Control Voltage Input Complement 88 A7 GAIN+ Gain Control Voltage Input True 89 A6 RBIAS External Resistor to Set the Internal ADC Core Bias Current 90 A5 VREF Voltage Reference Input/Output 91 K6 CWD4− CW Doppler Output Complement for Channel 4 92 J6 CWD4+ CW Doppler Output True for Channel 4 93 K5 CWD5− CW Doppler Output Complement for Channel 5 94 J5 CWD5+ CW Doppler Output True for Channel 5 95 K4 CWD6− CW Doppler Output Complement for Channel 6 96 J4 CWD6+ CW Doppler Output True for Channel 6 97 K3 CWD7− CW Doppler Output Complement for Channel 7 98 J3 CWD7+ CW Doppler Output True for Channel 7 99 C1 LO-E LNA Analog Inverted Output for Channel E 100 D1 LOSW-E LNA Analog Switched Output for Channel E Rev. B | Page 14 of 48 AD9273 TYPICAL PERFORMANCE CHARACTERISTICS fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = fSAMPLE/3, HPF = LPF cutoff/20.7 (default), GAIN− = 0.8 V 14 2.0 1.5 12 1.0 10 0.5 –40°C 8 +25°C 0 +85°C 6 –0.5 4 –1.0 2 –1.5 0 –2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) GAIN ERROR (dB) Figure 6. Gain Error vs. GAIN+ at Three Temperatures Figure 9. Gain Error Histogram, GAIN+ = 1.44 V 20 25 18 16 20 14 12 15 10 8 10 6 4 5 2 0 0 –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 GAIN ERROR (dB) CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 7. Gain Error Histogram, GAIN+ = 0.16 V Figure 10. Gain Match Histogram, GAIN+ = 0.3 V 25 14 12 20 10 15 8 6 10 4 5 2 0 0 –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) GAIN ERROR (dB) Figure 11. Gain Match Histogram, GAIN+ = 1.3 V Figure 8. Gain Error Histogram, GAIN+ = 0.8 V Rev. B | Page 15 of 48 GAIN ERROR (dB) PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) –1.0 –1.0 –0.9 –0.9 –0.8 –0.8 –0.7 –0.7 –0.6 –0.6 –0.5 –0.5 –0.4 –0.4 –0.3 –0.3 –0.2 –0.2 –0.1 –0.1 0 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1.0 1.0 07030-185 07030-184 07030-114 PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 07030-181 07030-180 07030-186 AD9273 500k –128 –129 450k –130 400k LNA GAIN = 12× –131 350k –132 300k LNA GAIN = 8× –133 250k –134 200k –135 150k –136 100k –137 LNA GAIN = 6× 50k –138 0 –139 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –7 –6 –5 –4 –3 –2 –1 0 123 45 67 CODES GAIN+ (V) Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V Figure 15. Short-Circuit, Output-Referred Noise vs. GAIN+ 200k 65 180k SNR 160k 60 140k SINAD 120k 55 100k 80k 50 60k 40k 45 20k 0 40 –7 –6 –5 –4 –3 –2 –1 0 123 45 67 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 CODES GAIN+ (V) Figure 13. Output-Referred Noise Histogram, GAIN+ = 1.6 V Figure 16. SNR/SINAD vs. GAIN+, AIN = −1.0 dBFS 3.0 0 –2 50MSPS 2.5 –4 –6 40MSPS 2.0 LNA GAIN = 15.6dB –8 LNA GAIN = 17.9dB 1.5 –10 25MSPS LNA GAIN = 21.3dB –12 1.0 –14 –16 0.5 –18 0 –20 0 5 10 15 20 25 123456789 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Antialiasing Filter (AAF) Pass-Band Response, Figure 14. Short-Circuit, Input-Referred Noise vs. Frequency, LPF Cutoff = 1 × (1/3) × fSAMPLE PGA Gain = 30 dB, GAIN+ = 1.6 V Rev. B | Page 16 of 48 NUMBER OF HITS NUMBER OF HITS INPUT-REFERRED NOISE (nV/√Hz) 07030-187 07030-116 07030-115 OUTPUT-REFERRED NOISE (dBFS/Hz) AMPLITUDE (dBFS) SNR/SINAD(dBFS) 07030-118 07030-120 07030-117 AD9273 150 0 125 –20 100 –40 GAIN+ = 1.6V GAIN+ = 0.8V 75 GAIN+ = 0.8V –60 GAIN+ = 0V GAIN+ = 0V GAIN+ = 1.6V 50 –80 25 –100 0 –120 –40 –35 –30 –25 –20 –15 –10 –5 0 0 5 10 15 20 25 30 35 40 ADC OUTPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 18. Antialiasing Filter (AAF) Group Delay Response Figure 21. Second-Order Harmonic Distortion vs. ADC Output Level 0 0 –10 –20 –20 –30 –40 –40 GAIN+ = 0.8V GAIN+ = 0V –50 –60 GAIN+ = 0.5V –60 –80 –70 GAIN+ = 1.6V GAIN+ = 1.6V –80 GAIN+ = 1.0V –100 –90 –100 –120 0 2 4 6 8 10 12 14 16 –40 –35 –30 –25 –20 –15 –10 –5 0 INPUT FREQUENCY (MHz) ADC OUTPUT LEVEL (dBFS) Figure 19. Second-Order Harmonic Distortion vs. Input Frequency, Figure 22. Third-Order Harmonic Distortion vs. ADC Output Level AIN = −1.0 dBFS 0 0 f = f +0.01MHz IN1 IN2 –10 –10 A 1 = –1dBFS, A 2 = –21dBFS IN IN –20 –20 –30 –30 –40 –40 GAIN+ = 0.5V –50 GAIN+ = 1.6V –50 –60 5MHz 8MHz –60 –70 –70 –80 GAIN+ = 1.0V 2.3MHz –90 –80 02 4 6 8 10 12 14 16 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 INPUT FREQUENCY (MHz) GAIN+ (V) Figure 20. Third-Order Harmonic Distortion vs. Input Frequency, Figure 23. IMD3 vs. GAIN+ AIN = −1.0 dBFS Rev. B | Page 17 of 48 SECOND-ORDER HARMONIC DISTORTION (dBFS) THIRD-ORDER HARMONIC DISTORTION (dBFS) GROUP DELAY (ns) 07030-123 07030-121 07030-122 SECOND-ORDER HARMONIC DISTORTION (dBFS) IMD3 (dBFS) THIRD-ORDER HARMONIC DISTORTION (dBFS) 07030-126 07030-125 07030-124 AD9273 0 f = 5.00MHz, f = 5.01MHz IN1 IN2 FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN+ = 0.8V GAIN+ = 0V –80 –100 GAIN+ = 1.6V –120 –40 –35 –30 –25 –20 –15 –10 –5 0 FUND1 LEVEL (dBFS) Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level Rev. B | Page 18 of 48 IMD3 (dBFS) 07030-127 AD9273 EQUIVALENT CIRCUITS AVDDx V AVDDx CM 15kΩ 350Ω LI-x, SDIO LG-x 30kΩ Figure 25. Equivalent LNA Input Circuit Figure 28. Equivalent SDIO Input Circuit DRVDD AVDDx V V DOUTx– DOUTx+ LO-x, 10Ω V V LOSW-x DRGND Figure 26. Equivalent LNA Output Circuit Figure 29. Equivalent Digital Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ 1kΩ SCLK, PDWN, 10Ω OR STBY CLK– 30kΩ Figure 27. Equivalent Clock Input Circuit Figure 30. Equivalent SCLK, PDWN, or STBY Input Circuit Rev. B | Page 19 of 48 07030-075 07030-073 07030-007 07030-009 07030-008 07030-010 AD9273 AVDDx 100Ω RBIAS AVDD2 50Ω GAIN+ Figure 31. Equivalent RBIAS Circuit Figure 34. Equivalent GAIN+ Input Circuit AVDDx 70kΩ 1kΩ 0.8V CSB AVDD2 70kΩ 50Ω GAIN– Figure 32. Equivalent CSB Input Circuit Figure 35. Equivalent GAIN− Input Circuit 10Ω CWDx+, +0.5V CWDx– VREF 6kΩ Figure 33. Equivalent VREF Circuit Figure 36. Equivalent CWDx± Output Circuit Rev. B | Page 20 of 48 07030-014 07030-011 07030-012 07030-076 07030-176 07030-276 AD9273 THEORY OF OPERATION following the TGC amplifier, and then beam forming is ULTRASOUND accomplished digitally. The primary application for the AD9273 is medical ultrasound. The ADC resolution of 12 bits with up to 50 MSPS sampling Figure 37 shows a simplified block diagram of an ultrasound satisfies the requirements of both general-purpose and high- system. A critical function of an ultrasound system is the time end systems. gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is Power conservation and low cost are two of the most important exponential with respect to distance (time), a linear-in-dB VGA factors in low-end and portable ultrasound machines, and the is the optimal solution. AD9273 is designed to meet these criteria. Key requirements in an ultrasound signal chain are very low noise, For additional information regarding ultrasound systems, refer active input termination, fast overload recovery, low power, and to “How Ultrasound System Considerations Influence Front-End differential drive to an ADC. Because ultrasound machines use Component Choice,” Analog Dialogue, Volume 36, Number 3, beam-forming techniques requiring a large binary-weighted May–July 2002, and “The AD9271—A Revolutionary Solution number of channels (for example, 32 to 512 channels), using the for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3, lowest power at the lowest possible noise is of chief importance. July 2007. Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately Tx HV AMPs BEAM-FORMER Tx BEAM FORMER CENTRAL CONTROL MULTICHANNELS AD9273 HV Rx BEAM FORMER MUX/ LNA VGA ADC T/R (B AND F MODES) DEMUX SWITCHES AAF CW TRANSDUCER ARRAY 128, 256, ETC., ELEMENTS CW (ANALOG) IMAGE AND BIDIRECTIONAL BEAM FORMER SPECTRAL COLOR MOTION CABLE DOPPLER DOPPLER (PW) PROCESSING PROCESSING PROCESSING (B MODE) MODE (F MODE) AUDIO DISPLAY OUTPUT Figure 37. Simplified Ultrasound System Block Diagram Rev. B | Page 21 of 48 07030-077 AD9273 R LO-x FB1 CWD[7:0]+ SWITCH g m ARRAY CWD[7:0]– C FB LOSW-x R FB2 T/R SWITCH C S LI-x DOUTx+ ATTENUATOR SERIAL PIPELINE LNA POSTAMP FILTER –42dB TO 0dB LVDS ADC C DOUTx– SH LG-x C LG 15.6dB, 21dB 17.9dB, 24dB, 21.3dB 27dB, GAIN 30dB INTERPOLATOR AD9273 Figure 38. Simplified Block Diagram of a Single Channel The LNA supports differential output voltages as high as CHANNEL OVERVIEW 4.4 V p-p with positive and negative excursions of ±1.1 V from a Each channel contains both a TGC signal path and a CW Doppler common-mode voltage of 1.5 V. The LNA differential gain sets signal path. Common to both signal paths, the LNA provides user- the maximum input signal before saturation. One of three gains adjustable input impedance termination. The CW Doppler path is set through the SPI. The corresponding full-scale input for includes a transconductance amplifier and a crosspoint switch. the gain settings of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and The TGC path includes a differential X-AMP® VGA, an antialiasing 367 mV p-p, respectively. Overload protection ensures quick filter, and an ADC. Figure 38 shows a simplified block diagram recovery time from large input voltages. Because the inputs are with external components. capacitively coupled to a bias voltage near midsupply, very large The signal path is fully differential throughout to maximize signal inputs can be handled without interacting with the ESD protection. swing and reduce even-order distortion; however, the LNA is Low value feedback resistors and the current-driving capability designed to be driven from a single-ended signal source. of the output stage allow the LNA to achieve a low input-referred Low Noise Amplifier (LNA) noise voltage of 1.26 nV/√Hz at a gain of 21.3 dB. This is achieved Good noise performance relies on a proprietary ultralow noise with a current consumption of only 10 mA per channel (30 mW). LNA at the beginning of the signal chain, which minimizes the On-chip resistor matching results in precise single-ended gains, noise contribution in the following VGA. Active impedance which are critical for accurate impedance control. The use of a control optimizes noise performance for applications that benefit fully differential topology and negative feedback minimizes from input impedance matching. distortion. Low second-order harmonic distortion is particularly important in second-order harmonic ultrasound imaging A simplified schematic of the LNA is shown in Figure 39. LI-x is applications. Differential signaling enables smaller swings at capacitively coupled to the source. An on-chip bias generator each output, further reducing third-order distortion. establishes dc input bias voltages of around 0.9 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by Recommendation 2). A capacitor, CLG, of the same value as the input coupling It is highly recommended that the LG-x pins form a Kelvin type capacitor, CS, is connected from the LG-x pin to ground. connection to the input or probe connection ground. Simply C FB R FB1 connecting the LG pin to ground near the device may allow V + O R FB2 differences in potential to be amplified through the LNA. This V – generally shows up as a dc offset voltage that can vary from O LOSW-x channel to channel and part to part, depending on the LO-x application and layout of the PCB (see Figure 38). V CM V CM T/R SWITCH C S LI-x LG-x C SH C LG Figure 39. Simplified LNA Schematic Rev. B | Page 22 of 48 TRANSDUCER TRANSDUCER 07030-101 GAIN+ GAIN– 07030-071 AD9273 1k Active Impedance Matching R = 500Ω, R = 2kΩ S FB The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output available externally. For example, with a fixed gain of 8× (17.9 dB), an active input R = 200Ω, R = 800Ω S FB termination is synthesized by connecting a feedback resistor R = 100Ω, R = 400Ω, C = 20pF S FB SH between the negative output pin, LO-x, and the positive input pin, 100 LI-x. This well-known technique is used for interfacing multiple R = 50Ω, R = 200Ω, C = 70pF S FB SH probe impedances to a single system. The input resistance is shown in Equation 1. R FB R = (1) IN A (1+ ) 2 10 100k 1M 10M 100M where A/2 is the single-ended gain or the gain from the LI-x FREQUENCY (Hz) inputs to the LO-x outputs, and RFB is the resulting impedance Figure 40. R vs. Frequency for Various Values of R IN FB of the RFB1 and RFB2 combination (see Figure 39). (Effects of R and C Are Also Shown) S SH Because the amplifier has a gain of 8× from its input to its Note that at the lowest value (50 Ω), RIN peaks at frequencies differential output, it is important to note that the gain A/2 is greater than 10 MHz. This is due to the BW roll-off of the LNA, the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the as mentioned previously. gain of the amplifier, or 12.1 dB (4×). The input resistance is However, as can be seen for larger R values, parasitic capacitance IN reduced by an internal bias resistor of 15 kΩ in parallel with the starts rolling off the signal BW before the LNA can produce source resistance connected to Pin LI-x while Pin LG-x is ac further degrades the match; therefore, C should peaking. CSH SH grounded. Equation 2 can be used to calculate the needed RFB not be used for values of RIN that are greater than 100 Ω. Table 7 for a desired RIN, even for higher values of RIN. lists the recommended values for RFB and CSH in terms of RIN. R FB (2) R = ||15 kΩ CFB is needed in series with RFB because the dc levels at Pin LO-x IN (1+ 3) and Pin LI-x are unequal. For example, to set RIN to 200 Ω, the value of RFB must be Table 7. Active Termination External Component Values 1000 Ω. If the simplified equation (Equation 2) is used to LNA Gain Minimum calculate RIN, the value is 188 Ω, resulting in a gain error less (dB) R (Ω) R (Ω) C (pF) BW (MHz) IN FB SH than 0.6 dB. Some factors, such as the presence of a dynamic 15.6 50 200 90 57 source resistance, might influence the absolute gain accuracy 17.9 50 250 70 69 more significantly. At higher frequencies, the input capacitance 21.3 50 350 50 88 of the LNA needs to be considered. The user must determine 15.6 100 400 30 57 accordingly. the level of matching accuracy and adjust RFB 17.9 100 500 20 69 The bandwidth (BW) of the LNA is greater than 100 MHz. 21.3 100 700 10 88 Ultimately, the BW of the LNA limits the accuracy of the 15.6 200 800 N/A 72 synthesized RIN. For RIN = RS up to about 200 Ω, the best match 17.9 200 1000 N/A 72 is between 100 kHz and 10 MHz, where the lower frequency 21.3 200 1400 N/A 72 limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and R limit the BW at higher frequencies. S Figure 40 shows RIN vs. frequency for various values of RFB. Rev. B | Page 23 of 48 INPUT RESISTANCE (Ω) 07030-188 AD9273 Figure 42 shows the relative noise figure performance. In this LNA Noise graph, the input impedance was swept with R to preserve the S The short-circuit noise voltage (input-referred noise) is an impor- match at each point. The noise figures for a source impedance of tant limit on system performance. The short-circuit input-referred 50 Ω are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination, noise voltage for the LNA is 1.4 nV/√Hz at a gain of 21.3 dB, active termination, and unterminated configurations, respectively. including the VGA noise at a VGA postamp gain of 27 dB. These The noise figures for 200 Ω are 4.5 dB, 1.7 dB, and 1.0 dB, measurements, which were taken without a feedback resistor, respectively. provide the basis for calculating the input noise and noise figure Figure 43 shows the noise figure as it relates to R for various values (NF) performance of the configurations shown in Figure 41. S of R , which is helpful for design purposes. IN UNTERMINATED R IN R S 12.0 + V OUT LI-x – 10.5 RESISTIVE TERMINATION 9.0 R IN R SHUNT TERMINATION S 7.5 + R V S OUT LI-x 6.0 – 4.5 UNTERMINATED ACTIVE TERMINATION ACTIVE IMPEDANCE MATCH 3.0 R R FB IN R S 1.5 + V OUT LI-x 0 – 10 100 1k R (Ω) S R FB R = Figure 42. Noise Figure vs. RS for Shunt Termination, IN 1 + A/2 Active Termination Matched, and Unterminated Inputs, VGAIN = 0.8 V Figure 41. Input Configurations 12.0 Figure 42 and Figure 43 are simulations of noise figure vs. source UNTERMINATED 10.5 R = 200Ω resistance (RS) results using these configurations and an input- IN R = 100Ω IN 9.0 referred noise voltage of 6 nV/√Hz for the VGA. Unterminated R = 75Ω IN R = 50Ω (RFB = ∞) operation exhibits the lowest equivalent input noise IN 7.5 and noise figure. Figure 43 shows the noise figure vs. RS rising at 6.0 low R —where the LNA voltage noise is large compared with the S source noise—and at high R due to the noise contribution from S 4.5 R . The lowest NF is achieved when R matches R . FB S IN 3.0 The main purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the 1.5 input noise increases due to the thermal noise of the matching 0 resistor and the increased contribution of the LNA’s input 10 100 1k R (Ω) S voltage noise generator. With active impedance matching, Figure 43. Noise Figure vs. RS for Various Fixed Values of RIN, however, the contributions of both are smaller (by a factor of Active Termination Matched Inputs, VGAIN = 0.8 V 1/(1 + LNA Gain)) than they would be for resistive termination. Rev. B | Page 24 of 48 07030-104 NOISE FIGURE (dB) NOISE FIGURE (dB) 07030-183 07030-182 AD9273 INPUT OVERDRIVE CW DOPPLER OPERATION Excellent overload behavior is of primary importance in Modern ultrasound machines used for medical applications N ultrasound. Both the LNA and VGA have built-in overdrive employ a 2 binary array of receivers for beam forming, with protection and quickly recover after an overload event. typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When Input Overload Protection used in multiples, the desired signals from each channel can be As with any amplifier, voltage clamping prior to the inputs is summed to yield a larger signal (increased by a factor N, where highly recommended if the application is subject to high N is the number of channels), and the noise is increased by the transient voltages. square root of the number of channels. This technique enhances In Figure 44, a simplified ultrasound transducer interface is the signal-to-noise performance of the machine. The critical shown. A common transducer element serves the dual functions elements in a beam-former design are the means to align the of transmitting and receiving ultrasound energy. During the incoming signals in the time domain and the means to sum the transmitting phase, high voltage pulses are applied to the ceramic individual signals into a composite whole. elements. A typical transmit/receive (T/R) switch can consist of Beam forming, as applied to medical ultrasound, is defined as the four high voltage diodes in a bridge configuration. Although the phase alignment and summation of signals that are generated diodes ideally block transmit pulses from the sensitive receiver from a common source but received at different times by a input, diode characteristics are not ideal, and the resulting leakage multielement ultrasound transducer. Beam forming has two transients imposed on the LI-x inputs can be problematic. functions: it imparts directivity to the transducer, enhancing its Because ultrasound is a pulse system and time-of-flight is used to gain, and it defines a focal point within the body from which the determine depth, quick recovery from input overloads is essential. location of the returning echo is derived. Overload can occur in the preamp and the VGA. Immediately The AD9273 includes the front-end components needed to following a transmit pulse, the typical VGA gains are low, and implement analog beam forming for CW Doppler operation. the LNA is subject to overload from T/R switch leakage. With These components allow CW channels with similar phases to be increasing gain, the VGA can become overloaded due to strong coherently combined before phase alignment and down mixing, echoes that occur near field echoes and acoustically dense materials, thus reducing the number of delay lines or adjustable phase shifters/ such as bone. down mixers (AD8333 or AD8339) required. Next, if delay lines Figure 44 illustrates an external overload protection scheme. A are used, the phase alignment is performed, and then the channels pair of back-to-back signal diodes is installed prior to installing the are coherently summed and down converted by a dynamic range ac-coupling capacitors. Keep in mind that all diodes shown in I/Q demodulator. Alternatively, if phase shifters/down mixers, this example are prone to exhibiting some amount of shot noise. such as the AD8333 and AD8339, are used, phase alignment Many types of diodes are available for achieving the desired noise and downconversion are done before coherently summing all performance. The configuration shown in Figure 44 tends to add channels into I/Q signals. In either case, the resultant I and Q 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ resistor signals are filtered and sampled by two high resolution ADCs, and increasing the 2 kΩ resistor may improve noise contribution, and the sampled signals are processed to extract the relevant depending on the application. With the diodes shown in Figure 44, Doppler information. clamping levels of ±0.5 V or less significantly enhance the overload Alternately, the LNA of the AD9273 can directly drive the AD8333 performance of the system. or AD8339 without the crosspoint switch. The LO-x pins present +5V the inverting LNA output, and the LOSW-x pins can be configured Tx 5kΩ via Register 0x2C (see Table 17) to connect to the noninverting DRIVER HV AD9273 output to provide a differential output of the LNA. The LNA output 10nF full-scale voltage of the AD9273 is 4.4 V p-p, and the input full- LNA scale voltage is 2.7 V p-p. If no attenuation is provided between 2kΩ 10nF 5kΩ the LNA output and the demodulator, the LNA input full-scale TRANSDUCER voltage must be limited. –5V Figure 44. Input Overload Protection Rev. B | Page 25 of 48 07030-100 AD9273 AD9273 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m AD8333 600µH g LNA 2.5V 700Ω m 600µH 600µH 2.5V 700Ω 600µH AD8333 AD9273 600µH 2.5V 700Ω LNA g 600µH m 600µH LNA g m 2.5V 700Ω 600µH SWITCH ARRAY I 8 × CHANNEL 16-BIT ADC LNA g m Q 16-BIT LNA g ADC m Figure 45. Typical Connection Interface with the AD8333 or AD8339 using the CWDx± Outputs 2.5V AD9273 5kΩ 5kΩ 1nF LO-A AD8339 500Ω LNA LOSW-A 500Ω 1nF 2.5V 5kΩ 5kΩ 1nF LOS-B 500Ω LNA LOSW-B 500Ω 1nF 2.5V 5kΩ 5kΩ 1nF AD8339 LO-H 500Ω LNA I LOSW-H 16-BIT 500Ω 1nF ADC Q 16-BIT ADC Figure 46. Typical Connection Interface with the AD8333 or AD8339 using the LO-x and LOSW-x Outputs Rev. B | Page 26 of 48 07030-111 07030-096 AD9273 Crosspoint Switch The maximum gain required is determined by Each LNA is followed by a transconductance amp for voltage- (ADC Noise Floor/VGA Input Noise Floor) + Margin = to-current conversion. Currents can be routed to one of eight 20 log(224/5.4) + 11 dB = 43 dB pairs of differential outputs or to 16 single-ended outputs for The minimum gain required is determined by summing. Each CWD output pin sinks 2.4 mA dc current, and (ADC Input FS/VGA Input FS) + Margin = the signal has a full-scale current of ±2 mA for each channel 20 log(2/0.55) – 10 dB = 3 dB selected by the crosspoint switch. For example, if four channels are summed on one CWD output, the output sinks 9.6 mA dc Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with and has a full-scale current output of ±8 mA. 15 MHz of bandwidth should suffice in achieving the dynamic range required for most of today’s ultrasound systems. The maximum number of channels combined must be considered when setting the load impedance for current-to-voltage conversion The system gain is distributed as listed in Table 8. to ensure that the full-scale swing and common-mode voltage Table 8. Channel Gain Distribution are within the operating limits of the AD9273. When interfacing Section Nominal Gain (dB) to the AD8339, a common-mode voltage of 2.5 V and a full-scale LNA 15.6/17.9/21.3 swing of 2.8 V p-p are desired. This can be accomplished by Attenuator −42 to 0 connecting an inductor between each CWD output and a 2.5 V VGA Amp 21/24/27/30 supply, and then connecting either a single-ended or differential Filter 0 load resistance to the CWDx± outputs. The value of resistance ADC 0 should be calculated based on the maximum number of channels that can be combined. The linear-in-dB gain (law conformance) range of the TGC path CWDx± outputs are required under full-scale swing to be is 42 dB. The slope of the gain control interface is 28 dB/V, and greater than 1.5 V and less than AVDD2 (3.0 V supply). the gain control range is −0.8 V to +0.8 V. Equation 3 is the TGC OPERATION expression for the differential voltage VGAIN, and Equation 4 is The TGC signal path is fully differential throughout to maximize the expression for the channel gain. signal swing and reduce even-order distortion; however, the LNAs V (V)= GAIN(+)− GAIN(−) (3) GAIN are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the dB Gain (dB)= 28 V + ICPT (4) GAIN differential ADC input. A simple exercise in understanding the V maximum and minimum gain requirements is shown in Figure 47. where ICPT is the intercept point of the TGC gain. In its default condition, the LNA has a gain of 21.3 dB (12×) and ADC FS (2V p-p) MINIMUM GAIN ~10dB MARGIN the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is LNA FS 0 V and the voltage on the GAIN− pin is 0.8 V (42 dB attenuation). 70dB ADC (0.55V p-p SE) This gives rise to a total gain (or ICPT) of 3.6 dB through the 91dB TGC path if the LNA input is unmatched, or of −2.4 dB if the >11dB MARGIN LNA ADC NOISE FLOOR LNA is matched to 50 Ω (RFB = 350 Ω). If the voltage on the (224µV rms) GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0.8 V MAXIMUM GAIN (0 dB attenuation), however, the VGA gain is 24 dB. This results LNA INPUT-REFERRED NOISE FLOOR in a total gain of 45 dB through the TGC path if the LNA input is (5.4µV rms) @ AAF BW = 15MHz LNA + VGA NOISE = 1.4nV/ Hz VGA GAIN RANGE > 42dB unmatched, or in a total gain of 39 dB if the LNA input is matched. MAX CHANNEL GAIN > 48dB Figure 47. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of −42 dB to 0 dB followed by an amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. Rev. B | Page 27 of 48 07030-097 AD9273 1, 2, 3 Table 9. Sensitivity and Dynamic Range of Trade-Offs LNA Channel Gain Typical Output Dynamic Range Input-Referred 6 Full-Scale Input Noise Voltage VGA Input-Referred Noise @ 4 5 (V/V) (dB) (V p-p) (nV/√Hz) Postamp Gain (dB) GAIN+ = 0 V GAIN+ = 1.6 V GAIN+ = 1.6 V (nV/√Hz) 6 15.6 0.733 1.6 21 65.9 62.3 1.98 24 64.1 59.7 1.91 27 61.8 57.0 1.87 30 59.2 54.1 1.85 8 17.9 0.550 1.42 21 65.9 61.6 1.66 24 64.1 58.9 1.61 27 61.8 56.2 1.58 30 59.2 53.3 1.57 12 21.3 0.367 1.26 21 65.9 60.1 1.35 24 64.1 57.3 1.32 27 61.8 54.4 1.31 30 59.2 51.5 1.30 1 LNA: output full scale = 4.4 V p-p differential. 2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V. 3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input. 4 Output dynamic range at minimum VGA gain (VGA dominated). 5 Output dynamic range at maximum VGA gain (LNA dominated). 6 Channel noise at maximum VGA gain. Table 9 demonstrates the sensitivity and dynamic range of GAIN+ and GAIN− pins. The LNA has three limitations, or full- trade-offs that can be achieved relative to various LNA and scale settings, that can be applied through the SPI. Similarly, the VGA gain settings. VGA has four postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN± pins determines For example, when the VGA is set for the minimum gain voltage, which amplifier (the LNA or VGA) saturates first. The maximum the TGC path is dominated by VGA noise and achieves the signal input level that can be applied as a function of voltage on maximum output SNR. However, as the postamp gain options the GAIN± pins for the selectable gain options of the SPI is shown are increased, the input-referred noise is reduced and the SNR in Figure 48 to Figure 50. is degraded. 0.40 If the VGA is set for the maximum gain voltage, the TGC path 0.35 is dominated by LNA noise and achieves the lowest input- PGA GAIN = 21dB referred noise, but with degraded output SNR. The higher the 0.30 TGC (LNA + VGC) gain, the lower the output SNR. As the PGA GAIN = 24dB 0.25 postamp gain is increased, the input-referred noise is reduced. PGA GAIN = 27dB At low gains, the VGA should limit the system noise perfor- 0.20 mance (SNR); at high gains, the noise is defined by the source and 0.15 the LNA. The maximum voltage swing is bound by the full- PGA GAIN = 30dB 0.10 scale peak-to-peak ADC input voltage (2 V p-p). Both the LNA and VGA have full-scale limitations within each 0.05 section of the TGC path. These limitations are dependent on the 0 gain setting of each function block and on the voltage applied to the 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 48. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations Rev. B | Page 28 of 48 INPUT FULL-SCALE (V p-p) 07030-117 AD9273 0.6 per side is 180 Ω nominally for a total differential resistance of PGA GAIN = 21dB 360 Ω. The ladder is driven by a fully differential input signal from 0.5 the LNA. LNA outputs are dc-coupled to avoid external decoupling PGA GAIN = 24dB capacitors. The common-mode voltage of the attenuator and the 0.4 VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA 0.3 to the VGA without introducing large offsets due to common- mode differences. However, any offset from the LNA becomes 0.2 amplified as the gain increases, producing an exponentially PGA GAIN = 27dB increasing VGA output offset. 0.1 The input stages of the X-AMP are distributed along the ladder, PGA GAIN = 30dB and a biasing interpolator, controlled by the gain interface, deter- 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 mines the input tap point. With overlapping bias currents, signals GAIN+ (V) from successive taps merge to provide a smooth attenuation range Figure 49. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations from −42 dB to 0 dB. This circuit technique results in linear-in-dB 0.9 gain law conformance and low distortion levels—only deviating 0.8 ±0.5 dB or less from the ideal. The gain slope is monotonic with PGA GAIN = 21dB respect to the control voltage and is stable with variations in 0.7 process, temperature, and supply. 0.6 PGA GAIN = 24dB The X-AMP inputs are part of a programmable gain feedback 0.5 amplifier that completes the VGA. Its bandwidth is approximately 0.4 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity 0.3 across the gain setting. 0.2 Gain Control PGA GAIN = 27dB 0.1 The gain control interface, GAIN±, is a differential input. VGAIN PGA GAIN = 30dB 0 varies the gain of all VGAs through the interpolator by selecting 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) the appropriate input stages connected to the input attenuator. Figure 50. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations For GAIN− at 0.8 V, the nominal GAIN+ range for 28 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to Variable Gain Amplifier 1.44 V, where the error is typically less than ±0.5 dB. For The differential X-AMP VGA provides precise input attenuation GAIN+ voltages greater than 1.44 V and less than 0.16 V, the and interpolation. It has a low input-referred noise of 6 nV/√Hz error increases. The value of GAIN+ can exceed the supply and excellent gain linearity. A simplified block diagram is shown in voltage by 1 V without gain foldover. Figure 51. Gain control response time is less than 750 ns to settle within 10% GAIN± GAIN INTERPOLATOR of the final value for a change from minimum to maximum gain. POSTAMP + There are two ways in which the GAIN+ and GAIN− pins can g be interfaced. With the single-ended method, a Kelvin type of m connection to ground can be used as shown in Figure 52. For 3dB VIP driving multiple devices, it is preferable to use the differential method shown in Figure 53. In either method, the GAIN+ and VIN GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input. AD9273 100Ω 0V TO 1.6V DC GAIN+ – POSTAMP 0.01µF 50Ω Figure 51. Simplified VGA Schematic GAIN– KELVIN 0.01µF CONNECTION The input of the VGA is a 14-stage differential resistor ladder with Figure 52. Single-Ended GAIN± Pins Configuration 3.5 dB per tap. The resulting total gain range is 42 dB, which allows for range loss at the endpoints. The effective input resistance Rev. B | Page 29 of 48 INPUT FULL-SCALE (V p-p) INPUT FULL-SCALE (V p-p) 07030-179 07030-178 07030-078 07030-109 AD9273 499Ω AVDD2 The antialaising filter is a combination of a single-pole high- pass filter and a second-order low-pass filter. The high-pass AD9273 ±0.4VDC AT 31.3kΩ 499Ω 100Ω 0.8V CM filter can be configured at a ratio of the low-pass filter cutoff. GAIN+ ±0.8V DC 0.01µF 0.8V CM 50Ω AD8138 This is selectable through the SPI. 100Ω 523Ω GAIN– 10kΩ The filter uses on-chip tuning to trim the capacitors and in turn ±0.4VDC AT 0.01µF 0.8V CM set the desired cutoff frequency and reduce variations. The 499Ω default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC Figure 53. Differential GAIN± Pins Configuration sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, VGA Noise 1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz. In a typical application, a VGA compresses a wide dynamic 4kΩ range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable C input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous 30C 4kΩ 2kΩ dynamic range that can be processed at any one particular gain 4C 10kΩ/n control voltage. This latter limit is set in accordance with the 2kΩ total noise floor of the ADC. 4kΩ 30C C Output-referred noise as a function of GAIN+ is shown in Figure 15 for the short-circuit input conditions. The input noise voltage is C = 0.8pF TO 5.1pF 4kΩ n = 0 TO 7 simply equal to the output noise divided by the measured gain Figure 54. Simplified Filter Schematic at each point in the control range. Tuning is normally off to avoid changing the capacitor settings The output-referred noise is a flat 90 nV/√Hz (postamp gain = during critical times. The tuning circuit is enabled and disabled 24 dB) over most of the gain range because it is dominated by through the SPI. Initializing the tuning of the filter must be the fixed output-referred noise of the VGA. At the high end of performed after initial power-up and after reprogramming the the gain control range, the noise of the LNA and of the source filter cutoff scaling or ADC sample rate. Occasional retuning prevail. The input-referred noise reaches its minimum value during an idle time is recommended to compensate for near the maximum gain control voltage, where the input- temperature drift. referred contribution of the VGA is miniscule. There is a total of eight SPI-programmable settings that allow the At lower gains, the input-referred noise, and therefore the noise user to vary the high-pass filter cutoff frequency as a function figure, increases as the gain decreases. The instantaneous of the low-pass cutoff frequency. Two examples are shown in dynamic range of the system is not lost, however, because the Table 10: one is for an 8 MHz low-pass cutoff frequency, and the input capacity increases as the input-referred noise increases. other is for an 18 MHz low-pass cutoff frequency. In both cases, The contribution of the ADC noise floor has the same as the ratio decreases, the amount of rejection on the low-end dependence. The important relationship is the magnitude of the frequencies increases. Therefore, making the entire AAF VGA output noise floor relative to that of the ADC. frequency pass band narrow can reduce low frequency noise or Gain control noise is a concern in very low noise applications. maximize dynamic range for harmonic processing. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output Table 10. SPI-Selectable High-Pass Filter Cutoff Options signal level and is usually evident only when a large signal is High-Pass Cutoff present. The gain interface includes an on-chip noise filter, which Low-Pass Cutoff Low-Pass Cutoff 1 significantly reduces this effect at frequencies greater than 5 MHz. SPI Setting Ratio = 8 MHz = 18 MHz Care should be taken to minimize noise impinging at the GAIN± 0 20.65 387 kHz 872 kHz inputs. An external RC filter can be used to remove V source GAIN 1 11.45 698 kHz 1.571 MHz noise. The filter bandwidth should be sufficient to accommodate 2 7.92 1.010 MHz 2.273 MHz the desired control bandwidth. 3 6.04 1.323 MHz 2.978 MHz 4 4.88 1.638 MHz 3.685 MHz Antialiasing Filter 5 4.10 1.953 MHz 4.394 MHz The filter that the signal reaches prior to the ADC is used to 6 3.52 2.270 MHz 5.107 MHz reject dc signals and to band limit the signal for antialiasing. 7 3.09 2.587 MHz 5.822 MHz Figure 54 shows the architecture of the filter. 1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency. Rev. B | Page 30 of 48 07030-098 07030-110 AD9273 3.3V ADC AD951x/AD952x * 50Ω FAMILY VFAC3 0.1µF 0.1µF The AD9273 uses a pipelined ADC architecture. The quantized OUT CLK CLK+ output from each stage is combined into a 12-bit result in the ADC 100Ω digital correction logic. The pipelined architecture permits the LVDS DRIVER AD9273 0.1µF 0.1µF first stage to operate on a new input sample and the remaining CLK– CLK stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. * 50Ω RESISTOR IS OPTIONAL. The output staging block aligns the data, corrects errors, and Figure 57. Differential LVDS Sample Clock passes the data to the output buffers. The data is then serialized In some applications, it is acceptable to drive the sample clock and aligned to the frame and output clocks. inputs with a single-ended CMOS signal. In such applications, CLOCK INPUT CONSIDERATIONS CLK+ should be driven directly from a CMOS gate, and the For optimum performance, the AD9273 sample clock inputs CLK− pin should be bypassed to ground with a 0.1 μF capacitor (CLK+ and CLK−) should be clocked with a differential signal. in parallel with a 39 kΩ resistor (see Figure 58). Although the This signal is typically ac-coupled into the CLK+ and CLK− pins CLK+ input circuit supply is AVDDx (1.8 V), this input is via a transformer or using capacitors. These pins are biased designed to withstand input voltages of up to 3.3 V, making the internally and require no additional bias. selection of the drive logic voltage very flexible. 3.3V Figure 55 shows the preferred method for clocking the AD9273. AD951x/AD952x FAMILY A low jitter clock source, such as the Valpey Fisher oscillator 0.1µF VFAC3 CLK OUT VFAC3-BHL-50MHz, is converted from single ended to OPTIONAL 0.1µF * 50Ω 100Ω differential using an RF transformer. The back-to-back Schottky CMOS DRIVER CLK+ ADC diodes across the secondary transformer limit clock excursions CLK AD9273 into the AD9273 to approximately 0.8 V p-p differential. This 0.1µF CLK– helps prevent the large voltage swings of the clock from feeding 0.1µF 39kΩ through to other portions of the AD9273, and it preserves the * 50Ω RESISTOR IS OPTIONAL. fast rise and fall times of the signal, which are critical to low jitter performance. Figure 58. Single-Ended 1.8 V CMOS Sample Clock 3.3V 3.3V AD951x/AD952x FAMILY MINI-CIRCUITS 0.1µF VFAC3 ADT1-1WT, 1:1Z CLK OUT 0.1µF 0.1µF OPTIONAL XFMR 0.1µF * OUT CLK+ 50Ω 100Ω CLK+ CMOS DRIVER 100Ω ADC 50Ω 0.1µF AD9273 VFAC3 ADC CLK– CLK AD9273 0.1µF 0.1µF SCHOTTKY 0.1µF CLK– DIODES: HSM2812 Figure 55. Transformer-Coupled Differential Clock * 50Ω RESISTOR IS OPTIONAL. If a low jitter clock is available, another option is to ac-couple a Figure 59. Single-Ended 3.3 V CMOS Sample Clock differential PECL signal to the sample clock input pins as shown Clock Duty Cycle Considerations in Figure 56. The AD951x/AD952x family of clock drivers offers Typical high speed ADCs use both clock edges to generate a excellent jitter performance. variety of internal timing signals. As a result, these ADCs may 3.3V AD951x/AD952x be sensitive to the clock duty cycle. Commonly, a 5% tolerance is * 50Ω FAMILY VFAC3 required on the clock duty cycle to maintain dynamic performance 0.1µF 0.1µF OUT CLK CLK+ characteristics. The AD9273 contains a duty cycle stabilizer (DCS) ADC 100Ω that retimes the nonsampling edge, providing an internal clock PECL DRIVER AD9273 0.1µF 0.1µF signal with a nominal 50% duty cycle. This allows a wide range CLK– CLK 240Ω 240Ω of clock input duty cycles without affecting the performance of the AD9273. When the DCS is on, noise and distortion perfor- * 50Ω RESISTOR IS OPTIONAL. mance are nearly flat for a wide range of duty cycles. However, Figure 56. Differential PECL Sample Clock some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 17 for more details on using this feature. Rev. B | Page 31 of 48 07030-050 07030-051 07030-054 07030-053 07030-052 AD9273 250 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles I , 50MSPS SPEED GRADE 200 AVDD1 to allow the DLL to acquire and lock to the new rate. I , 40MSPS SPEED GRADE AVDD1 Clock Jitter Considerations 150 High speed, high resolution ADCs are sensitive to the quality of the I , 25MSPS SPEED GRADE AVDD1 clock input. The degradation in SNR at a given input frequency (f ) A 100 due only to aperture jitter (t ) can be calculated by J SNR Degradation = 20 × log 10[1/2 × π × f × t ] A J 50 I DRVDD In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input 0 0 10 20 30 40 50 signal, and ADC aperture jitter. IF undersampling applications SAMPLING FREQUENCY (MSPS) are particularly sensitive to jitter (see Figure 60). Figure 61. Supply Current vs. f for f = 5 MHz SAMPLE IN The clock input should be treated as an analog signal in cases 120 where aperture jitter may affect the dynamic range of the AD9273. 115 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal 50MSPS SPEED GRADE 110 with digital noise. Low jitter, crystal-controlled oscillators make 105 the best clock sources, such as the Valpey Fisher VFAC3 series. 40MSPS SPEED GRADE If the clock is generated from another type of source (by gating, 100 dividing, or other methods), it should be retimed by the 95 original clock during the last step. 25MSPS SPEED GRADE Refer to the AN-501 Application Note and the AN-756 90 Application Note for more in-depth information about how 85 jitter performance relates to ADCs (visit www.analog.com). 80 130 0 10 20 30 40 50 RMS CLOCK JITTER REQUIREMENT 120 SAMPLING FREQUENCY (MSPS) Figure 62. Power per Channel vs. f for f = 5 MHz 110 SAMPLE IN 16 BITS 100 The AD9273 features scalable LNA bias currents (see Register 0x12 in Table 17). The default LNA bias current settings are high. 90 14 BITS Figure 63 shows the typical reduction of AVDD2 current with 80 12 BITS each bias setting. It is also recommended to adjust the LNA 70 10 BITS offset using Register 0x10 (see Table 17) when the LNA bias 60 setting is low. 0.125ps 8 BITS 50 0.25ps 0.5ps 1.0ps 40 HIGH 2.0ps 30 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) MID-HIGH Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 62, the power dissipated by the AD9273 is MID-LOW proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. LOW 0 204060 80 100 120 140 160 180 TOTAL AVDD2 CURRENT (mA) Figure 63. AVDD2 Current at Different LNA Bias Settings, AD9273-40 Rev. B | Page 32 of 48 SNR (dB) 07030-038 LNA BIAS SETTING POWER/CHANNEL (mW) SUPPLY CURRENT (mA) 07030-031 07030-032 07030-119 AD9273 By asserting the PDWN pin high, the AD9273 is placed into The AD9273 LVDS outputs facilitate interfacing with LVDS power-down mode. In this state, the device typically dissipates receivers in custom ASICs and FPGAs that have LVDS capability 2 mW. During power-down, the LVDS output drivers are placed for superior switching performance in noisy environments. into a high impedance state. The AD9273 returns to normal Single point-to-point net topologies are recommended with a operating mode when the PDWN pin is pulled low. This pin is 100 Ω termination resistor placed as close to the receiver as both 1.8 V and 3.3 V tolerant. possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended By asserting the STBY pin high, the AD9273 is placed into a that the trace length be no longer than 24 inches and that the standby mode. In this state, the device typically dissipates differential output traces be kept close together and at equal 140 mW. During standby, the entire part is powered down lengths. An example of the FCO, DCO, and data stream with except the internal references. The LVDS output drivers are proper trace length and position can be found in Figure 64. placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power this device back up is also greatly reduced. The AD9273 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter CH1 500mV/DIV Ω 5.0ns/DIV cycles result in proportionally shorter wake-up times. To restore CH2 500mV/DIV Ω CH3 500mV/DIV Ω the device to full operation, approximately 0.5 ms is required when Figure 64. LVDS Output Timing Example in ANSI-644 Mode (Default) using the recommended 1 μF and 0.1 μF decoupling capacitors An example of the LVDS output using the ANSI-644 standard on the VREF pin and a 0.01 μF capacitor on the GAIN± pins. (default) data eye and a time interval error (TIE) jitter histogram Most of this time is dependent on the gain decoupling: higher with trace lengths of less than 24 inches on regular FR-4 material value decoupling capacitors on the GAIN± pins result in longer is shown in Figure 65. Figure 66 shows an example of the trace wake-up times. lengths exceeding 24 inches on regular FR-4 material. Notice There are a number of other power-down options available that the TIE jitter histogram reflects the decrease of the data eye when using the SPI port interface. The user can individually opening as the edge deviates from the ideal position; therefore, power down each channel or put the entire device into standby the user must determine if the waveforms meet the timing budget mode. This allows the user to keep the internal PLL powered up of the design when the trace lengths exceed 24 inches. when fast wake-up times are required. The wake-up time is Additional SPI options allow the user to further increase the slightly dependent on gain. To achieve a 1 μs wake-up time internal termination and therefore increase the current of all when the device is in standby mode, 0.8 V must be applied to eight outputs in order to drive longer trace lengths (see Figure 67). the GAIN± pins. See Table 17 for more details on using these Even though this produces sharper rise and fall times on the features. data edges, is less prone to bit errors, and improves frequency Digital Outputs and Timing distribution (see Figure 67), the power dissipation of the DRVDD The AD9273 differential outputs conform to the ANSI-644 LVDS supply increases when this option is used. standard by default at power-up. This can be changed to a low In cases that require increased driver strength to the DCO± and power, reduced-signal option similar to the IEEE 1596.3 standard FCO± outputs because of load mismatch, Register 0x15 allows by using the SDIO pin or via the SPI. This LVDS standard can the user to double the drive strength. To do this, set Bit 0 in further reduce the overall power dissipation of the device by Register 0x15. Note that this feature cannot be used with Bit 4 approximately 36 mW. See the SDIO Pin section or Table 17 for and Bit 5 in Register 0x15 because these bits take precedence more information. over this feature. See Table 17 for more details. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differ- ential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. Rev. B | Page 33 of 48 07030-034 AD9273 600 400 EYE: ALL BITS EYE: ALL BITS ULS: 2398/2398 ULS: 2399/2399 400 300 200 200 100 100 0 0 –100 –100 –200 –200 –400 –300 –600 –400 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 25 25 20 20 15 15 10 10 5 5 0 0 –200ps –100ps 0ps 100ps 200ps –200ps –100ps 0ps 100ps 200ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less than 24 Inches on Standard FR-4 of Greater than 24 Inches on Standard FR-4 Rev. B | Page 34 of 48 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07030-035 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07030-036 AD9273 600 The format of the output data is offset binary by default. An EYE: ALL BITS ULS: 2396/2396 example of the output coding format can be found in Table 11. 400 To change the output data format to twos complement, see the Memory Map section. 200 Table 11. Digital Output Coding 0 (VIN+) − (VIN−), Digital Output Offset Binary Code Input Span = 2 V p-p (V) (D11 ... D0) 4095 +1.00 1111 1111 1111 –200 2048 0.00 1000 0000 0000 2047 −0.000488 0111 1111 1111 –400 0 −1.00 0000 0000 0000 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits 25 times the sample clock rate, with a maximum of 600 Mbps (12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion 20 rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See Table 17 for details on enabling this 15 feature. Two output clocks are provided to assist in capturing data from 10 the AD9273. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the 5 AD9273 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new 0 –200ps –100ps 0ps 100ps 200ps output byte and is equal to the sampling clock rate. See the Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination timing diagram shown in Figure 2 for more information. Resistor and Trace Lengths of Greater than 24 Inches on Standard FR-4 Table 12. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 1000 0000 0000 Yes 0010 +Full-scale short 1111 1111 1111 1111 1111 1111 Yes 0011 −Full-scale short 0000 0000 0000 0000 0000 0000 Yes 0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No 0101 PN sequence long N/A N/A Yes 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No 1001 1-/0-bit toggle 1010 1010 1010 N/A No 1010 1× sync 0000 0011 1111 N/A No 1011 One bit high 1000 0000 0000 N/A No 1100 Mixed bit frequency 1010 0011 0011 N/A No Rev. B | Page 35 of 48 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07030-037 AD9273 When using the serial port interface (SPI), the DCO± phase can Consult the Memory Map section for information on how to change be adjusted in 60° increments relative to the data edge. This these additional digital output timing features through the SPI. enables the user to refine system timing margins if required. SDIO Pin The default DCO± timing, as shown in Figure 2, is 90° relative This pin is required to operate the SPI. It has an internal 30 kΩ to the output data edge. pull-down resistor that pulls this pin low and is only 1.8 V An 8-, 10-, and 14-bit serial stream can also be initiated from the tolerant. If applications require that this pin be driven from a SPI. This allows the user to implement different serial streams and 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to to test the device’s compatibility with lower and higher resolution limit the current. systems. When changing the resolution to an 8- or 10-bit serial SCLK Pin stream, the data stream is shortened. When using the 14-bit This pin is required to operate the SPI port interface. It has an option, the data stream stuffs two 0s at the end of the normal internal 30 kΩ pull-down resistor that pulls this pin low and is 14-bit serial data. both 1.8 V and 3.3 V tolerant. When the SPI is used, all of the data outputs can also be inverted CSB Pin from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown This pin is required to operate the SPI port interface. It has an in Figure 2, the MSB is represented first in the data output serial internal 70 kΩ pull-up resistor that pulls this pin high and is both stream. However, this can be inverted so that the LSB is repre- 1.8 V and 3.3 V tolerant. sented first in the data output serial stream (see Figure 3). RBIAS Pin There are 12 digital output test pattern options available that To set the internal core bias current of the ADC, place a resistor can be initiated through the SPI. This is a useful feature when nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using validating receiver capture and timing. Refer to Table 12 for the other than the recommended 10.0 kΩ resistor for RBIAS degrades output bit sequencing options available. Some test patterns have the performance of the device. Therefore, it is imperative that at two serial sequential words and can be alternated in various least a 1% tolerance on this resistor be used to achieve consistent ways, depending on the test pattern chosen. Note that some performance. patterns may not adhere to the data format select option. In Voltage Reference addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options A stable and accurate 0.5 V voltage reference is built into the except PN sequence short and PN sequence long can support AD9273. This is gained up internally by a factor of 2, setting 8- to 14-bit word lengths in order to verify data capture to the VREF to 1.0 V, which results in a full-scale differential input receiver. span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V The PN sequence short pattern produces a pseudorandom reference to achieve more accuracy. However, this device does 9 bit sequence that repeats itself every 2 − 1 bits, or 511 bits. A not support ADC full-scale ranges below 2.0 V p-p. description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The When applying the decoupling capacitors to the VREF pin, use only difference is that the starting value is a specific value instead ceramic low-ESR capacitors. These capacitors should be close to of all 1s (see Table 13 for the initial values). the reference pin and on the same layer of the PCB as the AD9273. The VREF pin should have both a 0.1 μF capacitor The PN sequence long pattern produces a pseudorandom bit and a 1 μF capacitor connected in parallel to the analog ground. 23 sequence that repeats itself every 2 − 1 bits, or 8,388,607 bits. These capacitor values are recommended for the ADC to A description of the PN sequence and how it is generated can properly settle and acquire the next valid sample. be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value The reference settings can be selected using the SPI. The settings instead of all 1s and the AD9273 inverts the bit stream with allow two options: using the internal reference or using an external relation to the ITU standard (see Table 13 for the initial values). reference. The internal reference option is the default setting and has a resulting differential span of 2 V p-p. Table 13. PN Sequence Table 14. SPI-Selectable Reference Settings Initial First Three Output Samples Sequence Value (MSB First) Resulting Resulting Differential SPI-Selected Mode VREF (V) Span (V p-p) PN Sequence Short 0x0DF 0xDF9, 0x353, 0x301 PN Sequence Long 0x29B80A 0x591, 0xFD7, 0x0A3 External Reference N/A 2 × external reference Internal Reference (Default) 1.0 2.0 Rev. B | Page 36 of 48 AD9273 Power and Ground Recommendations the AD9273 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal When connecting power to the AD9273, it is recommended path for heat dissipation to flow through the bottom of the PCB. that two separate 1.8 V supplies be used: one for analog (AVDD) These vias should be filled or plugged with nonconductive epoxy. and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 first and then To maximize the coverage and adhesion between the device and tapped off and isolated with a ferrite bead or a filter choke PCB, partition the continuous copper pad by overlaying a silk- preceded by decoupling capacitors for the DRVDD. The user screen or solder mask to divide this into several uniform sections. should employ several decoupling capacitors on all supplies to This ensures several tie points between the two during the reflow cover both high and low frequencies. These should be located process. Using one continuous plane with no partitions only close to the point of entry at the PC board level and close to the guarantees one tie point between the AD9273 and PCB. See parts with minimal trace lengths. Figure 68 for a PCB layout example. For more detailed infor- mation on packaging and for more PCB layout examples, see A single PC board ground plane should be sufficient when the AN-772 Application Note. using the AD9273. With proper decoupling and smart parti- SILKSCREEN PARTITION tioning of the PC board’s analog, digital, and clock sections, PIN 1 INDICATOR optimum performance can be achieved easily. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD9273. An exposed continuous copper plane on the PCB should mate to Figure 68. Typical PCB Layout Rev. B | Page 37 of 48 07030-069 AD9273 SERIAL PORT INTERFACE (SPI) The AD9273 serial port interface allows the user to configure In addition to the operation modes, the SPI port can be the signal chain for specific functions or operations through a configured to operate in different manners. For applications structured register space provided inside the chip. This offers that do not require a control port, the CSB line can be tied and the user added flexibility and customization depending on the held high. This places the remainder of the SPI pins in their application. Addresses are accessed via the serial port and can secondary mode, as defined in the SDIO Pin and SCLK Pin be written to or read from via the port. Memory is organized sections. CSB can also be tied low to enable 2-wire mode. When into bytes that can be further divided down into fields, as doc- CSB is tied low, SCLK and SDIO are the only pins required for umented in the Memory Map section. Detailed operational communication. Although the device is synchronized during information can be found in the AN-877 Application Note, power-up, caution must be exercised when using this mode to Interfacing to High Speed ADCs via SPI. ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use There are three pins that define the serial port interface (SPI): a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used line, streaming mode can be entered but not exited. to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual-purpose pin that In addition to word length, the instruction phase determines if allows data to be sent to and read from the device’s internal the serial frame is a read or write operation, allowing the serial memory map registers. The CSB (chip select bar) is an active port to be used to both program the chip and read the contents low control that enables or disables the read and write cycles of the on-chip memory. If the instruction is a readback operation, (see Table 15). performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the Table 15. Serial Port Pins appropriate point in the serial frame. Pin Function Data can be sent in MSB- or LSB-first mode. MSB-first mode SCLK Serial clock. The serial shift clock input. SCLK is used to is the default at power-up and can be changed by adjusting the synchronize serial interface reads and writes. configuration register. For more information about this and SDIO Serial data input/output. A dual-purpose pin. The typical other features, see the AN-877 Application Note, Interfacing to role for this pin is as an input or output, depending on the instruction sent and the relative position in the High Speed ADCs via SPI. timing frame. HARDWARE INTERFACE CSB Chip select bar (active low). This control gates the read and write cycles. The pins described in Table 15 constitute the physical interface between the user’s programming device and the serial port of the AD9273. The SCLK and CSB pins function as inputs when The falling edge of the CSB in conjunction with the rising edge of using the SPI interface. The SDIO pin is bidirectional, functioning the SCLK determines the start of the framing sequence. During an as an input during write phases and as an output during readback. instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and In cases where multiple SDIO pins share a common connection, Bit Field W1. An example of the serial timing and its definitions care should be taken to ensure that proper V levels are met. OH can be found in Figure 70 and Table 16. Figure 69 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9273, as well as the During normal operation, CSB is used to signal to the device resulting VOH level. that SPI commands are to be received and processed. When 1.800 CSB is brought low, the device processes SCLK and SDIO to 1.795 process instructions. Normally, CSB remains low until the 1.790 1.785 communication cycle is complete. However, if connected to a 1.780 slow device, CSB can be brought high between bytes, allowing 1.775 older microcontrollers enough time to transfer data into shift 1.770 1.765 registers. CSB can be stalled when transferring one, two, or three 1.760 bytes of data. When W0 and W1 are set to 11, the device enters 1.755 1.750 streaming mode and continues to process data, either reading 1.745 or writing, until CSB is taken high to end the communication 1.740 1.735 cycle. This allows complete memory transfers without having 1.730 to provide additional instructtions. Regardless of the mode, 1.725 1.720 if CSB is taken high in the middle of any byte transfer, the SPI 1.715 state machine is reset and the device waits for a new instruction. 03 10 200 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 69. SDIO Pin Loading Rev. B | Page 38 of 48 V (V) OH 07030-113 AD9273 This interface is flexible enough to be controlled by either serial If the user chooses not to use the SPI interface, these pins serve PROMS or PIC mirocontrollers. This provides the user with a dual function and are associated with secondary functions an alternative method, other than a full SPI controller, for when the CSB is strapped to AVDD during device power-up. programming the device (see the AN-812 Application Note). See the SDIO Pin and SCLK Pin sections for details on which pin-strappable functions are supported on the SPI pins. t t DS HI t t CLK H t t S DH t LO CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 70. Serial Timing Details Table 16. Serial Timing Definitions Parameter Minimum Timing (ns) Description tDS 5 Setup time between the data and the rising edge of SCLK t 2 Hold time between the data and the rising edge of SCLK DH t 40 Period of the clock CLK t 5 Setup time between CSB and SCLK S tH 2 Hold time between CSB and SCLK tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state t 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK EN_SDIO falling edge (not shown in Figure 70) tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 70) Rev. B | Page 39 of 48 07030-068 AD9273 MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map table has eight address locations. when writing the default values suggested in this data sheet. The memory map is roughly divided into three sections: the Addresses that have values marked as 0 should be considered chip configuration register map (Address 0x00 to Address 0x02), reserved and have a 0 written into their registers during power-up. the device index and transfer register map (Address 0x04 to Address 0xFF), and the ADC functions register map DEFAULT VALUES (Address 0x08 to Address 0x2D). After a reset, critical registers are automatically loaded with The leftmost column of the memory map indicates the register default values. These values are indicated in Table 17, where an address number, and the default value is shown in the second X refers to an undefined feature. rightmost column. The Bit 7 (MSB) column is the start of the LOGIC LEVELS default hexadecimal value given. For example, Address 0x09, An explanation of various registers follows: “bit is set” is the clock register, has a default value of 0x01, meaning that Bit 7 synonymous with “bit is set to Logic 1” or “writing Logic 1 for = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, the bit.” Similarly, “clear a bit” is synonymous with “bit is set to and Bit 0 = 1, or 0000 0001 in binary. This setting is the default Logic 0” or “writing Logic 0 for the bit.” for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. Caution All registers except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. B | Page 40 of 48 AD9273 Table 17. AD9273 Memory Map Register Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments Chip Configuration Registers 00 CHIP_PORT_CONFIG 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so that (default) 0 = off 0 = off (default) LSB- or MSB-first (default) (default) mode is set cor- rectly regardless of shift mode. 01 CHIP_ID Chip ID Bits[7:0] Read Default is unique (AD9273 = 0x2F, default) only chip ID, different for each device. This is a read-only register. 02 CHIP_GRADE X X Child ID[5:4] X X X X 0x00 Child ID used to (identify device differentiate variants of Chip ID) graded devices. 00 = 40 MSPS (default) 01 = 25 MSPS 10 = 50 MSPS Device Index and Transfer Registers 04 DEVICE_INDEX_2 X X X X Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel determine which H G F E on-chip device 1 = on 1 = on 1 = on 1 = on receives the next (default) (default) (default) (default) write command. 0 = off 0 = off 0 = off 0 = off 05 DEVICE_INDEX_1 X X Clock Clock Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel Channel Channel determine which DCO± FCO± D C B A on-chip device 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next 0 = off 0 = off (default) (default) (default) (default) write command. (default) (default) 0 = off 0 = off 0 = off 0 = off FF DEVICE_UPDATE X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the master 0 = off shift register to (default) the slave. ADC Functions Registers 08 Modes X X X X 0 Internal power-down mode 0x00 Determines 000 = chip run (default) various generic 001 = full power-down modes of chip 010 = standby operation 011 = reset (global). 100 = CW mode (TGC PDWN) 09 Clock X X X X X X X Duty 0x01 Turns the internal cycle duty cycle stabilizer stabilizer on and off 1 = on (global). (default) 0 = off 0D TEST_IO User test mode Reset PN Reset PN Output test mode—see Table 12 0x00 When this register 00 = off (default) long short 0000 = off (default) is set, the test data 01 = on, single gen gen 0001 = midscale short is placed on the alternate 1 = on 1 = on 0010 = +FS short output pins in 10 = on, single once 0 = off 0 = off 0011 = −FS short place of normal 11 = on, alternate once (default) (default) 0100 = checkerboard output data. (Local, expect 0101 = PN sequence long for PN sequence.) 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register) Rev. B | Page 41 of 48 AD9273 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 0F FLEX_CHANNEL_ Filter cutoff frequency control X X X X 0x30 Antialiasing filter INPUT 0000 = 1.3 × 1/3 × fSAMPLE cutoff (global). 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × f (default) SAMPLE 0100 = 0.9 × 1/3 × f SAMPLE 0101 = 0.8 × 1/3 × f SAMPLE 0110 = 0.7 × 1/3 × f SAMPLE 1000 = 1.3 × 1/4.5 × f SAMPLE 1001 = 1.2 × 1/4.5 × f SAMPLE 1010 = 1.1 × 1/4.5 × f SAMPLE 1011 = 1.0 × 1/4.5 × f SAMPLE 1100 = 0.9 × 1/4.5 × f SAMPLE 1101 = 0.8 × 1/4.5 × f SAMPLE 1110 = 0.7 × 1/4.5 × f SAMPLE 10 FLEX_OFFSET X X 6-bit LNA offset adjustment 0x20 LNA force offset 10 0000 = LNA bias high, mid-high, mid-low (default) correction 10 0001 = LNA bias low (local). 11 FLEX_GAIN X X X X PGA gain LNA gain 0x06 LNA and PGA 00 = 21 dB 00 = 15.6 dB gain adjustment 01 = 24 dB (default) 01 = 17.9 dB (global). 10 = 27 dB 10 = 21.3 dB 11 = 30 dB (default) 12 BIAS_CURRENT X X X X 1 X LNA bias 0x08 LNA bias current 00 = high adjustment 01 = mid-high (global). (default) 10 = mid-low 11 = low 14 OUTPUT_MODE X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos format of the data 1 = LVDS 0 = off complement (Bits[7:3] and low power, (default) Bits[1:0] are global; (IEEE Bit 2 is local). 1596.3 similar) 15 OUTPUT_ADJUST X X Output driver X X X DCO± 0x00 Determines LVDS termination and or other output 00 = none (default) FCO± properties. Pri- 01 = 200 Ω 2× drive marily functions to 10 = 100 Ω strength set the LVDS span 11 = 100 Ω 1 = on and common- 0 = off mode levels in (default) place of an external resistor (Bits[7:1] are global; Bit 0 is local). 16 OUTPUT_PHASE X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) utilize global 0000 = 0° relative to data edge clock divide, 0001 = 60° relative to data edge determines which 0010 = 120° relative to data edge phase of the 0011 = 180° relative to data edge (default) divider output is 0100 = 240° relative to data edge used to supply 0101 = 300° relative to data edge the output clock. Internal latching 0110 = 360° relative to data edge 0111 = 420° relative to data edge is unaffected. 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge 18 FLEX_VREF X 0 = X X X X X X 0x00 Select internal internal reference reference (recommended 1 = default) or external external reference (global). reference Rev. B | Page 42 of 48 AD9273 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB (global). 1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB (global). 1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB (global). 1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB (global). 21 SERIAL_CONTROL LSB first X X X <10 000 = 12 bits (default, normal 0x00 Serial stream 1 = on MSPS, bit stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native bit rate 011 = 12 bits stream (global). mode 100 = 14 bits 1 = on 0 = off (default) 22 SERIAL_CH_STAT X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) 2B FLEX_FILTER X Enable X X High-pass filter cutoff 0x00 Filter cutoff automatic 0000 = f /20.7 (global). (f = LP LP low-pass 0001 = f /11.5 low-pass filter LP tuning 0010 = f /7.9 cutoff frequency.) LP 1 = on 0011 = f /6.0 LP (self- 0100 = f /4.9 LP clearing) 0101 = f /4.1 LP 0110 = f /3.5 LP 0111 = f /3.1 LP 2C ANALOG_INPUT X X X X X X LOSW-x connect 0x00 LNA active 00 = high-Z termination/input 01 = (−)LNA output impedance 10 = (+)LNA output (global). 11 = high-Z 2D CROSS_POINT_ X X Crosspoint switch enable 0x00 Crosspoint switch SWITCH 10 0000 = CWD0± (differential) enable (local). 10 0001 = CWD1± (differential) 10 0010 = CWD2± (differential) 10 0011 = CWD3± (differential) 10 0100 = CWD4± (differential) 10 0101 = CWD5± (differential) 10 0110 = CWD6± (differential) 10 0111 = CWD7± (differential) 11 0000 = CWD0+ (single ended) 11 0001 = CWD1+ (single ended) 11 0010 = CWD2+ (single ended) 11 0011 = CWD3+ (single ended) 11 0100 = CWD4+ (single ended) 11 0101 = CWD5+ (single ended) 11 0110 = CWD6+ (single ended) 11 0111 = CWD7+ (single ended) 11 1000 = CWD0− (single ended) 11 1001 = CWD1− (single ended) 11 1010 = CWD2− (single ended) 11 1011 = CWD3− (single ended) 11 1100 = CWD4− (single ended) 11 1101 = CWD5− (single ended) 11 1110 = CWD6− (single ended) 11 1111 = CWD7− (single ended) 0x xxxx = power down CW channel (default) Rev. B | Page 43 of 48 AD9273 OUTLINE DIMENSIONS 16.00 BSC SQ 1.20 0.75 MAX 0.60 14.00 BSC SQ 0.45 76 100 100 76 1 75 75 1 PIN 1 EXPOSED 9.50 SQ TOP VIEW PAD (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 (PINS UP) 0.09 51 51 25 25 0.95 7° 26 50 50 26 3.5° 0.50 BSC 0.27 0.15 VIEW A 0° SEATING LEAD PITCH 0.22 FOR PROPER CONNECTION OF 0.05 0.08 MAX PLANE THE EXPOSED PAD, REFER TO COPLANARITY 0.17 THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters A1 CORNER 10.10 INDEX AREA 10.00 9 11 7 5 3 1 9.90 12 10 8 6 4 2 A B BALL A1 INDICATOR C D E 8.80 F BSC SQ TOP VIEW G H J K L M BOTTOM VIEW 0.80 BSC DETAIL A 1.40 MAX DETAIL A 1.00 0.85 0.43 MAX 0.25 MIN COPLANARITY 0.55 SEATING 0.12 MAX 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-205-AC. Figure 72. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] (BC-144-1) Dimensions shown in millimeters Rev. B | Page 44 of 48 012006-0 100908-A AD9273 ORDERING GUIDE Temperature Package Model Range Package Description Option 1 AD9273BSVZ-50 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9273BSVZRL-50 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9273BSVZ-40 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9273BSVZRL-40 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9273BSVZ-25 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9273BSVZRL-25 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9273BBCZ-25 −40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1 1 AD9273BBCZ-40 −40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1 1 AD9273BBCZ-50 −40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1 1 AD9273-50EBZ Evaluation Board, 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 1 Z = RoHS Compliant Part. Rev. B | Page 45 of 48 AD9273 NOTES Rev. B | Page 46 of 48 AD9273 NOTES Rev. B | Page 47 of 48 AD9273 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07030-0-7/09(B) Rev. B | Page 48 of 48