ANALOG DEVICES AD9272

Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9272 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 0.75 nV/√Hz LOSW-A AD9272 (gain = 21.3 dB) @ 5 MHz typical LO-A SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB LI-A 12-BIT SERIAL DOUTA+ LNA VGA ADC LG-A LVDS DOUTA– Single-ended input; V maximum = 733 mV p-p/ IN AAF LOSW-B 550 mV p-p/367 mV p-p LO-B Dual-mode active input impedance matching LI-B 12-BIT DOUTB+ SERIAL LNA VGA ADC LVDS LG-B DOUTB– Bandwidth (BW) > 100 MHz AAF LOSW-C Full-scale (FS) output = 4.4 V p-p differential LO-C Variable gain amplifier (VGA) LI-C DOUTC+ 12-BIT SERIAL LNA VGA ADC Attenuator range = −42 dB to 0 dB LG-C LVDS DOUTC– AAF LOSW-D SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB LO-D Linear-in-dB gain control LI-D 12-BIT DOUTD+ SERIAL LNA VGA Antialiasing filter (AAF) ADC LG-D LVDS DOUTD– AAF LOSW-E Programmable 2nd-order low-pass filter (LPF) from LO-E 8 MHz to 18 MHz LI-E DOUTE+ 12-BIT SERIAL LNA VGA Programmable high-pass filter (HPF) ADC LVDS LG-E DOUTE– AAF Analog-to-digital converter (ADC) LOSW-F LO-F 12 bits at 10 MSPS to 80 MSPS LI-F DOUTF+ 12-BIT SERIAL SNR = 70 dB LNA VGA ADC LG-F LVDS DOUTF– AAF SFDR = 75 dB LOSW-G Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) LO-G LI-G DOUTG+ 12-BIT Data and frame clock outputs SERIAL LNA VGA LG-G ADC LVDS DOUTG– AAF Includes an 8 × 8 differential crosspoint switch to support LOSW-H continuous wave (CW) Doppler LO-H LI-H Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) 12-BIT DOUTH+ SERIAL LNA VGA ADC LG-H LVDS DOUTH– 120 mW per channel in CW Doppler AAF Flexible power-down modes FCO+ Overload recovery in <10 ns FCO– Fast recovery from low power standby mode, <2 μs REFERENCE DCO+ SWITCH 100-lead TQFP DCO– ARRAY APPLICATIONS Medical imaging/ultrasound Automotive radar GENERAL DESCRIPTION Figure 1. The AD9272 is designed for low cost, low power, small size, and The LNA has a single-ended-to-differential gain that is selectable ease of use. It contains eight channels of a low noise preamplifier through the SPI. The LNA input-referred noise voltage is typically (LNA) with a variable gain amplifier (VGA), an antialiasing 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to- noise voltage of the entire channel is 0.85 nV/√Hz at maximum digital converter (ADC). gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB Each channel features a variable gain range of 42 dB, a fully LNA gain, the input SNR is about 92 dB. In CW Doppler mode, differential signal path, an active input preamplifier termination, a the LNA output drives a transconductance amp that is switched maximum gain of up to 52 dB, and an ADC with a conversion through an 8 × 8 differential crosspoint switch. The switch is rate of up to 80 MSPS. The channel is optimized for dynamic programmable through the SPI. performance and low power in applications where a small package size is critical. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CWD[7:0]+ AND CWD[7:0]– GAIN+ AVDD1 GAIN– AVDD2 PDWN VREF STBY RBIAS CSB SERIAL SCLK PORT INTERFACE SDIO DRVDD DATA CLK+ RATE CLK– MULTIPLIER 07029-001 AD9272 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound .................................................................................. 21 Applications ....................................................................................... 1 Channel Overview ..................................................................... 22 General Description ......................................................................... 1 Input Overdrive .......................................................................... 25 Functional Block Diagram .............................................................. 1 CW Doppler Operation ............................................................. 25 Revision History ............................................................................... 2 TGC Operation ........................................................................... 27 Product Highlights ........................................................................... 3 ADC ............................................................................................. 31 Specif ica t ions ..................................................................................... 4 Clock Input Considerations ...................................................... 31 AC Specifications .......................................................................... 4 Serial Port Interface (SPI) .............................................................. 38 Digital Specifications ................................................................... 8 Hardware Interface ..................................................................... 38 Switching Specifications .............................................................. 9 Memory Map .................................................................................. 40 Absolute Maximum Ratings .......................................................... 11 Reading the Memory Map Table .............................................. 40 Thermal Impedance ................................................................... 11 Reserved Locations .................................................................... 40 ESD Caution ................................................................................ 11 Default Values ............................................................................. 40 Pin Configuration and Function Descriptions ........................... 12 Logic Levels ................................................................................. 40 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 44 Equivalent Circuits ......................................................................... 19 Ordering Guide .......................................................................... 44 Theory of Operation ...................................................................... 21 REVISION HISTORY 7/09—Rev. B to Rev. C Changes to Input Overload Protection Section and Figure 43 ....... 25 Changes to Digital Outputs and Timing Section and Changes to Figure 63 ...................................................................................... 33 Changes to Hardware Interface Section ...................................... 39 6/09—Rev. A to Rev. B Changes to Product Highlights Section ......................................... 3 Changes to Table 1 ............................................................................ 4 Changes to Absolute Maximum Ratings Table ........................... 11 Changes to Figure 22 ...................................................................... 17 Changes to Figure 33 and Figure 34 ............................................. 20 Changes to Low Noise Amplifier (LNA) Section ....................... 22 Changes to Active Impedance Matching Section ....................... 23 Changes to Figure 39 ...................................................................... 23 Changes to LNA Noise Section ..................................................... 24 Changes to Figure 47 ...................................................................... 28 Changes to Figure 48 and Figure 49 ............................................. 29 Changes to CSB Pin Section .......................................................... 36 Changes to Reading the Memory Map Table Section................ 40 4/09—Revision A: Initial Version Rev. C | Page 2 of 44 AD9272 The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible Fabricated in an advanced CMOS process, the AD9272 is sample rate clock for full performance operation. No external available in a 16 mm × 16 mm, RoHS-compliant, 100-lead reference or driver components are required for many TQFP. It is specified over the industrial temperature range of applications. −40°C to +85°C. The ADC automatically multiplies the sample rate clock for PRODUCT HIGHLIGHTS the appropriate LVDS serial data rate. A data clock (DCO±) for 1. Small Footprint. Eight channels are contained in a capturing data on the output and a frame clock (FCO±) trigger small, space-saving package. A full TGC path, ADC, and for signaling a new output byte are provided. crosspoint switch are contained within a 100-lead, 16 mm × Powering down individual channels is supported to increase 16 mm TQFP. battery life for portable applications. There is also a standby 2. Low Power of 195 mW Per Channel at 40 MSPS. mode option that allows quick power-up for power cycling. In 3. Integrated Crosspoint Switch. This switch allows numerous CW Doppler operation, the VGA, antialiasing filter (AAF), and multichannel configuration options to enable the CW ADC are powered down. The power of the time gain control Doppler mode. (TGC) path scales with selectable speed grades. 4. Ease of Use. A data clock output (DCO±) operates up to 480 MHz and supports double data rate (DDR) operation. The ADC contains several features designed to maximize flexibility 5. User Flexibility. Serial port interface (SPI) control offers a wide and minimize system cost, such as a programmable clock, data range of flexible features to meet specific system requirements. alignment, and programmable digital test pattern generation. The 6. Integrated Second-Order Antialiasing Filter. This filter is digital test patterns include built-in fixed patterns, built-in placed between the VGA and the ADC and is programmable pseudorandom patterns, and custom user-defined test patterns from 8 MHz to 18 MHz. entered via the serial port interface. Rev. C | Page 3 of 44 AD9272 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f = 5 MHz, R = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, IN S PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = f /4.5, HPF = LPF cutoff/20.7 (default), full temperature, ANSI-644 LVDS mode, SAMPLE unless otherwise noted. Table 1. AD9272-40 AD9272-65 AD9272-80 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit LNA CHARACTERISTICS Gain Single-ended 15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB input to differential output Single-ended 9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB input to single-ended output Input Voltage Range LNA gain = 733/550/367 733/550/367 733/550/367 mV p-p 2 15.6 dB/ SE 17.9 dB/ 21.3 dB, LNA output limited to 4.4 V p-p differential output Input Common 0.9 0.9 0.9 V Mode Input Resistance R = 250 Ω 50 50 50 Ω FB R = 500 Ω 100 100 100 Ω FB R = ∞ 15 15 15 kΩ FB Input Capacitance LI-x 22 22 22 pF −3 dB Bandwidth 100 100 100 MHz Input-Referred LNA gain = 0.98/0.86/0.75 0.98/0.86/0.75 0.98/0.86/0.75 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ Input Noise Current RFB = ∞ 1 1 1 pA/√Hz 1 dB Input Com- LNA gain = 1.0/0.8/0.5 1.0/0.8/0.5 1.0/0.8/0.5 mV p-p pression Point 15.6 dB/ 17.9 dB/ 21.3 dB, GAIN+ = 0 V Noise Figure LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Active Termination R = 50 Ω, 4.8/4.1/3.2 4.8/4.1/3.2 4.8/4.0/3.2 dB S Matched R = 200 Ω/ FB 250 Ω/350 Ω Unterminated R = ∞ 3.4/2.8/2.3 3.4/2.8/2.3 3.4/2.8/2.3 dB FB FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Filter −3 dB, 8 to 18 8 to 18 8 to 18 MHz Cutoff -In Range programmable AAF Low-Pass Filter −3 dB, 5 to 8 and 5 to 8 and 5 to 8 and MHz Cutoff - Out of programmable, 18 to 35 18 to 35 18 to 35 3 Range AAF Bandwidth Tolerance AAF Bandwidth ±10 ±10 ±10 % Tolerance -In Range Rev. C | Page 4 of 44 AD9272 AD9272-40 AD9272-65 AD9272-80 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit Group Delay f = 1 MHz to ±2 ±2 ±2 ns Variation 18 MHz, GAIN+ = 0 V to 1.6 V Input-Referred LNA gain = 1.26/1.04/0.85 1.26/1.04/0.85 1.26/1.04/0.85 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, R = ∞ FB Noise Figure LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Active Termina- R = 50 Ω, 8.0/6.6/4.7 7.7/6.2/4.5 7.6/6.1/4.4 dB S tion Matched R = 200 Ω/ FB 250 Ω/350 Ω Unterminated RFB = ∞ 4.7/3.7/2.8 4.6/3.6/2.8 4.5/3.6/2.7 dB Correlated Noise No signal, −30 −30 −30 dB Ratio correlated/ uncorrelated Output Offset −35 +35 −35 +35 −35 +35 LSB Signal-to-Noise fIN = 5 MHz at 65 64 63 dBFS Ratio (SNR) −10 dBFS, GAIN+ = 0 V fIN = 5 MHz at 57 56 54.5 dBFS −1 dBFS, GAIN+ = 1.6 V Harmonic Distortion Second f = 5 MHz at −62 −58 −55 dBc IN Harmonic −10 dBFS, GAIN+ = 0 V f = 5 MHz at −60 −61 −58 dBc IN −1 dBFS, GAIN+ = 1.6 V Third Harmonic f = 5 MHz at −71 −60 −60 dBc IN −10 dBFS, GAIN+ = 0 V f = 5 MHz at −57 −55 −56 dBc IN −1 dBFS, GAIN+ = 1.6 V Two-Tone IMD3 fIN1 = 5.0 MHz at −75 −75 −75 dBc (2 × F1 − F2) −1 dBFS, Distortion fIN2 = 5.01 MHz at −21 dBFS, GAIN+ = 1.6 V, LNA gain = 21.3 dB Channel-to-Channel fIN1 = 5.0 MHz at −1 −70 −70 −70 dB Crosstalk dBFS Overrange −65 −65 −65 dB 4 condition Channel-to-Channel Full TGC path, 0.3 0.3 0.3 Degrees Delay Variation f = 5 MHz, IN GAIN+ = 0 V to 1.6 V PGA GAIN Differential input 21/24/27/30 21/24/27/30 21/24/27/30 dB to differential output Rev. C | Page 5 of 44 AD9272 AD9272-40 AD9272-65 AD9272-80 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit GAIN ACCURACY 25°C Gain Law Confor- 0 V < GAIN+ < 1.5 1.5 1.5 dB mance Error 0.16 V 0.16 V < GAIN+ < −1.5 +1.5 −1.5 +1.5 −1.6 +1.6 dB 1.44 V 1.44 V < GAIN+ < −2.5 −2.5 −2.5 dB 1.6 V Linear Gain Error GAIN+ = 0.8 V, −1.5 +1.5 −1.5 +1.5 −1.6 +1.6 dB normalized for ideal AAF loss Channel-to-Channel 0.16 V < GAIN+ < 0.1 0.1 0.1 dB Matching 1.44 V GAIN CONTROL INTERFACE Normal Operating 0 1.6 0 1.6 0 1.6 V Range Gain Range GAIN+ = 0 V to 42 42 42 dB 1.6 V Scale Factor 28.5 28.5 28.5 dB/V Response Time 42 dB change 750 750 750 ns Gain+ Impedance Single-ended 10 10 10 MΩ Gain− Impedance Single-ended 70 70 70 kΩ CW DOPPLER MODE Transconductance LNA gain = 5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V (differential) 15.6 dB/ 17.9 dB/ 21.3 dB Output Level Range CW Doppler 1.5 3.6 1.5 3.6 1.5 3.6 V (differential) output pins Input-Referred LNA gain = 2.35/1.82/1.31 2.35/1.82/1.31 2.35/1.82/1.31 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, R = 0 Ω, S R = ∞, FB RL = 675 Ω Input-Referred LNA gain = 161/161/160 161/161/160 161/161/160 dBFS/√Hz Dynamic Range 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ Two-Tone IMD3 fIN1 = 5.0 MHz at −70 −70 −70 dBc (2 × F1 − F2) −1 dBFS (FS at LNA Distortion input), fIN2 = 5.01 MHz at −21 dBFS (FS at LNA input), LNA gain = 21.3 dB Output DC Bias Per channel 2.4 2.4 2.4 mA (single-ended) Maximum Output Per channel ±2 ±2 ±2 mA p-p Swing (single- ended) POWER SUPPLY AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Rev. C | Page 6 of 44 AD9272 AD9272-40 AD9272-65 AD9272-80 1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit IAVDD1 Full-channel 210 280 335 mA mode CW Doppler mode 32 32 32 mA with four channels enabled I Full-channel mode 365 365 365 mA AVDD2 CW Doppler mode 140 140 140 mA with four channels enabled I 49 51 52 mA DRVDD Total Power Includes output 1560 1713 1690 1860 1780 1975 mW Dissipation drivers, full- channel mode, no signal CW Doppler mode 475 475 475 mW with four channels enabled Power-Down 5 5 5 mW Dissipation Standby Power 175 200 210 mW Dissipation Power Supply 1.6 1.6 1.6 mV/V Rejection Ratio (PSRR) ADC RESOLUTION 12 12 12 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV Load Regulation At 1.0 mA, 2 2 2 mV VREF = 1 V Input Resistance 6 6 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 SE = single-ended. 3 AAF settings < 5 MHz are out of range and not supported. 4 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. C | Page 7 of 44 AD9272 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 2. 1 Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF 3 LOGIC OUTPUT (SDIO) Logic 1 Voltage (I = 800 μA) Full 1.79 V OH Logic 0 Voltage (IOL = 50 μA) Full 0.05 V 1 DIGITAL OUTPUTS (DOUTx+, DOUTx−), IN ANSI-644 MODE Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary DIGITAL OUTPUTS (DOUTx+, DOUTx−), WITH 1 LOW POWER, REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (V) Full 150 250 mV OD Output Offset Voltage (V) Full 1.10 1.30 V OS Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. C | Page 8 of 44 AD9272 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 3. 1 Parameter Temp Min Typ Max Unit 2 CLOCK Clock Rate Full 10 80 MSPS Clock Pulse Width High (tEH) Full 6.25 ns Clock Pulse Width Low (tEL) Full 6.25 ns 2, 3 OUTPUT PARAMETERS Propagation Delay (tPD) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns Rise Time (t ) (20% to 80%) Full 300 ps R Fall Time (t ) (20% to 80%) Full 300 ps F FCO± Propagation Delay (t ) Full (t /2) + 1.5 (t /2) + 2.3 (t /2) + 3.1 ns FCO SAMPLE SAMPLE SAMPLE 4 DCO± Propagation Delay (tCPD) Full tFCO + (tSAMPLE/24) ns 4 DCO± to Data Delay (tDATA) Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps 4 DCO± to FCO± Delay (tFRAME) Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps Data-to-Data Skew Full ±100 ±350 ps (t − t ) DATA-MAX DATA-MIN Wake-Up Time (Standby), GAIN+ = 0.8 V 25°C 2 μs Wake-Up Time (Power-Down) 25°C 1 ms Pipeline Latency Full 8 Clock cycles APERTURE Aperture Uncertainty (Jitter) 25°C <1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. Rev. C | Page 9 of 44 AD9272 ADC Timing Diagrams N – 1 AIN N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA DOUTx– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7 DOUTx+ Figure 2. 12-Bit Data Serial Stream (Default) N – 1 AIN N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA DOUTx– LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LSB D0 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7 DOUTx+ Figure 3. 12-Bit Data Serial Stream, LSB First Rev. C | Page 10 of 44 07029-002 07029-004 AD9272 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD1 GND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AVDD2 GND −0.3 V to +3.9 V maximum rating conditions for extended periods may affect DRVDD GND −0.3 V to +2.0 V device reliability. GND GND −0.3 V to +0.3 V AVDD2 AVDD1 −2.0 V to +3.9 V THERMAL IMPEDANCE AVDD1 DRVDD −2.0 V to +2.0 V Table 5. AVDD2 DRVDD −2.0 V to +3.9 V 1 Air Flow Velocity (m/sec) θ θ θ Unit Digital Outputs GND −0.3 V to +2.0 V JA JB JC (DOUTx+, DOUTx−, 0.0 20.3 N/A N/A °C/W DCO+, DCO−, 1.0 14.4 7.6 4.7 °C/W FCO+, FCO−) 2.5 12.9 N/A N/A °C/W CLK+, CLK−, GND −0.3 V to +3.9 V GAIN+,GAIN− 1 θ is for a 4-layer PCB with a solid ground plane (simulated). The exposed JA pad is soldered to the PCB. LI-x, LO-x, LOSW-x LG-x −0.3 V to +2.0 V CWDx−, CWDx+ GND −0.3 V to +3.9 V GND −0.3 V to +2.0 V ESD CAUTION PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V RBIAS, VREF, SDIO GND −0.3 V to +2.0 V Environmental Operating Temperature −40°C to +85°C Range (Ambient) Storage Temperature −65°C to +150°C Range (Ambient) Maximum Junction 150°C Temperature Lead Temperature 300°C (Soldering, 10 sec) Rev. C | Page 11 of 44 AD9272 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 75 LI-D INDICATOR LG-E 2 LG-D 74 AVDD2 3 73 AVDD2 AVDD1 4 72 AVDD1 EXPOSED PADDLE, PIN 0 LO-F LO-C 5 71 (BOTTOM OF PACKAGE) LOSW-F 6 70 LOSW-C LI-F 7 69 LI-C AD9272 LG-F 8 68 LG-C TOP VIEW AVDD2 9 (Not to Scale) 67 AVDD2 AVDD1 10 66 AVDD1 LO-G 11 65 LO-B LOSW-G 12 64 LOSW-B LI-G 13 63 LI-B LG-G 14 62 LG-B AVDD2 15 61 AVDD2 16 AVDD1 60 AVDD1 LO-H 17 59 LO-A LOSW-H 18 58 LOSW-A 19 LI-H 57 LI-A LG-H 20 56 LG-A AVDD2 21 55 AVDD2 AVDD1 22 54 AVDD1 23 CLK– 53 CSB CLK+ 24 52 SDIO AVDD1 25 51 SCLK NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. Figure 4. TQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. Name Description 0 GND Ground (exposed paddle should be tied to a quiet analog ground) 4, 10, 16, 22, 25, 50, AVDD1 1.8 V Analog Supply 54, 60, 66, 72 3, 9, 15, 21, 55, 61, AVDD2 3.0 V Analog Supply 67, 73, 86 26, 47 DRVDD 1.8 V Digital Output Driver Supply 1 LI-E LNA Analog Input for Channel E 2 LG-E LNA Ground for Channel E 5 LO-F LNA Analog Inverted Output for Channel F 6 LOSW-F LNA Analog Switched Output for Channel F 7 LI-F LNA Analog Input for Channel F 8 LG-F LNA Ground for Channel F 11 LO-G LNA Analog Inverted Output for Channel G 12 LOSW-G LNA Analog Switched Output for Channel G 13 LI-G LNA Analog Input for Channel G 14 LG-G LNA Ground for Channel G 17 LO-H LNA Analog Inverted Output for Channel H 18 LOSW-H LNA Analog Switched Output for Channel H 19 LI-H LNA Analog Input for Channel H Rev. C | Page 12 of 44 DRVDD 26 100 LOSW-E DOUTH– 27 99 LO-E DOUTH+ 28 98 CWD7+ DOUTG– 29 97 CWD7– DOUTG+ 30 96 CWD6+ DOUTF– 31 95 CWD6– DOUTF+ 32 94 CWD5+ DOUTE– 33 93 CWD5– DOUTE+ 34 92 CWD4+ DCO– 35 91 CWD4– DCO+ 36 90 VREF 37 FCO– 89 RBIAS FCO+ 38 88 GAIN+ DOUTD– 39 87 GAIN– DOUTD+ 40 86 AVDD2 41 DOUTC– 85 CWD3+ DOUTC+ 42 84 CWD3– DOUTB– 43 83 CWD2+ DOUTB+ 44 82 CWD2– DOUTA– 45 81 CWD1+ DOUTA+ 46 80 CWD1– DRVDD 47 79 CWD0+ STBY 48 78 CWD0– PDWN 49 77 LO-D AVDD1 50 76 LOSW-D 07029-005 AD9272 Pin No. Name Description 20 LG-H LNA Ground for Channel H 23 CLK− Clock Input Complement 24 CLK+ Clock Input True 27 DOUTH− ADC H Digital Output Complement 28 DOUTH+ ADC H Digital Output True 29 DOUTG− ADC G Digital Output Complement 30 DOUTG+ ADC G Digital Output True 31 DOUTF− ADC F Digital Output Complement 32 DOUTF+ ADC F Digital Output True 33 DOUTE− ADC E Digital Output Complement 34 DOUTE+ ADC E Digital Output True 35 DCO− Digital Clock Output Complement 36 DCO+ Digital Clock Output True 37 FCO− Frame Clock Digital Output Complement 38 FCO+ Frame Clock Digital Output True 39 DOUTD− ADC D Digital Output Complement 40 DOUTD+ ADC D Digital Output True 41 DOUTC− ADC C Digital Output Complement 42 DOUTC+ ADC C Digital Output True 43 DOUTB− ADC B Digital Output Complement 44 DOUTB+ ADC B Digital Output True 45 DOUTA− ADC A Digital Output Complement 46 DOUTA+ ADC A Digital Output True 48 STBY Standby Power-Down 49 PDWN Full Power-Down 51 SCLK Serial Clock 52 SDIO Serial Data Input/Output 53 CSB Chip Select Bar 56 LG-A LNA Ground for Channel A 57 LI-A LNA Analog Input for Channel A 58 LOSW-A LNA Analog Switched Output for Channel A 59 LO-A LNA Analog Inverted Output for Channel A 62 LG-B LNA Ground for Channel B 63 LI-B LNA Analog Input for Channel B 64 LOSW-B LNA Analog Switched Output for Channel B 65 LO-B LNA Analog Inverted Output for Channel B 68 LG-C LNA Ground for Channel C 69 LI-C LNA Analog Input for Channel C 70 LOSW-C LNA Analog Switched Output for Channel C 71 LO-C LNA Analog Inverted Output for Channel C 74 LG-D LNA Ground for Channel D 75 LI-D LNA Analog Input for Channel D 76 LOSW-D LNA Analog Switched Output for Channel D 77 LO-D LNA Analog Inverted Output for Channel D 78 CWD0− CW Doppler Output Complement for Channel 0 79 CWD0+ CW Doppler Output True for Channel 0 80 CWD1− CW Doppler Output Complement for Channel 1 81 CWD1+ CW Doppler Output True for Channel 1 82 CWD2− CW Doppler Output Complement for Channel 2 83 CWD2+ CW Doppler Output True for Channel 2 84 CWD3− CW Doppler Output Complement for Channel 3 85 CWD3+ CW Doppler Output True for Channel 3 87 GAIN− Gain Control Voltage Input Complement Rev. C | Page 13 of 44 AD9272 Pin No. Name Description 88 GAIN+ Gain Control Voltage Input True 89 RBIAS External Resistor to Set the Internal ADC Core Bias Current 90 VREF Voltage Reference Input/Output 91 CWD4− CW Doppler Output Complement for Channel 4 92 CWD4+ CW Doppler Output True for Channel 4 93 CWD5− CW Doppler Output Complement for Channel 5 94 CWD5+ CW Doppler Output True for Channel 5 95 CWD6− CW Doppler Output Complement for Channel 6 96 CWD6+ CW Doppler Output True for Channel 6 97 CWD7− CW Doppler Output Complement for Channel 7 98 CWD7+ CW Doppler Output True for Channel 7 99 LO-E LNA Analog Inverted Output for Channel E 100 LOSW-E LNA Analog Switched Output for Channel E Rev. C | Page 14 of 44 AD9272 TYPICAL PERFORMANCE CHARACTERISTICS fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF cutoff/20.7 (default), unless otherwise noted. 25 2.0 1.5 20 1.0 –40°C 0.5 15 +25°C 0 +85°C 10 –0.5 –1.0 5 –1.5 0 –2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) GAIN ERROR (dB) Figure 5. Gain Error vs. GAIN+ at Three Temperatures Figure 8. Gain Error Histogram, GAIN+ = 1.44 V 25 25 20 20 15 15 10 10 5 5 0 0 –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 GAIN ERROR (dB) CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 6. Gain Error Histogram, GAIN+ = 0.16 V Figure 9. Gain Match Histogram, GAIN+ = 0.3 V 25 14 12 20 10 15 8 6 10 4 5 2 0 0 –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) GAIN ERROR (dB) Figure 10. Gain Match Histogram, GAIN+ = 1.3 V Figure 7. Gain Error Histogram, GAIN+ = 0.8 V Rev. C | Page 15 of 44 GAIN ERROR (dB) PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) –1.0 –1.0 –0.9 –0.9 –0.8 –0.8 –0.7 –0.7 –0.6 –0.6 –0.5 –0.5 –0.4 –0.4 –0.3 –0.3 –0.2 –0.2 –0.1 –0.1 0 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1.0 1.0 07029-185 07029-184 07029-114 PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 07029-181 07029-180 07029-186 AD9272 500k –126 450k –128 400k LNA GAIN = 12× –130 350k 300k –132 LNA GAIN = 8× 250k –134 200k 150k –136 100k LNA GAIN = 6× –138 50k 0 –140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –7 –6 –5 –4 –3 –2 –1 01 234 56 7 CODES GAIN+ (V) Figure 11. Output-Referred Noise Histogram, GAIN+ = 0 V Figure 14. Short-Circuit, Output-Referred Noise vs. GAIN+ 180k 64 160k 62 SNR 140k 60 120k 58 100k SINAD 80k 56 60k 54 40k 52 20k 0 50 –7 –6 –5 –4 –3 –2 –1 01 234 56 7 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 CODES GAIN+ (V) Figure 15. SNR/SINAD vs. GAIN+, AIN = −1 dBFS Figure 12. Output-Referred Noise Histogram, GAIN+ = 1.6 V 0 1.8 1.6 AD9272-65 –5 1.4 AD9272-80 LNA GAIN = 15.6dB 1.2 –10 1.0 LNA GAIN = 17.9dB AD9272-40 0.8 –15 LNA GAIN = 21.3dB 0.6 0.4 –20 0.2 –25 0 0 5 10 15 20 25 30 35 40 123456789 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Antialiasing Filter (AAF) Pass-Band Response, Figure 13. Short-Circuit, Input-Referred Noise vs. Frequency, LPF Cutoff = 1 × (1/4.5) × fSAMPLE PGA Gain = 30 dB, GAIN+ = 1.6 V Rev. C | Page 16 of 44 NUMBER OF HITS NUMBER OF HITS INPUT-REFERRED NOISE (nV/√Hz) 07029-187 07029-116 07029-115 OUTPUT-REFERRED NOISE (dBFS/Hz) AMPLITUDE (dBFS) SNR/SINAD(dBFS) 07029-118 07029-120 07029-117 AD9272 150 0 125 –20 100 –40 GAIN+ = 1.6V GAIN+ = 0.8V 75 GAIN+ = 0.8V –60 GAIN+ = 0V GAIN+ = 0V 50 –80 GAIN+ = 1.6V 25 –100 0 –120 –50 –40 –30 –20 –10 0 0 5 10 15 20 25 30 35 40 ADC OUTPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 17. Antialiasing Filter (AAF) Group Delay Response Figure 20. Second-Order Harmonic Distortion vs. ADC Output 0 0 –10 –20 –20 –30 –40 –40 GAIN+ = 1.6V GAIN+ = 0V –60 GAIN+ = 0.4V –50 –60 –80 GAIN+ = 1.6V –70 GAIN+ = 0.8V –100 GAIN+ = 1.0V –80 –90 –120 02 46 8 10 12 14 16 –40 –35 –30 –25 –20 –15 –10 –5 0 INPUT FREQUENCY (MHz) ADC OUTPUT LEVEL (dBFS) Figure 18. Second-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS Figure 21. Third-Order Harmonic Distortion vs. ADC Output Level 0 0 f = f +0.01MHz IN2 IN1 –10 –10 A = –1dBFS, A = –21dBFS IN1 IN2 –20 –20 –30 –30 –40 GAIN+ = 0.4V –40 –50 GAIN+ = 1.6V –50 –60 2.3MHz 5MHz 8MHz –60 –70 –70 –80 GAIN+ = 1.0V –90 –80 02 4 6 8 10 12 14 16 0.4 0.6 0.8 1.0 1.2 1.4 1.6 INPUT FREQUENCY (MHz) GAIN+ (V) Figure 19. Third-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS Figure 22. IMD3 vs. GAIN+ Rev. C | Page 17 of 44 SECOND-ORDER HARMONIC DISTORTION (dBFS) THIRD-ORDER HARMONIC DISTORTION (dBFS) GROUP DELAY (ns) 07029-123 07029-121 07029-122 SECOND-ORDER HARMONIC DISTORTION (dBFS) THIRD-ORDER HARMONIC DISTORTION (dBFS) IMD3 (dBFS) 07029-126 07029-125 07029-124 AD9272 0 f = 5.00MHz, f = 5.01MHz IN1 IN2 FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN+ = 1.6V GAIN+ = 0V –80 –100 GAIN+ = 0.8V –120 –40 –35 –30 –25 –20 –15 –10 –5 0 FUND1 LEVEL (dBFS) Figure 23. IMD3 vs. Fundamental 1 Amplitude Level Rev. C | Page 18 of 44 IMD3 (dBFS) 07029-127 AD9272 EQUIVALENT CIRCUITS AVDDx V AVDDx CM 15kΩ 350Ω LI-x, SDIO LG-x 30kΩ Figure 24. Equivalent LNA Input Circuit Figure 27. Equivalent SDIO Input Circuit DRVDD AVDDx V V DOUTx– DOUTx+ 10Ω LO-x, V V LOSW-x DRGND Figure 25. Equivalent LNA Output Circuit Figure 28. Equivalent Digital Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ 1kΩ SCLK, PDWN, 10Ω OR STBY CLK– 30kΩ Figure 26. Equivalent Clock Input Circuit Figure 29. Equivalent SCLK, PDWN, or STBY Input Circuit Rev. C | Page 19 of 44 07029-073 07029-075 07029-007 07029-009 07029-008 07029-010 AD9272 AVDDx 100Ω RBIAS AVDD2 50Ω GAIN+ Figure 30. Equivalent RBIAS Circuit Figure 33. Equivalent GAIN+ Input Circuit AVDDx 70kΩ 1kΩ CSB 40Ω GAIN– +0.5V Figure 31. Equivalent CSB Input Circuit Figure 34. Equivalent GAIN− Input Circuit 10Ω CWDx+, +0.5V CWDx– VREF 6kΩ Figure 32. Equivalent VREF Circuit Figure 35. Equivalent CWDx± Output Circuit Rev. C | Page 20 of 44 07029-014 07029-011 07029-012 07029-176 07029-076 07029-074 AD9272 THEORY OF OPERATION following the TGC amplifier, and then beam forming is ULTRASOUND accomplished digitally. The primary application for the AD9272 is medical ultrasound. The ADC resolution of 12 bits with up to 80 MSPS sampling Figure 36 shows a simplified block diagram of an ultrasound satisfies the requirements of both general-purpose and high- system. A critical function of an ultrasound system is the time end systems. gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is Power conservation and low cost are two of the most important exponential with respect to distance (time), a linear-in-dB VGA factors in low-end and portable ultrasound machines, and the is the optimal solution. AD9272 is designed to meet these criteria. Key requirements in an ultrasound signal chain are very low For additional information regarding ultrasound systems, refer noise, active input termination, fast overload recovery, low to “How Ultrasound System Considerations Influence Front-End power, and differential drive to an ADC. Because ultrasound Component Choice,” Analog Dialogue, Volume 36, Number 1, machines use beam-forming techniques requiring large binary- May–July 2002, and “The AD9271—A Revolutionary Solution weighted numbers (for example, 32 to 512) of channels, using for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3, the lowest power at the lowest possible noise is of chief importance. July 2007. Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately Tx HV AMPs BEAM-FORMER Tx BEAM FORMER CENTRAL CONTROL MULTICHANNELS AD9272 HV Rx BEAM FORMER MUX/ LNA VGA ADC T/R (B AND F MODES) DEMUX SWITCHES AAF CW TRANSDUCER ARRAY 128, 256, ... CW (ANALOG) ELEMENTS IMAGE AND BIDIRECTIONAL BEAM FORMER SPECTRAL COLOR MOTION DOPPLER DOPPLER (PW) CABLE PROCESSING PROCESSING PROCESSING (B MODE) MODE (F MODE) AUDIO DISPLAY OUTPUT Figure 36. Simplified Ultrasound System Block Diagram Rev. C | Page 21 of 44 07029-077 AD9272 R LO-x FB1 CWD[7:0]+ SWITCH g m ARRAY CWD[7:0]– C FB LOSW-x R FB2 T/R SWITCH C S LI-x DOUTx+ ATTENUATOR SERIAL PIPELINE LNA POSTAMP FILTER –42dB TO 0dB LVDS ADC C SH DOUTx– LG-x C LG 15.6dB, 21dB 17.9dB, 24dB, 21.3dB 27dB, GAIN 30dB INTERPOLATOR AD9272 Figure 37. Simplified Block Diagram of a Single Channel The LNA supports differential output voltages as high as 4.4 V p-p CHANNEL OVERVIEW with positive and negative excursions of ±1.1 V from a common- Each channel contains both a TGC signal path and a CW Doppler mode voltage of 1.5 V. The LNA differential gain sets the maximum signal path. Common to both signal paths, the LNA provides user- input signal before saturation. One of three gains is set through adjustable input impedance termination. The CW Doppler path the SPI. The corresponding full-scale input for the gain settings includes a transconductance amplifier and a crosspoint switch. of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and 367 mV p-p, The TGC path includes a differential X-AMP® VGA, an antialiasing respectively. Overload protection ensures quick recovery time filter, and an ADC. Figure 37 shows a simplified block diagram from large input voltages. Because the inputs are capacitively with external components. coupled to a bias voltage near midsupply, very large inputs can The signal path is fully differential throughout to maximize signal be handled without interacting with the ESD protection. swing and reduce even-order distortion; however, the LNA is Low value feedback resistors and the current-driving capability designed to be driven from a single-ended signal source. of the output stage allow the LNA to achieve a low input-referred Low Noise Amplifier (LNA) noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB). This is Good noise performance relies on a proprietary ultralow noise achieved with a current consumption of only 27 mA per channel LNA at the beginning of the signal chain, which minimizes the (80 mW). On-chip resistor matching results in precise single- noise contribution in the following VGA. Active impedance ended gains, which are critical for accurate impedance control. control optimizes noise performance for applications that benefit The use of a fully differential topology and negative feedback from input impedance matching. minimizes distortion. Low second-order harmonic distortion is particularly important in second harmonic ultrasound imaging A simplified schematic of the LNA is shown in Figure 38. LI-x is applications. Differential signaling enables smaller swings at each capacitively coupled to the source. An on-chip bias generator output, further reducing third-order distortion. establishes dc input bias voltages of around 0.9 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by Recommendation 2). A capacitor, C , of the same value as the input coupling LG It is highly recommended that the LG-x pins form a Kelvin type capacitor, C , is connected from the LG-x pin to ground. S connection to the input or probe connection ground. Simply C FB R FB1 connecting the LG pin to ground near the device can allow V + O R FB2 differences in potential to be amplified through the LNA. This V – O generally shows up as a dc offset voltage that can vary from LOSW-x channel to channel and part to part given the application and LO-x V CM layout of the PCB (see Figure 38). V CM T/R SWITCH C S LI-x LG-x C SH C LG Figure 38. Simplified LNA Schematic Rev. C | Page 22 of 44 TRANSDUCER TRANSDUCER 07029-101 GAIN+ GAIN– 07029-071 AD9272 1k Active Impedance Matching R = 500Ω, R = 2kΩ S FB The LNA consists of a single-ended voltage gain amplifier with differential outputs, and the negative output is externally available. For example, with a fixed gain of 8× (17.9 dB), an R = 200Ω, R = 800Ω S FB active input termination is synthesized by connecting a R = 100Ω, R = 400Ω, C = 20pF S FB SH feedback resistor between the negative output pin, LO-x, and the 100 positive input pin, LI-x. This is a well known technique used for R = 50Ω, R = 200Ω, C = 70pF S FB SH interfacing multiple probe impedances to a single system. The input resistance is shown in Equation 1. R FB R = (1) IN A (1+ ) 10 2 100k 1M 10M 100M FREQUENCY (Hz) where A/2 is the single-ended gain or the gain from the LI-x Figure 39. R vs. Frequency for Various Values of R IN FB inputs to the LO-x outputs, and RFB is the resulting impedance (Effects of R and C Are Also Shown) S SH of the RFB1 and RFB2 combination (see Figure 38). Note that at the lowest value (50 Ω), RIN peaks at frequencies Because the amplifier has a gain of 8× from its input to its greater than 10 MHz. This is due to the BW roll-off of the LNA, differential output, it is important to note that the gain A/2 is as mentioned previously. the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier or 12.1 dB (4×). The input resistance is However, as can be seen for larger R values, parasitic capacitance IN starts rolling off the signal BW before the LNA can produce reduced by an internal bias resistor of 15 kΩ in parallel with the peaking. C further degrades the match; therefore, C should source resistance connected to Pin LI-x, with Pin LG-x ac SH SH grounded. Equation 2 can be used to calculate the needed RFB not be used for values of RIN that are greater than 100 Ω. Table 7 for a desired RIN, even for higher values of RIN. lists the recommended values for RFB and CSH in terms of RIN. R CFB is needed in series with RFB because the dc levels at Pin LO-x FB (2) R = ||15 kΩ IN and Pin LI-x are unequal. (1+ 3) For example, to set RIN to 200 Ω, the value of RFB must be Table 7. Active Termination External Component Values 1000 Ω. If the simplified equation (Equation 2) is used to LNA Gain Minimum calculate RIN, the value is 188 Ω, resulting in a gain error less (dB) R (Ω) R (Ω) C (pF) BW (MHz) IN FB SH than 0.6 dB. Some factors, such as the presence of a dynamic 15.6 50 200 90 57 source resistance, might influence the absolute gain accuracy 17.9 50 250 70 69 more significantly. At higher frequencies, the input capacitance 21.3 50 350 50 88 of the LNA must be considered. The user must determine the 15.6 100 400 30 57 level of matching accuracy and adjust RFB accordingly. 17.9 100 500 20 69 21.3 100 700 10 88 The bandwidth (BW) of the LNA is greater than 100 MHz. 15.6 200 800 N/A 72 Ultimately, the BW of the LNA limits the accuracy of the 17.9 200 1000 N/A 72 synthesized RIN. For RIN = RS up to about 200 Ω, the best match 21.3 200 1400 N/A 72 is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and R limit the BW at higher frequencies. S Figure 39 shows RIN vs. frequency for various values of RFB. Rev. C | Page 23 of 44 INPUT RESISTANCE (Ω) 07029-188 AD9272 Figure 41 shows the relative noise figure performance. In this LNA Noise graph, the input impedance was swept with R to preserve the S The short-circuit noise voltage (input-referred noise) is an impor- match at each point. The noise figures for a source impedance of tant limit on system performance. The short-circuit input-referred 50 Ω are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination, noise voltage for the LNA is 0.85 nV/√Hz at a gain of 21.3 dB, active termination, and unterminated configurations, respectively. including the VGA noise at a VGA postamp gain of 27 dB. These The noise figures for 200 Ω are 4.5 dB, 1.7 dB, and 1 dB, measurements, which were taken without a feedback resistor, respectively. provide the basis for calculating the input noise and noise figure Figure 42 shows the noise figure as it relates to R for various values (NF) performance of the configurations shown in Figure 40. S of R , which is helpful for design purposes. IN UNTERMINATED R IN 12.0 R S + 10.5 V OUT LI-x – 9.0 RESISTIVE TERMINATION RESISTIVE TERMINATION 7.5 R IN R S 6.0 + R V S OUT LI-x 4.5 – 3.0 ACTIVE TERMINATION UNTERMINATED ACTIVE IMPEDANCE MATCH 1.5 R R FB IN R S 0 + 10 100 1k V OUT LI-x R (Ω) S – Figure 41. Noise Figure vs. RS for Resistive Termination, Active Termination Matched, and Unterminated Inputs, VGAIN = 0.8 V R FB R = IN 1 + A/2 8 Figure 40. Input Configurations R = 50Ω IN 7 R = 75Ω IN Figure 41 and Figure 42 are simulations of noise figure vs. RS R = 100Ω IN 6 R = 200Ω IN results using these configurations and an input-referred noise UNTERMINATED voltage of 3.8 nV/√Hz for the VGA. Unterminated (RFB = ∞) 5 operation exhibits the lowest equivalent input noise and noise 4 figure. Figure 42 shows the noise figure vs. source resistance rising at low R —where the LNA voltage noise is large compared S 3 with the source noise—and at high R due to the noise contribution S 2 from RFB. The lowest NF is achieved when RS matches RIN. 1 The main purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the 0 10 100 1k input noise increases due to the thermal noise of the matching R (Ω) S resistor and the increased contribution of the input voltage Figure 42. Noise Figure vs. R for Various Fixed Values of R , S IN noise generator of the LNA. With active impedance matching, Active Termination Matched Inputs, V = 0.8 V GAIN however, the contributions of both are smaller (by a factor of 1/(1 + LNA Gain)) than they would be for resistive termination. Rev. C | Page 24 of 44 07029-104 NOISE FIGURE (dB) NOISE FIGURE (dB) 07029-183 07029-182 AD9272 INPUT OVERDRIVE CW DOPPLER OPERATION Excellent overload behavior is of primary importance in Modern ultrasound machines used for medical applications N ultrasound. Both the LNA and VGA have built-in overdrive employ a 2 binary array of receivers for beam forming, with protection and quickly recover after an overload event. typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When Input Overload Protection used in multiples, the desired signals from each channel can be As with any amplifier, voltage clamping prior to the inputs is summed to yield a larger signal (increased by a factor N, where highly recommended if the application is subject to high N is the number of channels), and the noise is increased by the transient voltages. square root of the number of channels. This technique enhances In Figure 43, a simplified ultrasound transducer interface is the signal-to-noise performance of the machine. The critical shown. A common transducer element serves the dual functions elements in a beam-former design are the means to align the of transmitting and receiving ultrasound energy. During the incoming signals in the time domain and the means to sum the transmitting phase, high voltage pulses are applied to the ceramic individual signals into a composite whole. elements. A typical transmit/receive (T/R) switch can consist of Beam forming, as applied to medical ultrasound, is defined as the four high voltage diodes in a bridge configuration. Although the phase alignment and summation of signals that are generated diodes ideally block transmit pulses from the sensitive receiver from a common source but received at different times by a input, diode characteristics are not ideal, and the resulting leakage multi-element ultrasound transducer. Beam forming has two transients imposed on the LI-x inputs can be problematic. functions: it imparts directivity to the transducer, enhancing its Because ultrasound is a pulse system and time-of-flight is used to gain, and it defines a focal point within the body from which the determine depth, quick recovery from input overloads is essential. location of the returning echo is derived. Overload can occur in the preamp and the VGA. Immediately The AD9272 includes the front-end components needed to following a transmit pulse, the typical VGA gains are low, and implement analog beam forming for CW Doppler operation. the LNA is subject to overload from T/R switch leakage. With These components allow CW channels with similar phases to be increasing gain, the VGA can become overloaded due to strong coherently combined before phase alignment and down mixing, echoes that occur near field echoes and acoustically dense materials, thus reducing the number of delay lines or adjustable phase shifters/ such as bone. down mixers (AD8333 or AD8339) required. Next, if delay lines Figure 43 illustrates an external overload protection scheme. A are used, the phase alignment is performed, and then the channels pair of back-to-back signal diodes is installed prior to installing the are coherently summed and down converted by a dynamic range ac-coupling capacitors. Keep in mind that all diodes shown in I/Q demodulator. Alternatively, if phase shifters/down mixers, this example are prone to exhibiting some amount of shot noise. such as the AD8333 and AD8339, are used, phase alignment Many types of diodes are available for achieving the desired and down conversion are done before coherently summing all noise performance. The configuration shown in Figure 43 tends channels into I/Q signals. In either case, the resultant I and Q to add 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ signals are filtered and sampled by two high resolution ADCs, resistor and increasing the 2 kΩ resistor may improve noise and the sampled signals are processed to extract the relevant contribution, depending on the application. With the diodes Doppler information. shown in Figure 43, clamping levels of ±0.5 V or less Alternately, the LNA of the AD9272 can directly drive the AD8333 significantly enhance the overload performance of the system. or AD8339 without the crosspoint switch. The LO-x pin presents +5V the inverting LNA output, and the LOSW-x pin can be configured Tx 5kΩ via Register 0x2C (see Table 17) to connect to the noninverting DRIVER HV AD9272 output to provide a differential output of the LNA. The LNA output 10nF full-scale voltage of the AD9272 is 4.4 V p-p, and the input full- LNA scale voltage is 2.7 V p-p. If no attenuation is provided between 2kΩ 10nF 5kΩ the LNA output and the demodulator, the LNA input full-scale TRANSDUCER voltage must be limited. –5V Figure 43. Input Overload Protection Rev. C | Page 25 of 44 07029-100 AD9272 AD9272 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m AD8333 600µH g LNA 2.5V 700Ω m 600µH 600µH 2.5V 700Ω 600µH AD8333 AD9272 600µH 2.5V 700Ω LNA g 600µH m 600µH LNA g m 2.5V 700Ω 600µH SWITCH ARRAY I 8 × CHANNEL 16-BIT ADC LNA g m Q 16-BIT LNA g ADC m Figure 44. Typical Connection Interface with the AD8333 or AD8339 Using the CWDx± Outputs 2.5V AD9272 5kΩ 5kΩ 1nF LO-A AD8339 500Ω LNA LOSW-A 500Ω 1nF 2.5V 5kΩ 5kΩ 1nF LOS-B 500Ω LNA LOSW-B 500Ω 1nF 2.5V 5kΩ 5kΩ 1nF AD8339 LO-H 500Ω LNA I LOSW-H 16-BIT 500Ω 1nF ADC Q 16-BIT ADC Figure 45. Typical Connection Interface with the AD8333 or AD8339 Using the LO-x and LOSW-x Outputs Rev. C | Page 26 of 44 07029-111 07029-096 AD9272 Crosspoint Switch The maximum gain required is determined by Each LNA is followed by a transconductance amp for voltage- (ADC Noise Floor/VGA Input Noise Floor) + Margin = to-current conversion. Currents can be routed to one of eight 20 log(224/3.9) + 11 dB = 46 dB pairs of differential outputs or to 16 single-ended outputs for The minimum gain required is determined by summing. Each CWD output pin sinks 2.4 mA dc current, and (ADC Input FS/VGA Input FS) + Margin = the signal has a full-scale current of ±2 mA for each channel 20 log(2/0.55) − 10 dB = 3 dB selected by the crosspoint switch. For example, if four channels are summed on one CWD output, the output sinks 9.6 mA dc Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with and has a full-scale current output of ±8 mA. 15 MHz of bandwidth should suffice in achieving the dynamic range required for most ultrasound systems today. The maximum number of channels combined must be considered when setting the load impedance for current-to-voltage conversion The system gain is distributed as listed in Table 8. to ensure that the full-scale swing and common-mode voltage Table 8. Channel Gain Distribution are within the operating limits of the AD9272. When interfacing Section Nominal Gain (dB) to the AD8339, a common-mode voltage of 2.5 V and a full-scale LNA 15.6/17.9/21.3 swing of 2.8 V p-p are desired. This can be accomplished by Attenuator 0 to −42 connecting an inductor between each CWD output and a 2.5 V VGA Amp 21/24/27/30 supply and then connecting either a single-ended or differential Filter 0 load resistance to the CWDx± outputs. The value of resistance ADC 0 should be calculated based on the maximum number of channels that can be combined. The linear-in-dB gain (law conformance) range of the TGC path CWDx± outputs are required under full-scale swing to be is 42 dB. The slope of the gain control interface is 28 dB/V, and greater than 1.5 V and less than AVDD2 (3.0 V supply). the gain control range is −0.8 V to +0.8 V. Equation 3 is the TGC OPERATION expression for the differential voltage VGAIN, and Equation 4 is The TGC signal path is fully differential throughout to the expression for the channel gain. maximize signal swing and reduce even-order distortion; (3) V (V )= GAIN(+)− GAIN(−) GAIN however, the LNAs are designed to be driven from a single- dB ended signal source. Gain values are referenced from the single- (4) Gain (dB)= 28.5 V + ICPT GAIN V ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain where ICPT is the intercept point of the TGC gain. requirements is shown in Figure 46. In its default condition, the LNA has a gain of 21.3 dB (12×), and the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is ADC FS (2V p-p) MINIMUM GAIN 0 V and GAIN− is 0.8 V (42 dB attenuation). This gives rise to a ~10dB MARGIN total gain (or ICPT) of 3.6 dB through the TGC path if the LNA LNA FS 70dB ADC (0.55V p-p SE) input is unmatched or of −2.4 dB if the LNA is matched to 50 Ω (RFB = 350 Ω). If the voltage on the GAIN+ pin is 1.6 V and the 94dB >11dB MARGIN GAIN− pin is 0.8 V (0 dB attenuation), however, the VGA gain ADC NOISE FLOOR LNA (224µV rms) is 24 dB. This results in a total gain of 45 dB through the TGC path MAXIMUM GAIN if the LNA input is unmatched or in a total gain of 39 dB if the LNA INPUT-REFERRED NOISE FLOOR LNA input is matched. (3.9µV rms) @ AAF BW = 15MHz LNA + VGA NOISE = 1.0nV/ Hz VGA GAIN RANGE > 42dB Each LNA output is dc-coupled to a VGA input. The VGA consists MAX CHANNEL GAIN > 48dB of an attenuator with a range of −42 dB to 0 dB followed by an Figure 46. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. Rev. C | Page 27 of 44 07029-097 AD9272 1, 2, 3 Table 9. Sensitivity and Dynamic Range of Trade-Offs LNA VGA Channel Gain Input-Referred Typical Output Dynamic Range 4 Full-Scale Input Noise Voltage Input-Referred Noise @ 5 6 GAIN+ = 1.6 V (nV/√Hz) (V/V) (dB) (V p-p) (nV/√Hz) Postamp Gain (dB) GAIN+ = 0 V GAIN+ = 1.6 V 6 15.6 0.733 0.98 21 67.5 65.1 1.395 24 66.4 63.0 1.286 27 64.6 60.6 1.227 30 62.5 57.9 1.197 8 17.9 0.550 0.86 21 67.5 64.5 1.149 24 66.4 62.3 1.071 27 64.5 59.8 1.030 30 62.5 57.1 1.009 12 21.3 0.367 0.75 21 67.5 63.3 0.910 24 66.4 60.9 0.865 27 64.6 58.2 0.842 30 62.5 55.4 0.830 1 LNA: output full scale = 4.4 V p-p differential. 2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V. 3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input. 4 Channel noise at maximum VGA gain. 5 Output dynamic range at minimum VGA gain (VGA dominated). 6 Output dynamic range at maximum VGA gain (LNA dominated). Table 9 demonstrates the sensitivity and dynamic range of GAIN± pins. The LNA has three limitations, or full-scale settings, trade-offs that can be achieved relative to various LNA and that can be applied through the SPI. Similarly, the VGA has four VGA gain settings. postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN± pins determines which amplifier For example, when the VGA is set for the minimum gain voltage, (the LNA or VGA) saturates first. The maximum signal input level the TGC path is dominated by VGA noise and achieves the that can be applied as a function of voltage on the GAIN± pins maximum output SNR. However, as the postamp gain options for the selectable gain options of the SPI is shown in Figure 47 to are increased, the input-referred noise is reduced, and the SNR Figure 49. is degraded. 0.9 If the VGA is set for the maximum gain voltage, the TGC path 0.8 is dominated by LNA noise and achieves the lowest input- 0.7 referred noise but with degraded output SNR. The higher the TGC (LNA + VGC) gain, the lower the output SNR. As the 0.6 PGA GAIN = 21dB postamp gain is increased, the input-referred noise is reduced. 0.5 At low gains, the VGA should limit the system noise perfor- 0.4 PGA GAIN = 24dB mance (SNR); at high gains, the noise is defined by the source and the LNA. The maximum voltage swing is bound by the full- 0.3 PGA GAIN = 27dB scale peak-to-peak ADC input voltage (2 V p-p). 0.2 PGA GAIN = 30dB Both the LNA and VGA have full-scale limitations within each 0.1 section of the TGC path. These limitations are dependent on the 0 gain setting of each function block and on the voltage applied to the 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 47. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations Rev. C | Page 28 of 44 INPUT FULL SCALE (V p-p) 07029-177 AD9272 0.6 per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from 0.5 the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the 0.4 VGA is controlled by an amplifier that uses the same midsupply PGA GAIN = 21dB voltage derived in the LNA, permitting dc coupling of the LNA 0.3 to the VGA without introducing large offsets due to common- PGA GAIN = 24dB PGA GAIN = 27dB mode differences. However, any offset from the LNA becomes 0.2 amplified as the gain increases, producing an exponentially PGA GAIN = 30dB increasing VGA output offset. 0.1 The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, deter- 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 mines the input tap point. With overlapping bias currents, signals GAIN+ (V) from successive taps merge to provide a smooth attenuation range Figure 48. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations from −42 dB to 0 dB. This circuit technique results in linear-in-dB 0.9 gain law conformance and low distortion levels—only deviating 0.8 ±0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in 0.7 PGA GAIN = 21dB process, temperature, and supply. 0.6 The X-AMP inputs are part of a programmable gain feedback 0.5 amplifier that completes the VGA. Its bandwidth is approximately PGA GAIN = 24dB 0.4 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity 0.3 PGA GAIN = 27dB across the gain setting. 0.2 Gain Control PGA GAIN = 30dB 0.1 PGA GAIN = 30dB The gain control interface, GAIN±, is a differential input. VGAIN 0 varies the gain of all VGAs through the interpolator by selecting 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) the appropriate input stages connected to the input attenuator. Figure 49. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations For GAIN− at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to Variable Gain Amplifier 1.44 V, where the error is typically less than ±0.5 dB. For The differential X-AMP VGA provides precise input attenuation GAIN+ voltages greater than 1.44 V and less than 0.16 V, the and interpolation. It has a low input-referred noise of 3.8 nV/√Hz error increases. The value of GAIN+ can exceed the supply and excellent gain linearity. A simplified block diagram is shown in voltage by 1 V without gain foldover. Figure 50. Gain control response time is less than 750 ns to settle within 10% GAIN± GAIN INTERPOLATOR of the final value for a change from minimum to maximum gain. POSTAMP + There are two ways in which the GAIN+ and GAIN− pins can g m be interfaced. Using a single-ended method, a Kelvin type of 3dB connection to ground can be used as shown in Figure 51. For VIP driving multiple devices, it is preferable to use a differential method, as shown in Figure 52. In either method, the GAIN+ VIN and GAIN− pins should be dc-coupled and driven to accom- modate a 1.6 V full-scale input. AD9272 100Ω 0V TO 1.6V DC – GAIN+ POSTAMP 0.01µF 50Ω Figure 50. Simplified VGA Schematic GAIN– KELVIN 0.01µF CONNECTION The input of the VGA is a 14-stage differential resistor ladder with Figure 51. Single-Ended GAIN± Pins Configuration 3.5 dB per tap. The resulting total gain range is 42 dB, which allows for range loss at the endpoints. The effective input resistance Rev. C | Page 29 of 44 INPUT FULL SCALE (V p-p) INPUT FULL SCALE (V p-p) 07029-179 07029-178 07029-078 07029-109 AD9272 499Ω AVDD2 The antialaising filter is a combination of a single-pole high- pass filter and a second-order low-pass filter. The high-pass ±0.4DC AT AD9272 31.3kΩ 499Ω 100Ω 0.8V CM GAIN+ filter can be configured at a ratio of the low-pass filter cutoff. ±0.8V DC 0.01µF 0.8V CM 50Ω AD8138 This is selectable through the SPI. 523Ω 100Ω GAIN– 10kΩ The filter uses on-chip tuning to trim the capacitors and in turn ±0.4DC AT 0.01µF 0.8V CM set the desired cutoff frequency and reduce variations. The 499Ω default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC Figure 52. Differential GAIN± Pins Configuration sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, VGA Noise 1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz. In a typical application, a VGA compresses a wide dynamic 4kΩ range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable C input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous 30C 4kΩ 2kΩ dynamic range that can be processed at any one particular gain 4C 10kΩ/n control voltage. This latter limit is set in accordance with the 2kΩ total noise floor of the ADC. 4kΩ 30C C Output-referred noise as a function of GAIN+ is shown in Figure 14 for the short-circuit input conditions. The input C = 0.8pF TO 5.1pF 4kΩ n = 0 TO 7 noise voltage is simply equal to the output noise divided by Figure 53. Simplified Filter Schematic the measured gain at each point in the control range. Tuning is normally off to avoid changing the capacitor settings The output-referred noise is a flat 60 nV/√Hz (postamp gain = during critical times. The tuning circuit is enabled and disabled 24 dB) over most of the gain range because it is dominated by through the SPI. Initializing the tuning of the filter must be the fixed output-referred noise of the VGA. At the high end of performed after initial power-up and after reprogramming the gain control range, the noise of the LNA and of the source the filter cutoff scaling or ADC sample rate. Occasional prevail. The input-referred noise reaches its minimum value retuning during an idle time is recommended to compensate near the maximum gain control voltage, where the input- for temperature drift. referred contribution of the VGA is miniscule. There is a total of eight SPI-programmable settings that allow the At lower gains, the input-referred noise, and therefore, the noise user to vary the high-pass filter cutoff frequency as a function figure, increases as the gain decreases. The instantaneous of the low-pass cutoff frequency. Two examples are shown in dynamic range of the system is not lost, however, because the Table 10: one is for an 8 MHz low-pass cutoff frequency and the input capacity increases as the input-referred noise increases. other is for an 18 MHz low-pass cutoff frequency. In both cases, The contribution of the ADC noise floor has the same dependence. as the ratio decreases, the amount of rejection on the low-end The important relationship is the magnitude of the VGA output frequencies increases. Therefore, making the entire AAF noise floor relative to that of the ADC. frequency pass band narrow can reduce low frequency noise or Gain control noise is a concern in very low noise applications. maximize dynamic range for harmonic processing. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output Table 10. SPI-Selectable High-Pass Filter Cutoff Options signal level and is usually evident only when a large signal is High-Pass Cutoff present. The gain interface includes an on-chip noise filter, which Low-Pass Cutoff Low-Pass Cutoff 1 significantly reduces this effect at frequencies above 5 MHz. Care SPI Setting Ratio = 8 MHz = 18 MHz should be taken to minimize noise impinging at the GAIN± 0 20.65 387 kHz 872 kHz inputs. An external RC filter can be used to remove VGAIN source 1 11.45 698 kHz 1.571 MHz noise. The filter bandwidth should be sufficient to accommodate 2 7.92 1.010 MHz 2.273 MHz the desired control bandwidth. 3 6.04 1.323 MHz 2.978 MHz 4 4.88 1.638 MHz 3.685 MHz Antialiasing Filter 5 4.10 1.953 MHz 4.394 MHz The filter that the signal reaches prior to the ADC is used to 6 3.52 2.270 MHz 5.107 MHz reject dc signals and to band limit the signal for antialiasing. 7 3.09 2.587 MHz 5.822 MHz Figure 53 shows the architecture of the filter. 1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency. Rev. C | Page 30 of 44 07029-098 07029-110 AD9272 3.3V ADC * 50Ω AD951x FAMILY VFAC3 0.1µF 0.1µF The AD9272 uses a pipelined ADC architecture. The quantized OUT CLK CLK+ output from each stage is combined into a 12-bit result in the ADC 100Ω digital correction logic. The pipelined architecture permits the LVDS DRIVER AD9272 0.1µF 0.1µF first stage to operate on a new input sample and the remaining CLK– CLK stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. * 50Ω RESISTOR IS OPTIONAL. The output staging block aligns the data, corrects errors, and Figure 56. Differential LVDS Sample Clock passes the data to the output buffers. The data is then serialized In some applications, it is acceptable to drive the sample clock and aligned to the frame and output clocks. inputs with a single-ended CMOS signal. In such applications, CLOCK INPUT CONSIDERATIONS CLK+ should be driven directly from a CMOS gate, and the For optimum performance, the AD9272 sample clock inputs CLK− pin should be bypassed to ground with a 0.1 μF capacitor (CLK+ and CLK−) should be clocked with a differential signal. in parallel with a 39 kΩ resistor (see Figure 57). Although the This signal is typically ac-coupled into the CLK+ and CLK− pins CLK+ input circuit supply is AVDDx (1.8 V), this input is via a transformer or capacitors. These pins are biased internally designed to withstand input voltages of up to 3.3 V, making the and require no additional bias. selection of the drive logic voltage very flexible. 3.3V Figure 54 shows the preferred method for clocking the AD9272. AD951x FAMILY A low jitter clock source, such as the Valpey Fisher oscillator 0.1µF VFAC3 OUT CLK VFAC3-BHL-50 MHz, is converted from single-ended to OPTIONAL 0.1µF * 50Ω 100Ω differential using an RF transformer. The back-to-back Schottky CMOS DRIVER CLK+ ADC diodes across the secondary transformer limit clock excursions CLK AD9272 into the AD9272 to approximately 0.8 V p-p differential. This 0.1µF CLK– helps prevent the large voltage swings of the clock from feeding 0.1µF 39kΩ through to other portions of the AD9272, and it preserves the * 50Ω RESISTOR IS OPTIONAL. fast rise and fall times of the signal, which are critical to low Figure 57. Single-Ended 1.8 V CMOS Sample Clock jitter performance. 3.3V 3.3V MINI-CIRCUITS AD951x FAMILY 0.1µF VFAC3 ADT1-1WT, 1:1Z CLK OUT 0.1µF 0.1µF OPTIONAL XFMR * 0.1µF 50Ω 100Ω OUT CLK+ CLK+ CMOS DRIVER 100Ω ADC 50Ω 0.1µF AD9272 ADC VFAC3 CLK CLK– AD9272 0.1µF 0.1µF SCHOTTKY 0.1µF CLK– DIODES: HSM2812 Figure 54. Transformer-Coupled Differential Clock * 50Ω RESISTOR IS OPTIONAL. If a low jitter clock is available, another option is to ac-couple a Figure 58. Single-Ended 3.3 V CMOS Sample Clock differential PECL signal to the sample clock input pins as shown Clock Duty Cycle Considerations in Figure 55. The AD951x family of clock drivers offers excellent Typical high speed ADCs use both clock edges to generate a jitter performance. variety of internal timing signals. As a result, these ADCs may 3.3V be sensitive to the clock duty cycle. Commonly, a 5% tolerance is * 50Ω AD951x FAMILY required on the clock duty cycle to maintain dynamic performance VFAC3 0.1µF 0.1µF OUT CLK+ CLK characteristics. The AD9272 contains a duty cycle stabilizer (DCS) ADC that retimes the nonsampling edge, providing an internal clock 100Ω PECL DRIVER AD9272 0.1µF 0.1µF signal with a nominal 50% duty cycle. This allows a wide range CLK– CLK of clock input duty cycles without affecting the performance of 240Ω 240Ω the AD9272. When the DCS is on, noise and distortion perfor- * 50Ω RESISTOR IS OPTIONAL. mance are nearly flat for a wide range of duty cycles. However, Figure 55. Differential PECL Sample Clock some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 17 for more details on using this feature. Rev. C | Page 31 of 44 07029-050 07029-051 07029-054 07029-053 07029-052 AD9272 400 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the 350 sampling frequency require approximately eight clock cycles 300 I , 80MSPS SPEED GRADE AVDD1 to allow the DLL to acquire and lock to the new rate. 250 Clock Jitter Considerations I , 65MSPS SPEED GRADE AVDD1 High speed, high resolution ADCs are sensitive to the quality of the 200 clock input. The degradation in SNR at a given input frequency (f ) I , 40MSPS SPEED GRADE A AVDD1 150 due only to aperture jitter (t ) can be calculated by J 100 SNR Degradation = 20 × log 10[1/2 × π × f × t ] A J I DRVDD 50 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input 0 0 10 20 30 40 50 60 70 80 signal, and ADC aperture jitter. IF undersampling applications SAMPLING FREQUENCY (MSPS) are particularly sensitive to jitter (see Figure 59). Figure 60. Supply Current vs. f for f = 5 MHz SAMPLE IN The clock input should be treated as an analog signal in cases 220 where aperture jitter may affect the dynamic range of the AD9272. 215 Power supplies for clock drivers should be separated from the 210 80MSPS SPEED GRADE ADC output driver supplies to avoid modulating the clock signal 205 with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. 200 If the clock is generated from another type of source (by gating, 195 65MSPS SPEED GRADE dividing, or other methods), it should be retimed by the 190 original clock during the last step. 185 Refer to the AN-501 Application Note and the AN-756 180 40MSPS SPEED GRADE Application Note for more in-depth information about how 175 jitter performance relates to ADCs (visit www.analog.com). 170 130 0 10 20 30 40 50 60 70 80 RMS CLOCK JITTER REQUIREMENT 120 SAMPLING FREQUENCY (MSPS) Figure 61. Power per Channel vs. f for f = 5 MHz 110 SAMPLE IN 16 BITS 100 The AD9272 features scalable LNA bias currents (see Register 0x12 in Table 17). The default LNA bias current settings are high. 90 14 BITS Figure 62 shows the typical reduction of AVDD2 current with 80 12 BITS each bias setting. It is also recommended to adjust the LNA offset 70 10 BITS using Register 0x10 in Table 17 when the LNA bias setting is low. 60 0.125ps 8 BITS 50 0.25ps HIGH 0.5ps 1.0ps 40 2.0ps 30 1 10 100 1000 MID-HIGH ANALOG INPUT FREQUENCY (MHz) Figure 59. Ideal SNR vs. Analog Input Frequency and Jitter Power Dissipation and Power-Down Mode MID-LOW As shown in Figure 61, the power dissipated by the AD9272 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the LOW DRVDD supply and bias current of the LVDS output drivers. 0 50 100 150 200 250 300 350 400 TOTAL AVDD2 CURRENT (mA) Figure 62. AVDD2 Current at Different LNA Bias Settings, AD9272-40 Rev. C | Page 32 of 44 SNR (dB) 07029-038 LNA BIAS SETTING POWER/CHANNEL (mW) CURRENT (mA) 07029-031 07029-032 07029-119 AD9272 By asserting the PDWN pin high, the AD9272 is placed into The AD9272 LVDS outputs facilitate interfacing with LVDS power-down mode. In this state, the device typically dissipates receivers in custom ASICs and FPGAs that have LVDS capability 2 mW. During power-down, the LVDS output drivers are placed for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a into a high impedance state. The AD9272 returns to normal operating mode when the PDWN pin is pulled low. This pin is 100 Ω termination resistor placed as close to the receiver as both 1.8 V and 3.3 V tolerant. possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended By asserting the STBY pin high, the AD9272 is placed into a that the trace length be no longer than 24 inches and that the standby mode. In this state, the device typically dissipates differential output traces be kept close together and at equal 150 mW. During standby, the entire part is powered down lengths. An example of the FCO, DCO, and data stream with except the internal references. The LVDS output drivers are proper trace length and position can be found in Figure 63. placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power this device back up is also greatly reduced. The AD9272 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles CH1 500mV/DIV = DCO 5.0ns/DIV result in proportionally shorter wake-up times. To restore the CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO device to full operation, approximately 0.5 ms is required when Figure 63. LVDS Output Timing Example in ANSI-644 Mode (Default) using the recommended 1 μF and 0.1 μF decoupling capacitors An example of the LVDS output using the ANSI-644 standard on the VREF pin and 0.01 μF on the GAIN± pins. Most of this (default) data eye and a time interval error (TIE) jitter histogram time is dependent on the gain decoupling: higher value decoupling with trace lengths less than 24 inches on regular FR-4 material is capacitors on the GAIN± pins result in longer wake-up times. shown in Figure 64. Figure 65 shows an example of the trace There are a number of other power-down options available when lengths exceeding 24 inches on regular FR-4 material. Notice using the SPI port interface. The user can individually power that the TIE jitter histogram reflects the decrease of the data eye down each channel or put the entire device into standby mode. opening as the edge deviates from the ideal position; therefore, This allows the user to keep the internal PLL powered up when fast the user must determine if the waveforms meet the timing budget wake-up times are required. The wake-up time is slightly dependent of the design when the trace lengths exceed 24 inches. on gain. To achieve a 1 μs wake-up time when the device is in Additional SPI options allow the user to further increase the standby mode, 0.8 V must be applied to the GAIN± pins. See internal termination (and therefore increase the current) of all Table 17 for more details on using these features. eight outputs in order to drive longer trace lengths (see Figure 66). Digital Outputs and Timing Even though this produces sharper rise and fall times on the The AD9272 differential outputs conform to the ANSI-644 LVDS data edges, is less prone to bit errors, and improves frequency standard on default power-up. This can be changed to a low power, distribution (see Figure 66), the power dissipation of the DRVDD reduced signal option similar to the IEEE 1596.3 standard by supply increases when this option is used. using Register 14, Bit 6 or via the SPI. This LVDS standard can In cases that require increased driver strength to the DCO± and further reduce the overall power dissipation of the device by FCO± outputs because of load mismatch, Register 0x15 allows approximately 36 mW. the user to double the drive strength. To do this, set the appropriate The LVDS driver current is derived on chip and sets the output bit in Register 0x05. Note that this feature cannot be used with current at each output equal to a nominal 3.5 mA. A 100 Ω differ- Bit 4 and Bit 5 in Register 0x15 because these bits take precedence ential termination resistor placed at the LVDS receiver inputs over this feature. See Table 17 for more details. results in a nominal 350 mV swing at the receiver. Rev. C | Page 33 of 44 07029-034 AD9272 600 400 EYE: ALL BITS EYE: ALL BITS ULS: 2398/2398 ULS: 2399/2399 400 300 200 200 100 100 0 0 –100 –100 –200 –200 –400 –300 –600 –400 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 25 25 20 20 15 15 10 10 5 5 0 0 –200ps –100ps 0ps 100ps 200ps –200ps –100ps 0ps 100ps 200ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches On Standard FR-4 of Greater Than 24 Inches On Standard FR-4 Rev. C | Page 34 of 44 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07029-035 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07029-036 AD9272 600 EYE: ALL BITS ULS: 2396/2396 The format of the output data is offset binary by default. An 400 example of the output coding format can be found in Table 11. To change the output data format to twos complement, see the 200 Memory Map section. 0 Table 11. Digital Output Coding (VIN+) − (VIN−), Digital Output Offset Binary –200 Code Input Span = 2 V p-p (V) (D11...D0) 4095 +1.00 1111 1111 1111 –400 2048 0.00 1000 0000 0000 2047 −0.000488 0111 1111 1111 0 −1.00 0000 0000 0000 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits 25 times the sample clock rate, with a maximum of 960 Mbps (12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion 20 rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for 15 a specific application. See Table 17 for details on enabling this feature. 10 Two output clocks are provided to assist in capturing data from the AD9272. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the 5 AD9272 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The 0 frame clock output (FCO±) is used to signal the start of a new –200ps –100ps 0ps 100ps 200ps output byte and is equal to the sampling clock rate. See the Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4 timing diagram shown in Figure 2 for more information. Table 12. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 1000 0000 0000 Yes 0010 +Full-scale short 1111 1111 1111 1111 1111 1111 Yes 0011 −Full-scale short 0000 0000 0000 0000 0000 0000 Yes 0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No 0101 PN sequence long N/A N/A Yes 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 1010 1010 1010 N/A No 1010 1× sync 0000 0011 1111 N/A No 1011 One bit high 1000 0000 0000 N/A No 1100 Mixed bit frequency 1010 0011 0011 N/A No Rev. C | Page 35 of 44 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 07029-037 AD9272 When using the serial port interface (SPI), the DCO± phase can SDIO Pin be adjusted in 60° increments relative to the data edge. This This pin is required to operate the SPI. It has an internal 30 kΩ enables the user to refine system timing margins if required. pull-down resistor that pulls this pin low and is only 1.8 V The default DCO± timing, as shown in Figure 2, is 90° relative tolerant. If applications require that this pin be driven from a to the output data edge. 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams SCLK Pin and test the compatibility of the device, with lower and higher This pin is required to operate the SPI port interface. It has an resolution systems. When changing the resolution to an 8- or internal 30 kΩ pull-down resistor that pulls this pin low and is 10-bit serial stream, the data stream is shortened. When using both 1.8 V and 3.3 V tolerant. the 14-bit option, the data stream stuffs two 0s at the end of the CSB Pin normal 14-bit serial data. This pin is required to operate the SPI port interface. It has an When using the SPI, all of the data outputs can also be inverted internal 70 kΩ pull-up resistor that pulls this pin high and is both from their nominal state. This is not to be confused with inverting 1.8 V and 3.3 V tolerant. the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial RBIAS Pin stream. However, this can be inverted so that the LSB is repre- To set the internal core bias current of the ADC, place a resistor sented first in the data output serial stream (see Figure 3). nominally equal to 10 kΩ to ground at the RBIAS pin. Using There are 12 digital output test pattern options available that other than the recommended 10 kΩ resistor for RBIAS degrades can be initiated through the SPI. This is a useful feature when the performance of the device. Therefore, it is imperative that at validating receiver capture and timing. Refer to Table 12 for the least a 1% tolerance on this resistor be used to achieve consistent output bit sequencing options available. Some test patterns have performance. two serial sequential words and can be alternated in various Voltage Reference ways, depending on the test pattern chosen. Note that some A stable and accurate 0.5 V voltage reference is built into the patterns may not adhere to the data format select option. In AD9272. This is gained up internally by a factor of 2, setting addition, user patterns can be assigned in the 0x19, 0x1A, 0x1B, VREF to 1 V, which results in a full-scale differential input span and 0x1C register addresses. All test mode options except PN of 2 V p-p for the ADC. VREF is set internally by default, but the sequence short and PN sequence long can support 8- to 14-bit VREF pin can be driven externally with a 1.0 V reference to word lengths in order to verify data capture to the receiver. achieve more accuracy. However, this device does not support The PN sequence short pattern produces a pseudorandom ADC full-scale ranges below 2 V p-p. 9 bit sequence that repeats itself every 2 − 1 bits or 511 bits. A When applying the decoupling capacitors to the VREF pin, use description of the PN sequence and how it is generated can be ceramic low-ESR capacitors. These capacitors should be close to found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The the reference pin and on the same layer of the PCB as the AD9272. only difference is that the starting value is a specific value instead The VREF pin should have both a 0.1 μF capacitor and a 1 μF of all 1s (see Table 13 for the initial values). capacitor connected in parallel to the analog ground. These The PN sequence long pattern produces a pseudorandom bit capacitor values are recommended for the ADC to properly 23 sequence that repeats itself every 2 − 1 bits or 8,388,607 bits. A settle and acquire the next valid sample. description of the PN sequence and how it is generated can be The reference settings can be selected using the SPI. The settings found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The allow two options: using the internal reference or using an external only differences are that the starting value is a specific value reference. The internal reference option is the default setting and instead of all 1s, and the AD9272 inverts the bit stream with has a resulting differential span of 2 V p-p. relation to the ITU standard (see Table 13 for the initial values). Table 14. SPI-Selectable Reference Settings Table 13. PN Sequence Resulting Resulting Differential Initial First Three Output Samples SPI-Selected Mode VREF (V) Span (V p-p) Sequence Value (MSB First) External Reference N/A 2 × external reference PN Sequence Short 0x0DF 0xDF9, 0x353, 0x301 Internal Reference (Default) 1 2 PN Sequence Long 0x29B80A 0x591, 0xFD7, 0x0A3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. C | Page 36 of 44 AD9272 Power and Ground Recommendations the AD9272 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal When connecting power to the AD9272, it is recommended path for heat dissipation to flow through the bottom of the PCB. that two separate 1.8 V supplies be used: one for analog (AVDD) These vias should be filled or plugged with nonconductive epoxy. and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 first and then To maximize the coverage and adhesion between the device and tapped off and isolated with a ferrite bead or a filter choke PCB, partition the continuous copper pad by overlaying a silk- preceded by decoupling capacitors for the DRVDD. The user screen or solder mask to divide it into several uniform sections. should employ several decoupling capacitors on all supplies to This ensures several tie points between the two during the reflow cover both high and low frequencies. These should be located process. Using one continuous plane with no partitions only close to the point of entry at the PC board level and close to the guarantees one tie point between the AD9272 and PCB. See parts with minimal trace lengths. Figure 67 for a PCB layout example. For more detailed infor- mation on packaging and for more PCB layout examples, see A single PC board ground plane should be sufficient when the AN-772 Application Note. using the AD9272. With proper decoupling and smart parti- SILKSCREEN PARTITION tioning of the analog, digital, and clock sections of the PC PIN 1 INDICATOR board, optimum performance can be easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD9272. An exposed continuous copper plane on the PCB should mate to Figure 67. Typical PCB Layout Rev. C | Page 37 of 44 07029-069 AD9272 SERIAL PORT INTERFACE (SPI) The AD9272 serial port interface allows the user to configure In addition to the operation modes, the SPI port can be the signal chain for specific functions or operations through a configured to operate in different manners. For applications structured register space provided inside the chip. This offers that do not require a control port, the CSB line can be tied and the user added flexibility and customization, depending on the held high. This places the remainder of the SPI pins in their application. Addresses are accessed via the serial port and can secondary mode as defined in the SDIO Pin and SCLK Pin be written to or read from via the port. Memory is organized sections. CSB can also be tied low to enable 2-wire mode. When into bytes that can be further divided down into fields, as doc- CSB is tied low, SCLK and SDIO are the only pins required for umented in the Memory Map section. Detailed operational communication. Although the device is synchronized during information can be found in the Analog Devices, Inc., AN-877 power-up, caution must be exercised when using this mode to Application Note, Interfacing to High Speed ADCs via SPI. ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use There are three pins that define the serial port interface or SPI. a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB They are the SCLK, SDIO, and CSB pins. The SCLK (serial line, streaming mode can be entered but not exited. clock) is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual- In addition to word length, the instruction phase determines if purpose pin that allows data to be sent to and read from the the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents internal memory map registers of the device. The CSB (chip select bar) is an active low control that enables or disables the of the on-chip memory. If the instruction is a readback operation, read and write cycles (see Table 15). performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the Table 15. Serial Port Pins appropriate point in the serial frame. Pin Function Data can be sent in MSB- or LSB-first mode. MSB-first mode SCLK Serial clock. The serial shift clock input. SCLK is used to is the default at power-up and can be changed by adjusting the synchronize serial interface reads and writes. configuration register. For more information about this and SDIO Serial data input/output. A dual-purpose pin. The typical other features, see the AN-877 Application Note, Interfacing to role for this pin is as an input or output, depending on the instruction sent and the relative position in the High Speed ADCs via SPI. timing frame. HARDWARE INTERFACE CSB Chip select bar (active low). This control gates the read and write cycles. The pins described in Table 15 constitute the physical interface between the programming device of the user and the serial port of the AD9272. The SCLK and CSB pins function as inputs The falling edge of the CSB pin in conjunction with the rising edge when using the SPI interface. The SDIO pin is bidirectional, of the SCLK determines the start of the framing sequence. During functioning as an input during write phases and as an output an instruction phase, a 16-bit instruction is transmitted, followed during readback. by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its In cases where multiple SDIO pins share a common connection, definitions can be found in Figure 69 and Table 16. care should be taken to ensure that proper V levels are met. OH Figure 68 shows the number of SDIO pins that can be connected In normal operation, CSB is used to signal to the device that SPI together, assuming the same load as the AD9272 and the commands are to be received and processed. When CSB is brought resulting VOH level. low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instruct- tions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset, and the device waits for a new instruction. Rev. C | Page 38 of 44 AD9272 1.800 This interface is flexible enough to be controlled by either serial 1.795 PROMS or PIC mirocontrollers. This provides the user with 1.790 1.785 an alternative method, other than a full SPI controller, for 1.780 programming the device (see the AN-812 Application Note). 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 03 10 200 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading t t t t DS HI CLK H t t S t DH LO CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 69. Serial Timing Details Table 16. Serial Timing Definitions Parameter Minimum Timing (ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock t 5 Setup time between CSB and SCLK S t 2 Hold time between CSB and SCLK H tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 69) t 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK DIS_SDIO rising edge (not shown in Figure 69) Rev. C | Page 39 of 44 V (V) OH 07029-113 07029-068 AD9272 MEMORY MAP Caution READING THE MEMORY MAP TABLE All registers except Register 0x00, Register 0x02, Register 0x04, Each row in the memory map table has eight address locations. Register 0x05, and Register 0xFF are buffered with a master The memory map is roughly divided into three sections: the slave latch and require writing to the transfer bit. For more chip configuration register map (Address 0x00 to Address 0x02), information on this and other functions, consult the AN-877 the device index and transfer register map (Address 0x04 to Application Note, Interfacing to High Speed ADCs via SPI. Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D). RESERVED LOCATIONS The leftmost column of the memory map indicates the register Undefined memory locations should not be written to except address number, and the default value is shown in the second when writing the default values suggested in this data sheet. rightmost column. The Bit 7 (MSB) column is the start of the Addresses that have values marked as 0 should be considered default hexadecimal value given. For example, Address 0x09, reserved and have a 0 written into their registers during power-up. the clock register, has a default value of 0x01, meaning that Bit 7 DEFAULT VALUES = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, After a reset, critical registers are automatically loaded with and Bit 0 = 1, or 0000 0001 in binary. This setting is the default default values. These values are indicated in Table 17, where an for the duty cycle stabilizer in the on condition. When a 0 is X refers to an undefined feature. written to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It LOGIC LEVELS is important to follow each writing sequence with a write to the An explanation of various registers follows: “bit is set” is SW transfer bit to update the SPI registers. synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. C | Page 40 of 44 AD9272 Table 17. AD9272 Memory Map Register Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments Chip Configuration Registers 00 Chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so that (default) 0 = off 0 = off (default) LSB- or MSB-first (default) (default) mode is set cor- rectly regardless of shift mode. 01 Chip_id Chip ID Bits[7:0] Read Default is unique (AD9272 = 0x2E, default) only chip ID, different for each device. This is a read-only register. 02 Chip_grade X X Child ID[5:4] X X X X 0x00 Child ID used to (identify device differentiate variants of Chip ID) graded devices. 00 = 40 MSPS (default) 01 = 65 MSPS 10 = 80 MSPS Device Index and Transfer Registers 04 Device_index_2 X X X X Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel determine which H G F E on-chip device 1 = on 1 = on 1 = on 1 = on receives the next (default) (default) (default) (default) write command. 0 = off 0 = off 0 = off 0 = off 05 Device_index_1 X X Clock Clock Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel Channel Channel determine which DCO± FCO± D C B A on-chip device 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next 0 = off 0 = off (default) (default) (default) (default) write command. (default) (default) 0 = off 0 = off 0 = off 0 = off FF device_update X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the master 0 = off shift register to (default) the slave. ADC Functions 08 Modes X X X X 0 Internal power-down mode 0x00 Determines 000 = chip run (default) various generic 001 = full power-down modes of chip 010 = standby operation 011 = reset (global). 100 = CW mode (TGC PDWN) 09 Clock X X X X X X X Duty 0x01 Turns the internal cycle duty cycle stabilizer stabilizer on and off 1 = on (global). (default) 0 = off 0D Test_io User test mode Reset PN Reset PN Output test mode—see Table 12 0x00 When this register 00 = off (default) long short 0000 = off (default) is set, the test data 01 = on, single gen gen 0001 = midscale short is placed on the alternate 1 = on 1 = on 0010 = +FS short output pins in 10 = on, single once 0 = off 0 = off 0011 = −FS short place of normal data. (Local, expect 11 = on, alternate once (default) (default) 0100 = checkerboard output 0101 = PN sequence long for PN sequence.) 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the output_mode register) Rev. C | Page 41 of 44 AD9272 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 0F Flex_channel_input Filter cutoff frequency control X X X X 0x30 Antialiasing filter 0000 = 1.3 × 1/3 × fSAMPLE cutoff (global). 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × f (default) SAMPLE 0100 = 0.9 × 1/3 × f SAMPLE 0101 = 0.8 × 1/3 × f SAMPLE 0110 = 0.7 × 1/3 × f SAMPLE 1000 = 1.3 × 1/4.5 × f SAMPLE 1001 = 1.2 × 1/4.5 × f SAMPLE 1010 = 1.1 × 1/4.5 × f SAMPLE 1011 = 1.0 × 1/4.5 × f SAMPLE 1100 = 0.9 × 1/4.5 × f SAMPLE 1101 = 0.8 × 1/4.5 × f SAMPLE 1110 = 0.7 × 1/4.5 × f SAMPLE 10 Flex_offset X X 6-bit LNA offset adjustment 0x20 LNA force offset 10 0000 for LNA bias high, mid-high, mid-low (default) correction 10 0001 for LNA bias low (local). 11 Flex_gain X X X X PGA gain LNA gain 0x06 LNA and PGA 00 = 21 dB 00 = 15.6 dB gain adjustment 01 = 24 dB (default) 01 = 17.9 dB (global). 10 = 27 dB 10 = 21.3 dB 11 = 30 dB (default) 12 Bias_current X X X X 1 X LNA bias 0x08 LNA bias current 00 = high (default) adjustment 01 = mid-high (global). 10 = mid-low 11 = low 14 Output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos format of the data 1 = LVDS 0 = off complement (Bits[7:3] and low power, (default) Bits[1:0] are global; (IEEE Bit 2 is local). 1596.3 similar) 15 Output_adjust X X Output driver X X X DCO± 0x00 Determines LVDS termination and or other output 00 = none (default) FCO± properties. 01 = 200 Ω 2× drive Primarily functions 10 = 100 Ω strength to set the LVDS 11 = 100 Ω 1 = on span and 0 = off common-mode (default) levels in place of an external resistor (Bits[7:1] are global; Bit 0 is local). 16 Output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) use global clock (Default: 180° relative to data edge) divide, 0000 = 0° relative to data edge determines which 0001 = 60° relative to data edge phase of the 0010 = 120° relative to data edge divider output is 0011 = 180° relative to data edge used to supply 0100 = 240° relative to data edge the output clock. 0101 = 300° relative to data edge Internal latching is unaffected. 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge 18 Flex_vref X 0 = X X X X X X 0x00 Select internal internal reference reference (recommended 1 = default) or external external reference reference (global). Rev. C | Page 42 of 44 AD9272 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 19 User_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB (global). 1A User_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB (global). 1B User_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB (global). 1C User_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB (global). 21 Serial_control LSB first X X X <10 000 = 12 bits (default, normal 0x00 Serial stream 1 = on MSPS, bit stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native bit rate 011 = 12 bits stream (global). mode 100 = 14 bits 1 = on 0 = off (default) 22 Serial_ch_stat X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) 2B Flex_filter X Enable X X High-pass filter cutoff 0x00 Filter cutoff automatic 0000 = f /20.7 (global). (f = LP LP low-pass 0001 = f /11.5 low-pass filter LP tuning 0010 = f /7.9 cutoff frequency.) LP 1 = on 0011 = f /6.0 LP (self- 0100 = f /4.9 LP clearing) 0101 = f /4.1 LP 0110 = f /3.5 LP 0111 = f /3.1 LP 2C Analog_input X X X X X X LOSW-x connect 0x00 LNA active 00 = high Z termination/input 01 = (−)LNA output impedance 10 = (+)LNA output (global). 11 = high Z 2D Cross_point_switch X X Crosspoint switch enable 0x00 Crosspoint switch 10 0000 = CWD0± (differential) enable (local). 10 0001 = CWD1± (differential) 10 0010 = CWD2± (differential) 10 0011 = CWD3± (differential) 10 0100 = CWD4± (differential) 10 0101 = CWD5± (differential) 10 0110 = CWD6± (differential) 10 0111 = CWD7± (differential) 11 0000 = CWD0+ (single-ended) 11 0001 = CWD1+ (single-ended) 11 0010 = CWD2+ (single-ended) 11 0011 = CWD3+ (single-ended) 11 0100 = CWD4+ (single-ended) 11 0101 = CWD5+ (single-ended) 11 0110 = CWD6+ (single-ended) 11 0111 = CWD7+ (single-ended) 11 1000 = CWD0− (single-ended) 11 1001 = CWD1− (single-ended) 11 1010 = CWD2− (single-ended) 11 1011 = CWD3− (single-ended) 11 1100 = CWD4− (single-ended) 11 1101 = CWD5− (single-ended) 11 1110 = CWD6− (single-ended) 11 1111 = CWD7− (single-ended) 0x xxxx = power down CW channel (default) Rev. C | Page 43 of 44 AD9272 OUTLINE DIMENSIONS 16.00 BSC SQ 1.20 0.75 MAX 0.60 14.00 BSC SQ 0.45 76 100 100 76 1 75 75 1 PIN 1 EXPOSED 9.50 SQ TOP VIEW PAD (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 (PINS UP) 0.09 51 51 25 25 0.95 7° 26 50 50 26 3.5° 0.50 BSC 0.27 0.15 VIEW A 0° SEATING LEAD PITCH 0.22 FOR PROPER CONNECTION OF 0.05 0.08 MAX PLANE THE EXPOSED PAD, REFER TO COPLANARITY 0.17 THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Model Range Package Description Option 1 AD9272BSVZ-80 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9272BSVZRL-80 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9272BSVZ-65 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9272BSVZRL-65 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9272BSVZ-40 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 1 AD9272BSVZRL-40 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 1 AD9272-65EBZ Evaluation Board 1 AD9272-80KITZ Evaluation Board and High Speed FPGA-Based Data Capture Board 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07029-0-7/09(C) Rev. C | Page 44 of 44 100908-A