ANALOG DEVICES AD9269

16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V to 3.3 V output supply SPI Integrated quadrature error correction (QEC) AD9269 ORA SNR 77.6 dBFS at 9.7 MHz input PROGRAMMING DATA D15A VIN+A ADC 71 dBFS at 200 MHz input VIN–A D0A SFDR DCOA 93 dBc at 9.7 MHz input VREF 80 dBc at 200 MHz input QUADRATURE SENSE DRVDD ERROR Low power CORRECTION REF VCM 44 mW per channel at 20 MSPS SELECT ORB RBIAS 100 mW per channel at 80 MSPS D15B Differential input with 700 MHz bandwidth VIN–B ADC On-chip voltage reference and sample-and-hold circuit VIN+B D0B 2 V p-p differential analog input DCOB DNL = −0.5/+1.1 LSB Serial port control options DIVIDE DUTY CYCLE MODE 1TO 6 STABILIZER CONTROLS Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer (DCS) CLK+ CLK– SYNC DCS PDWN DFS OEB Integer 1-to-6 input clock divider Figure 1. Data output multiplex option Built-in selectable digital test pattern generation PRODUCT HIGHLIGHTS Energy-saving power-down modes 1. The AD9269 operates from a single 1.8 V analog power Data clock output (DCO) with programmable clock and supply and features a separate digital output driver supply data alignment to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent APPLICATIONS performance for input frequencies up to 200 MHz and is Communications designed for low cost, low power, and ease of use. Diversity radio systems 3. An optional SPI selectable dc correction and quadrature Multimode digital receivers error correction (QEC) feature corrects for dc offset, gain, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA and phase mismatches between the two channels. I/Q demodulation systems 4. A standard serial port interface (SPI) supports various Smart antenna systems product features and functions, such as data output format- Battery-powered instruments ting, internal clock divider, power-down, DCO/data timing Handheld scope meters and offset adjustments, and voltage reference modes. Portable medical imaging 5. The AD9269 is packaged in a 64-lead RoHS-compliant Ultrasound LFCSP that is pin compatible with the AD9268 16-bit Radar/LIDAR ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MUX OPTION CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 08538-001 AD9269 TABLE OF CONTENTS Features .............................................................................................. 1  Clock Input Considerations ...................................................... 22  Applications ....................................................................................... 1  Power Dissipation and Standby Mode .................................... 24  Functional Block Diagram .............................................................. 1  Digital Outputs ........................................................................... 25  Product Highlights ........................................................................... 1  Timing ......................................................................................... 25  Revision History ............................................................................... 2  Built-In Self-Test (BIST) and Output Test .................................. 26  General Description ......................................................................... 3  Built-In Self-Test (BIST) ............................................................ 26  Specif ica t ions ..................................................................................... 4  Output Test Modes ..................................................................... 26  DC Specifications ......................................................................... 4  Channel/Chip Synchronization .................................................... 27  AC Specifications .......................................................................... 6  DC and Quadrature Error Correction (QEC) ............................ 28  Digital Specifications ................................................................... 7  Serial Port Interface (SPI) .............................................................. 29  Switching Specifications .............................................................. 8  Configuration Using the SPI ..................................................... 29  Timing Specifications .................................................................. 9  Hardware Interface ..................................................................... 29  Absolute Maximum Ratings .......................................................... 10  Configuration Without the SPI ................................................ 30  Thermal Characteristics ............................................................ 10  SPI Accessible Features .............................................................. 30  ESD Caution ................................................................................ 10  Memory Map .................................................................................. 31  Pin Configuration and Function Descriptions ........................... 11  Reading the Memory Map Register Table ............................... 31  Typical Performance Characteristics ........................................... 13  Open Locations .......................................................................... 31  AD9269-80 .................................................................................. 13  Default Values ............................................................................. 31  AD9269-65 .................................................................................. 15  Memory Map Register Table ..................................................... 32  AD9269-40 .................................................................................. 16  Memory Map Register Descriptions ........................................ 34  AD9269-20 .................................................................................. 17  Applications Information .............................................................. 36  Equivalent Circuits ......................................................................... 18  Design Guidelines ...................................................................... 36  Theory of Operation ...................................................................... 19  Outline Dimensions ....................................................................... 37  ADC Architecture ...................................................................... 19  Ordering Guide .......................................................................... 37  Analog Input Considerations .................................................... 19  Voltage Reference ....................................................................... 21  REVISION HISTORY 1/10—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD9269 GENERAL DESCRIPTION generation. The available digital test patterns include built-in The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, deterministic and pseudorandom patterns, along with custom 20/40/65/80 MSPS analog-to-digital converter (ADC). It features user-defined test patterns entered via the serial port interface (SPI). a high performance sample-and-hold circuit and on-chip voltage reference. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide The product uses multistage differential pipeline architecture with variations in the clock duty cycle while maintaining excellent output error correction logic to provide 16-bit accuracy at 80 MSPS overall ADC performance. data rates and to guarantee no missing codes over the full operating temperature range. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro- The AD9269 incorporates an optional integrated dc correction and vided for each ADC channel to ensure proper latch timing with quadrature error correction block (QEC) that corrects for dc receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, offset, gain, and phase mismatch between the two channels. and output data can be multiplexed onto a single output bus. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers. The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to The ADC also contains several features designed to maximize +85°C). flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern Rev. 0 | Page 3 of 40 AD9269 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. AD9269-20/AD9269-40 AD9269-65 AD9269-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.40 ±0.05 ±0.50 ±0.05 ±0.50 % FSR 1 Gain Error Full −2.0 −2.0 −2.0 % FSR Differential Full −0.9/+1.2 −0.9/+1.4 −0.9/+1.65 LSB Nonlinearity 2 (DNL) 25°C −0.5/+0.6 −0.5/+1.1 −0.5/+1.1 LSB Integral Nonlinearity Full ±5.50 ±6.50 ±6.50 LSB 2 (INL) 25°C ±2.0 ±2.2 ±3.3 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.50 ±0.0 ±0.55 ±0.0 ±0.65 % FSR 1 Gain Error 25°C ±0.2 ±0.2 ±0.2 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V (1 V Mode) Load Regulation Full 2 2 2 mV Error at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.8 2.8 2.8 LSB rms ANALOG INPUT Input Span, Full 2 2 2 V p-p VREF = 1.0 V 3 Input Capacitance Full 6.5 6.5 6.5 pF Input Common- Full 0.9 0.9 0.9 V Mode Voltage Input Common- Full 0.5 1.3 0.5 1.3 0.5 1.3 V Mode Range REFERENCE INPUT Full 7.5 7.5 7.5 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 Full 50.0/69.3 52.5/72.6 96.6 101.2 113 119 mA IAVDD 2 Full 3.9/6.4 9.6 11.8 mA IDRVDD (1.8 V) 2 IDRVDD (3.3 V) Full 7.4/12.4 18.7 23 mA Rev. 0 | Page 4 of 40 AD9269 AD9269-20/AD9269-40 AD9269-65 AD9269-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit POWER CONSUMPTION DC Input Full 87.7/121.7 170.7 200 mW 2 Sine Wave Input Full 96.9/136.3 102.0/142.3 191.2 199.8 224.6 240 mW (DRVDD = 1.8 V) 2 Sine Wave Input Full 114.4/165.7 235.6 279 mW (DRVDD = 3.3 V) 4 Standby Power Full 37/37 37 37 mW Power-Down Power Full 1.0 1.0 1.0 mW 1 Measured with a 1.0 V external reference. 2 Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK+, CLK− active. Rev. 0 | Page 5 of 40 AD9269 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. AD9269-20/AD9269-40 AD9269-65 AD9269-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 78.0 77.5 77.6 dBFS IN f = 30.5 MHz 25°C 77.5 77.5 77.2 dBFS IN Full 76.5 76.5 dBFS fIN = 70 MHz 25°C 76.5 76.5 76.3 dBFS Full 75.5 dBFS fIN = 200 MHz 25°C 71.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 77.9 77.4 77.4 dBFS fIN = 30.5 MHz 25°C 77.2 77.2 76.9 dBFS Full 76.0 76.0 dBFS f = 70 MHz 25°C 76.4 76.4 76.1 dBFS IN Full 75.0 dBFS fIN = 200 MHz 25°C 69.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.6 12.6 12.6 Bits fIN = 30.5 MHz 25°C 12.5 12.5 12.5 Bits fIN = 70 MHz 25°C 12.4 12.4 12.3 Bits f = 200 MHz 25°C 11.2 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −97 −93 dBc f = 30.5 MHz 25°C −90 −93 −92 dBc IN Full −80 −80 dBc fIN = 70 MHz 25°C −89 −97 −90 dBc Full −80 dBc fIN = 200 MHz 25°C −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 90 91 92 dBc Full 80 80 dBc f = 70 MHz 25°C 89 95 90 dBc IN Full 80 dBc fIN = 200 MHz 25°C 80 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −99 −89 −99 dBc IN fIN = 30.5 MHz 25°C −100 −100 −99 dBc Full −90 −91 dBc f = 70 MHz 25°C −99 −100 −97 dBc IN Full −89 dBc f = 200 MHz 25°C −86 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc IN 2 CROSSTALK Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 6 of 40 AD9269 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. AD9269-20/AD9269-40/AD9269-65/AD9269-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (SDIO/DCS) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 μA Full 3.29 V OH High Level Output Voltage, I = 0.5 mA Full 3.25 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, I = 50 μA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. 0 | Page 7 of 40 AD9269 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. AD9269-20/AD9269-40 AD9269-65 AD9269-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 480 480 480 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (t) Full 3 3 3 ns DCO DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 9 9 9 Cycles With QEC Active Full 11 11 11 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 9 N – 8 N – 7 N – 6 N – 5 t PD Figure 2. CMOS Output Data Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 t PD Figure 3. CMOS Interleaved Output Timing Rev. 0 | Page 8 of 40 08538-003 08538-002 AD9269 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge CLK+ t t SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev. 0 | Page 9 of 40 08538-004 AD9269 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s PCB. Soldering the exposed paddle to the user’s board VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V also increases the reliability of the solder joints and maximizes CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V the thermal capability of the package. SYNC to AGND −0.3 V to DRVDD + 0.3 V Table 7. Thermal Resistance VREF to AGND −0.3 V to AVDD + 0.2 V Airflow SENSE to AGND −0.3 V to AVDD + 0.2 V Velocity VCM to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 Package Type (m/sec) θ θ θ Unit JA JC JB RBIAS to AGND −0.3 V to AVDD + 0.2 V 64-Lead LFCSP 0 23 2.0 °C/W CSB to AGND −0.3 V to DRVDD + 0.3 V 9 mm × 9 mm 1.0 20 12 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V (CP-64-4) 2.5 18 °C/W SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V 1 OEB to AGND −0.3 V to DRVDD + 0.3 V Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). PDWN to AGND −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. D0x through D15x to AGND −0.3 V to DRVDD + 0.3 V 4 Per JEDEC JESD51-8 (still air). DCOx to AGND −0.3 V to DRVDD + 0.3 V Typical θJA is specified for a 4-layer PCB with a solid ground Operating Temperature Range (Ambient) −40°C to +85°C plane. As shown in Table 7, airflow improves heat dissipation, Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C which reduces θ . In addition, metal in direct contact with the JA package leads from metal traces, through holes, ground, and power planes, reduces the θ . JA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any ESD CAUTION other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 10 of 40 AD9269 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 CLK+ 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB D0B (LSB) 4 45 SCLK/DFS D1B 5 44 SDIO/DCS D2B 6 43 ORA D3B 7 42 D15A (MSB) AD9269 D4B 8 41 D14A TOP VIEW D5B 9 40 D13A (Not to Scale) DRVDD 10 39 D12A D6B 11 38 D11A D7B 12 37 DRVDD D8B 13 36 D10A D9B 35 D9A 14 34 D8A D10B 15 D11B 16 33 D7A NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0, EP AGND The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. Channel B Digital Outputs. D0B is the LSB; D15B is the MSB. 4 to 9, 11 to D0B (LSB) to 18, 20, 21 D15B (MSB) 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. Channel A Digital Outputs. D0A is the LSB; D15A is the MSB. 25 to 27, 29 to D0A (LSB) to 36, 38 to 42 D15A (MSB) 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high: twos complement output. DFS low: offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. 30 kΩ internal pull-down. Low: enable Channel A and Channel B digital outputs. High: three-state outputs. 48 PDWN Digital Input. 30 kΩ internal pull-down. High: power down device. Low: run device, normal operation. Rev. 0 | Page 11 of 40 D12B 17 64 AVDD D13B 18 63 AVDD DRVDD 19 62 VIN+B D14B 20 61 VIN–B D15B (MSB) 21 60 AVDD ORB 22 59 AVDD DCOB 23 58 RBIAS DCOA 24 57 VCM D0A (LSB) 25 56 SENSE VREF D1A 26 55 D2A 27 54 AVDD DRVDD 28 53 AVDD D3A 29 52 VIN–A D4A 30 51 VIN+A D5A 31 50 AVDD D6A 32 49 AVDD 08538-005 AD9269 Pin No. Mnemonic Description 49, 50, 53, 54, AVDD 1.8 V Analog Supply Pins. 59, 60, 63, 64 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs. 58 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs. Rev. 0 | Page 12 of 40 AD9269 TYPICAL PERFORMANCE CHARACTERISTICS AD9269-80 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 9.7MHz @ –1dBFS 30.6MHz @ –1dBFS –20 –20 SNR = 76.8dB (77.8dBFS) SNR = 76.5dB (77.5dBFS) SFDR = 94.3dBc SFDR = 85.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9269-80 Single-Tone FFT with f = 9.7 MHz Figure 9. AD9269-80 Single-Tone FFT with f = 30.6 MHz IN IN 0 0 80MSPS 80MSPS 69MHz @ –1dBFS 210MHz @ –1dBFS –20 –20 SNR = 75.1dB (76.1dBFS) SNR = 70dB (71dBFS) SFDR = 89.5dBc SFDR = 79.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD9269-80 Single-Tone FFT with fIN = 69 MHz Figure 10. AD9269-80 Single-Tone FFT with fIN = 210 MHz 0 10 80MSPS –15 28.3MHz @ –7dBFS –10 30.6MHz @ –7dBFS SFDR (dBc) –30 SFDR = 89.5dBc (96.5dBFS) –30 –45 IMD3 (dBc) –50 –60 –75 –70 2F1 + F2 –90 2F2 + F1 SFDR (dBFS) F1 + F2 –90 2F1 – F2 F2–F1 2F2 – F1 –105 –110 –120 IMD3 (dBFS) –135 –130 4 8 12 16 20 24 28 32 36 –95 –85 –75 –65 –55 –45 –35 –25 –15 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 8. AD9269-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Rev. 0 | Page 13 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08538-053 08538-035 08538-033 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/IMD3 (dBc/dBFS) 08538-054 08538-036 08538-034 AD9269 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 120 SFDRFS SFDR (dBc) 90 100 80 70 SNR (dBFS) 80 SNRFS 60 SFDR 50 60 40 SNR 40 30 20 20 10 0 0 –65 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 12. AD9269-80 SNR/SFDR vs. Input Frequency (AIN) Figure 15. AD9269-80 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN with 2 V p-p Full Scale 100 4.0M 90 2.8 LSB RMS SFDR (dBc) 3.5M 80 3.0M 70 SNR (dBFS) 2.5M 60 50 2.0M 40 1.5M 30 1.0M 20 500k 10 0 0 10 20 30 40 50 60 70 80 SAMPLE RATE (MSPS) OUTPUT CODE Figure 13. AD9269-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 16. Grounded Input Histogram 1.5 6 4 1.0 2 0.5 0 0 –2 –0.5 –1.0 –4 –1.5 –6 0 16,384 32,768 49,152 65,536 0 16,384 32,768 49,152 65,536 OUTPUT CODE OUTPUT CODE Figure 14. DNL Error with f = 9.7 MHz Figure 17. INL with f = 9.7 MHz IN IN Rev. 0 | Page 14 of 40 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08538-055 08538-057 08538-038 INL ERROR (LSB) NUMBER OF HITS SNR/SFDR (dBc/dBFS) N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 08538-061 08538-048 08538-037 AD9269 AD9269-65 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 0 65MSPS SFDRFS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.9dBc –40 80 SNRFS –60 SFDR 60 –80 SNR 40 –100 20 –120 –140 0 03 5 10 15 20 250 –65 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 21. AD9269-65 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz Figure 18. AD9269-65 Single-Tone FFT with fIN = 9.7 MHz IN 0 100 65MSPS SFDR (dBc) 69MHz @ –1dBFS 90 –20 SNR = 75.5dB (76.5dBFS) SFDR = 87.4dBc 80 –40 70 SNR (dBFS) 60 –60 50 –80 40 –100 30 20 –120 10 –140 0 03 5 10 15 20 250 0 50 100 150 200 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 19. AD9269-65 Single-Tone FFT with fIN = 69 MHz Figure 22. AD9269-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 0 65MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 89.9dBc –40 –60 –80 –100 –120 –140 03 5 10 15 20 250 FREQUENCY (MHz) Figure 20. AD9269-65 Single-Tone FFT with f = 30.6 MHz IN Rev. 0 | Page 15 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08538-031 08538-032 08538-030 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBc/dBFS) 08538-060 08539-056 AD9269 AD9269-40 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 0 40MSPS SFDRFS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.1dBc –40 80 SNRFS –60 SFDR 60 –80 SNR 40 –100 20 –120 –140 0 0 2 4 6 8 10 12 14 16 18 20 –65 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 25. AD9269-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 23. AD9269-40 Single-Tone FFT with fIN = 9.7 MHz 0 40MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 88.8dBc –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Figure 24. AD9269-40 Single-Tone FFT with fIN = 30.6 MHz Rev. 0 | Page 16 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08538-029 08538-028 SNR/SFDR (dBFS/dBFS) 08538-059 AD9269 AD9269-20 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 20MSPS SFDRFS 9.7MHz @ –1dBFS –20 100 SNR = 76.9dB (77.9dBFS) SFDR = 95.6dBc –40 SNRFS 80 –60 60 SFDR (dBc) –80 40 –100 SNR (dBc) 20 –120 –140 0 012 3 4 567 8 9 10 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 28. AD9269-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 26. AD9269-20 Single-Tone FFT with fIN = 9.7 MHz 0 20MSPS 30.6MHz @ –1dBFS –20 SNR = 76.7dB (77.7dBFS) SFDR = 90.7dBc –40 –60 –80 –100 –120 –140 012 3 4 567 8 9 10 FREQUENCY (MHz) Figure 27. AD9269-20 Single-Tone FFT with f = 30.6 MHz IN Rev. 0 | Page 17 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08538-026 08538-024 SNR/SFDR (dBc/dBFS) 08538-058 AD9269 EQUIVALENT CIRCUITS DRVDD AVDD VIN±x Figure 29. Equivalent Analog Input Circuit Figure 34. Equivalent Digital Output Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS 375Ω RBIAS 30kΩ AND VCM Figure 35. Equivalent RBIAS, VCM Circuit Figure 30. Equivalent SDIO/DCS Input Circuit DRVDD DRVDD AVDD 30kΩ 350Ω 350Ω SCLK/DFS, SYNC, CSB OEB, AND PDWN 30kΩ Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 36. Equivalent CSB Input Circuit AVDD AVDD 375Ω SENSE 375Ω VREF 7.5kΩ Figure 32. Equivalent VREF Circuit Figure 37. Equivalent SENSE Circuit AVDD 5Ω CLK+ 15kΩ 0.9V AVDD 15kΩ 5Ω CLK– Figure 33. Equivalent Clock Input Circuit Rev. 0 | Page 18 of 40 08538-039 08538-047 08538-040 08538-041 08538-043 08538-042 08538-046 08538-045 08538-044 AD9269 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9269 dual-channel ADC design can be used for diversity reception of signals, where the ADCs are operating identically on The analog input to the AD9269 is a differential switched- the same carrier but from two separate antennae. The ADCs can capacitor circuit designed for processing differential input signals. also be operated with independent analog inputs. The user can This circuit can support a wide common-mode range while main- sample any f /2 frequency segment from dc to 200 MHz, using S taining excellent performance. By using an input common-mode appropriate low-pass or band-pass filtering at the ADC inputs voltage of midsupply, users can minimize signal-dependent errors with little loss in ADC performance. Operation to 300 MHz and achieve optimum performance. analog input is permitted, but it occurs at the expense of The clock signal alternately switches the input circuit between increased ADC noise and distortion. sample mode and hold mode (see Figure 38). When the input In nondiversity applications, the AD9269 can be used as a base- circuit is switched to sample mode, the signal source must be band or direct downconversion receiver, in which one ADC is capable of charging the sample capacitors and settling within used for I input data and the other is used for Q input data. one-half of a clock cycle. The AD9269 incorporates an optional, integrated dc correction A small resistor in series with each input can help reduce the and quadrature error correction block (QEC) that can correct peak transient current injected from the output stage of the for dc offset, gain, and phase mismatch between the two channels. driving source. In addition, low Q inductors or ferrite beads can This functional block can be very beneficial to complex signal be placed on each leg of the input to reduce high differential processing applications such as direct conversion receivers. capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors Synchronization capability is provided to allow synchronized or ferrite beads is required when driving the converter front end timing between multiple channels or multiple devices. at high IF frequencies. Either a shunt capacitor or two single-ended Programming and control of the AD9269 are accomplished capacitors can be placed on the inputs to provide a matching using a 3-wire SPI-compatible serial interface. passive network. This ultimately creates a low-pass filter at the ADC ARCHITECTURE input to limit unwanted broadband noise. Refer to the AN-742 Application Note, Frequency Domain Response of Switched- The AD9269 architecture consists of a multistage, pipelined ADC. Capacitor ADCs; the AN-827 Application Note, A Resonant Each stage provides sufficient overlap to correct for flash errors in Approach to Interfacing Amplifiers to Switched-Capacitor the preceding stage. The quantized outputs from each stage are ADCs (see www.analog.com); and the Analog Dialogue article, combined into a final 16-bit result in the digital correction logic. “Transformer-Coupled Front-End for Wideband A/D Converters” The pipelined architecture permits the first stage to operate with a (Volume 39, April 2005) for more information. In general, the new input sample while the remaining stages operate with pre- precise values depend on the application. ceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC H and an interstage residue amplifier (for example, a multiplying C PAR digital-to-analog converter (MDAC)). The residue amplifier H VIN+x magnifies the difference between the reconstructed DAC output C SAMPLE SS and the flash input for the next stage in the pipeline. One bit of SS redundancy is used in each stage to facilitate digital correction C SAMPLE of flash errors. The last stage consists of a flash ADC. VIN–x H C PAR The output staging block aligns the data, corrects errors, and H passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjust- Figure 38. Switched-Capacitor Input Circuit ment of the output voltage swing. During power-down, the output buffers go into a high impedance state. Rev. 0 | Page 19 of 40 08538-006 AD9269 Input Common Mode driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. The analog inputs of the AD9269 are not internally dc-biased. 200Ω Therefore, in ac-coupled applications, the user must provide a dc 33Ω VIN–x VIN 76.8Ω AVDD bias externally. Setting the device so that VCM = AVDD/2 is 90Ω recommended for optimum performance, but the device can 10pF ADC ADA4938-2 function over a wider range with reasonable performance, as 0.1µF 120Ω 33Ω VCM shown in Figure 39. VIN+x 100 200Ω Figure 40. Differential Input Configuration Using the ADA4938-2 95 SFDR (dBc) For baseband applications below ~10 MHz where SNR is a key 90 parameter, differential transformer-coupling is the recommended 85 input configuration (see Figure 41). To bias the analog input, the VCM voltage can be connected to the center tap of the secondary 80 SNR (dBFS) winding of the transformer. 75 VIN+x R 70 2V p-p 49.9Ω C ADC 65 R VCM VIN–x 60 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.1µF INPUT COMMON-MODE VOLTAGE (V) Figure 41. Differential Transformer-Coupled Configuration Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 32.5 MHz, fS = 80 MSPS The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below An on-board, common-mode voltage reference is included in the a few megahertz (MHz). Excessive signal power can also cause design and is available from the VCM pin. The VCM pin must core saturation, which leads to distortion. be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve Differential Input Configurations the true SNR performance of the AD9269. For applications above Optimum performance is achieved while driving the AD9269 in a ~10 MHz where SNR is a key parameter, differential double balun differential input configuration. For baseband applications, the coupling is the recommended input configuration (see Figure 42). AD8138, ADA4937-2, and ADA4938-2 differential drivers provide An alternative to using a transformer-coupled input at frequencies excellent performance and a flexible interface to the ADC. in the second Nyquist zone is to use the AD8352 differential driver The output common-mode voltage of the ADA4938-2 is easily (see Figure 43). Refer to the AD8352 data sheet for more set with the VCM pin of the AD9269 (see Figure 40), and the information. 0.1µF 0.1µF R VIN+x 2V p-p 25Ω P S S P C A ADC 0.1µF 25Ω 0.1µF R VCM VIN–x Figure 42. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+x 2 200Ω C ADC R R AD8352 C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN–x 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 43. Differential Input Configuration Using the AD8352 Rev. 0 | Page 20 of 40 SNR/SFDR (dBFS/dBc) 08538-049 08538-010 08538-011 08538-008 08538-007 AD9269 In any configuration, the value of Shunt Capacitor C is dependent Internal Reference Connection on the input frequency and source impedance and may need to A comparator within the AD9269 detects the potential at the be reduced or removed. Table 9 displays the suggested values to set SENSE pin and configures the reference into two possible modes, the RC network. However, these values are dependent on the which are summarized in Table 10. If SENSE is grounded, the input signal and should be used only as a starting guide. reference amplifier switch is connected to the internal resistor divider (see Figure 45), setting VREF to 1.0 V. Table 9. Example RC Network VIN+A/VIN+B R Series Frequency Range (MHz) (Ω Each) C Differential (pF) VIN–A/VIN–B 0 to 70 33 22 70 to 200 125 Open ADC CORE Single-Ended Input Configuration VREF A single-ended input can provide adequate performance in 1.0µF 0.1µF cost-sensitive applications. In this configuration, SFDR and SELECT LOGIC distortion performance degrade due to the large input common- SENSE mode swing. If the source impedances on each input are matched, 0.5V there should be little effect on SNR performance. Figure 44 shows a typical single-ended input configuration. ADC 10µF AVDD 1kΩ R Figure 45. Internal Reference Configuration VIN+x 1V p-p 0.1µF 49.9Ω 1kΩ If the internal reference of the AD9269 is used to drive multiple AVDD C ADC converters to improve gain matching, the loading of the reference 1kΩ R by the other converters must be considered. Figure 46 shows VIN–x 10µF 0.1µF 1kΩ how the internal reference voltage is affected by loading. 0 Figure 44. Single-Ended Input Configuration VOLTAGE REFERENCE –0.5 A stable and accurate 1.0 V voltage reference is built into the AD9269. V can be configured using either the internal 1.0 V REF –1.0 reference or an externally applied 1.0 V reference voltage. The INTERNAL V = 0.993V REF various reference modes are summarized in the sections that –1.5 follow. The Reference Decoupling section describes the best- practices PCB layout of the reference. –2.0 –2.5 –3.0 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 LOAD CURRENT (mA) Figure 46. VREF Accuracy vs. Load Current Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. 0 | Page 21 of 40 08538-009 REFERENCE VOLTAGE ERROR (%) 08538-012 08538-014 AD9269 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance The AD9269 has a very flexible clock input structure. The clock the gain accuracy of the ADC or to improve thermal drift input can be a CMOS, LVDS, LVPECL, or sine wave signal. characteristics. Figure 47 shows the typical drift characteristics Regardless of the type of signal being used, clock source jitter of the internal reference in 1.0 V mode. is of the most concern, as described in the Jitter Considerations section. 4 3 Figure 49 and Figure 50 show two preferred methods for clock- ing the AD9269 (at rates up to 6× the specified sample rate when 2 V ERROR (mV) REF using the internal clock divider function). A low jitter clock source 1 is converted from a single-ended signal to a differential signal 0 using either an RF balun or an RF transformer. –1 The RF balun configuration is recommended for clock frequencies –2 between 125 MHz and 480 MHz, and the RF transformer is recom- –3 mended for clock frequencies from 10 MHz to 200 MHz. The –4 back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9269 to approxi- –5 mately 0.8 V p-p differential. –6 –40 –20 0 20 40 60 80 This limit helps prevent the large voltage swings of the clock TEMPERATURE (°C) from feeding through to other portions of the AD9269 while pre- Figure 47. Typical V Drift REF serving the fast rise and fall times of the signal that are critical to When the SENSE pin is tied to AVDD, the internal reference is a low jitter performance. disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 32). The internal buffer generates the 1nF 0.1µF positive and negative full-scale references for the ADC core. CLOCK CLK+ INPUT Therefore, the external reference must be limited to a maximum 50Ω ADC 0.1µF of 1.0 V. 1nF CLK– SCHOTTKY CLOCK INPUT CONSIDERATIONS DIODES: HSMS2822 For optimum performance, clock the AD9269 sample clock Figure 49. Balun-Coupled Differential Clock (Up to 480 MHz) inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally ® Mini-Circuits (see Figure 48) and require no external bias. ADT1-1WT, 1:1 Z 0.1µF 0.1µF AVDD XFMR CLOCK CLK+ INPUT 100Ω 50Ω ADC 0.1µF 0.9V CLK– SCHOTTKY CLK+ CLK– 0.1µF DIODES: HSMS2822 2pF 2pF Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) Figure 48. Equivalent Clock Input Circuit Rev. 0 | Page 22 of 40 V ERROR (mV) REF 08538-016 08538-052 08538-018 08538-017 AD9269 If a low jitter clock source is not available, another option is to The AD9269 clock divider can be synchronized using the external ac couple a differential PECL signal to the sample clock input SYNC input. Bits[2:1] in Register 0x100 allow the clock divider pins, as shown in Figure 51. The AD9510/AD9511/AD9512/ to be resynchronized on every SYNC signal or only on the first AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer SYNC signal after the register is written. A valid SYNC causes excellent jitter performance. the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. 0.1µF 0.1µF CLOCK CLK+ Clock Duty Cycle INPUT AD951x 100Ω ADC Typical high speed ADCs use both clock edges to generate PECL DRIVER 0.1µF 0.1µF CLOCK a variety of internal timing signals and, as a result, may be CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic Figure 51. Differential PECL Sample Clock (Up to 480 MHz) performance characteristics. A third option is to ac couple a differential LVDS signal to the The AD9269 contains a duty cycle stabilizer (DCS) that retimes sample clock input pins, as shown in Figure 52. The AD9510/ the nonsampling (falling) edge, providing an internal clock AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 signal with a nominal 50% duty cycle. This allows the user to clock drivers offer excellent jitter performance. provide a wide range of clock input duty cycles without affecting the performance of the AD9269. Noise and distortion perform- ance are nearly flat for a wide range of duty cycles with the DCS 0.1µF 0.1µF CLOCK on, as shown in Figure 54. CLK+ INPUT 80 AD951x 100Ω ADC LVDS DRIVER DCS OFF 0.1µF 0.1µF 79 DCS ON CLOCK CLK– INPUT 78 50kΩ 50kΩ 77 Figure 52. Differential LVDS Sample Clock (Up to 480 MHz) 76 In some applications, it may be acceptable to drive the sample 75 clock inputs with a single-ended 1.8 V CMOS signal. In such 74 applications, drive the CLK+ pin directly from a CMOS gate, and 73 bypass the CLK− pin to ground with a 0.1 μF capacitor (see 72 Figure 53). 71 V CC 70 OPTIONAL 0.1µF 0.1µF 30 35 40 45 50 55 60 65 70 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER POSITIVE DUTY CYCLE (%) INPUT 1 1kΩ 50Ω Figure 54. SNR vs. Duty Cycle Stabilizer On/Off ADC Jitter in the rising edge of the input is still of concern and is not CLK– 0.1µF easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 1 50Ω RESISTOR IS OPTIONAL. 20 MHz nominally. The loop has a time constant associated Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) with it that must be considered in applications in which the Input Clock Divider clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after the dynamic clock frequency increases or decreases The AD9269 contains an input clock divider with the ability before the DCS loop is relocked to the input signal. to divide the input clock by integer values between 1 and 6. Optimum performance is obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. Rev. 0 | Page 23 of 40 08538-021 08538-020 08538-019 SNR (dBFS) 08538-064 AD9269 Jitter Considerations POWER DISSIPATION AND STANDBY MODE High speed, high resolution ADCs are sensitive to the quality As shown in Figure 56, the analog core power dissipated by the of the clock input. The degradation in SNR from the low fre- AD9269 is proportional to its sample rate. The digital power dis- quency SNR (SNRLF) at a given input frequency (fINPUT) due to sipation of the CMOS outputs is determined primarily by the jitter (tJRMS) can be calculated by strength of the digital drivers and the load on each output bit. (−SNR /10) 2 LF The maximum DRVDD current (IDRVDD) can be calculated as SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS IDRVDD = V × C × f × N DRVDD LOAD CLK In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications where N is the number of output bits (34, in the case of the are particularly sensitive to jitter, as illustrated in Figure 55. AD9269). 80 210 75 0.05ps 190 AD9269-80 70 170 0.2ps 65 150 AD9269-65 60 0.5ps 130 55 110 AD9269-40 1.0ps 1.5ps 50 90 2.0ps AD9269-20 3.0ps 2.5ps 45 70 1 10 100 1k 10 20 30 40 50 60 70 80 FREQUENCY (MHz) CLOCK RATE (MSPS) Figure 55. SNR vs. Input Frequency and Jitter Figure 56. Analog Core Power vs. Clock Rate The clock input should be treated as an analog signal in cases in This maximum current occurs when every output bit switches which aperture jitter may affect the dynamic range of the AD9269. on every clock cycle, that is, a full-scale square wave at the Nyquist To avoid modulating the clock signal with digital noise, keep power frequency of f /2. In practice, the DRVDD current is estab- CLK supplies for clock drivers separate from the ADC output driver lished by the average number of output bits switching, which supplies. Low jitter, crystal-controlled oscillators make the best is determined by the sample rate and the characteristics of the clock sources. If the clock is generated from another type of source analog input signal. (by gating, dividing, or another method), it should be retimed by Reducing the capacitive load presented to the output drivers can the original clock at the last step. minimize digital power consumption. The data in Figure 56 was For more information, see the AN-501 Application Note and the taken using the same operating conditions as those used for the AN-756 Application Note, available on www.analog.com. Typical Performance Characteristics, with a 5 pF load on each output driver. Rev. 0 | Page 24 of 40 SNR (dBFS) 07938-022 ANALOG CORE POWER (mW) 08538-051 AD9269 The AD9269 is placed in power-down mode either by the SPI Table 11. SCLK/DFS Mode Selection (External Pin Mode) port or by asserting the PDWN pin high. In this state, the ADC Voltage at Pin SCLK/DFS SDIO/DCS typically dissipates 1 mW. During power-down, the output AGND Offset binary (default) DCS disabled drivers are placed in a high impedance state. Asserting the PDWN DRVDD Twos complement DCS enabled (default) pin low returns the AD9269 to its normal operating mode. Note As detailed in the AN-877 Application Note, Interfacing to High that PDWN is referenced to the digital output driver supply Speed ADCs via SPI, the data format can be selected for offset (DRVDD) and should not exceed that supply voltage. binary, twos complement, or gray code when using the SPI control. Low power dissipation in power-down mode is achieved by Digital Output Enable Function (OEB) shutting down the reference, reference buffer, biasing networks, The AD9269 provides a flexible three-state ability for the digital and clock. Internal capacitors are discharged when entering power- output pins. The three-state mode is enabled by the OEB pin or down mode and then must be recharged when returning to normal through the SPI interface. If the OEB pin is low, the output data operation. As a result, wake-up time is related to the time spent drivers and DCOs are enabled. If the OEB pin is high, the output in power-down mode, and shorter power-down cycles result in data drivers and DCOs are placed in a high impedance state. proportionally shorter wake-up times. This OEB function is not intended for rapid access to the data When using the SPI port interface, the user can place the ADC bus. Note that OEB is referenced to the digital output driver in power-down mode or standby mode. Standby mode allows supply (DRVDD) and should not exceed that supply voltage. the user to keep the internal reference circuitry powered when When using the SPI interface, the data outputs and DCO of faster wake-up times are required. See the Memory Map section each channel can be independently three-stated by using the for more details. output disable (OEB) bit, Bit 4 in Register 0x14. DIGITAL OUTPUTS TIMING The AD9269 output drivers can be configured to interface with The AD9269 provides latched data with a pipeline delay of nine 1.8 V to 3.3 V CMOS logic families. Output data can also be multi- clock cycles. Data outputs are available one propagation delay (t ) PD plexed onto a single output bus to reduce the total number of after the rising edge of the clock signal. traces required. Minimize the length of the output data lines and loads placed The CMOS output drivers are sized to provide sufficient output on them to reduce transients within the AD9269. These transients current to drive a wide variety of logic families. However, large may degrade converter dynamic performance. drive currents tend to cause current glitches on the supplies and may affect converter performance. The lowest typical conversion rate of the AD9269 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. Data Clock Output (DCO) The output data format can be selected to be either offset binary The AD9269 provides two data clock output (DCO) signals that or twos complement by setting the SCLK/DFS pin when operating are designed to capture the data in an external register. The CMOS in the external pin mode (see Table 11). data outputs are valid on the rising edge of DCO unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 0000 1000 0000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111 1 Rev. 0 | Page 25 of 40 AD9269 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9269 includes a built-in test feature that is designed to This enables Bit 0 (BIST enable) in Register 0x0E and resets the PN enable verification of the integrity of each channel as well as to sequence generator, Bit 2 (BIST init) in Register 0x0E. At the facilitate board-level debugging. A built-in self-test (BIST) feature completion of the BIST, Bit 0 in Register 0x24 is automatically that verifies the integrity of the digital datapath of the AD9269 cleared. The PN sequence can be continued from its last value is included. Various output test options are also provided to place by writing a 0 in Bit 2 in Register 0x0E. However, if the PN predictable values on the outputs of the AD9269. sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user BUILT-IN SELF-TEST (BIST) must rely on verifying the output data. The BIST is a thorough test of the digital portion of the selected OUTPUT TEST MODES AD9269 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During BIST, data from an internal The output test options are described in Table 17 at Address 0x0D. pseudorandom noise (PN) source is driven through the digital When an output test mode is enabled, the analog section of the datapath of both channels, starting at the ADC block output. ADC is disconnected from the digital back end blocks, and the At the datapath output, CRC logic calculates a signature from test pattern is run through the output formatting block. Some of the data. The BIST sequence runs for 512 cycles and then stops. the test patterns are subject to output formatting, and some are When the sequence is complete, the BIST compares the signature not. The PN generators from the PN sequence tests can be reset results with a predetermined value. If the signatures match, the by setting Bit 4 or Bit 5 in Register 0x0D. These tests can be per- BIST sets Bit 0 in Register 0x24, signifying that the test passed. formed with or without an analog signal (if present, the analog If the BIST test failed, Bit 0 in Register 0x24 is cleared. The outputs signal is ignored), but they do require an encode clock. For more are connected during this test, so the PN sequence can be observed information, see the AN-877 Application Note, Interfacing to High as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. Speed ADCs via SPI. Rev. 0 | Page 26 of 40 AD9269 CHANNEL/CHIP SYNCHRONIZATION The AD9269 has a SYNC input that offers the user flexible the sample clock; however, to ensure that there is no timing synchronization options for synchronizing sample clocks uncertainty between multiple parts, the SYNC input signal should across multiple ADCs. The input clock divider can be enabled be externally synchronized to the input clock signal, meeting the to synchronize on a single occurrence of the SYNC signal or on setup and hold times that are shown in Table 5. Drive the SYNC every occurrence. The SYNC input is internally synchronized to input using a single-ended CMOS-type signal. Rev. 0 | Page 27 of 40 AD9269 DC AND QUADRATURE ERROR CORRECTION (QEC) In direct conversion or other quadrature systems, mismatches The default configuration on the AD9269 has the QEC and dc between the real (I) and imaginary (Q) signal paths cause fre- correction blocks disabled, and Bits[2:0] in Register 0x110 must quencies in the positive spectrum to image into the negative be pulled high to enable the correction blocks. The quadrature spectrum, and vice versa. From an RF point of view, this is gain, quadrature phase, and dc correction algorithms can also equivalent to information above the local oscillator (LO) be disabled independently for system debugging or to save frequency interfering with information below the LO frequency, power by pulling Bits[2:0] low in Register 0x110. and vice versa. These mismatches may occur from gain and/or When the QEC is enabled and a correction value has been phase mismatches in the analog quadrature demodulator or in calculated, the value remains active as long as any of the QEC any other mismatches between the I and Q signal chains. In a functions (DC, gain, or phase correction) are being used. single-carrier zero-IF system where the carrier has been placed symmetrically around dc, this causes self-distortion of the carrier QEC and DC Correction Range as the two sidebands fold onto one another and degrade the Table 13 gives the minimum and maximum correction ranges error vector magnitude (EVM) of the signal. of the algorithms. If the mismatches are greater than these ranges, an imperfect correction results. In a multicarrier communication system, this can be even more problematic because carriers of widely different power levels Table 13. QEC and DC Correction Range can interfere with one another. For example, a large carrier Parameter Minimum Maximum centered at +f1 can have an image appear at −f1 that may be Gain −1.1 dB +1.0 dB much larger than the desired carrier at −f1. Phase −1.79 degrees +1.79 degrees The integrated quadrature error correction (QEC) algorithm of DC −6 % +6% the AD9269 attempts to measure and correct the amplitude and 0 phase imbalances of the I and Q signal paths to achieve higher –15 levels of image suppression than is achievable by analog means alone. These errors can be corrected in an adapted manner, in –30 which the I and Q gain and quadrature phase mismatches are IMAGE DC OFFSET –45 constantly estimated and corrected, allowing for constant –60 tracking of slow changes in mismatches that are due to supply and temperature. –75 2 The quadrature errors are corrected in a frequency independent –90 5 6 manner on the AD9269; therefore, systems with significant –105 4 3 mismatch in the baseband I and Q signal chains may have –120 reduced image suppression. The AD9269 QEC still corrects the systematic imbalances. –135 The convergence time of the QEC algorithm is dependent on the statistics of the input signal. For large signals and large FREQUENCY (MHz) imbalance errors, this convergence time is typically less than Figure 57. QEC Mode Off 2 million samples of the AD9269 data rate. 0 LO Leakage (DC) Correction –15 In a direct conversion receiver subsystem, LO to RF leakage of –30 the quadrature modulator shows up as dc offsets at baseband. These offsets are added to dc offsets in the baseband signal –45 paths, and both contribute to a carrier at dc. In a zero-IF receiver, –60 this dc energy can cause problems because it appears in band of –75 a desired channel. As part of the QEC function, the dc offset is DC OFFSET IMAGE suppressed by applying a low frequency notch filter to form –90 2 5 a null around dc. 6 –105 4 3 In applications where constant tracking of the dc offsets and –120 quadrature errors are not needed, the algorithms can be –135 independently frozen to save power. When frozen, the image and LO leakage (dc) correction are still performed, but changes are no longer tracked. Bits[5:3] in Register 0x110 disable the FREQUENCY (MHz) respective correction when frozen. Figure 58. QEC Mode On Rev. 0 | Page 28 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –37.5M –37.5M –30.0M –30.0M –22.5M –22.5M –15.0M –15.0M –7.5M –7.5M 0M 0M 7.5M 7.5M 15M 15M 22.5M 22.5M 30M 30M 37.5M 37.5M 08538-066 08538-065 AD9269 SERIAL PORT INTERFACE (SPI) SPI functions are placed in high impedance mode. This mode The AD9269 serial port interface (SPI) allows the user to configure turns on any secondary functions of the SPI function pins. the converter for specific functions or operations through a struc- tured register space provided inside the ADC. The SPI provides During an instruction phase, a 16-bit instruction is transmitted. added flexibility and customization, depending on the application. Data follows the instruction phase, and the length of the data Addresses are accessed via the serial port and can be written to stream is determined by the W1 and W0 bits, as shown in or read from via the port. Memory is organized into bytes that Figure 59. can be further divided into fields, which are documented in the All data is composed of 8-bit words. The first bit of the first byte in Memory Map section. For detailed operational information, see a multibyte serial data transfer frame indicates whether a read com- the AN-877 Application Note, Interfacing to High Speed ADCs mand or a write command is issued. This allows the serial data via SPI. input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK, the SDIO, and In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the CSB (see Table 14). The SCLK (a serial clock) is used to syn- the serial port to be used both to program the chip and to read chronize the read and write data presented from and to the ADC. the contents of the on-chip memory. If the instruction is a readback The SDIO (serial data input/output) is a dual-purpose pin that operation, performing a readback causes the serial data input/ allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active- output (SDIO) pin to change direction from an input to an output low control that enables or disables the read and write cycles. at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB Table 14. Serial Port Interface Pins first is the default on power-up and can be changed via the SPI Pin Function port configuration register. For more information about this SCLK Serial clock. A serial shift clock input that is used to and other features, see the AN-877 Application Note, Interfacing synchronize serial interface reads and writes. to High Speed ADCs via SPI. SDIO Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on HARDWARE INTERFACE the instruction being sent and the relative position in the The pins described in Table 14 constitute the physical interface timing frame. between the programming device of the user and the serial port CSB Chip select bar. An active-low control that gates the read and write cycles. of the AD9269. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, The falling edge of the CSB, in conjunction with the rising edge functioning as an input during write phases and as an output of SCLK, determines the start of the framing. An example of the during readback. serial timing and its definitions can be found in Figure 59 and The SPI interface is flexible enough to be controlled by either Table 5. FPGAs or microcontrollers. One method for SPI configuration Other modes involving the CSB are available. The CSB can be is described in detail in the AN-812 Application Note, Micro- held low indefinitely, permanently enabling the device; this is controller-Based Serial Port Interface (SPI) Boot Circuit. called streaming. The CSB can stall high between bytes to allow for additional external timing. When the CSB is tied high, the t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 59. Serial Port Interface Timing Diagram Rev. 0 | Page 29 of 40 08538-023 AD9269 The SPI port should not be active during periods when the full SPI ACCESSIBLE FEATURES dynamic performance of the converter is required. Because the Table 16 provides a brief description of the general features that SCLK signal, the CSB signal, and the SDIO signal are typically are accessible via the SPI. These features are described in detail asynchronous to the ADC clock, noise from these signals can in the AN-877 Application Note, Interfacing to High Speed ADCs degrade converter performance. If the on-board SPI bus is used for via SPI. The AD9269 part-specific features are described in other devices, it may be necessary to provide buffers between this detail in Table 17. bus and the AD9269 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Table 16. Features Accessible Using the SPI Feature Description SDIO/DCS and SCLK/DFS serve a dual function when the Mode Allows the user to set either power-down mode SPI interface is not being used. When the pins are strapped to or standby mode DRVDD or ground during device power-on, they are associated Clock Allows the user to access the DCS via the SPI with a specific function. The Digital Outputs section describes Offset Allows the user to digitally adjust the the strappable functions supported on the AD9269. converter offset CONFIGURATION WITHOUT THE SPI Test I/O Allows the user to set test modes to have known data on output bits In applications that do not interface to the SPI control registers, Output Mode Allows the user to set up outputs the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the Output Phase Allows the user to set the output clock polarity PDWN pin serve as standalone CMOS-compatible control pins. Output Delay Allows the user to vary the DCO delay When the device is powered up, it is assumed that the user intends VREF Allows the user to set the reference voltage to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature con- trol. In this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. Table 15. Mode Selection External Pin Voltage Configuration SDIO/DCS DRVDD (default) Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SCLK/DFS DRVDD Twos complement enabled AGND (default) Offset binary enabled OEB DRVDD Outputs in high impedance AGND (default) Outputs enabled PDWN DRVDD Chip in power-down or standby AGND (default) Normal operation Rev. 0 | Page 30 of 40 AD9269 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 17) contains After the AD9269 is reset, critical registers are loaded with default eight bit locations. The memory map is divided into four sections: values. The default values for the registers are given in the memory the chip configuration registers (Address 0x00 to Address 0x02); map register table (see Table 17). the device index and transfer registers (Address 0x05 and Logic Levels Address 0xFF); the program registers, including setup, control, An explanation of logic level terminology follows: and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 to Address 0x11D). • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 17 documents the default hexadecimal value for each • “Clear a bit” is synonymous with “bit is set to Logic 0” or hexadecimal address shown. The column with the heading Bit 7 “writing Logic 0 for the bit.” (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the channel index register, has a hexa- Transfer Register Map decimal default value of 0x03. This means that in Address 0x05, Address 0x08 to Address 0x18 are shadowed. Writes to these Bits[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is addresses do not affect part operation until a transfer command the default channel index setting. The default value results in is issued by writing 0x01 to Address 0xFF, setting the transfer bit. both ADC channels receiving the next write command. For This allows these registers to be updated internally and simulta- more information on this function and others, see the AN-877 neously when the transfer bit is set. The internal update takes Application Note, Interfacing to High Speed ADCs via SPI. This place when the transfer bit is set, and then the bit autoclears. document details the functions controlled by Register 0x00 to Channel-Specific Registers Register 0xFF. The remaining registers, Register 0x100 to Register 0x11D, are documented in the Memory Map Register Some channel setup functions can be programmed differently Descriptions section following Table 17. for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits OPEN LOCATIONS are designated in the memory map register table as local. These All address and bit locations that are not included in the SPI local registers and bits can be accessed by setting the appropriate map are not currently supported for this device. Unused bits of Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. a valid address location should be written with 0s. Writing to these If both bits are set, the subsequent write affects the registers of locations is required only when part of an address location is both channels. In a read cycle, set only Channel A or Channel B open (for example, Address 0x05). If the entire address location to read one of the two registers. If both bits are set during an is open, it is omitted from the SPI map (for example, Address 0x13) SPI read cycle, the part returns the value for Channel A. and should not be written. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 31 of 40 AD9269 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip configuration registers 0x00 SPI port 0 LSB Soft reset 1 1 Soft LSB first 0 0x18 The nibbles are configuration first reset mirrored so that (global) LSB- or MSB-first mode registers correctly, regard- less of shift mode 0x01 Chip ID (global) 8-bit chip ID, Bits[7:0] 0x75 Unique chip ID AD9269 = 0x75 used to differ- entiate devices; read only 0x02 Chip grade (global) Open Speed grade ID, Bits[6:4] Open N/A Unique speed 20 MSPS = 000 grade ID used to 40 MSPS = 001 differentiate 65 MSPS = 010 devices; read 80 MSPS = 011 only Device index and transfer registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set to default default determine which device on chip receives the next write command; the default is all devices on chip 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program registers (may or may not be indexed by device index) 0x08 Modes External External pin function Open Open 00 = chip run 0x80 Determines power- 0x00 = 01 = full power- various generic down full power-down down modes of chip enable 0x01 = standby 10 = standby operation (local) (local) 11 = chip-wide digital reset (local) 0x09 Clock (global) Open Open Open Open Open Duty 0x00 cycle stabilize 0x0B Clock divider Open Clock divider, Bits[2:0] 0x00 The divide ratio is (global) the value plus 1 Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 Rev. 0 | Page 32 of 40 AD9269 Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0x0D Test mode (local) User test mode Reset PN Reset PN Output test mode [3:0] (local) 0x00 When set, the test (local) long gen short data is placed on 0000 = off (default) 00 = single gen the output pins 0001 = midscale short 01 = alternate in place of 0010 = positive FS 10 = single once normal data 0011 = negative FS 11 = alternate 0100 = alternating checkerboard once 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x0E BIST enable Open Open Open Open Open BIST init Open BIST 0x00 When Bit 0 is set, enable the BIST function is initiated 0x10 Offset adjust 8-bit device offset adjustment [7:0] (local) 0x00 Device offset trim (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS Output mux Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS enable disable invert 01 = twos outputs and the complement format of the data (interleaved) (OEB) (local) 10 = gray code (local) 11 = offset binary (local) 0x15 OUTPUT_ADJUST 3.3 V DCO 1.8 V DCO drive strength 3.3 V data 1.8 V data 0x22 Determines drive strength drive strength drive strength CMOS output 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe drive strength 01 = 2 stripes (default) (default) 01 = 2 stripes properties 10 = 3 stripes (default) 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes 10 = 3 stripes 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 OUTPUT_PHASE DCO Open Open Open Open Input clock phase adjust, Bits[2:0] 0x00 On devices that output (Value is number of input clock utilize global polarity cycles of phase delay) clock divide, 0 = determines 000 = no delay normal which phase of 001 = 1 input clock cycle 1 = the divider 010 = 2 input clock cycles inverted output is used to 011 = 3 input clock cycles (local) supply the 100 = 4 input clock cycles output clock; 101 = 5 input clock cycles internal latching 110 = 6 input clock cycles is unaffected 111 = 7 input clock cycles 0x17 OUTPUT_DELAY Enable Open Enable Open Open DCO/data delay, Bits[2:0] 0x00 This sets the fine DCO data output delay of 000 = 0.56 ns delay delay the output clock 001 = 1.12 ns but does not 010 = 1.68 ns change internal 011 = 2.24 ns timing 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-Defined Pattern 1, LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined Pattern 1, MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-Defined Pattern 2, LSB 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-Defined Pattern 2, MSB 0x24 MISR_LSB Open Open Open Open Open Open Open B0 0x00 Least significant byte of MISR; read only Rev. 0 | Page 33 of 40 AD9269 Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0x2A Features Open Open Open Open Open Open Open OR OE 0x01 Disable the OR pin (local) for the indexed channel 0x2E Output assign Open Open Open Open Open Open Open 0 = Ch A = Assign an ADC ADC A 0x00 to an output 1 = Ch B = channel ADC B 0x01 (local) Digital feature control 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x01 (global) divider divider sync next sync enable sync enable only 0x101 USR2 Enable Open Enable Run Open Disable 0x88 Enables internal OEB GCLK GCLK SDIO oscillator for (Pin 47) detect pull- clock rates of (local) down <5 MHz 0x110 QEC Control 0 Open Open Freeze DC Freeze Freeze DC Phase Gain 0x00 phase gain enable enable enable 0x111 QEC Control 1 Open Open Open Force Force Force 0x00 DC phase gain 0x112 QEC gain Open KEXP_GAIN 0x02 bandwidth control 0x113 QEC phase Open KEXP_PHASE 0x02 bandwidth control 0x114 QEC DC Open KEXP_DC 0x02 bandwidth control 0x116 QEC Initial Gain 0 Initial gain, Bits[7:0] 0x00 0x117 QEC Initial Gain 1 Open Initial gain, Bits[14:8] 0x00 0x118 QEC Initial Phase 0 Initial phase, Bits[7:0] 0x00 0x119 QEC Initial Phase 1 Open Initial phase, Bits[12:8] 0x00 0x11A QEC Initial DC I 0 Initial DC I, Bits[7:0] 0x00 0x11B QEC Initial DC I 1 Open Initial DC I, Bits[13:8] 0x00 0x11C QEC Initial DC Q 0 Initial DC Q, Bits[7:0] 0x00 0x11D QEC Initial DC Q 1 Open Initial DC Q, Bits[13:8] 0x00 MEMORY MAP REGISTER DESCRIPTIONS Bit 0—Master Sync Enable For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Bit 0 must be high to enable any of the sync functions. Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Sync Control (Register 0x100) Bit 7—Enable OEB (Pin 47) Bits[7:3]—Open Normally set high, this bit allows Pin 47 to function as the output Bit 2—Clock Divider Next Sync Only enable. If this bit is set low, it disables Pin 47. If the master sync enable bit (Address 0x100, Bit 0) and the Bits [6:4]—Open clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 3—Enable GCLK Detect Bit 2 allows the clock divider to sync to the first sync pulse it Normally set high, this bit enables a circuit that detects encode receives and to ignore the rest. The clock divider sync enable bit rates below ~5 MSPS. When a low encode rate is detected, an (Address 0x100, Bit 1) resets after it syncs. internal oscillator, GCLK, is enabled to ensure the proper operation Bit 1—Clock Divider Sync Enable of several circuits. If this bit is set low, the detector is disabled. Bit 1 gates the sync pulse to the clock divider. The sync signal is Bit 2—Run GCLK enabled when Bit 1 and Bit 0 are high, and the device is operating This bit enables the GCLK oscillator. For some applications in continuous sync mode as long as Bit 2 of the sync control is low. with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Rev. 0 | Page 34 of 40 AD9269 QEC Phase Bandwidth Control (Register 0x113) Bit 1—Open Bits[7:5]—Open Bit 0—Disable SDIO Pull-Down Bits[4:0]—KEXP_PHASE This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when These bits adjust the time constants of the phase control many devices are connected to the SPI bus. feedback loop for quadrature error correction. QEC Control 0 (Register 0x110) QEC DC Bandwidth Control (Register 0x114) Bits[7:6]—Open Bits[7:5]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[4:0]—KEXP_DC These bits can be used to freeze the corresponding dc, phase, These bits adjust the time constants of the dc control feedback and gain offset corrections of the quadrature error correction loop for quadrature error correction. (QEC) independently. When asserted high, QEC is applied QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and using frozen values, and the estimation of the quadrature errors Register 0x117) is halted. Bits[14:0]—Initial Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable When the force gain bit (Register 0x111, Bit 0) is set high, these These bits allow the corresponding dc, phase, and gain offset values are used for gain error correction. corrections to be enabled independently. QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and QEC Control 1 (Register 0x111) Register 0x119) Bits[7:3]—Open Bits[12:0]—Initial Phase Bit 2—Force DC When the force phase bit (Register 0x111, Bit 1) is set high, these values are used for phase error correction. When set high, this bit forces the initial static correction values from Register 0x11A and Register 0x11B for the I data and QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11C and Register 0x11D for the Q data. Register 0x11B) Bit 1—Force Phase Bits[13:0]—Initial DC I When set high, this bit forces the initial static correction values When the force dc bit (Register 0x111, Bit 2) is set high, these from Register 0x118 and Register 0x119. values are used for dc error correction. Bit 0—Force Gain QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) When set high, this bit forces the initial static correction values Bits[13:0]—Initial DC Q from Register 0x116 and Register 0x117. When the force dc bit (Register 0x111, Bit 2) is set high, these QEC Gain Bandwidth Control (Register 0x112) values are used for dc error correction. Bits[7:5]—Open Bits[4:0]—KEXP_GAIN These bits adjust the time constants of the gain control feedback loop for quadrature error correction. Rev. 0 | Page 35 of 40 AD9269 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting design and layout of the AD9269 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements required for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9269, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V supply (LFCSP), at www.analog.com. for analog (AVDD), and use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and VCM DRVDD supply must be used, the AVDD and DRVDD domains The VCM pin should be decoupled to ground with a 0.1 μF must be isolated with a ferrite bead or filter choke and separate capacitor, as shown in Figure 41. decoupling capacitors. Several different decoupling capacitors RBIAS can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close The AD9269 requires that a 10 kΩ resistor be placed between to the pins of the part, with minimal trace length. the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. A single PCB ground plane should be sufficient when using the AD9269. With proper decoupling and smart partitioning of the Reference Decoupling PCB analog, digital, and clock sections, optimum performance Externally decouple the VREF pin to ground with a low ESR, is easily achieved. 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for SPI Port the AD9269; therefore, it must be connected to analog ground The SPI port should not be active during periods when the full (AGND) on the customer’s PCB. To achieve the best electrical dynamic performance of the converter is required. Because the and thermal performance, mate an exposed (no solder mask) SCLK, CSB, and SDIO signals are typically asynchronous to the continuous copper plane on the PCB to the AD9269 exposed ADC clock, noise from these signals can degrade converter per- paddle, Pin 0. formance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the The copper plane should have several vias to achieve the lowest AD9269 to keep these signals from transitioning at the converter possible resistive thermal path for heat dissipation to flow through inputs during critical sampling periods. the bottom of the PCB. Fill or plug these vias with nonconduc- tive epoxy. Rev. 0 | Page 36 of 40 AD9269 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option 2 AD9269BCPZ-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZRL7-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZ-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZRL7-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZ-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZRL7-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZ-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 2 AD9269BCPZRL7-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9269-80EBZ Evaluation Board AD9269-65EBZ Evaluation Board AD9269-40EBZ Evaluation Board AD9269-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. Rev. 0 | Page 37 of 40 091707-C AD9269 NOTES Rev. 0 | Page 38 of 40 AD9269 NOTES Rev. 0 | Page 39 of 40 AD9269 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08538-0-1/10(0) Rev. 0 | Page 40 of 40