ANALOG DEVICES AD9268

16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9268 FEATURES FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ SNR = 78.2 dBFS @ 70 MHz and 125 MSPS AVDD CSB DRVDD DCS DFS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS SPI AD9268 1.8 V analog supply operation ORA 1.8 V CMOS or LVDS output supply PROGRAMMING DATA D15A (MSB) VIN+A Integer 1-to-8 input clock divider 16 CMOS/LVDS ADC TO OUTPUT BUFFER IF sampling frequencies to 300 MHz VIN–A D0A (LSB) −153.6 dBm/Hz small-signal input noise with 200 Ω input CLK+ DIVIDE 1 impedance @ 70 MHz and 125 MSPS VREF TO 8 CLK– Optional on-chip dither SENSE DCOA Programmable internal ADC voltage reference DUTY CYCLE DCO REF STABILIZER GENERATION DCOB Integrated ADC sample-and-hold inputs VCM SELECT Flexible analog input range: 1 V p-p to 2 V p-p RBIAS ORB Differential analog inputs with 650 MHz bandwidth D15B (MSB) VIN–B 16 CMOS/LVDS TO ADC clock duty cycle stabilizer ADC OUTPUT BUFFER VIN+B D0B (LSB) 95 dB channel isolation/crosstalk MULTICHIP Serial port control SYNC User-configurable, built-in self-test (BIST) capability AGND SYNC PDWN OEB Energy-saving power-down modes NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. APPLICATIONS Figure 1. Communications Diversity radio systems PRODUCT HIGHLIGHTS Multimode digital receivers (3G) 1. On-chip dither option for improved SFDR performance GSM, EDGE, W-CDMA, LTE, with low power analog input. CDMA2000, WiMAX, TD-SCDMA 2. Proprietary differential input that maintains excellent SNR I/Q demodulation systems performance for input frequencies up to 300 MHz. Smart antenna systems 3. Operation from a single 1.8 V supply and a separate digital General-purpose software radios output driver supply accommodating 1.8 V CMOS or Broadband data applications LVDS outputs. Ultrasound equipment 4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 5. Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08123-001 AD9268 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 30 Applications ....................................................................................... 1 Channel/Chip Synchronization ................................................ 31 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 32 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 32 Revision History ............................................................................... 2 Timing ......................................................................................... 33 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 34 Specif ica t ions ..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 34 ADC DC Specifications ............................................................... 4 Output Test Modes ..................................................................... 34 ADC AC Specifications ................................................................. 6 Serial Port Interface (SPI) .............................................................. 35 Digital Specifications ................................................................... 7 Configuration Using the SPI ..................................................... 35 Switching Specifications ................................................................ 9 Hardware Interface ..................................................................... 36 Timing Specifications ................................................................ 10 Configuration Without the SPI ................................................ 36 Absolute Maximum Ratings .......................................................... 12 SPI Accessible Features .............................................................. 36 Thermal Characteristics ............................................................ 12 Memory Map .................................................................................. 37 ESD Caution ................................................................................ 12 Reading the Memory Map Register Table ............................... 37 Pin Configurations and Function Descriptions ......................... 13 Memory Map Register Table ..................................................... 38 Typical Performance Characteristics ........................................... 17 Memory Map Register Descriptions ........................................ 40 Equivalent Circuits ......................................................................... 25 Applications Information .............................................................. 41 Theory of Operation ...................................................................... 26 Design Guidelines ...................................................................... 41 ADC Architecture ...................................................................... 26 Outline Dimensions ....................................................................... 42 Analog Input Considerations .................................................... 26 Ordering Guide .......................................................................... 42 Voltage Reference ....................................................................... 29 REVISION HISTORY 9/09—Rev. 0 to Rev. A Changes to Features List .................................................................. 1 Changes to Specifications Section .................................................. 4 Changes to Table 5 .......................................................................... 10 Changes to Typical Performance Characteristics Section ......... 17 5/09—Revision 0: Initial Version Rev. A | Page 2 of 44 AD9268 GENERAL DESCRIPTION The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS The ADC output data can be routed directly to the two external analog-to-digital converter (ADC). The AD9268 is designed to 16-bit output ports. These outputs can be set to either 1.8 V support communications applications where high performance, CMOS or LVDS. combined with low cost, small size, and versatility, is desired. Flexible power-down options allow significant power savings, The dual ADC core features a multistage, differential pipelined when desired. architecture with integrated output error correction logic. Each Programming for setup and control is accomplished using a 3-wire ADC features wide bandwidth, differential sample-and-hold SPI-compatible serial interface. analog input amplifiers that support a variety of user-selectable The AD9268 is available in a 64-lead LFCSP and is specified over input ranges. An integrated voltage reference eases design consid- the industrial temperature range of −40°C to +85°C. erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Rev. A | Page 3 of 44 AD9268 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.2 ±0.4 ±0.2 ±0.5 ±0.4 ±0.65 % FSR Gain Error Full ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 % FSR Differential Full −1.0 +1.4 −1.0 +1.3 −1.0 +1.2 LSB 1 Nonlinearity (DNL) 25°C ±0.65 ±0.7 ±0.7 LSB Integral Nonlinearity Full ±4.5 ±5.1 ±5.5 LSB 1 (INL) 25°C ±2.0 ±3.0 ±3.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±0.4 ±0.1 ±0.4 ±0.2 ±0.45 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error Full ±5 ±12 ±5 ±12 ±5 ±12 mV (1 V Mode) Load Regulation @ Full 5 5 5 mV 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V 25°C 2.17 2.23 2.27 LSB rms ANALOG INPUT Input Span, VREF = Full 2 2 2 V p-p 1.0 V 2 Input Capacitance Full 8 8 8 pF Input Common- Full 0.9 0.9 0.9 V Mode Voltage REFERENCE INPUT Full 6 6 6 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 IAVDD Full 234 240 293 300 390 400 mA 1 IDRVDD (1.8 V Full 35 45 55 mA CMOS) 1 IDRVDD (1.8 V Full 89 89 94 mA LVDS) Rev. A | Page 4 of 44 AD9268 AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit POWER CONSUMPTION DC Input Full 420 450 565 590 750 777 mW 1 Sine Wave Input Full 485 608 800 mW (DRVDD = 1.8 V CMOS Output Mode) 1 Sine Wave Input Full 582 685 870 mW (DRVDD = 1.8 V LVDS Output Mode) 3 Standby Power Full 45 45 45 mW Power-Down Power Full 0.5 2.5 0.5 2.5 0.5 2.5 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). Rev. A | Page 5 of 44 AD9268 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz 25°C 79.7 78.9 78.8 dBFS IN f = 70 MHz 25°C 78.3 79.0 77.2 78.8 77.2 78.2 dBFS IN Full 78.0 77.1 76.5 dBFS fIN = 140 MHz 25°C 77.4 76.9 77.1 dBFS fIN = 200 MHz 25°C 75.5 75.0 75.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 2.4 MHz 25°C 79.4 78.3 78.3 dBFS fIN = 70 MHz 25°C 78.1 78.5 77.1 78.6 76.8 77.7 dBFS Full 77.7 76.8 76.2 dBFS f = 140 MHz 25°C 75.4 75.9 75.8 dBFS IN f = 200 MHz 25°C 74.3 72.2 74.0 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz 25°C 12.9 12.7 12.7 Bits IN f = 70 MHz 25°C 12.8 12.7 12.6 Bits IN fIN = 140 MHz 25°C 12.2 12.3 12.3 Bits fIN = 200 MHz 25°C 12.0 11.7 12.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −92 −87 −90 dBc fIN = 70 MHz 25°C −91 −88 −93 −87 −88 −85 dBc Full −87 −87 −84 dBc f = 140 MHz 25°C −80 −84 −83 dBc IN f = 200 MHz 25°C −82 −77 −79 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz 25°C 92 87 90 dBc IN f = 70 MHz 25°C 88 91 87 93 85 88 dBc IN Full 87 87 84 dBc fIN = 140 MHz 25°C 80 84 83 dBc fIN = 200 MHz 25°C 82 77 79 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN@ −23 dBFS) fIN = 2.4 MHz 25°C 93 100 88 dBFS f = 70 MHz 25°C 95 96 89 dBFS IN f = 140 MHz 25°C 98 96 90 dBFS IN f = 200 MHz 25°C 102 100 89 dBFS IN With On-Chip Dither (AIN @ −23 dBFS) fIN = 2.4 MHz 25°C 107 106 106 dBFS f = 70 MHz 25°C 107 109 106 dBFS IN f = 140 MHz 25°C 106 104 104 dBFS IN f = 200 MHz 25°C 104 108 105 dBFS IN Rev. A | Page 6 of 44 AD9268 AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER (HARMONIC OR SPUR) Without Dither f = 2.4 MHz 25°C −99 −100 −100 dBc IN f = 70 MHz 25°C −100 −96 −99 −94 −100 −94 dBc IN Full −96 −94 −94 dBc fIN = 140 MHz 25°C −98 −98 −98 dBc fIN = 200 MHz 25°C −96 −94 −96 dBc With On-Chip Dither f = 2.4 MHz 25°C −108 −107 −108 dBc IN fIN = 70 MHz 25°C −106 −96 −107 −95 −106 −95 dBc Full −96 −95 −95 dBc fIN = 140 MHz 25°C −105 −104 −103 dBc f = 200 MHz 25°C −102 −102 −99 dBc IN TWO-TONE SFDR, WITHOUT DITHER fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS) 25°C 93 92 90 dBc f = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS) 25°C 81 80 82 dBc IN 2 CROSSTALK Full −95 −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ Rev. A | Page 7 of 44 AD9268 Parameter Temperature Min Typ Max Unit 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUT/OUTPUT (SDIO/DCS) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 2 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage I = 50 μA Full 1.79 V OH I = 0.5 mA Full 1.75 V OH Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (V ), ANSI Mode Full 290 345 400 mV OD Output Offset Voltage (V ), ANSI Mode Full 1.15 1.25 1.35 V OS Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull up. 2 Pull down. Rev. A | Page 8 of 44 AD9268 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 8 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 4.5 4.75 5.0 3.8 4 4.2 ns Divide-by-2 Mode Through Divide-Full 0.8 0.8 0.8 ns by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, t) Full 0.07 0.07 0.07 ps J rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (t ) Full 2.8 3.5 4.2 2.8 3.5 4.2 2.8 3.5 4.2 ns PD 2 DCO Propagation Delay (t ) Full 3.1 3.1 3.1 ns DCO DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay (tPD) Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns 2 DCO Propagation Delay (t ) Full 3.9 3.9 3.9 ns DCO DCO to Data Skew (t ) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns SKEW CMOS Mode Pipeline Delay Full 12 12 12 Cycles (Latency) LVDS Mode Pipeline Delay (Latency) Full 12/12.5 12/12.5 12/12.5 Cycles Channel A/Channel B 3 Wake-Up Time Full 500 500 500 μs Out-of-Range Recovery Time Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. A | Page 9 of 44 AD9268 TIMING SPECIFICATIONS Table 5. Parameter Conditions Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.3 ns typ t SYNC to rising edge of CLK+ hold time 0.40 ns typ HSYNC SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min t Time required for the SDIO pin to switch from an input to an output relative to the SCLK 10 ns min EN_SDIO falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK 10 ns min rising edge Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 t PD Figure 2. CMOS Default Output Mode Data Output Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW t PD CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 Figure 3. CMOS Interleaved Output Mode Data Output Timing Rev. A | Page 10 of 44 08123-002 08123-057 AD9268 N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW t PD CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8 Figure 4. LVDS Mode Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. A | Page 11 of 44 08123-004 08123-003 AD9268 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating 1 the LFCSP package. Soldering the exposed paddle to the PCB ELECTRICAL increases the reliability of the solder joints and maximizes the AVDD to AGND −0.3 V to +2.0 V thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V plane. As shown in Table 7, airflow improves heat dissipation, SYNC to AGND −0.3 V to AVDD + 0.2 V which reduces θJA. In addition, metal in direct contact with the VREF to AGND −0.3 V to AVDD + 0.2 V package leads from metal traces, through holes, ground, and SENSE to AGND −0.3 V to AVDD + 0.2 V power planes, reduces θ . JA VCM to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance RBIAS to AGND −0.3 V to AVDD + 0.2 V Airflow CSB to AGND −0.3 V to DRVDD + 0.2 V Velocity SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V 1, 2 1, 3 1, 4 Package Type (m/sec) θJA θJC θJB Unit SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 64-Lead LFCSP 0 18.5 1.0 °C/W OEB −0.3 V to DRVDD + 0.2 V (CP-64-6) 1.0 16.1 9.2 °C/W PDWN −0.3 V to DRVDD + 0.2 V 2.5 14.5 °C/W D0A/D0B through D15A/D15B to −0.3 V to DRVDD + 0.2 V 1 AGND Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCOA/DCOB to AGND −0.3 V to DRVDD + 0.2 V 3 Per MIL-Std 883, Method 1012.1. 4 ENVIRONMENTAL Per JEDEC JESD51-8 (still air). Operating Temperature Range −40°C to +85°C (Ambient) Maximum Junction Temperature 150°C ESD CAUTION Under Bias Storage Temperature Range −65°C to +150°C (Ambient) 1 The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) + 0.2 V but should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 12 of 44 AD9268 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB D0B (LSB) 4 45 SCLK/DFS D1B 5 44 SDIO/DCS D2B 6 43 ORA D3B 7 42 D15A (MSB) D4B 8 AD9268 41 D14A D5B 9 40 D13A PARALLEL CMOS DRVDD 39 D12A 10 TOP VIEW D6B 38 D11A 11 (Not to Scale) D7B 12 37 DRVDD D8B 13 36 D10A D9B 14 35 D9A D10B 15 34 D8A D11B 16 33 D7A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). AVDD Supply Analog Power Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 25 D0A (LSB) Output Channel A CMOS Output Data. 26 D1A Output Channel A CMOS Output Data. 27 D2A Output Channel A CMOS Output Data. 29 D3A Output Channel A CMOS Output Data. 30 D4A Output Channel A CMOS Output Data. 31 D5A Output Channel A CMOS Output Data. 32 D6A Output Channel A CMOS Output Data. Rev. A | Page 13 of 44 D12B 64 AVDD 17 AVDD D13B 18 63 DRVDD 19 62 VIN+B D14B 20 61 VIN–B D15B (MSB) 21 60 AVDD ORB 22 59 AVDD DCOB 23 58 RBIAS DCOA 24 57 VCM D0A (LSB) 25 56 SENSE D1A 26 55 VREF D2A 27 54 AVDD DRVDD 28 53 AVDD 52 VIN–A D3A 29 D4A 30 51 VIN+A D5A 31 50 AVDD D6A 32 49 AVDD 08123-005 AD9268 Pin No. Mnemonic Type Description 33 D7A Output Channel A CMOS Output Data. 34 D8A Output Channel A CMOS Output Data. 35 D9A Output Channel A CMOS Output Data. 36 D10A Output Channel A CMOS Output Data. 38 D11A Output Channel A CMOS Output Data. 39 D12A Output Channel A CMOS Output Data. 40 D13A Output Channel A CMOS Output Data. 41 D14A Output Channel A CMOS Output Data. 42 D15A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 4 D0B (LSB) Output Channel B CMOS Output Data. 5 D1B Output Channel B CMOS Output Data. 6 D2B Output Channel B CMOS Output Data. 7 D3B Output Channel B CMOS Output Data. 8 D4B Output Channel B CMOS Output Data. 9 D5B Output Channel B CMOS Output Data. 11 D6B Output Channel B CMOS Output Data. 12 D7B Output Channel B CMOS Output Data. 13 D8B Output Channel B CMOS Output Data. 14 D9B Output Channel B CMOS Output Data. 15 D10B Output Channel B CMOS Output Data. 16 D11B Output Channel B CMOS Output Data. 17 D12B Output Channel B CMOS Output Data. 18 D13B Output Channel B CMOS Output Data. 20 D14B Output Channel B CMOS Output Data. 21 D15B (MSB) Output Channel B CMOS Output Data. 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low) in External Pin Mode. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 14 of 44 AD9268 PIN 1 48 PDWN CLK+ 1 INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB D0– (LSB) 4 45 SCLK/DFS D0+ (LSB) 5 44 SDIO/DCS D1– 6 43 OR+ D1+ 7 42 OR– D2– 8 AD9268 41 D15+ (MSB) D2+ 9 PARALLEL LVDS 40 D15– (MSB) DRVDD 10 39 D14+ TOP VIEW D3– 11 38 D14– (Not to Scale) D3+ 12 37 DRVDD D4– 13 36 D13+ D4+ 14 35 D13– D5– 15 34 D12+ D5+ 16 33 D12– NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, AVDD Supply Analog Power Supply (1.8 V Nominal). 60, 63, 64 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 12 D3+ Output Channel A/Channel B LVDS Output Data 3—True. Rev. A | Page 15 of 44 D6– 64 AVDD 17 AVDD D6+ 18 63 DRVDD 19 62 VIN+B D7– 20 61 VIN–B D7+ 21 60 AVDD D8– 22 59 AVDD D8+ 23 58 RBIAS DCO– 24 57 VCM DCO+ 25 56 SENSE D9– 26 55 VREF D9+ 27 54 AVDD DRVDD 28 53 AVDD 52 VIN–A D10– 29 D10+ 30 51 VIN+A D11– 31 50 AVDD D11+ 32 49 AVDD 08123-006 AD9268 Pin No. Mnemonic Type Description 11 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 14 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 13 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 16 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 15 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 18 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 17 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 21 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 20 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 23 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 22 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 27 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 26 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 34 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 33 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 36 D13+ Output Channel A/Channel B LVDS Output Data 13—True. 35 D13− Output Channel A/Channel B LVDS Output Data 13—Complement. 39 D14+ Output Channel A/Channel B LVDS Output Data 14—True. 38 D14− Output Channel A/Channel B LVDS Output Data 14—Complement. 41 D15+ (MSB) Output Channel A/Channel B LVDS Output Data 15—True. 40 D15− (MSB) Output Channel A/Channel B LVDS Output Data 15—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low) in External Pin Mode. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 16 of 44 AD9268 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted. 0 0 80MSPS 80MSPS 200.3MHz @ –1dBFS 2.4MHz @ –1dBFS –20 –20 SNR = 74.3dB (75.3dBFS) SNR = 79.0dB (80.0dBFS) SFDR = 83dBc SFDR = 98dBc –40 –40 –60 –60 SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 20 010 20 30 40 010 30 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. AD9268-80 Single-Tone FFT with fIN = 2.4 MHz Figure 11. AD9268-80 Single-Tone FFT with fIN = 200.1 MHz 0 0 80MSPS 80MSPS 70.1MHz @ –6dBFS 70.1MHz @ –1dBFS –20 –20 SNR = 73.0dB (79.0dBFS) SNR = 77.5dB (78.5dBFS) SFDR = 98dBc SFDR = 89.2dBc –40 –40 –60 –60 THIRD HARMONIC THIRD HARMONIC –80 –80 SECOND HARMONIC SECOND HARMONIC –100 –100 –120 –120 –140 –140 010 20 30 40 010 20 30 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. AD9268-80 Single-Tone FFT with f = 70.1 MHz Figure 12. AD9268-80 Single-Tone FFT with f = 70.1 MHz with Dither IN IN Enabled 0 120 80MSPS 140.1MHz @ –1dBFS –20 SNR = 76.0dB (77.0dBFS) 100 SFDR = 81.1dBc –40 80 –60 THIRD HARMONIC 60 SECOND HARMONIC –80 40 –100 SNR (dBFS) 20 –120 SFDR (dBc) SNR (dBc) SFDR (dBFS) –140 0 010 20 30 40 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 10. AD9268-80 Single-Tone FFT with fIN = 140.1 MHz Figure 13. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz Rev. A | Page 17 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08123-064 08123-063 08123-062 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 08123-067 08123-066 08123-065 AD9268 120 200,000 2.17 LSB rms 180,000 110 160,000 140,000 100 120,000 100,000 SNRFS (DITHER ON) SNRFS (DITHER OFF) 80,000 90 SFDRFS (DITHER ON) SFDRFS (DITHER OFF) 60,000 40,000 80 20,000 0 70 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 14. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (A ) with IN Figure 17. AD9268-80 Grounded Input Histogram f = 30 MHz with and without Dither Enabled IN 100 4 SNR @ –40°C DITHER ENABLED SFDR @ –40°C DITHER DISABLED 95 SNR @ +25°C SFDR @ +25°C SNR @ +85°C 2 90 SFDR @ +85°C 85 0 80 75 –2 70 65 –4 0 50 100 150 200 250 300 0 10,000 20,000 30,000 40,000 50,000 60,000 INPUT FREQUENCY (MHz) OUTPUT CODE Figure 15. AD9268-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN) Figure 18. AD9268-80 INL with fIN = 9.7 MHz with 2 V p-p Full Scale 1.00 105 SNR, CHANNEL B SFDR, CHANNEL B 0.75 SNR, CHANNEL A 100 SFDR, CHANNEL A 0.50 95 0.25 90 0 –0.25 85 –0.50 80 –0.75 –1.00 75 25 30 35 40 45 50 55 60 65 70 75 80 0 10,000 20,000 30,000 40,000 50,000 60,000 OUTPUT CODE SAMPLE RATE (MSPS) Figure 16. AD9268-80 Single-Tone SNR/SFDR vs. Sample Rate (f ) Figure 19. AD9268-80 DNL with fIN = 9.7 MHz S with f = 70.1 MHz IN Rev. A | Page 18 of 44 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBFS) 08123-068 08123-070 08123-069 NUMBER OF HITS DNL ERROR (LSB) INL ERROR (LSB) N – 11 N – 10 N – 9 N – 8 N – 7 N –6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 08123-072 08123-073 08123-071 AD9268 0 0 105MSPS 105MSPS 200.3MHz @ –1dBFS 2.4MHz @ –6dBFS –20 –20 SNR = 74.0dB (75.0dBFS) SNR = 78.2dB (79.2dBFS) SFDR = 79dBc SFDR = 90dBc –40 –40 SECOND SECOND HARMONIC THIRD HARMONIC HARMONIC –60 –60 THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 010 20 30 40 50 010 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. AD9268-105 Single-Tone FFT with fIN = 2.4 MHz Figure 23. AD9268-105 Single-Tone FFT with fIN = 200.3 MHz 0 0 105MSPS 105MSPS 70.1MHz @ –1dBFS 70.1MHz @ –6dBFS –20 SNR = 77.5dB (78.5dBFS) –20 SNR = 72.7dB (78.7dBFS) SFDR = 93.0dBc SFDR = 97.6dBc –40 –40 –60 –60 SECOND SECOND THIRD HARMONIC HARMONIC HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 010 20 30 40 50 010 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. AD9268-105 Single-Tone FFT with f = 70.1 MHz Figure 24. AD9268-105 Single-Tone FFT with f = 70.1 MHz with Dither IN IN Enabled 0 120 105MSPS 140.1MHz @ –1dBFS –20 SNR = 75.7dB (76.7dBFS) 100 SFDR = 85.5dBc –40 80 SECOND HARMONIC –60 THIRD HARMONIC 60 –80 40 –100 SNR (dBFS) 20 SFDR (dBc) –120 SNR (dBc) SFDR (dBFS) –140 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 010 20 30 40 50 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 22. AD9268-105 Single-Tone FFT with f = 140.1 MHz Figure 25. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) IN with fIN = 98.12 MHz Rev. A | Page 19 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08123-076 08123-075 08123-074 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 08123-079 08123-078 08123-077 AD9268 120 250,000 2.23 LSB rms 110 200,000 100 150,000 SNRFS (DITHER ON) SNRFS (DITHER OFF) 100,000 90 SFDRFS (DITHER ON) SFDRFS (DITHER OFF) 50,000 80 0 70 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 26. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (A ) IN Figure 29. AD9268-105 Grounded Input Histogram with f = 30 MHz with and without Dither Enabled IN 100 6 SNR @ –40°C DITHER ENABLED SFDR @ –40°C DITHER DISABLED 95 SNR @ +25°C 4 SFDR @ +25°C SNR @ +85°C 90 SFDR @ +85°C 2 85 0 80 –2 75 –4 70 65 –6 0 50 100 150 200 250 300 0 10,000 20,000 30,000 40,000 50,000 60,000 INPUT FREQUENCY (MHz) OUTPUT CODE Figure 27. AD9268-105 Single-Tone SNR/SFDR vs. Input Frequency (fIN) Figure 30. AD9268-105 INL with fIN = 9.7 MHz with 2 V p-p Full Scale 105 1.00 SNR, CHANNEL B SFDR, CHANNEL B 0.75 100 SNR, CHANNEL A SFDR, CHANNEL A 0.50 95 0.25 90 0 –0.25 85 –0.50 80 –0.75 75 –1.00 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 0 10,000 20,000 30,000 40,000 50,000 60,000 SAMPLE RATE (MSPS) OUTPUT CODE Figure 28. AD9268-105 Single-Tone SNR/SFDR vs. Sample Rate (f ) S Figure 31. AD9268-105 DNL with f = 9.7 MHz IN with f = 70.1 MHz IN Rev. A | Page 20 of 44 SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBFS) 08123-080 08123-082 08123-081 NUMBER OF HITS DNL ERROR (LSB) INL ERROR (LSB) N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 08123-084 08123-073 08123-083 AD9268 0 0 125MSPS 125MSPS 2.4MHz @ –1dBFS 140.1MHz @ –1dBFS –20 –20 SNR = 77.7dB (78.7dBFS) SNR = 76.0dB (77.0dBFS) SFDR = 90dBc SFDR = 84.0dBc –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 10 2030 4050 60 0 10 2030 4050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 35. AD9268-125 Single-Tone FFT with fIN = 140.1 MHz Figure 32. AD9268-125 Single-Tone FFT with fIN = 2.4 MHz 0 0 125MSPS 125MSPS 200.3MHz @ –1dBFS 30.3MHz @ –1dBFS –20 SNR = 74.7dB (75.7dBFS) –20 SNR = 77.4dB (78.4dBFS) SFDR = 80dBc SFDR = 91.2dBc –40 –40 –60 –60 THIRD HARMONIC SECOND HARMONIC THIRD HARMONIC –80 –80 SECOND HARMONIC –100 –100 –120 –120 –140 –140 0 10 2030 4050 60 0 10 2030 4050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. AD9268-125 Single-Tone FFT with f = 200.3 MHz IN Figure 33. AD9268-125 Single-Tone FFT with fIN = 30.3 MHz 0 0 125MSPS 125MSPS 220.1MHz @ –1dBFS 70.1MHz @ –1dBFS –20 SNR = 74.3dB (75.3dBFS) –20 SNR = 77.2dB (78.2dBFS) SFDR = 78.5dBc SFDR = 87.8dBc –40 –40 THIRD HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 0 10 2030 4050 60 0 10 2030 4050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 37. AD9268-125 Single-Tone FFT with fIN = 220.1 MHz Figure 34. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz Rev. A | Page 21 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08123-018 08123-017 08123-016 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08123-021 08123-020 08123-019 AD9268 0 120 125MSPS SFDR (dBFS) 70.1MHz @ –6dBFS –20 SNR = 72.2dB (78.2dBFS) 100 SFDR = 97dBc –40 SNR (dBFS) 80 –60 60 –80 SFDR (dBc) SECOND HARMONIC THIRD HARMONIC 40 –100 SNR (dBc) 20 –120 –140 0 0 10 2030 4050 60 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 41. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) Figure 38. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS with fIN = 2.4 MHz with Dither Enabled 120 0 SFDR (dBFS) 125MSPS –15 70.1MHz @ –23dBFS 100 SNR = 56.8dB (79.8dBFS) SFDR = 67.7dBc –30 SNR (dBFS) –45 80 –60 THIRD HARMONIC 60 –75 SECOND HARMONIC SFDR (dBc) –90 40 –105 SNR (dBc) –120 20 –135 0 –150 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 6 12 18 24 30 36 42 48 54 60 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 42. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) Figure 39. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS with fIN = 98.12 MHz with Dither Disabled, 1M Sample 120 0 125MSPS –15 70.1MHz @ –23dBFS SFDR (DITHER ON) SNR = 56.2dB (57.2dBFS) 110 –30 SFDR = 86.6dBc –45 100 –60 –75 SECOND HARMONIC THIRD HARMONIC SFDR (DITHER OFF) 90 –90 –105 SNR (DITHER OFF) 80 –120 SNR (DITHER ON) –135 70 –150 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 6 12 18 24 30 36 42 48 54 60 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 43. AD9268-125 Single Tone SNR/SFDR vs. Input Amplitude (AIN) Figure 40. AD9268-125 Single-Tone FFT with f = 70.1 MHz @ −23 dBFS IN with fIN = 30 MHz with and without Dither Enabled with Dither Enabled, 1M Sample Rev. A | Page 22 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08123-089 08123-088 08123-022 SNR/SFDR (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 08123-061 08123-024 08123-023 AD9268 0 100 SNR @ –40°C SFDR @ –40°C 95 SNR @ +25°C –20 SFDR @ +25°C SNR @ +85°C SFDR (dBc) 90 SFDR @ +85°C –40 85 –60 IMD3 (dBc) 80 –80 75 SFDR (dBFS) –100 70 IMD3 (dBFS) –120 65 0 50 100 150 200 250 300 –90 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 47. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 44. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (f ) IN IN with f = 169.1 MHz, f = 172.1 MHz, f = 125 MSPS with 2 V p-p Full Scale IN1 IN2 S 0 95 125MSPS 29.1MHz @ –7dBFS –20 90 32.1MHz @ –7dBFS SFDR = 89dBc (96dBFS) SFDR (dBc) –40 85 –60 80 –80 75 SNR (dBFS) –100 70 65 –120 –140 60 0 10 2030 4050 60 0 50 100 150 200 250 300 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 45. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) Figure 48. AD9268-125 Two-Tone FFT with f = 29.1 MHz and f = 32.1 MHz IN1 IN2 with 1 V p-p Full Scale 0 0 125MSPS 169.1MHz @ –7dBFS –20 172.1MHz @ –7dBFS –20 SFDR = 81.8dBc (88.8dBFS) SFDR (dBc) –40 –40 –60 IMD3 (dBc) –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –120 0 10 2030 4050 60 –90 –78 –66 –54 –42 –30 –18 –6 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 49. AD9268-125 Two-Tone FFT with fIN1 = 169.1 MHz and Figure 46. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 29.1 MHz, f = 32.1 MHz, f = 125 MSPS fIN2 = 172.1 MHz IN1 IN2 S Rev. A | Page 23 of 44 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS AND dBc) 08123-026 08123-025 08123-027 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/IMD3 (dBc AND dBFS) 08123-030 08123-029 08123-028 AD9268 1.00 100 SFDR (dBc), CHANNEL B 0.75 95 0.50 0.25 90 0 85 –0.25 SFDR (dBc), CHANNEL A SNR (dBFS), CHANNEL B –0.50 80 –0.75 SNR (dBFS), CHANNEL A 75 –1.00 25 35 45 55 65 75 85 95 105 115 125 0 16,384 32,768 49,152 65,536 OUTPUT CODE SAMPLE RATE (MSPS) Figure 50. AD9268-125 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 53. AD9268-125 DNL with fIN = 9.7 MHz with fIN = 70.1 MHz 3500 100 2.27LSB rms SFDR (dBc) 3000 90 2500 80 SNR (dBFS) 70 2000 1500 60 50 1000 500 40 30 0 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 INPUT COMMON-MODE VOLTAGE (V) OUTPUT CODE Figure 51. AD9268-125 Grounded Input Histogram Figure 54. SNR/SFDR vs. Input Common Mode (VCM) with f = 30 MHz IN 4 DITHER ENABLED DITHER DISABLED 2 0 –2 –4 0 16,384 32,768 49,152 65,536 OUTPUT CODE Figure 52. AD9268-125 INL with fIN = 9.7 MHz Rev. A | Page 24 of 44 INL ERROR (LSB) NUMBER OF HITS SNR/SFDR (dBFS/dBc) N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 08123-059 08123-031 08123-032 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) 08123-053 08123-033 AD9268 EQUIVALENT CIRCUITS AVDD VIN 350Ω SENSE Figure 55. Equivalent Analog Input Circuit Figure 60. Equivalent SENSE Circuit AVDD DRVDD 0.9V 26kΩ 10kΩ 10kΩ 350Ω CLK– CLK+ CSB Figure 61. Equivalent CSB Input Circuit Figure 56. Equivalent Clock Input Circuit AVDD DRVDD VREF PAD 6kΩ Figure 62. Equivalent VREF Circuit Figure 57. Digital Output DRVDD 26kΩ 350Ω 350Ω PDWN SDIO/DCS 26kΩ Figure 63. Equivalent PDWN Input Circuit Figure 58. Equivalent SDIO/DCS Circuit DRVDD 350Ω SCLK/DFS OR OEB 26kΩ Figure 59. Equivalent SCLK/DFS or OEB Input Circuit Rev. A | Page 25 of 44 08123-007 08123-009 08123-011 08123-008 08123-010 08123-014 08123-012 08123-013 08123-015 AD9268 THEORY OF OPERATION A small resistor in series with each input can help reduce the The AD9268 dual-core analog-to-digital converter (ADC) peak transient current required from the output stage of the design can be used for diversity reception of signals, in which the driving source. A shunt capacitor can be placed across the inputs ADCs are operating identically on the same carrier but from two to provide dynamic charging currents. This passive network separate antennae. The ADCs can also be operated with inde- creates a low-pass filter at the ADC input; therefore, the precise pendent analog inputs. The user can sample any f /2 frequency S values are dependent on the application. segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC In intermediate frequency (IF) undersampling applications, any performance. Operation to 300 MHz analog input is permitted, shunt capacitors should be reduced. In combination with the but it occurs at the expense of increased ADC noise and distortion. driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency In nondiversity applications, the AD9268 can be used as a base- Domain Response of Switched-Capacitor ADCs; the AN-827 band or direct downconversion receiver, in which one ADC is Application Note, A Resonant Approach to Interfacing Amplifiers to used for I input data, and the other is used for Q input data. Switched-Capacitor ADCs; and the Analog Dialogue article, Synchronization capability is provided to allow synchronized “Transformer-Coupled Front-End for Wideband A/D Converters,” timing between multiple devices. for more information on this subject (refer to www.analog.com). Programming and control of the AD9268 are accomplished BIAS using a 3-wire SPI-compatible serial interface. S S C C ADC ARCHITECTURE S FB VIN+ The AD9268 architecture consists of a dual front-end sample- C C PAR1 PAR2 and-hold circuit, followed by a pipelined, switched-capacitor S H S ADC. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined C S VIN– architecture permits the first stage to operate on a new input C C PAR1 C FB PAR2 S sample and the remaining stages to operate on the preceding S samples. Sampling occurs on the rising edge of the clock. BIAS Figure 64. Switched-Capacitor Input Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digital- For best dynamic performance, the source impedances driving to-analog converter (DAC) and an interstage residue amplifier VIN+ and VIN− should be matched, and the inputs should be (MDAC). The MDAC magnifies the difference between the differentially balanced. reconstructed DAC output and the flash input for the next stage An internal differential reference buffer creates positive and in the pipeline. One bit of redundancy is used in each stage to negative reference voltages that define the input span of the ADC facilitate digital correction of flash errors. The last stage simply core. The span of the ADC core is set by this buffer to 2 × VREF. consists of a flash ADC. Input Common Mode The input stage of each channel contains a differential sampling The analog inputs of the AD9268 are not internally dc biased. circuit that can be ac- or dc-coupled in differential or single- In ac-coupled applications, the user must provide this bias exter- ended modes. The output staging block aligns the data, corrects nally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is errors, and passes the data to the output buffers. The output buffers recommended for optimum performance, but the device are powered from a separate supply, allowing digital output noise to functions over a wider range with reasonable performance be separated from the analog core. During power-down, the output (see Figure 54). An on-board common-mode voltage reference buffers go into a high impedance state. is included in the design and is available from the VCM pin. ANALOG INPUT CONSIDERATIONS Optimum performance is achieved when the common-mode The analog input to the AD9268 is a differential switched- voltage of the analog input is set by the VCM pin voltage capacitor circuit that has been designed for optimum performance (typically 0.5 × AVDD). The VCM pin must be decoupled to while processing a differential input signal. ground by a 0.1 μF capacitor, as described in the Applications Information section. The clock signal alternatively switches the input between sample mode and hold mode (see Figure 64). When the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ½ of a clock cycle. Rev. A | Page 26 of 44 08123-034 AD9268 Common-Mode Voltage Servo typically at very low levels and do not limit SFDR when the ADC is quantizing large-signal inputs, dithering converts these In applications where there may be a voltage loss between the VCM tones to noise and produces a whiter noise floor. output of the AD9268 and the analog inputs, the common-mode voltage servo can be enabled. When the inputs are ac-coupled and Small-Signal FFT a resistance of >100 Ω is placed between the VCM output and the For small-signal inputs, the front-end sampling circuit typically analog inputs, a significant voltage drop can occur and the contributes very little distortion, and, therefore, the SFDR is likely common-mode voltage servo should be enabled. Setting Bit 0 in to be limited by tones caused by DNL errors due to random com- Register 0x0F to a logic high enables the VCM servo mode. In ponent mismatches. Therefore, for small-signal inputs (typically, this mode, the AD9268 monitors the common-mode input level those below −6 dBFS), dithering can significantly improve at the analog inputs and adjusts the VCM output level to keep the SFDR by converting these DNL tones to white noise. common-mode input voltage at an optimal level. If both channels Static Linearity are operational, Channel A is monitored. However, if Channel A is in power-down or standby mode, then the Channel B input is Dithering also removes sharp local discontinuities in the INL monitored. transfer function of the ADC and reduces the overall peak-to- peak INL. Dither In receiver applications, utilizing dither helps to reduce DNL errors The AD9268 has an optional dither mode that can be selected that cause small-signal gain errors. Often this issue is overcome for one or both channels. Dithering is the act of injecting a known by setting the input noise 5 dB to 10 dB above the converter but random amount of white noise, commonly referred to as noise. By utilizing dither within the converter to correct the dither, into the input of the ADC. Dithering has the effect of DNL errors, the input noise requirement can be reduced. improving the local linearity at various points along the ADC transfer function. Dithering can significantly improve the SFDR Differential Input Configurations when quantizing small-signal inputs, typically when the input Optimum performance is achieved while driving the AD9268 level is below −6 dBFS. in a differential input configuration. For baseband applications, As shown in Figure 65, the dither that is added to the input of the AD8138, ADA4937-2, and ADA4938-2 differential drivers the ADC through the dither DAC is precisely subtracted out provide excellent performance and a flexible interface to the digitally to minimize SNR degradation. When dithering is ADC. enabled, the dither DAC is driven by a pseudorandom number The output common-mode voltage of the ADA4938-2 is easily generator (PN gen). In the AD9268, the dither DAC is precisely set with the VCM pin of the AD9268 (see Figure 66), and the calibrated to result in only a very small degradation in SNR and driver can be configured in a Sallen-Key filter topology to SINAD. The typical SNR and SINAD degradation values, with provide band limiting of the input signal. dithering enabled, are only 1 dB and 0.8 dB, respectively. 15pF AD9268 200Ω 33Ω 15Ω VIN ADC CORE DOUT 90Ω VIN– AVDD VIN 76.8Ω 5pF AD9268 ADA4938-2 0.1µF DITHER 33Ω 15Ω VCM DAC VIN+ 120Ω 15pF 200Ω PN GEN DITHER ENABLE Figure 66. Differential Input Configuration Using the ADA4938-2 Figure 65. Dither Block Diagram For baseband applications in which SNR is a key parameter, differential transformer coupling is the recommended input Large-Signal FFT configuration. An example is shown in Figure 67. To bias the In most cases, dithering does not improve SFDR for large-signal analog input, the VCM voltage can be connected to the center inputs close to full scale, for example, with a −1 dBFS input. For tap of the secondary winding of the transformer. large-signal inputs, the SFDR is typically limited by front-end C2 sampling distortion, which dithering cannot improve. However, R2 even for such large-signal inputs, dithering may be useful for VIN+ R1 certain applications because it makes the noise floor whiter. 2V p-p 49.9Ω C1 AD9268 As is common in pipeline ADCs, the AD9268 contains small R2 R1 DNL errors caused by random component mismatches that VCM VIN– produce spurs or tones that make the noise floor somewhat 0.1µF C2 randomly colored part-to-part. Although these tones are Figure 67. Differential Transformer-Coupled Configuration Rev. A | Page 27 of 44 08123-058 08123-036 08123-035 AD9268 The signal characteristics must be considered when selecting achieved by using a ferrite bead in series with a resistor and a transformer. Most RF transformers saturate at frequencies removing the capacitors. However, these values are dependent below a few megahertz (MHz). Excessive signal power can also on the input signal and should be used only as a starting guide. cause core saturation, which leads to distortion. Table 10. Example RC Network At input frequencies in the second Nyquist zone and above, the Frequency noise performance of most amplifiers is not adequate to achieve Range R1 Series C1 Differential R2 Series C2 Shunt the true SNR performance of the AD9268. For applications in (MHz) (Ω Each) (pF) (Ω Each) (pF Each) which SNR is a key parameter, differential double balun coupling 0 to 100 33 5 15 15 is the recommended input configuration (see Figure 68). In this 100 to 200 10 5 10 10 1 configuration, the input is ac-coupled, and the CML is provided 100 to 300 10 Remove 66 Remove to each input through a 33 Ω resistor. These resistors compensate 1 In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz. for losses in the input baluns to provide a 50 Ω impedance to An alternative to using a transformer-coupled input at fre- the driver. quencies in the second Nyquist zone is to use the AD8352 In the double balun and transformer configurations, the value of differential driver. An example is shown in Figure 69. See the the input capacitors and resistors is dependent on the input fre- AD8352 data sheet for more information. quency and source impedance and may need to be reduced or removed. Table 10 displays recommended values to set the RC network. At higher input frequencies, good performance can be C2 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P A C1 AD9268 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– C2 Figure 68. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+ 2 200Ω C AD9268 R AD8352 R G C D D 3 200Ω 0.1µF 10 R 4 VCM VIN– 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 69. Differential Input Configuration Using the AD8352 Rev. A | Page 28 of 44 08123-038 08123-039 AD9268 If a resistor divider is connected external to the chip, as shown VOLTAGE REFERENCE in Figure 71, the switch again sets to the SENSE pin. This puts A stable and accurate voltage reference is built into the AD9268. the reference amplifier in a noninverting mode with the VREF The input range can be adjusted by varying the reference voltage output, defined as follows: applied to the AD9268, using either the internal reference or an R2 ⎛ ⎞ externally applied reference voltage. The input span of the ADC VREF =0 .5× 1+ ⎜ ⎟ R1 tracks reference voltage changes linearly. The various reference ⎝ ⎠ modes are summarized in the sections that follow. The Reference The input range of the ADC always equals twice the voltage at Decoupling section describes the best practices PCB layout of the reference pin (VREF) for either an internal or an external the reference. reference. Internal Reference Connection VIN+A/VIN+B A comparator within the AD9268 detects the potential at the VIN–A/VIN–B SENSE pin and configures the reference into four possible modes, which are summarized in Table 11. If SENSE is grounded, the ADC CORE reference amplifier switch is connected to the internal resistor divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full- VREF scale input. In this mode, with SENSE grounded, the full scale can 1.0µF 0.1µF R2 also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of SELECT LOGIC Register 0x18. These bits can be used to change the full scale to SENSE 1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p, as shown in Table 17. 0.5V R1 Connecting the SENSE pin to the VREF pin switches the reference AD9268 amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output for a 1 V p-p full-scale input. Figure 71. Programmable Reference Configuration VIN+A/VIN+B If the internal reference of the AD9268 is used to drive multiple VIN–A/VIN–B converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows ADC how the internal reference voltage is affected by loading. CORE 0 VREF –0.5 1.0µF 0.1µF VREF = 0.5V SELECT LOGIC –1.0 SENSE VREF = 1V 0.5V –1.5 AD9268 –2.0 Figure 70. Internal Reference Configuration –2.5 –3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) Figure 72. Reference Voltage Accuracy vs. Load Current Table 11. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × external reference Internal Fixed Reference VREF 0.5 1.0 R2 ⎛ ⎞ (see Figure 71) Programmable Reference 0.2 V to VREF 0.5 × ⎜1+ ⎟ 2 × VREF R1 ⎝ ⎠ Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. A | Page 29 of 44 08123-040 REFERENCE VOLTAGE ERROR (%) 08123-041 08123-054 AD9268 External Reference Operation The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- The use of an external reference may be necessary to enhance mended for clock frequencies from 10 MHz to 200 MHz. The the gain accuracy of the ADC or improve thermal drift charac- back-to-back Schottky diodes across the transformer/balun teristics. Figure 73 shows the typical drift characteristics of the secondary limit clock excursions into the AD9268 to approx- internal reference in 1.0 V mode. imately 0.8 V p-p differential. When the SENSE pin is tied to AVDD, the internal reference is This limit helps prevent the large voltage swings of the clock disabled, allowing the use of an external reference. An internal from feeding through to other portions of the AD9268 while reference buffer loads the external reference with an equivalent preserving the fast rise and fall times of the signal that are critical 6 kΩ load (see Figure 62). The internal buffer generates the positive to a low jitter performance. and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. ® Mini-Circuits ADC 2.0 ADT1-1WT, 1:1Z AD9268 0.1µF 0.1µF XFMR CLOCK 1.5 CLK+ INPUT 100Ω VREF = 1.0V 50Ω 0.1µF 1.0 CLK– SCHOTTKY 0.5 0.1µF DIODES: HSMS2822 0 Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz) –0.5 ADC –1.0 AD9268 1nF 0.1µF CLOCK CLK+ –1.5 INPUT 50Ω 0.1µF –2.0 1nF CLK– –40 –20 0 20 40 60 80 TEMPERATURE (°C) SCHOTTKY DIODES: Figure 73. Typical VREF Drift HSMS2822 Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz) CLOCK INPUT CONSIDERATIONS If a low jitter clock source is not available, another option is to For optimum performance, the AD9268 sample clock inputs, ac couple a differential PECL signal to the sample clock input CLK+ and CLK−, should be clocked with a differential signal. pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ The signal is typically ac-coupled into the CLK+ and CLK− pins AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock via a transformer or capacitors. These pins are biased internally drivers offer excellent jitter performance. (see Figure 74) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. AVDD 0.1µF 0.1µF CLOCK CLK+ INPUT ADC AD951x 100Ω 0.9V PECL DRIVER AD9268 0.1µF 0.1µF CLOCK CLK– CLK+ CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ 4pF 4pF Figure 77. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ Figure 74. Equivalent Clock Input Circuit AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ Clock Input Options AD9518 clock drivers offer excellent jitter performance. The AD9268 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of 0.1µF 0.1µF the type of signal being used, clock source jitter is of the most CLOCK CLK+ INPUT concern, as described in the Jitter Considerations section. ADC AD951x 100Ω LVDS DRIVER AD9268 0.1µF Figure 75 and Figure 76 show two preferred methods for clocking 0.1µF CLOCK CLK– the AD9268 (at clock rates up to 625 MHz). A low jitter clock INPUT 50kΩ 50kΩ source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. Figure 78. Differential LVDS Sample Clock (Up to 625 MHz) Rev. A | Page 30 of 44 REFERENCE VOLTAGE ERROR (mV) 08123-044 08123-055 08123-046 08123-045 08123-048 08123-047 AD9268 In some applications, it may be acceptable to drive the sample Jitter Considerations clock inputs with a single-ended CMOS signal. In such applica- High speed, high resolution ADCs are sensitive to the quality tions, the CLK+ pin should be driven directly from a CMOS gate, of the clock input. For inputs near full scale, the degradation in and the CLK− pin should be bypassed to ground with a 0.1 μF SNR from the low frequency SNR (SNRLF) at a given input capacitor (see Figure 79). frequency (fINPUT) due to jitter (tJRMS) can be calculated by (−SNR /10) 2 LF V SNR = −10 log[(2π × f × t ) + 10 ] CC HF INPUT JRMS OPTIONAL 0.1µF 0.1µF 1kΩ 100Ω AD951x In the equation, the rms aperture jitter represents the clock input CLOCK CLK+ CMOS DRIVER INPUT jitter specification. IF undersampling applications are particularly 1 1kΩ ADC 50Ω AD9268 sensitive to jitter, as illustrated in Figure 80. The measured curve in CLK– Figure 80 was taken using an ADC clock source with approxi- 0.1µF mately 65 fs of jitter, which combines with the 70 fs of jitter inherent in the AD9268 to produce the results shown. 1 50Ω RESISTOR IS OPTIONAL. 80 Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 0.05ps Input Clock Divider 75 MEASURED The AD9268 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. For 70 divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is 0.20ps optional. For other divide ratios, divide by 3, 5, 6, 7, and 8, the 65 duty cycle stabilizer must be enabled for proper part operation. 0.50ps 60 The AD9268 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock 55 1.00ps divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC 1.50ps 50 causes the clock divider to reset to its initial state. This synchro- 1 10 100 1k INPUT FREQUENCY (MHz) nization feature allows multiple parts to have their clock dividers Figure 80. SNR vs. Input Frequency and Jitter aligned to guarantee simultaneous input sampling. The clock input should be treated as an analog signal in cases in Clock Duty Cycle which aperture jitter may affect the dynamic range of the AD9268. Typical high speed ADCs use both clock edges to generate a variety Power supplies for clock drivers should be separated from the of internal timing signals and, as a result, may be sensitive to clock ADC output driver supplies to avoid modulating the clock signal duty cycle. The AD9268 requires a tight tolerance on the clock duty with digital noise. Low jitter, crystal-controlled oscillators make cycle to maintain dynamic performance characteristics. the best clock sources. If the clock is generated from another type of The AD9268 contains a duty cycle stabilizer (DCS) that retimes source (by gating, dividing, or another method), it should be the nonsampling (falling) edge, providing an internal clock signal retimed by the original clock at the last step. with a nominal 50% duty cycle. This allows the user to provide Refer to the AN-501 Application Note and the AN-756 Application a wide range of clock input duty cycles without affecting the Note (see www.analog.com) for more information about jitter perfor-mance of the AD9268. Noise and distortion performance performance as it relates to ADCs. are nearly flat for a wide range of duty cycles with the DCS enabled. CHANNEL/CHIP SYNCHRONIZATION Jitter in the rising edge of the input is still of paramount concern The AD9268 has a SYNC input that offers the user flexible and is not easily reduced by the internal stabilization circuit. The synchronization options for synchronizing the clock divider. duty cycle control loop does not function for clock rates of less The clock divider sync feature is useful for guaranteeing synchro- than 20 MHz, nominally. The loop has a time constant associated nized sample clocks across multiple ADCs. The input clock with it that must be considered in applications in which the clock divider can be enabled to synchronize on a single occurrence of rate can change dynamically. A wait time of 1.5 μs to 5 μs is the SYNC signal or on every occurrence. required after a dynamic clock frequency increase or decrease The SYNC input is internally synchronized to the sample clock; before the DCS loop is relocked to the input signal. During the however, to ensure that there is no timing uncertainty between time period that the loop is not locked, the DCS loop is bypassed, multiple parts, the SYNC input signal should be externally syn- and internal device timing is dependent on the duty cycle of the chronized to the input clock signal, meeting the setup and hold input clock signal. In such applications, it may be appropriate to times shown in Table 5. The SYNC input should be driven using disable the duty cycle stabilizer. In all other applications, enabling a single-ended CMOS-type signal. the DCS circuit is recommended to maximize ac performance. Rev. A | Page 31 of 44 08123-049 SNR (dBc) 08123-050 AD9268 1.0 0.25 POWER DISSIPATION AND STANDBY MODE I AVDD As shown in Figure 81, the power dissipated by the AD9268 0.8 0.20 varies with its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. TOTAL POWER 0.6 0.15 The maximum DRVDD current (IDRVDD) can be calculated as 0.4 0.10 IDRVDD = VDRVDD × C × f × N LOAD CLK where N is the number of output bits (32 plus two DCO 0.2 I 0.05 DRVDD outputs, in the case of the AD9268). This maximum current occurs when every output bit switches on 0 0 every clock cycle, that is, a full-scale square wave at the Nyquist 25 35 45 55 65 75 frequency of f /2. In practice, the DRVDD current is estab- CLK ENCODE FREQUENCY (MSPS) Figure 83. AD9268-80 Power and Current vs. Encode Frequency (LVDS lished by the average number of output bits switching, which is Output Mode) determined by the sample rate and the characteristics of the analog input signal. By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9268 is placed in power-down Reducing the capacitive load presented to the output drivers mode. In this state, the ADC typically dissipates 3.3 mW. reduces digital power consumption. The data in Figure 81 was During power-down, the output drivers are placed in a high taken in LVDS output mode, using the same operating conditions impedance state. Asserting the PDWN pin low returns the as those used for the Typical Performance Characteristics. AD9268 to its normal operating mode. 1.25 0.5 Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, 1.00 0.4 and clock. Internal capacitors are discharged when entering power- IAVDD down mode and then must be recharged when returning to normal 0.75 0.3 operation. TOTAL POWER When using the SPI port interface, the user can place the ADC 0.50 0.2 in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. 0.25 0.1 IDRVDD DIGITAL OUTPUTS 0 0 The AD9268 output drivers can be configured to interface with 25 50 75 100 125 1.8 V CMOS logic families. The AD9268 can also be configured ENCODE FREQUENCY (MHz) for LVDS outputs (standard ANSI or reduced output swing mode) Figure 81. AD9268-125 Power and Current vs. Encode Frequency (LVDS Output Mode) using a DRVDD supply voltage of 1.8 V. 1.0 0.5 In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. 0.8 0.4 However, large drive currents tend to cause current glitches on TOTAL POWER the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads 0.6 0.3 or large fanouts may require external buffers or latches. 0.4 0.2 The default output mode is CMOS, with each channel output I AVDD I on separate busses as shown in Figure 2. The output can also be DRVDD configured for interleaved CMOS via the SPI port. In interleaved 0.2 0.1 CMOS mode, the data for both channels is output through the Channel A output bits, and the Channel B output is placed into 0 0 high impedance mode. The timing diagram for interleaved 25 35 45 55 65 75 85 95 105 CMOS output mode is shown in Figure 3. ENCODE FREQUENCY (MSPS) Figure 82. AD9268-105 Power and Current vs. Encode Frequency (LVDS The output data format can be selected for either offset binary Output Mode) or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). Rev. A | Page 32 of 44 TOTAL POWER (W) TOTAL POWER (W) SUPPLY CURRENT (A) 08123-086 SUPPLY CURRENT (A) 08123-056 TOTAL POWER (W) 08123-087 SUPPLY CURRENT (A) AD9268 As detailed in the AN-877 Application Note, Interfacing to High TIMING Speed ADCs via SPI, the data format can be selected for offset The AD9268 provides latched data with a pipeline delay of binary, twos complement, or gray code when using the SPI control. 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Table 12. SCLK/DFS Mode Selection (External Pin Mode) The length of the output data lines and loads placed on them Voltage at Pin SCLK/DFS SDIO/DCS should be minimized to reduce transients within the AD9268. AGND Offset binary (default) DCS disabled These transients can degrade converter dynamic performance. AVDD Twos complement DCS enabled (default) The lowest typical conversion rate of the AD9268 is 10 MSPS. Digital Output Enable Function (OEB) At clock rates below 10 MSPS, dynamic performance can degrade. The AD9268 has a flexible three-state ability for the digital output Data Clock Output (DCO) pins. The three-state mode is enabled using the OEB pin or The AD9268 provides two data clock output (DCO) signals through the SPI. If the OEB pin is low, the output data drivers and intended for capturing the data in an external register. In CMOS DCOs are enabled. If the OEB pin is high, the output data drivers output mode, the data outputs are valid on the rising edge of DCO, and DCOs are placed in a high impedance state. This OEB unless the DCO clock polarity has been changed via the SPI. In function is not intended for rapid access to the data bus. Note LVDS output mode, the DCO and data output switching edges that OEB is referenced to the digital output driver supply are closely aligned. Additional delay can be added to the DCO (DRVDD) and should not exceed that supply voltage. output using SPI Register 0x17 to increase the data setup time. When using the SPI, the data outputs and DCO of each channel In this case, the Channel A output data is valid on the rising can be independently three-stated by using the output enable edge of DCO, and the Channel B output data is valid on the bar bit (Bit 4) in Register 0x14. falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a graphical timing description of the output modes. Table 13. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 0000 1000 0000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111 1 Rev. A | Page 33 of 44 AD9268 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9268 includes built-in test features designed to enable The outputs are not disconnected during this test, so the PN verification of the integrity of each channel as well as facilitate sequence can be observed as it runs. The PN sequence can be board level debugging. A BIST (built-in self-test) feature is included continued from its last value or reset from the beginning, based that verifies the integrity of the digital datapath of the AD9268. on the value programmed in Register 0x0E, Bit 2. The BIST Various output test options are also provided to place predictable signature result varies based on the channel configuration. values on the outputs of the AD9268. OUTPUT TEST MODES BUILT-IN SELF-TEST (BIST) The output test options are shown in Table 17. When an output The BIST is a thorough test of the digital portion of the selected test mode is enabled, the analog section of the ADC is discon- AD9268 signal path. When enabled, the test runs from an internal nected from the digital back end blocks and the test pattern is run pseudorandom noise (PN) source through the digital datapath through the output formatting block. Some of the test patterns are starting at the ADC block output. The BIST sequence runs for subject to output formatting, and some are not. The seed value for 512 cycles and stops. The BIST signature value for Channel A or the PN sequence tests can be forced if the PN reset bits are used Channel B is placed in Register 0x24 and Register 0x25. If one to hold the generator in reset mode by setting Bit 4 or Bit 5 of channel is chosen, its BIST signature is written to the two registers. Register 0x0D. These tests can be performed with or without If both channels are chosen, the results from Channel A are placed an analog signal (if present, the analog signal is ignored), but in the BIST signature registers. they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. A | Page 34 of 44 AD9268 SERIAL PORT INTERFACE (SPI) The AD9268 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 84 gives the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. When the CSB is can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device, into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK/DFS pin, the Data follows the instruction phase, and its length is determined by the W0 and W1 bits. SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS (a serial clock) is used to synchronize the read and write data In addition to word length, the instruction phase determines presented from and to the ADC. The SDIO/DCS (serial data whether the serial frame is a read or write operation, allowing input/output) is a dual-purpose pin that allows data to be sent the serial port to be used both to program the chip and to read to and read from the internal ADC memory map registers. The the contents of the on-chip memory. The first bit of the first byte in CSB (chip select bar) is an active-low control that enables or a multibyte serial data transfer frame indicates whether a read disables the read and write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial Table 14. Serial Port Interface Pins data input/output (SDIO) pin to change direction from an input to Pin Function an output at the appropriate point in the serial frame. SCLK Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB-first SDIO Serial Data Input/Output. A dual-purpose pin that mode or in LSB-first mode. MSB first is the default on power-up typically serves as an input or an output, depending on and can be changed via the SPI port configuration register. For the instruction being sent and the relative position in the more information about this and other features, see the AN-877 timing frame. Application Note, Interfacing to High Speed ADCs via SPI. CSB Chip Select Bar. An active-low control that gates the read and write cycles. t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 84. Serial Port Interface Timing Diagram Rev. A | Page 35 of 44 08123-052 AD9268 When the device is in SPI mode, the PDWN and OEB pins HARDWARE INTERFACE remain active. For SPI control of output enable and power-down, The pins described in Table 14 comprise the physical interface the OEB and PDWN pins should be set to their default states. between the user programming device and the serial port of the AD9268. The SCLK pin and the CSB pin function as inputs Table 15. Mode Selection when using the SPI. The SDIO pin is bidirectional, functioning External as an input during write phases and as an output during Pin Voltage Configuration readback. SDIO/DCS AVDD (default) Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled The SPI is flexible enough to be controlled by either FPGAs or SCLK/DFS AVDD Twos complement enabled microcontrollers. One method for SPI configuration is AGND (default) Offset binary enabled described in detail in the AN-812 Application Note, Micro- OEB AVDD Outputs in high impedance controller-Based Serial Port Interface (SPI) Boot Circuit. AGND (default) Outputs enabled The SPI port should not be active during periods when the full PDWN AVDD Chip in power-down or dynamic performance of the converter is required. Because the standby SCLK signal, the CSB signal, and the SDIO signal are typically AGND (default) Normal operation asynchronous to the ADC clock, noise from these signals can SPI ACCESSIBLE FEATURES degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between Table 16 provides a brief description of the general features that this bus and the AD9268 to prevent these signals from transi- are accessible via the SPI. These features are described in detail in tioning at the converter inputs during critical sampling periods. the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9268 part-specific features are described in detail Some pins serve a dual function when the SPI is not being used. following Table 17, the external memory map register table. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Table 16. Features Accessible Using the SPI Digital Outputs section describes the strappable functions Feature Name Description supported on the AD9268. Mode Allows the user to set either power-down mode CONFIGURATION WITHOUT THE SPI or standby mode Clock Allows the user to access the DCS, set the In applications that do not interface to the SPI control registers, clock divider, set the clock divider phase, and the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the enable the sync PDWN pin serve as standalone CMOS-compatible control pins. Offset Allows the user to digitally adjust the When the device is powered up, it is assumed that the user converter offset intends to use the pins as static control lines for the duty cycle Test I/O Allows the user to set test modes to have stabilizer, output data format, output enable, and power-down known data on output bits feature control. In this mode, the CSB chip select bar should be Output Mode Allows the user to set the output mode, including LVDS connected to AVDD, which disables the serial port interface. Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Rev. A | Page 36 of 44 AD9268 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip • “Bit is set” is synonymous with “bit is set to Logic 1” or configuration registers (Address 0x00 to Address 0x02); the “writing Logic 1 for the bit.” channel index and transfer registers (Address 0x05 and • “Clear a bit” is synonymous with “bit is set to Logic 0” or Address 0xFF); the ADC functions registers, including setup, “writing Logic 0 for the bit.” control, and test (Address 0x08 to Address 0x30); and the digital Transfer Register Map feature control register (Address 0x100). Address 0x08 through Address 0x18 and Address 0x30 are The memory map register table (see Table 17) documents the shadowed. Writes to these addresses do not affect part default hexadecimal value for each hexadecimal address shown. operation until a transfer command is issued by writing 0x01 to The column with the heading Bit 7 (MSB) is the start of the Address 0xFF, setting the transfer bit. This allows these registers default hexadecimal value given. For example, Address 0x18, to be updated internally and simultaneously when the transfer the VREF select register, has a hexadecimal default value of 0xC0. bit is set. The internal update takes place when the transfer bit is This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. set, and the bit autoclears. This setting is the default reference selection setting. The default Channel-Specific Registers value uses a 2.0 V p-p reference. For more information on this function and others, see the AN-877 Application Note, Interfacing Some channel setup functions, such as the signal monitor to High Speed ADCs via SPI. This application note details the thresholds, can be programmed differently for each channel. In functions controlled by Register 0x00 to Register 0xFF. The these cases, channel address locations are internally duplicated for remaining register, Register 0x100, is documented in the Memory each channel. These registers and bits are designated in Table 17 Map Register Table section. as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. Open Locations If both bits are set, the subsequent write affects the registers of All address and bit locations that are not included in Table 17 both channels. In a read cycle, only Channel A or Channel B are not currently supported for this device. Unused bits of a should be set to read one of the two registers. If both bits are set valid address location should be written with 0s. Writing to these during an SPI read cycle, the part returns the value for Channel A. locations is required only when part of an address location is Registers and bits designated as global in Table 17 affect the entire open (for example, Address 0x18). If the entire address location part or the channel features for which independent settings are not is open (for example, Address 0x13), this address location should allowed between channels. The settings in Register 0x05 do not not be written. affect the global registers and bits. Default Values After the AD9268 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. Rev. A | Page 37 of 44 AD9268 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Default Default Address Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are mirrored so LSB-first (global) mode or MSB- first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit Chip ID[7:0] 0x32 Read only (AD9268 = 0x32) (global) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade ID used to (global) 01 = 125 MSPS differentiate 10 = 105 MSPS devices; read 11 = 80 MSPS only Channel Index and Transfer Registers 0x05 Channel Open Open Open Open Open Open Data Data 0x03 Bits are set index Channel Channel A to determine B which device (default) on the chip (default) receives the next write command; applies to local registers only 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Functions 0x08 Power modes 1 Open External Open Open Open Internal power-down 0x80 Determines power- mode (local) various generic (local) down pin modes of chip 00 = normal operation function operation 01 = full power-down (local) 10 = standby 0 = pdwn 11 = normal operation 1 = stndby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (global) (default) 0x0B Clock divide Open Open Open Open Open Clock divide ratio 0x00 Clock divide values other (global) 000 = divide by 1 than 000 001 = divide by 2 automatically 010 = divide by 3 cause the duty 011 = divide by 4 cycle stabilizer 100 = divide by 5 to become 101 = divide by 6 active 110 = divide by 7 111 = divide by 8 0x0D Test mode Open Open Reset PN Reset Open Output test mode 0x00 When this (local) long gen PN short register is set, 000 = off (default) gen the test data 001 = midscale short is placed on 010 = positive FS the output 011 = negative FS pins in place of 100 = alternating checkerboard normal data 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle Rev. A | Page 38 of 44 AD9268 Default Default Address Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST 0x04 sequence enable (global) 0x0F ADC input Open Open Open Open Open Open Open Common- 0x00 (global) mode servo enable 0x10 Offset adjust Offset adjust in LSBs from +127 to −128 0x00 (twos complement format) (local) 0x14 Output mode Drive Output CMOS Output Open Output Output format 0x00 Configures the strength type output enable (must be invert outputs and 00 = offset binary bar written (local) the format of 0 = ANSI 0 = CMOS interleave 01 = twos (local) low) the data LVDS; 1 = LVDS enable complement 1 = (global) (global) 01 = gray code reduced 11 = offset binary swing (local) LVDS (global) 0x16 Clock phase Invert Open Open Open Open Input clock divider phase adjust 0x00 Allows control DCO clock selection of 000 = no delay (global) clock delays 001 = 1 input clock cycle into the input 010 = 2 input clock cycles clock divider 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 DCO output Open Open Open DCO clock delay 0x00 delay (global) (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps … 11110 = 2419 ps 11111 = 2500 ps 0x18 VREF select Reference voltage Open Open Open Open Open Open 0xC0 selection (global) 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) 0x24 BIST signature BIST signature[7:0] 0x00 Read only LSB (local) 0x25 BIST signature BIST signature[15:8] 0x00 Read only MSB (local) 0x30 Dither enable Open Open Open Dither Open Open Open Open 0x00 (local) enable Digital Feature Control 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x00 divider divider sync (global) next sync sync enable only enable Rev. A | Page 39 of 44 AD9268 ignore the rest. The clock divider sync enable bit (Address 0x100, MEMORY MAP REGISTER DESCRIPTIONS Bit 1) resets after it syncs. For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Bit 1—Clock Divider Sync Enable Interfacing to High Speed ADCs via SPI. Bit 1 gates the sync pulse to the clock divider. The sync signal is Sync Control (Register 0x100) enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bits[7:3]—Reserved Bit 0—Master Sync Enable Bit 2—Clock Divider Next Sync Only Bit 0 must be high to enable any of the sync functions. If the If the master sync enable bit (Address 0x100, Bit 0) and the clock sync capability is not used this bit should remain low to divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows conserve power. the clock divider to sync to the first sync pulse it receives and to Rev. A | Page 40 of 44 AD9268 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting design and layout of the AD9268 as a system, the bottom of the PCB. These vias should be filled or plugged to it is recommended that the designer become familiar with these prevent solder wicking through the vias, which can compromise guidelines, which discuss the special circuit connections and the connection. layout requirements that are needed for certain pins. To maximize the coverage and adhesion between the ADC and Power and Ground Recommendations the PCB, a silkscreen should be overlaid to partition the continuous When connecting power to the AD9268, it is recommended that plane on the PCB into several uniform sections. This provides two separate 1.8 V supplies be used. Use one supply for analog several tie points between the ADC and the PCB during the reflow (AVDD); use a separate supply for the digital outputs (DRVDD). process. Using one continuous plane with no partitions guarantees For both AVDD and DRVDD several different decoupling capa- only one tie point between the ADC and the PCB. For detailed citors should be used to cover both high and low frequencies. information about packaging and PCB layout of chip scale Place these capacitors close to the point of entry at the PCB packages, see the AN-772 Application Note, A Design and level and close to the pins of the part, with minimal trace length. Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. A single PCB ground plane should be sufficient when using the AD9268. With proper decoupling and smart partitioning of the VCM PCB analog, digital, and clock sections, optimum performance The VCM pin should be decoupled to ground with a 0.1 μF is easily achieved. capacitor, as shown in Figure 67. LVDS Operation RBIAS The AD9268 defaults to CMOS output mode on power-up. The AD9268 requires that a 10 kΩ resistor be placed between If LVDS operation is desired, this mode must be programmed, the RBIAS pin and ground. This resistor sets the master current using the SPI configuration registers after power-up. When the reference of the ADC core and should have at least a 1% tolerance. AD9268 powers up in CMOS mode with LVDS termination Reference Decoupling resistors (100 Ω) on the outputs, the DRVDD current can be The VREF pin should be externally decoupled to ground with higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF to the AD9268, but it should be taken into account when consid- ceramic capacitor. ering the maximum DRVDD current for the part. SPI Port To avoid this additional DRVDD current, the AD9268 outputs The SPI port should not be active during periods when the full can be disabled at power-up by taking the OEB pin high. After dynamic performance of the converter is required. Because the the part is placed in LVDS mode via the SPI port, the OEB pin SCLK, CSB, and SDIO signals are typically asynchronous to the can be taken low to enable the outputs. ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, Exposed Paddle Thermal Heat Slug Recommendations it may be necessary to provide buffers between this bus and the It is mandatory that the exposed paddle on the underside of the AD9268 to keep these signals from transitioning at the converter ADC be connected to analog ground (AGND) to achieve the inputs during critical sampling periods. best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9268 exposed paddle, Pin 0. Rev. A | Page 41 of 44 AD9268 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 64 49 1 48 PIN 1 INDICATOR 0.50 7.65 8.75 TOP VIEW BSC EXPOSED PAD 7.50 SQ BSC SQ (BOTTOM VIEW) 7.35 0.50 16 33 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9268BCPZ-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268BCPZRL7-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268BCPZRL7-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268BCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268BCPZRL7-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 1 AD9268-80EBZ Evaluation Board 1 AD9268-105EBZ Evaluation Board 1 AD9268-125EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 42 of 44 041509-A AD9268 NOTES Rev. A | Page 43 of 44 AD9268 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08123-0-9/09(A) Rev. A | Page 44 of 44