ANALOG DEVICES AD9267

10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWNB PDWNA DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: −88 dBc to 10 MHz input OR±A VIN+A Noise figure: 15 dB D3±A Σ-Δ Input impedance: 1 kΩ MODULATOR VIN–A D0±A Power: 416 mW PLL_LOCKED 10 MHz real or 20 MHz complex bandwidth PLLMULT4 AD9267 PLLMULT3 1.8 V analog supply operation PLLMULT2 On-chip PLL clock multiplier CLK+ PHASE- On-chip voltage reference VREF LOCKED CLK– LOOP Twos complement data format CFILT DCO± 640 MSPS, 4-bit LVDS data output VIN–B D3±B Serial control interface (SPI) Σ-Δ MODULATOR VIN+B D0±B APPLICATIONS SERIAL OR±B Baseband quadrature receivers: CDMA2000, W-CDMA, INTERFACE multicarrier GSM/EDGE, 802.16x, and LTE Quadrature sampling instrumentation AGND SDIO/ SCLK/ CSB DGND PLLMULT1 PLLMULT0 GENERAL DESCRIPTION Figure 1. The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ) The AD9267 operates on a 1.8 V power supply, consuming modulator with −88 dBc of dynamic range over 10 MHz real 416 mW. The AD9267 is available in a 64-lead LFCSP and or 20 MHz complex bandwidth. The combination of high is specified over the industrial temperature range (−40°C dynamic range, wide bandwidth, and characteristics unique to +85°C). to the continuous time Σ-Δ modulator architecture makes the PRODUCT HIGHLIGHTS AD9267 an ideal solution for wireless communication systems. 1. Continuous time Σ-Δ architecture efficiently achieves high The AD9267 has a resistive input impedance that significantly dynamic range and wide bandwidth. relaxes the requirements of the driver amplifier. In addition, a 2. Passive input structure reduces or eliminates the require- 32× oversampled fifth-order continuous time loop filter attenuates ments for a driver amplifier. out-of-band signals and aliases, reducing the need for external 3. An oversampling ratio of 32× and high order loop filter filters at the input. The low noise figure of 15 dB relaxes the provide excellent alias rejection, reducing or eliminating linearity requirements of the front-end signal chain components, the need for antialiasing filters. and the high dynamic range reduces the need for an automatic 4. Operates from a single 1.8 V power supply. gain control (AGC) loop. 5. A standard serial port interface (SPI) supports various A differential input clock controls all internal conversion cycles. product features and functions. An external clock input or the integrated integer-N PLL provides 6. Features a low pin count, high speed LVDS interface with the 640 MHz internal clock needed for the oversampled conti- data output clock. nuous time Σ-Δ modulator. The digital output data is presented as 4-bit, LVDS at 640 MSPS in twos complement format. A data clock output (DCO) is provided to ensure proper latch timing with receiving logic. Additional digital signal processing may be required on the 4-bit modulator output to remove the out-of-band noise and to reduce the sample rate. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. LVDS LVDS DRIVERS DRIVERS 07773-001 AD9267 TABLE OF CONTENTS Features .............................................................................................. 1  Equivalent Circuits ......................................................................... 12  Applications ....................................................................................... 1  Theory of Operation ...................................................................... 13  General Description ......................................................................... 1  Analog Input Considerations ................................................... 13  Functional Block Diagram .............................................................. 1  Clock Input Considerations ...................................................... 14  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 17  Revision History ............................................................................... 2  Digital Outputs ........................................................................... 17  Specif ica t ions ..................................................................................... 3  Timing ......................................................................................... 18  DC Specifications ......................................................................... 3  Serial Port Interface (SPI) .............................................................. 19  AC Specifications .......................................................................... 4  Configuration Using the SPI ..................................................... 19  Digital Specifications ................................................................... 5  Hardware Interface ..................................................................... 20  Switching Specifications .............................................................. 6  Applications Information .............................................................. 21  Absolute Maximum Ratings ............................................................ 7  Filtering Requirement ................................................................ 21  Thermal Resistance ...................................................................... 7  Memory Map .................................................................................. 23  ESD Caution .................................................................................. 7  Memory Map Definitions ......................................................... 23  Pin Configuration and Function Descriptions ............................. 8  Outline Dimensions ....................................................................... 24  Typical Performance Characteristics ............................................. 9  Ordering Guide .......................................................................... 24  REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD9267 SPECIFICATIONS DC SPECIFICATIONS 1 All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 1. Parameter Temp Min Typ Max Unit RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±2.5 % FSR 2 Integral Nonlinearity (INL) 25°C ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.035 ±0.2 % FSR Gain Error Full ±0.2 ±1.2 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±47 ppm/°C INTERNAL VOLTAGE REFERENCE Full 496 500 505 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Input Resistance Full 1 kΩ Input Common Mode Full 1.7 1.8 1.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current 2 IAVDD , PLL Enabled Full 150.7 162 mA 2 IAVDD , PLL Disabled Full 151.2 161 mA 2 I , PLL Enabled Full 57 63 mA CVDD 2 I , PLL Disabled Full 8 9.2 mA CVDD 2 IDVDD Full 71.5 78 mA 2 IDRVDD Full 0.26 0.3 mA POWER CONSUMPTION 2 Sine Wave Input , PLL Disabled Full 416 mW Sine Wave Input, PLL Enabled Full 503 mW Power-Down Power 25°C 110 mW Standby Power 25°C 9 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave with approximately 5 pF loading on each output bit. Rev. 0 | Page 3 of 24 AD9267 AC SPECIFICATIONS 1 All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 2. 2 Parameter Temp Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 81 83 dB fIN = 4.2 MHz 25°C 83 dB fIN = 8.4 MHz 25°C 83 dB 3 SPURIOUS-FREE DYNAMIC RANGE (WORST SECOND OR THIRD HARMONIC) fIN = 2.4 MHz Full −88 −80 dBc f = 4.2 MHz 25°C −88 dBc IN f = 8.4 MHz 25°C <−120 dBc IN NOISE SPECTRAL DENSITY AIN = −2 dBFS Full −155 −153 dBFS/Hz AIN = −40 dBFS Full −156 −155 dBFS/Hz 2, 4 NOISE FIGURE AIN = −2 dBFS 25°C 16 dB AIN = −40 dBFS 25°C 15 dB TWO-TONE SFDR f = 1.8 MHz @ −8 dBFS, f = 2.1 MHz @ −8 dBFS 25°C −89.5 dBc IN1 IN2 f = 3.7 MHz @ −8 dBFS, f = 4.2 MHz @ −8 dBFS 25°C −93 dBc IN1 IN2 fIN1 = 7.2 MHz @ −8 dBFS, fIN2 = 8.4 MHz @ −8 dBFS 25°C −87 dBc ANALOG INPUT BANDWIDTH 25°C 10 MHz 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 3 Spurious-free dynamic range excluding the second or third harmonic is limited by the FFT size, <−120 dBFS. 4 Noise figure with respect to 50 Ω. AD9267 internal impedance is 1000 Ω differential. See the AN-835 for a definition. Rev. 0 | Page 4 of 24 AD9267 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) 1 Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage Full 0.4 0.8 2 V p-p Input Common-Mode Range Full 450 mV High Level Input Current Full −60 +60 μA Low Level Input Current Full −60 +60 μA Input Resistance Full 20 kΩ diff Input Capacitance Full 1 pF LOGIC INPUTS (SCLK) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO, CSB, RESET) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (D0±x to D3±x) ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Twos complement Low Power, Reduced Signal Option Logic Compliance LVDS Differential Output Voltage (V) Full 150 250 mV OD Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Twos complement 1 For voltage swings beyond the specified range, clamping diodes are recommended. Rev. 0 | Page 5 of 24 AD9267 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 4. 1 Parameter Conditions/Comments Temp Min Typ Max Unit CLOCK INPUT PARAMETERS Using clock multiplier Input CLK Rate Full 30 160 MSPS CLK± Period Full 6.25 33.3 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT PARAMETERS Direct clocking Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.48 1.5625 1.72 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS 2 Data Propagation Delay (t ) Full 160 510 840 ps PD DCO± Propagation Delay (t) Full DCO -60 268 570 ps DCO± to Data Skew (t) Full SKEW 180 200 280 Ps Aperture Uncertainty (Jitter, tJ) Full 1 ps rms WAKE-UP TIME Power-Down Power 25°C 3 Μs Standby Power 25°C 9 μs Sleep Power 25°C 15 μs OUT-OF-RANGE RECOVERY TIME 25°C 100 ns 3 SERIAL PORT INTERFACE SCLK Period (t) Full SCLK 40 ns SCLK Pulse Width High Time (tSHIGH) Full 16 ns SCLK Pulse Width Low Time (tSLOW) Full 16 ns SDIO to SCLK Set-Up Time (tSDS) Full 5 ns SDIO to SCLK Hold Time (t) Full SDH 2 ns CSB to SCLK Set-Up Time (t ) Full 5 ns SS CSB to SCLK Hold Time (t ) Full 2 ns SH 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK± 50% transition to data D0±x to D3±x 50% transition, with 5 pF load. 3 See Figure 42 and the Serial Port Interface (SPI) section. Timing Diagram CLK± t DCO DCO± t t PD SKEW D0±x TO D3±x Figure 2. Timing Diagram Rev. 0 | Page 6 of 24 07773-057 AD9267 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DVDD to DGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect DRVDD to DGND −0.3 V to +3.9 V device reliability. AGND to DGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V THERMAL RESISTANCE CVDD to CGND −0.3 V to +2.0 V The exposed paddle must be soldered to the ground plane for CGND to DGND −0.3 V to +0.3 V the LFCSP package. Soldering the exposed paddle to the PCB D0±A to D3±A to DGND −0.3 V to +2.0 V increases the reliability of the solder joints, maximizing the D0±B to D3±B to DGND −0.3 V to +2.0 V thermal capability of the package. DCO± to DGND −0.3 V to +2.0 V Typical θJA and θJC are specified for a 4-layer board in still air. OR±A, OR±B to DGND −0.3 V to +2.0 V Airflow increases heat dissipation, effectively reducing θJA. In PDWNA to DGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from PDWNB to DGND −0.3 V to +3.9 V metal traces, through holes, ground, and power planes reduces PLLMULTx to DGND −0.3 V to +3.9 V the θ . JA SDIO to DGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V Table 6. Thermal Resistance SCLK to AGND −0.3 V to +3.9 V Package Type θ Unit JA VIN±A, VIN±B to AGND −0.3 V to +2.5 V 64-Lead LFCSP (CP-64-4) 22 °C/W CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C ESD CAUTION Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Rev. 0 | Page 7 of 24 AD9267 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK– 1 PIN 1 48 SCLK/PLLMULT0 INDICATOR CVDD 2 47 SDIO/PLLMULT1 PDWNA 3 46 PLLMULT2 PDWNB 4 45 PLLMULT3 PLL_LOCKED 5 44 PLLMULT4 AD9267 DVDD 6 43 DVDD DGND 7 42 DGND DRVDD 8 41 DRVDD TOP VIEW D0–B 9 40 D3+A (Not to Scale) D0+B 10 39 D3–A D1–B 11 38 D2+A 37 D2–A D1+B 12 36 D2–B 13 D1+A D2+B 14 35 D1–A D3–B 15 34 D0+A D3+B 16 33 D0–A NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Differential Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3, 4 PDWNA, PDWNB Power-Down Pins. Active high. 5 PLL_LOCKED PLL Lock Indicator. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply 9 to 16 D0−B, D0+B to D3−B, D3+B Channel B Differential LVDS Data Output Bits. D0+B is the LSB and D3+B is the MSB. 17, 18 OR−B, OR+B Channel B Overrange Indicator Pins. 19, 20 DCO−, DCO+ Differential Data Clock Output. 21, 22, 26 to 30 DNC Do Not Connect. 31, 32 OR−A, OR+A Channel A Overrange Indicator Pins. 33 to 40 D0−A, D0+A to D3−A, D3+A Channel A Differential LVDS Data Output Bits. D0+A is the LSB and D3+A is the MSB. 44, 45, 46 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 47 SDIO/PLLMULT1 Serial Port Interface Data Input/Output/PLL Mode Selection Pins. 48 SCLK/PLLMULT0 Serial Port Interface Clock/PLL Mode Selection Pins. 49 CSB Serial Port Interface Chip Select Pin Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53, 54 VIN+A, VIN−A Channel A Analog Input. 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59, 60 VIN+B, VIN−B Channel B Analog Input. 63 CGND Clock Ground. 64 CLK+ Differential Clock Input (+). 65 Exposed paddle (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed paddle must be soldered to analog ground of the PCB to achieve optimal electrical and thermal performance. Rev. 0 | Page 8 of 24 OR–B 64 CLK+ 17 CGND OR+B 18 63 DCO– 19 62 AGND DCO+ 20 61 AVDD DNC 21 60 VIN–B DNC 22 59 VIN+B DRVDD 23 58 AVDD DGND 24 57 CFILT DVDD 25 56 VREF DNC 26 55 AVDD DNC 27 54 VIN–A DNC 28 53 VIN+A 52 AVDD DNC 29 DNC 30 51 AGND OR–A 31 50 RESET OR+A 32 49 CSB 07773-003 AD9267 TYPICAL PERFORMANCE CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, TA = 25°C, unless otherwise noted. The output spectrums shown in Figure 4 through Figure 9 were obtained after 16× decimation at the output of the AD9267 and are shown for a 10 MHz bandwidth. 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 0 1 2 3 456 7 8 9 10 0 1 23 4 5 678 9 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Single-Tone FFT with fIN = 2.4 MHz Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2= 2.4 MHz 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 0 1 2 3 456 7 8 9 10 0 1 2 3 456 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Single-Tone FFT with fIN = 4.2 MHz Figure 8. Two-Tone FFT with fIN1 = 3.6 MHz, fIN2 = 4.2 MHz 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 0 1 2 3 456 7 8 9 10 0 1 2 3 456 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone FFT with fIN = 8.4 MHz Figure 9. Two-Tone FFT with fIN1 = 7.2 MHz, fIN2 = 8.4 MHz Rev. 0 | Page 9 of 24 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07773-006 07773-005 07773-004 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07773-011 07773-010 07773-009 AD9267 84.0 –50 83.8 –60 83.6 –70 83.4 –80 83.2 –90 83.0 82.8 –100 82.6 –110 82.4 –120 82.2 –130 82.0 0 50 100 150 200 250 300 0 1234 56789 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Noise Transfer Function (NTF) Figure 13. Single-Tone SNR vs. Input Frequency 120 84.0 83.8 SFDR 100 (dBFS) 83.6 83.4 80 SNR 83.2 (dBFS) SFDR 60 83.0 (dBc) SNR 82.8 (dB) 40 82.6 82.4 20 82.2 0 82.0 1.70 1.75 1.80 1.85 1.90 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) COMMON-MODE VOLTAGE (V) Figure 11. Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 2.4 MHz Figure 14. SNR vs. Input Common-Mode Voltage 83.4 91 83.2 90 83.0 89 1.9V 1.9V 82.8 88 87 82.6 1.8V 1.8V 86 82.4 85 82.2 1.7V 1.7V 84 82.0 81.8 83 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. SNR vs. Temperature Figure 12. SFDR vs. Temperature Rev. 0 | Page 10 of 24 SFDR (dBc) SNR/SFDR AMPLITUDE (dBFS) 07773-042 07773-012 07773-007 SNR (dB) SNR (dB) SNR (dB) 07773-044 07773-043 07773-013 AD9267 –40 84 –50 2.4MHz 83 –60 SFDR (dBc) 82 8.4MHz –70 –80 81 –90 80 SFDR (dBFS) –100 79 –110 78 –120 –60 –50 –40 –30 –20 –10 4.0 5.0 7.0 8.0 9.0 10.5 12.5 15.0 17.0 4.5 6.0 7.5 8.5 10.0 12.0 14.0 16.0 21.0 INPUT AMPLITUDE (dBFS) PLL DIVIDE RATIO Figure 16. Two-Tone SFDR vs. Input Amplitude with Figure 18. Single-Tone SNR vs. PLL Divide Ratio with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz f = 2.4 MHz, f = 8.4 MHz IN1 IN2 –40 0.5 –50 0 –60 –0.5 SFDR (dBc) –70 –1.0 –80 –1.5 –90 –2.0 –100 SFDR (dBFS) –2.5 –110 –120 –3.0 –60 –50 –40 –30 –20 –10 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 19. INL with f = 2.4 MHz Figure 17. Two-Tone SFDR vs. Input Amplitude with IN f = 7.2 MHz, f = 8.4 MHz IN1 IN2 Rev. 0 | Page 11 of 24 SFDR SFDR 07773-045 07773-046 INL ERROR (LSB) SNR (dB) 07773-047 07773-048 AD9267 EQUIVALENT CIRCUITS 1kΩ SCLK 30kΩ 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 20. Equivalent Analog Input Circuit Figure 23. Equivalent SCLK Input Circuit CVDD AVDD 26kΩ 1kΩ CSB CLK+ CLK– 10kΩ 10kΩ 90kΩ 30kΩ CVDD Figure 21. Equivalent Clock Input Circuit Figure 24. Equivalent CSB Input Circuit DRVDD V V D– D+ DRVDD V V 1kΩ SDIO DGND NOTES 1. D– AND D+ REFERS TO THE D0±x TO D3±x PINS. Figure 22. Equivalent SDIO Input Circuit Figure 25. Equivalent Digital Output Circuit 2.85kΩ 8.5kΩ 10kΩ 0.5V 3.5kΩ 10µF TO CURRENT GENERATOR Figure 26. Equivalent VREF Circuit Rev. 0 | Page 12 of 24 07773-015 07773-016 07773-014 07773-017 07773-019 07773-018 07773-020 AD9267 THEORY OF OPERATION The AD9267 uses a continuous time Σ-Δ modulator to convert In contrast, the continuous time Σ-Δ modulator used within the the analog input to a digital word. The modulator consists of a AD9267 has inherent antialiasing. The antialiasing property continuous time loop filter preceding a quantizer (see Figure 27), results from sampling occurring at the output of the loop filter which samples at fMOD = 640 MSPS. This produces an oversam- (see Figure 31), and thus aliasing occurs at the same point in the pling ratio (OSR) of 32 for a 10 MHz input bandwidth. The output loop as quantization noise is injected; aliases are shaped by the of the quantizer is fed back to a DAC that ideally cancels the same mechanism as quantization noise. The quantization noise input signal. The incomplete input cancellation residue is filtered transfer function, NTF(f), has zeros in the band of interest and by the loop filter and is used to form the next quantizer sample. in all alias bands because NTF(f) is a discrete time transfer MODULATOR function, whereas the loop filter transfer function, LF(f), introduces poles only in the band of interest because LF(f) is a LOOP FILTER QUANTIZER continuous time transfer function. The signal transfer function, + ADC H(f) being the product of NTF(f) and LF(f), only has zeros in all – alias bands and therefore suppresses all aliases. LF(f) LOOP FILTER INPUT Figure 27. Σ-Δ Modulator Overview LF(f) QUANTIZATION f MOD The quantizer produces a nine-level digital word. The quantiza- NOISE f MOD tion noise is spread uniformly over the Nyquist band (see OUTPUT Figure 28) but the feedback loop causes the quantization noise H(z) present in the nine-level output to have a nonuniform spectral NTF(f) shape. This noise shaping technique (see Figure 29) pushes the in-band noise out of band; therefore, the amount of quantiza- f tion noise in the frequency band of interest is minimal. f MOD Figure 31. Continuous Time Converter Input Common Mode QUANTIZATION NOISE The analog inputs of the AD9267 are not internally dc biased. In ac-coupled applications, the user must provide this bias f /2 MOD BAND OF INTEREST externally. Setting the device such that V = AVDD is CM Figure 28. Quantization Noise recommended for optimum performance. The analog inputs are 500 Ω resistors and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 32). With 0 V differential input, the driver sources 1 mA into each analog input. NOISE SHAPING 2.3V AVDD – 0.5V 1.8V 1.3V f /2 MOD 500Ω BAND OF INTEREST VIN+x TO LOOP FILTER Figure 29. Noise Shaping STAGE 2 VIN–x ANALOG INPUT CONSIDERATIONS 500Ω 2.3V 1.8V The continuous time modulator removes the need for an anti- 1.3V DAC alias filter at the input to the AD9267. A discrete time converter aliases signals around the sample clock frequency and its FROM QUANTIZER multiples to the band of interest (see Figure 30). An external Figure 32. Input Common Mode antialias filter is needed to reject these signals. DESIRED UNDESIRED INPUT SIGNAL f f /2 S S ADC Figure 30. Discrete Time Converter Rev. 0 | Page 13 of 24 DAC 07773-021 07773-024 07773-023 07773-022 07773-025 07773-026 AD9267 AVDD – 0.5V Differential Input Configurations V =AVDD Optimum performance can be achieved by driving the AD9267 CM V p-p = 2V 500Ω IN VIN+x in a differential input configuration. The ADA4937-2 differential 500Ω driver provides excellent performance and a flexible interface to 0.5V VIN–x TO LOOP VREF the ADC. The output common-mode voltage of the ADA4937-2 is 10kΩ FILTER REF AVDD STAGE 2 easily set by connecting AVDD to the V pin of the ADA4937-2 OCMx 10µF AVDD – 0.5V 500Ω (see Figure 33). The noise and linearity of the ADA4937-2 needs important consideration because the system performance may be limited by the ADA4937-2. +5V +1.8V CFILT 10µF 0.1µF 0.1µF Figure 35. Voltage Reference Loop 200Ω Internal Reference Connection 9 2V p-p 50Ω 200Ω 6 13 VIN–x AVDD To minimize thermal noise, the internal reference on the AD9267 V OCM2 11 ADA4937-2 AD9267 V R is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor, S T 7 60.4 12 VIN+x which, when externally decoupled with a 10 μF capacitor, limits SIGNAL 15 SOURCE the noise (see Figure 36). Do not use the unbuffered reference 200Ω to drive any external circuitry. The internal reference is used by 49.9Ω 60.4Ω 0.1µF default and when Serial Register 0x18[6] is reset. 0.1µF –5V Figure 33. Differential Input Configuration Using the ADA4937-2 For frequencies offset from dc, where SNR is a key parameter, 2.85kΩ 8.5kΩ differential transformer coupling is the recommended input 10kΩ 0.5V configuration. An example is shown in Figure 34. The center 10µF 3.5kΩ tap of the secondary winding of the transformer is connected to AVDD to bias the analog input. TO CURRENT GENERATOR The signal characteristics must be considered when selecting a Figure 36. Internal Reference Configuration transformer. Most RF transformers saturate at frequencies External Reference Operation below a couple of megahertz (MHz), and excessive signal power can cause core saturation, which leads to distortion. If an external reference is desired, the internal reference can be disabled by setting Serial Register 0x18[6] high. Figure 37 shows 50Ω 2V p-p VIN+x 1:1 an application using the ADR130B as a stable external reference. R T V 0.5V AD9267 S 50Ω AVDD ADR130B 10kΩ 0.1µF 10µF SIGNAL VIN–x SOURCE AVDD TO CURRENT 0.1µF GENERATOR Figure 37. External Reference Configuration Figure 34. Differential Transformer Configuration CLOCK INPUT CONSIDERATIONS Voltage Reference The AD9267 offers two modes of sourcing the ADC sample A stable and accurate 0.5 V voltage reference is built into the clock (CLK+ and CLK−). The first mode uses an on-chip clock AD9267. The reference voltage should be decoupled to minim- multiplier that accepts a reference clock operating at the lower ize the noise bandwidth using a 10 μF capacitor. The reference input frequency. The on-chip phase-locked loop (PLL) then is used to generate a bias current into a matched resistor such multiplies the reference clock up to a higher frequency, which is that when used to bias the current in the feedback DAC, a then used to generate all the internal clocks required by the Σ-Δ voltage of AVDD − 0.5 V is developed at the internal side of the modulator. input resistors (see Figure 35). The current bias circuit should also be decoupled on the CFILT pin with a 10 μF capacitor. For The clock multiplier provides a high quality clock that meets this reason, the VREF voltage should always be 0.5 V. the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed clock. Rev. 0 | Page 14 of 24 07773-028 07773-027 07773-030 07773-031 07773-029 AD9267 The second mode bypasses the clock multiplier circuitry and If a differential clock is not available, the AD9267 can be driven allows the clock to be directly sourced. This mode enables the by a single-ended signal into the CLK+ terminal with the CLK− user to source a very high quality clock directly to the Σ-Δ terminal ac-coupled to ground. Figure 39 shows the circuit configuration. modulator. Sourcing the clock directly may be necessary in demanding applications that require the lowest possible output noise. Refer to Figure 18, which shows the degradation in SNR 0.1µF performance for the various PLL settings. CLK+ CLOCK INPUT ADC In either case, when using the on-chip clock multiplier or AD9267 50Ω CLK– sourcing the high speed clock directly, it is necessary that the SCHOTTKY clock source have low jitter to maximize the Σ-Δ modulator DIODES: 0.1µF HSM2812 noise performance. High speed, high resolution ADCs and modulators are sensitive to the quality of the clock input. As Figure 39. Single-Ended Clock jitter increases, the SNR performance of the AD9267 degrades Another option is to ac couple a differential LVPECL signal to from that specified in Table 2. The jitter inherent to the part due the sample clock input pins, as shown in Figure 40. The AD951x to the PLL root sum squares with any external clock jitter, family of clock drivers is recommended because it offers excellent thereby degrading performance. To prevent jitter from dominating jitter performance. the performance of the AD9267, the input clock source should be no greater than 1 ps rms of jitter. The CLK± inputs are self-biased to 450 mV (see Figure 21); if 0.1µF 0.1µF CLK+ CLOCK CLK dc-coupled, it is important to maintain the specified 450 mV INPUT ADC AD951x LVPECL 100Ω AD9267 input common-mode voltage. Each input pin can safely swing CLK– DRIVER CLOCK from 200 mV p-p to 1 V p-p single-ended about the 450 mV INPUT CLK 0.1µF 0.1µF 240Ω 240Ω common-mode voltage. The recommended clock inputs are 1 1 50Ω 50Ω CMOS or LVPECL. The specified clock rate of the Σ-Δ modulator, f , is 640 MHz. MOD 1 50Ω RESISTORS ARE OPTIONAL. The clock rate possesses a direct relationship with the available Figure 40. Differential LVPECL Sample Clock input bandwidth of the ADC. Internal PLL Clock Distribution Bandwidth = fMOD ÷ 64 The alternative clocking option available on the AD9267 is to In either case, using the on-chip clock multiplier to generate the apply a low frequency reference clock and use the on-chip clock Σ-Δ modulator clock rate or directly sourcing the clock, any multiplier to generate the high frequency fMOD rate. The internal deviation from 640 MHz results in a change in input bandwidth. clock architecture is shown in Figure 41. The input range of the clock is limited to 640 MHz ± 5%. CLK± Direct Clocking PHASE LOOP VCO DETECTOR FILTER The default configuration of the AD9267 is for direct clocking PLL where the PLL is bypassed. Figure 38 shows one preferred DIVIDER method for clocking the AD9267. A low jitter clock source is ÷N converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes PLLMULT ÷2 MODULATOR 0x0A[5:0] across the secondary side of the transformer limits clock CLOCK 640MSPS excursions into the AD9267 to approximately 0.8 V p-p differen- tial. This helps prevent the large voltage swings of the clock PLLENABLE 0x09[2] from feeding through to other portions of the AD9267 while preserving the fast rise and fall times of the signal, which are Figure 41. Internal Clock Architecture critical to achieving low jitter. The clock multiplication circuit operates such that the VCO outputs a frequency, f , equal to the reference clock input VCO MINI-CIRCUITS TC1-1-13M+, 1:1 multiplied by N 0.1µF 0.1µF CLOCK XFMR CLK+ INPUT ADC fVCO = (CLK±) × (N) AD9267 50Ω 0.1µF CLK– where N is the PLL multiplication (PLLMULT) factor. SCHOTTKY The Σ-Δ modulator clock frequency, fMOD, is equal to DIODES: 0.1µF HSM2812 f = f ÷ 2 MOD VCO Figure 38. Transformer-Coupled Differential Clock Rev. 0 | Page 15 of 24 07773-053 07773-054 07773-040 07773-055 AD9267 The reference clock, CLK±, is limited to 30 MHz to 160 MHz Table 8. PLL Multiplication Factors when configured to use the on-chip clock multiplier. Given the 0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N) input range of the reference clock and the available multiplica- 1 8 33 32 tion factors, the fVCO is approximately 1280 MHz. This results in 2 8 34 34 the desired fMOD rate of 640 MHz with a 50% duty cycle. 3 8 35 34 4 8 36 34 The PLL of the AD9267 can be controlled through either the serial 5 8 37 34 port interface or the PLLMULTx pins. For serial port interface 6 8 38 34 control, Register 0x09 and Register 0x0A are used. Before the 7 8 39 34 PLL enable register bit (PLLENABLE) is set, the PLL multiplica- 8 8 40 34 tion factor should be programmed into Register 0x0A[5:0]. 9 9 41 34 After setting the PLLENABLE bit, the PLL locks and reports a 10 10 42 42 locked state in Register 0x0A[7]. If the PLL multiplication factor 11 10 43 42 is changed, the PLL enable bit should be reset and set again. 12 12 44 42 Some common clock multiplication factors are shown in Table 8. 13 12 45 42 The recommended sequence for enabling and programming the 14 14 46 42 on-chip clock multiplier is as follows: 15 15 47 42 1. Apply a reference clock to the CLK± pins. 16 16 48 42 2. Program the PLL multiplication factor in 17 17 49 42 Register 0x0A[5:0]. See Table 8. 18 18 50 42 3. Enable the PLL; Register 0x09 = 04 (decimal). 19 18 51 42 20 20 52 42 External PLL Control 21 21 53 42 At power-up, the serial interface is disabled until the first serial 22 21 54 42 port access. If the serial interface is disabled, the PLLMULTx 23 21 55 42 pins control the PLL multiplication factor. The five PLLMULTx 24 24 56 42 pins (Pin 44 to Pin 48) offer all the available multiplication 25 25 57 42 factors. If all PLLMULTx pins are tied high, the PLL is disabled 26 25 58 42 and the AD9267 assumes the high frequency modulator clock 27 25 59 42 rate that is applied to the CLK± pins. Table 10 shows the relation- 28 28 60 42 ship between PLLMULTx pins and the PLL multiplication factor. 29 28 61 42 PLL Autoband Select 30 30 62 42 31 30 63 42 The PLL VCO has a wide operating range that is covered by 32 32 64 42 overlapping frequency bands. For any desired VCO output fre- quency, there are multiple valid PLL band select values. The AD9267 possesses an automatic PLL band select feature on chip Table 9. Common Modulator Clock Multiplication Factors that determines the optimal PLL band setting. This feature can CLK± 0x0A[5:0] fVCO fMOD BW be enabled by writing to Register 0x0A[6] and is the recom- (MHz) (PLLMULT) (MHz) (MHz) (MHz) mended configuration with the PLL clocking option. 30.72 42 1290.24 645.12 10.08 39.3216 32 1258.29 629.15 9.83 52.00 25 1300.00 650.00 10.16 61.44 21 1290.24 645.12 10.08 76.80 17 1305.60 652.80 10.20 78.00 17 1326.00 663.00 10.36 78.6432 16 1258.29 629.15 9.83 89.60 15 1344.00 672.00 10.50 92.16 14 1290.24 645.12 10.08 122.88 10 1228.80 614.40 9.60 134.40 10 1344.00 672.00 10.50 153.60 8 1228.80 614.40 9.60 157.2864 8 1258.29 629.15 9.83 Rev. 0 | Page 16 of 24 AD9267 Table 10. PLLMULTx Pins and PLL Multiplication Factor DIGITAL OUTPUTS PLLMULT[4:0] Pins PLL Multiplication Factors (N) Digital Output Format 0 8 The AD9267 digital bus outputs twos complement, single data 1 9 rate, LVDS data at 640 MSPS. The output is four bits wide per 2 10 channel. 3 12 The AD9267 supports both the ANSI-644 and a reduced power 4 14 data format similar to the IEEE1596.3 standard. The default 5 15 configuration at power-up is ANSI-644. This can be changed to 6 16 a low power reduced signal option by addressing Register 7 17 0x14[7], DRVSTD. 8 18 9 20 The LVDS driver current is derived on chip and sets the output 10 21 current at each output equal to a nominal 3.5 mA for the ANSI- 11 24 644 standard. A 100 Ω differential termination resistor placed at 12 25 the LVDS receiver inputs result in a nominal 350 mV swing at 13 28 the receiver. In the reduced power data format, the output swing 14 30 is limited to 200 mV and the resulting output current into the 15 32 100 Ω termination is 2 mA. As a result of the reduced LVDS 16 34 voltage swing, an additional 25% digital power savings can be 17 to 30 42 achieved over the ANSI-644 standard. 31 Direct clocking The desired output format can be selected by addressing Register 0x14[7], DRVSTD. The LVDSTERM bits, Register POWER DISSIPATION AND STANDBY MODE 0x15[5:4], provide either 100 Ω or 200 Ω, or no termination The AD9267 consumes 415 mW. This power consumption can at the output of the data bus. Selecting the appropriate termina- be further reduced by configuring the chip in channel power- tion resistor is important to allow maximum signal transfer and down, standby, or sleep mode. The low power modes turn off to minimize reflections for signal integrity. This can be achieved internal blocks of the chip including the reference. As a result, by selecting a termination resistor that impedance matches the the wake-up time is dependent on the amount of circuitry that termination of the receiver. is turned off. Fewer internal circuits powered down result in Overrange (OR) Condition proportionally shorter wake-up time. The different low power modes are shown in Table 11. In the standby mode, all clock An overrange condition can be triggered by large in-band signals related activity is disabled in addition to each channel; the that exceed the full-scale range of the Σ-Δ modulator, or it references and LVDS outputs remain powered up to ensure a can be triggered by out-of-band signals gained by the transfer short recovery and link integrity, respectively. During sleep characteristics of the modulator. Figure 43 shows the signal mode, all internal circuits are powered down, putting the device transfer function of the Σ-Δ modulator. The modulator output into its lowest power mode; the LVDS outputs are disabled. possesses out-of-band gain above 10 MHz. As a result, the input signal may exceed full scale for input frequencies beyond 10 MHz Each ADC channel can be independently powered down or and the ADC may be in an overrange state. The OR±x pins both channels can be set simultaneously by writing to the serve as indicators for the overrange condition. channel index, Register 0x05[1:0]. Additionally, if the serial port interface is not available, each channel can be indepen- The OR±x pins are synchronous outputs that are updated at the dently configured by tying the PDWNA (Pin 3) or PDWNB output data rate. The pins indicate whether an overrange condi- (Pin 4) high. tion has occurred within the AD9267. Ideally, OR±x should be latched on the falling edge of DCO± to ensure proper setup-and- Table 11. Low Power Modes hold time. However, because an overrange condition typically Analog extends well beyond one clock cycle (that is, does not toggle at Mode 0x08[1:0] Circuitry Clock Ref. the DCO± rate); data can usually be successfully detected on Normal 0x0 On On On the rising edge of DCO± or monitored asynchronously. The Channel Power-Down 0x1 Off On On user has the ability to select how the overrange condition is Standby 0x2 Off Off On reported and this is controlled through the SPI bits (AUTORST, Sleep 0x3 Off Off Off OR_IND1, and OR_IND2) in Register 0x111[7:5]. The two modes of operation are normal and data valid mode. Rev. 0 | Page 17 of 24 AD9267 In normal operation mode, the analog input can toggle the cycles where OR±x remains high or if the loop filter becomes OR±x pin for a number of clock cycles as it approaches full saturated. The OR±x pin remains high until the automatic reset scale. The OR±x pin is a pulse-width modulated (PWM) signal; has completed. therefore, as the analog input increases in amplitude, the If the AD9267 is used in a system that incorporates automatic duration of OR±x pin toggling increases. Eventually, when the gain control (AGC), the OR±x signals can be used to indicate OR±x pin is high for an extended period of time, the ADC that the signal amplitude should be reduced. This may be overloads; thus, there is little correspondence between analog particularly effective for use in maximizing the signal dynamic input and digital output. In this mode, the duration of the range if the signal includes high occurrence components that OR±x pin can be used as a coarse indicator to the signal occasionally exceed full scale by a small amount. amplitude at the input of the ADC. In data valid mode, the TIMING OR±x pin remains high when there are no memory access operations taking place, such as internal calibration or factory The AD9267 provides latched data outputs with a latency of memory transfer, and the inputs of the ADC are within the seven clock cycles. The AD9267 also provides a data clock operating range. output (DCO±) pin intended to assist in capturing the data in an external register. The data outputs are valid on the rising In either modes of operation, the AUTORST bit can be enabled edge of DCO±, unless changed by setting Serial Register 0x16[7] and this automatically resets the modulator in an overload (see the Serial Port Interface (SPI) section). See Figure 2 for a condition. Because the OR±x signal is a PWM signal and the graphical timing description. toggling of OR±x does not always indicate an overload condition, the modulator only resets after 16 consecutive clock Table 12. OR±x Conditions Reset State AUTORST OR_IND1 OR_IND2 Function Normal Reset Off 0 0 0 If overrange: OR±x = 1, else OR±x = 0 Data Valid Reset Off 0 1 1 If memory access: OR±x = 0, else OR±x = 1 Normal Reset On 1 0 0 If overrange or reset: OR±x = 1, else OR±x = 0 Data Valid Reset On 1 1 1 If memory access, or reset: OR±x = 0, else OR±x = 1 Rev. 0 | Page 18 of 24 AD9267 SERIAL PORT INTERFACE (SPI) additional external timing. When CSB is tied high, SPI The AD9267 serial port interface (SPI) allows the user to functions are placed in a high impedance mode. configure the converter for specific functions or operations through a structured register space provided inside the ADC. During an instruction phase, a 16-bit instruction is transmitted. This provides the user added flexibility and customization Data follows the instruction phase and the length is determined depending on the application. Addresses are accessed via the by the W0 bit and the W1 bit. All data is composed of 8-bit words. serial port and can be written to or read from via the port. The first bit of each individual byte of serial data indicates whether Memory is organized into bytes that are further divided into a read or write command is issued. This allows the serial data fields, as documented in the Memory Map section. For detailed input/output (SDIO) pin to change direction from an input to operational information, see the see the AN-877 Application an output. Note, Interfacing to High Speed ADCs via SPI. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial CONFIGURATION USING THE SPI port to be used to both program the chip as well as to read the As summarized in Table 13, three pins define the SPI of this contents of the on-chip memory. If the instruction is a readback ADC. The SCLK pin synchronizes the read and write data operation, performing a readback causes the serial data input/ presented to the ADC. The SDIO pin allows data to be sent and output (SDIO) pin to change direction from an input to an read from the internal ADC memory map registers. The CSB output at the appropriate point in the serial frame. pin is an active low control that enables or disables the read and write cycles. Data can be sent in MSB- or in LSB-first mode. MSB first is the default setting on power-up and can be changed via the Table 13. Serial Port Interface Pins configuration register. For more information, see the AN-877 Pin Function Application Note, Interfacing to High Speed ADCs via SPI. SCLK SCLK (serial clock) is the serial shift clock. SCLK synchronizes serial interface reads and writes. Table 14. SPI Timing Diagram Specifications SDIO SDIO (serial data input/output) is an input and output Parameter Definition depending on the instruction being sent and the tSDS Setup time between data and rising edge of SCLK relative position in the timing frame. tSDH Hold time between data and rising edge of SCLK CSB CSB (chip select) is an active low control that gates the t Period of the clock SCLK read and write cycles. t Setup time between CSB and SCLK SS The falling edge of CSB in conjunction with the rising edge of t Hold time between CSB and SCLK SH the SCLK determines the start of the framing. Figure 42 and tSHIGH Minimum period that SCLK should be in a logic Table 14 provide an example of the serial timing and its high state definitions. tSLOW Minimum period that SCLK should be in a logic low state Other modes involving CSB are available. CSB can be held low indefinitely to permanently enable the device (this is called streaming). CSB can stall high between bytes to allow for t t SHIGH t t SDS SCLK SH t t SS SDH t SLOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 42. Serial Port Interface Timing Diagram Rev. 0 | Page 19 of 24 07773-036 AD9267 The SPI interface is flexible enough to be controlled by either HARDWARE INTERFACE PROM or PIC microcontrollers. This provides the user with the The pins described in Table 13 comprise the physical interface ability to use an alternate method to program the ADC. One between the programming device of the user and the serial port such method is described in detail in the AN-812 Application of the AD9267. The SCLK and CSB pins function as inputs Note, MicroController-Based Serial Port Interface (SPI) Boot when using the SPI interface. The SDIO pin is bidirectional, Circuit. functioning as an input during write phases and as an output during readback. When the SPI interface is not used, SCLK/PLLMULT0 and SDIO/PLLMULT1 serve a dual function. When strapped to AVDD or ground during device power-on, the pins are associated with a specific function. Rev. 0 | Page 20 of 24 AD9267 APPLICATIONS INFORMATION Figure 43 shows the gain profile of the AD9267 and this can be FILTERING REQUIREMENT interpreted as the level in which the signal power should be The need for anti-alias protection often requires one or two scaled back to prevent an overload condition. This is the octaves for a transition band, which reduces the usable ultimate trip point and before this point is reached, the in-band bandwidth of a Nyquist converter to between 25% and 50% of noise (IBN) slowly degrades. As a result, it is recommended that the available bandwidth. A CT Σ-Δ converter maximizes the the low-pass filter be designed to match the profile of Figure 44, available signal bandwidth by forgoing the need for an which shows the maximum input signal for a 3 dB degradation antialiasing filter because the architecture possesses inherent of in-band noise. The input signal is attenuated to allow only antialiasing. Although a high order, sharp cutoff antialiasing 3 dB of noise degradation over frequency. filter may not be necessary because of the unique characteristics The noise performance is normalized to a −2 dBFS in-band of the architecture, a low order filter may still be required to signal. The AD9267 STF and NTF are flat within the band of precede the ADC for out-of-band signal handling. interest and should result in almost no change in input level and Depending on the application and the system architecture, this IBN. Beyond the bandwidth of the AD9267, out-of-band low order filter may or may not be necessary. The signal peaking adds gain to the system, therefore requiring the input transfer function (STF) of a continuous time feedforward ADC power to be scaled back to prevent in-band noise degradation. usually contains out-of-band peaks. Because these STF peaks The input power is scaled back to a point where only 3 dB of are typically one or two octaves above the pass-band edge, they noise degradation is allowed, therefore resulting in Figure 44. are not problematic in applications where the bulk of the signal 5 energy is in or near the pass band. However, in applications with large far-out interferers, it is necessary to either add a filter 0 to attenuate these problematic signals or to allocate some of the ADC dynamic range to accommodate them. –5 –40°C Figure 43 shows the normalized STF of the AD9267 CT Σ-Δ –10 converter. The figure shows out-of-band peaking beyond the band edge of the ADC. Within the 10 MHz band of interest, the CHEBYSHEV II FILTER RESPONSE –15 STF is maximally flat with less than 0.1 dB of gain. Maximum +85°C peaking occurs at 60 MHz with 10 dB of gain. To put this into +25°C –20 perspective, for a fixed input power, a 5 MHz in-band-signal appears at −5 dBFS, a 25 MHz tone appears at −2 dBFS and –25 60 MHz tone at +5 dBFS. Because the maximum input to the 0 10 2030 405060 7080 90 100 ADC is −2 dBFS, large out-of-band signals can quickly saturate FREQUENCY (MHz) the system. This implies that under these conditions, the digital Figure 44. Maximum Input Level for 3 dB Noise Degradation outputs of the ADC no longer accurately represents the input. An example third-order low-pass Chebyshev II type filter is Refer to the Overrange (OR) Condition section for details on shown in Figure 45 and the corresponding magnitude vs. overrange detection and recovery. frequency response of the filter is shown in Figure 44. 15 L1 13 180nH 11 VIN+ 9 C2 390pF C1 C3 AD9267 7 1kΩ 39pF 220pF L1 CTΣ-Δ 180nH 5 VIN– 3 1 C2 390pF –1 Figure 45. Third-Order Low-Pass Chebyshev II Filter –3 –5 0 1020 3040 5060 708090 100 FREQUENCY (MHz) Figure 43. STF Rev. 0 | Page 21 of 24 GAIN (dB) 07773-049 AMPLITUDE (dB) 07773-052 07773-051 AD9267 0 40 Referring to Figure 46, the 3 dB cutoff frequency of the low- –2 30 pass Chebyshev II filter response resides at 15.75 MHz, and at 10 MHz, there is 0.43 dB of attenuation due to the sharp roll-off –4 20 of the filter. Table 15 summarizes the components and –6 10 manufacturers used to build the circuit. –8 0 –10 –10 Table 15. Chebyshev II Filter Components Parameter Value Unit Manufacturer –12 –20 C1 39 pF Murata GRM188 series, 0603 –14 –30 L1 180 nH Coil Craft 0402AF, 2% –16 –40 C2 390 pF Murata GRM188 series, 0603 –18 –50 C3 220 pF Murata GRM188 series, 0603 –20 –60 0 2 4 6 8 1012 14161820 FREQUENCY (MHz) Figure 46. Low-Pass Chebyshev II Filter Response In addition to matching the profile of Figure 44, group delay and channel matching are important filter design criteria. Low tolerance components are highly recommended for improved channel matching, which translates to minimal degradation in image rejection for quadrature systems. Rev. 0 | Page 22 of 24 AMPLITUDE (dB) GROUP DELAY (ns) 07773-050 AD9267 MEMORY MAP Table 16. Memory Map Register Address (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Port Config 00 0 LSBFIRST SOFTRESET 1 1 SOFTRESET LSBFIRST 0 Chip ID 01 CHIPID[7:0] Chip Grade 02 CHILDID[1:0] Channel Index 05 Channel[1:0] Power Modes 08 PWRDWN[1:0] PLLENABLE 09 PLLENABLE PLL 0A PLLLOCKED PLLAUTO PLLMULT[5:0] Output Modes 14 DRVSTD OUTENB Output Adjust 15 LVDSTERM[1:0] Output Clock 16 DCOINV Reference 18 EXTREF Overrange 111 AUTORST OR_IND1 OR_IND2 MEMORY MAP DEFINITIONS Table 17. Memory Map Definitions Register Address Bit Name Bit(s) Default Description SPI Port Config 0x00 LSBFIRST [6], [1] 0 0: serial interface uses MSB-first format 1: serial interface uses LSB-first format SOFTRESET [5], [2] 0 1: default all serial registers except 0x00, 0x09, and 0x0A Chip ID 0x01 CHIPID [7:0] 0x22 0x22: AD9267 Chip Grade 0x02 CHILDID 5:4] 0 0x00: 10 MHz bandwidth 0x10: 5 MHz bandwidth 0x20: 2.5 MHz bandwidth 0x30: modulator only Channel Index 0x05 Channel [1:0] 0 0x1: Channel A only addressed 0x2: Channel B only addressed 0x3: both channels addressed simultaneously Power Modes 0x08 PWRDWN [1:0] 0 0x0: normal operation 0x1: channel power-down (local) 0x2: standby (everything except reference circuits) 0x3: sleep PLLENABLE 0x09 PLLENABLE [2] 0 1: enable PLL PLL 0x0A PLLLOCKED [7] 0 0: PLL is not locked 1: PLL is locked PLLAUTO [6] 0 0: disable PLL auto band select 1: enable PLL auto band select PLLMULT [5:0] 0 See Table 8 Output Modes 0x14 DRVSTD [7] 0 0: ANSI-644 1: Low power (IEEE1596.3 similar) OUTENB [4] 0 1: Channel A and Channel B outputs tristated Output Adjust 0x15 LVDSTERM [5:4] 0 0: no termination 1: 200 Ω 2: 100 Ω 3: 100 Ω Output Clock 0x16 DCOINV [7] 0 1: invert DCO± Reference 0x18 EXTREF [6] 0 1: use external reference Overrange 0x111 AUTORST [7] 0 1: enable autoreset OR_IND1 [6] 0 See Table 12 OR_IND2 [5] 0 See Table 12 Rev. 0 | Page 23 of 24 AD9267 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9267BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1 AD9267EBZ Evaluation Board 1 Z = RoHs Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07773-0-7/09(0) Rev. 0 | Page 24 of 24 091707-C