ANALOG DEVICES AD9266

16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9266 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK CSB DRVDD 1.8 V analog supply operation 1.8 V to 3.3 V output supply RBIAS SPI SNR AD9266 VCM OR 77.6 dBFS at 9.7 MHz input PROGRAMMING DATA D15_D14 71.1 dBFS at 200 MHz input VIN+ ADC 8 CORE SFDR VIN– D1_D0 93 dBc at 9.7 MHz input DCO 80 dBc at 200 MHz input VREF Low power SENSE 56 mW at 20 MSPS REF SELECT 113 mW at 80 MSPS Differential input with 700 MHz bandwidth DIVIDE DUTY CYCLE MODE 1TO 8 STABILIZER CONTROLS On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input CLK+ CLK– PDWN DFS MODE DNL = −0.6/+1.1 LSB Figure 1. Interleaved data output for reduced pin-count interface Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer PRODUCT HIGHLIGHTS Integer 1-to-8 input clock divider 1. The AD9266 operates from a single 1.8 V analog power Built-in selectable digital test pattern generation supply and features a separate digital output driver supply Energy-saving power-down modes to accommodate 1.8 V to 3.3 V logic families. Data clock output (DCO) with programmable clock and 2. The patented sample-and-hold circuit maintains excellent data alignment performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. APPLICATIONS 3. A standard serial port interface supports various product Communications features and functions, such as data output formatting, Diversity radio systems internal clock divider, power-down, DCO and data output Multimode digital receivers (D15_D14 to D1_D0) timing and offset adjustments, and GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA voltage reference modes. Smart antenna systems 4. The AD9266 is packaged in a 32-lead RoHS-compliant Battery-powered instruments LFCSP that is pin compatible with the AD9609 10-bit Handheld scope meters ADC, the AD9629 12-bit ADC, and the AD9649 14-bit Portable medical imaging ADC, enabling a simple migration path between 10-bit and Ultrasound 16-bit converters sampling from 20 MSPS to 80 MSPS. Radar/LIDAR PET/SPECT imaging Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 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CMOS OUTPUT BUFFER 08678-001 AD9266 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 22 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 22 Revision History ............................................................................... 2 Timing ......................................................................................... 23 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 24 Specif ica t ions ..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 24 DC Specifications ......................................................................... 4 Output Test Modes ..................................................................... 24 AC Specifications .......................................................................... 5 Serial Port Interface (SPI) .............................................................. 25 Digital Specifications ................................................................... 6 Configuration Using the SPI ..................................................... 25 Switching Specifications .............................................................. 7 Hardware Interface ..................................................................... 26 Timing Specifications .................................................................. 8 Configuration Without the SPI ................................................ 26 Absolute Maximum Ratings ............................................................ 9 SPI Accessible Features .............................................................. 26 Thermal Characteristics .............................................................. 9 Memory Map .................................................................................. 27 ESD Caution .................................................................................. 9 Reading the Memory Map Register Table ............................... 27 Pin Configuration and Function Descriptions ........................... 10 Open Locations .......................................................................... 27 Typical Performance Characteristics ........................................... 11 Default Values ............................................................................. 27 AD9266-80 .................................................................................. 11 Memory Map Register Table ..................................................... 28 AD9266-65 .................................................................................. 13 Memory Map Register Descriptions ........................................ 30 AD9266-40 .................................................................................. 14 Applications Information .............................................................. 31 AD9266-20 .................................................................................. 15 Design Guidelines ...................................................................... 31 Equivalent Circuits ......................................................................... 16 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 32 Analog Input Considerations .................................................... 17 REVISION HISTORY 04/10—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9266 GENERAL DESCRIPTION A differential clock input with a selectable internal 1-to-8 divide The AD9266 is a monolithic, single-channel 1.8 V supply, ratio controls all internal conversion cycles. An optional duty cycle 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital stabilizer (DCS) compensates for wide variations in the clock duty converter (ADC). It features a high performance sample-and- cycle while maintaining excellent overall ADC performance. hold circuit and on-chip voltage reference. The interleaved digital output data is presented in offset binary, The product uses multistage differential pipeline architecture gray code, or twos complement format. A data output clock with output error correction logic to provide 16-bit accuracy at (DCO) is provided to ensure proper latch timing with receiving 80 MSPS data rates and to guarantee no missing codes over the logic. Both 1.8 V and 3.3 V CMOS levels are supported. full operating temperature range. The AD9266 is available in a 32-lead RoHS-compliant LFCSP The ADC contains several features designed to maximize and is specified over the industrial temperature range (−40°C flexibility and minimize system cost, such as programmable to +85°C). clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 0 | Page 3 of 32 AD9266 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full +0.05 ±0.30 +0.05 ±0.30 +0.05 ±0.30 % FSR 1 Gain Error Full −2.5/−2.0 −1.0 +1.0 % FSR Differential Nonlinearity Full −0.9/+1.2 −0.9/+1.7 −0.9/+1.7 LSB 2 (DNL) 25°C −0.5/+0.6 −0.5/+1.0 −0.6/+1.1 LSB Integral Nonlinearity Full ±5.5 ±6.5 ±6.2 LSB 2 (INL) 25°C ±1.8 ±2.4 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.983 0.995 1.007 0.983 0.995 1.007 0.983 0.995 1.007 V Load Regulation Error Full 2 2 2 mV at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.8 2.8 2.8 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p 3 Input Capacitance Full 6.5 6.5 6.5 pF Input Common-Mode Full 0.9 0.9 0.9 V Voltage Input Common-Mode Full 0.5 1.3 0.5 1.3 0.5 1.3 V Range REFERENCE INPUT Full 7.5 7.5 7.5 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 Full 31.4/40.7 33.2/42.5 54.5 57.6 62.5 65.7 mA IAVDD 2 Full 1.7/3.3 5.2 6.3 mA IDRVDD (1.8 V) 2 Full 3.0/5.9 9.3 11.6 mA IDRVDD (3.3 V) POWER CONSUMPTION DC Input Full 57/73 98 113 mW 2 Full 60/79 63/82 107 113 124 130 mW Sine Wave Input (DRVDD = 1.8 V) 2 Full 66/93 129 151 mW Sine Wave Input (DRVDD = 3.3 V) 4 Standby Power Full 40 44 44 mW Power-Down Power Full 0.5 0.5 0.5 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. 0 | Page 4 of 32 AD9266 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. AD9266-20/AD9266-40 AD9266-65 AD9266-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 78.2 77.9 77.6 dBFS IN f = 30.5 MHz 25°C 77.6 77.5 77.3 dBFS IN Full 76.7 76.6 dBFS fIN = 70 MHz 25°C 75.8/76.4 76.6 76.6 dBFS Full 75.5 dBFS fIN = 200 MHz 25°C 72.1 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 78.0 77.7 77.4 dBFS fIN = 30.5 MHz 25°C 77.5 77.3 77.1 dBFS Full 76.2 76.2 dBFS f = 70 MHz 25°C 75.7/76.3 76.5 76.6 dBFS IN Full 75.5 dBFS fIN = 200 MHz 25°C 69.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.7 12.6 12.6 Bits fIN = 30.5 MHz 25°C 12.6 12.5 12.5 Bits fIN = 70 MHz 25°C 12.3/12.4 12.4 12.4 Bits f = 200 MHz 25°C 11.2 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −97 −96 −95 dBc f = 30.5 MHz 25°C −96/−93 −94 −93 dBc IN Full −80 −80 dBc fIN = 70 MHz 25°C −97/−95 −98 −95 dBc Full −80 dBc fIN = 200 MHz 25°C −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 94 dBc fIN = 30.5 MHz 25°C 93 92 92 dBc Full 80 80 dBc f = 70 MHz 25°C 93 95 93 dBc IN Full 80 dBc fIN = 200 MHz 25°C 80 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −102 −101 −99 dBc IN fIN = 30.5 MHz 25°C −102 −101 −98 dBc Full −89 −89 dBc f = 70 MHz 25°C −101 −100 −98 dBc IN Full −89 dBc f = 200 MHz 25°C −86 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc IN ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 32 AD9266 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. AD9266-20/AD9266-40/AD9266-65/AD9266-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 μA Full 3.29 V OH High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, I = 50 μA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 32 AD9266 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 80/320 520 625 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (t) Full 3 3 3 ns DCO DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 9 9 9 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. t A N N + 6 N + 7 N – 1 N + 1 N + 5 V IN N + 8 N + 2 N + 3 t CLK CLK+ CLK– t DCO DCO t t SKEW SKEW D1 D1_D0 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 N–9 N–9 N–8 N–8 N–7 N–7 N–6 N–6 N–5 N–5 N–4 N–4 t PD D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 N–9 N–9 N–8 N–8 N–7 N–7 N–6 N–6 N–5 N–5 N–4 N–4 D15_D14 Figure 2. CMOS Output Data Timing Rev. 0 | Page 7 of 32 08678-002 AD9266 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an output 10 ns EN_SDIO relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Rev. 0 | Page 8 of 32 AD9266 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. VREF to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance SENSE to AGND −0.3 V to AVDD + 0.2 V Airflow VCM to AGND −0.3 V to AVDD + 0.2 V Package Velocity RBIAS to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 1, 2 Type (m/sec) θJA θJC θJB ΨJT Unit CSB to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 0.3 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 0.5 °C/W SDIO/PDWN to AGND −0.3 V to DRVDD + 0.3 V 2.5 29.1 0.8 °C/W MODE/OR to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. D1_D0 Through D15_D14 to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCO to AGND −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Typical θJA is specified for a 4-layer PCB with a solid ground Storage Temperature Range (Ambient) −65°C to +150°C plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and Stresses above those listed under Absolute Maximum Ratings power planes reduces the θ . JA may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational ESD CAUTION section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 32 AD9266 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 24 AVDD CLK– 2 23 MODE/OR AVDD 3 22 DCO AD9266 CSB 4 21 (MSB) D15_D14 5 TOP VIEW 20 D13_D12 SCLK/DFS (Not to Scale) SDIO/PDWN 6 19 D11_D10 NC 7 18 D9_D8 8 17 D7_D6 NC NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE (PIN 0) IS THE ONLY GND CONNECTION ON THE CHIP AND MUST BE CONNECTED TO THE PCB AGND. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0, Exposed Paddle AGND The exposed paddle is the only ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull- down. See Table 14 for details. 7 to 12 NC No Connect. D1_D0 (LSB) to 14 to 21 ADC Digital Outputs. (MSB) D15_D14 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 25 VREF 1.0 V Voltage Reference Input/Output. See Table 10. 26 SENSE Reference Mode Selection. See Table 10. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. 0 | Page 10 of 32 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 08678-003 NC AVDD VIN+ NC NC VIN– AVDD NC RBIAS DRVDD VCM D1_D0 (LSB) SENSE D3_D2 VREF D5_D4 AD9266 TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 9.7MHz @ –1dBFS 30.6MHz @ –1dBFS –20 –20 SNR = 76.8dB (77.8dBFS) SNR = 76.5dB (77.5dBFS) SFDR = 94.3dBc SFDR = 85.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9266-80 Single-Tone FFT with fIN = 9.7 MHz Figure 7. AD9266-80 Single-Tone FFT with fIN = 30.6 MHz 0 0 80MSPS 80MSPS 69MHz @ –1dBFS 210MHz @ –1dBFS –20 –20 SNR = 75.1dB (76.1dBFS) SNR = 70dB (71dBFS) SFDR = 89.5dBc SFDR = 79.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9266-80 Single-Tone FFT with fIN = 69 MHz Figure 8. AD9266-80 Single-Tone FFT with fIN = 210 MHz 0 10 80MSPS –15 28.3MHz @ –7dBFS –10 30.6MHz @ –7dBFS SFDR (dBc) –30 SFDR = 89.5dBc (96.5dBFS) –30 –45 IMD3 (dBc) –50 –60 –75 –70 2F1 + F2 –90 2F2 + F1 SFDR (dBFS) F1 + F2 –90 2F1 – F2 F2–F1 2F2 – F1 –105 –110 –120 IMD3 (dBFS) –135 –130 –95 –85 –75 –65 –55 –45 –35 –25 –15 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 6. AD9266-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Rev. 0 | Page 11 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08678-053 08678-035 08678-033 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SFDR/IMD3 (dBc/dBFS) 08678-054 08678-036 08678-034 AD9266 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 100 1.5 SFDR (dBc) 90 1.0 80 70 SNR (dBFS) 0.5 60 50 0 40 –0.5 30 20 –1.0 10 0 –1.5 0 16,384 32,768 49,152 65,536 0 50 100 150 200 INPUT FREQUENCY (MHz) OUTPUT CODE Figure 10. AD9266-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 13. DNL Error with f = 9.7 MHz IN 100 6 90 SFDR (dBc) 4 80 70 SNR (dBFS) 2 60 50 0 40 –2 30 20 –4 10 0 –6 10 20 30 40 50 60 70 80 0 16,384 32,768 49,152 65,536 SAMPLE RATE (MSPS) OUTPUT CODE Figure 11. AD9266-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 14. INL with f = 9.7 MHz IN 120 4.0M SFDRFS 2.8 LSB RMS 3.5M 100 3.0M 80 2.5M SNRFS SFDR 2.0M 60 1.5M SNR 40 1.0M 20 500k 0 0 –65 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 12. AD9266-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 15. Grounded Input Histogram Rev. 0 | Page 12 of 32 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08678-061 08678-055 08678-057 INL ERROR (LSB) DNL ERROR (LSB) NUMBER OF HITS N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 08678-048 08678-037 08678-038 AD9266 AD9266-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 120 0 65MSPS SFDRFS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.9dBc –40 80 SNRFS –60 SFDR 60 –80 SNR 40 –100 20 –120 –140 0 03 5 10 15 20 250 –65 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 19. AD9266-65 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz Figure 16. AD9266-65 Single-Tone FFT with fIN = 9.7 MHz IN 0 100 65MSPS SFDR (dBc) 69MHz @ –1dBFS 90 –20 SNR = 75.5dB (76.5dBFS) SFDR = 87.4dBc 80 –40 70 SNR (dBFS) 60 –60 50 –80 40 30 –100 20 –120 10 –140 0 03 5 10 15 20 250 0 50 100 150 200 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. AD9266-65 SNR/SFDR vs. Input Frequency (AIN) with Figure 17. AD9266-65 Single-Tone FFT with f = 69 MHz IN 2 V p-p Full Scale 0 65MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 89.9dBc –40 –60 –80 –100 –120 –140 03 5 10 15 20 250 FREQUENCY (MHz) Figure 18. AD9266-65 Single-Tone FFT with f = 30.6 MHz IN Rev. 0 | Page 13 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08678-031 08678-032 08678-030 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08678-060 08678-056 AD9266 AD9266-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 120 0 40MSPS SFDRFS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.1dBc –40 80 SNRFS –60 SFDR 60 –80 SNR 40 –100 20 –120 –140 0 0 2 4 6 8 10 12 14 16 18 20 –65 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 23. AD9266-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 21. AD9266-40 Single-Tone FFT with fIN = 9.7 MHz 0 40MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 88.8dBc –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Figure 22. AD9266-40 Single-Tone FFT with fIN = 30.6 MHz Rev. 0 | Page 14 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08678-029 08678-028 SNR/SFDR (dBFS/dBc) 08678-059 AD9266 AD9266-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 120 20MSPS SFDRFS 9.7MHz @ –1dBFS –20 100 SNR = 76.9dB (77.9dBFS) SFDR = 95.6dBc –40 SNRFS 80 –60 60 SFDR (dBc) –80 40 –100 SNR (dBc) 20 –120 –140 0 012 3 4 56 7 8 9 10 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 24. AD9266-20 Single-Tone FFT with fIN = 9.7 MHz Figure 26. AD9266-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 20MSPS 30.6MHz @ –1dBFS –20 SNR = 76.7dB (77.7dBFS) SFDR = 90.7dBc –40 –60 –80 –100 –120 –140 012 3 4 56 7 8 9 10 FREQUENCY (MHz) Figure 25. AD9266-20 Single-Tone FFT with f = 30.6 MHz IN Rev. 0 | Page 15 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08678-026 08678-024 SNR/SFDR (dBFS/dBc) 08678-058 AD9266 EQUIVALENT CIRCUITS DRVDD AVDD VIN± D1_D0 TO D15_D14, OR Figure 27. Equivalent Analog Input Circuit Figure 31. Equivalent D1_D0 to D15_D14 and OR Digital Output Circuit DRVDD AVDD SCLK/DFS, 350Ω MODE, 375Ω SDIO/PDWN VREF 30kΩ 7.5kΩ Figure 32. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit Figure 28. Equivalent VREF Circuit AVDD DRVDD AVDD 30kΩ 375Ω 350Ω SENSE CSB Figure 29. Equivalent SENSE Circuit Figure 33. Equivalent CSB Input Circuit AVDD 5Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 375Ω RBIAS AND VCM 5Ω CLK– Figure 30. Equivalent Clock Input Circuit Figure 34. Equivalent RBIAS and VCM Circuit Rev. 0 | Page 16 of 32 08678-039 08678-046 08678-040 08678-047 08678-042 08678-045 08678-044 08678-043 AD9266 THEORY OF OPERATION high IF frequencies. Either a shunt capacitor or two single-ended The AD9266 architecture consists of a multistage, pipelined ADC. capacitors can be placed on the inputs to provide a matching Each stage provides sufficient overlap to correct for flash errors in passive network. This ultimately creates a low-pass filter at the the preceding stage. The quantized outputs from each stage are input to limit unwanted broadband noise. See the AN-742 combined into a final 16-bit result in the digital correction logic. Application Note, the AN-827 Application Note, and the Analog The pipelined architecture permits the first stage to operate with Dialogue article “Transformer-Coupled Front-End for Wideband a new input sample, whereas the remaining stages operate with A/D Converters” (Volume 39, April 2005) for more information. In preceding samples. Sampling occurs on the rising edge of the clock. general, the precise values depend on the application. Each stage of the pipeline, excluding the last, consists of a low Input Common Mode resolution flash ADC connected to a switched-capacitor DAC The analog inputs of the AD9266 are not internally dc-biased. and an interstage residue amplifier (for example, a multiplying Therefore, in ac-coupled applications, the user must provide digital-to-analog converter (MDAC)). The residue amplifier a dc bias externally. Setting the device so that VCM = AVDD/2 magnifies the difference between the reconstructed DAC output is recommended for optimum performance, but the device can and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction function over a wider range with reasonable performance, as of flash errors. The last stage simply consists of a flash ADC. shown in Figure 36. 100 The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers 95 are powered from a separate (DRVDD) supply, allowing adjust- SFDR (dBc) 90 ment of the output voltage swing. During power-down, the output buffers go into a high impedance state. 85 ANALOG INPUT CONSIDERATIONS 80 SNR (dBFS) The analog input to the AD9266 is a differential switched- 75 capacitor circuit designed for processing differential input 70 signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input 65 common-mode voltage of midsupply, users can minimize 60 signal-dependent errors and achieve optimum performance. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 INPUT COMMON-MODE VOLTAGE (V) Figure 36. SNR/SFDR vs. Input Common-Mode Voltage, f = 32.5 MHz, f = 80 MSPS IN S H C An on-board, common-mode voltage reference is included in PAR H VIN+ the design and is available from the VCM pin. The VCM pin C SAMPLE must be decoupled to ground by a 0.1 μF capacitor, as described SS in the Applications Information section. SS C SAMPLE VIN– Differential Input Configurations H C PAR Optimum performance is achieved while driving the AD9266 in a H differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide Figure 35. Switched-Capacitor Input Circuit excellent performance and a flexible interface to the ADC. The clock signal alternately switches the input circuit between The output common-mode voltage of the ADA4938-2 is easily sample-and-hold mode (see Figure 35). When the input circuit set with the VCM pin of the AD9266 (see Figure 37), and the is switched to sample mode, the signal source must be capable driver can be configured in a Sallen-Key filter topology to of charging the sample capacitors and settling within one-half provide band limiting of the input signal. of a clock cycle. A small resistor in series with each input can 200Ω 33Ω help reduce the peak transient current injected from the output VIN VIN– 76.8Ω AVDD 90Ω stage of the driving source. In addition, low Q inductors or ferrite 10pF ADC beads can be placed on each leg of the input to reduce high differ- ADA4938-2 0.1µF ential capacitance at the analog inputs and, therefore, achieve 120Ω 33Ω VCM VIN+ the maximum bandwidth of the ADC. Such use of low Q inductors 200Ω or ferrite beads is required when driving the converter front end at Figure 37. Differential Input Configuration Using the ADA4938-2 Rev. 0 | Page 17 of 32 08678-006 SNR/SFDR (dBFS/dBc) 08678-049 08678-007 AD9266 For baseband applications below ~10 MHz where SNR is a key In any configuration, the value of Shunt Capacitor C is dependent parameter, differential transformer coupling is the recommended on the input frequency and source impedance and may need to input configuration. An example is shown in Figure 38. To bias be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. input signal and should be used only as a starting guide. VIN+ Table 9. Example RC Network R 2V p-p 49.9Ω R Series C ADC Frequency Range (MHz) (Ω Each) C Differential (pF) R VCM VIN– 0 to 70 33 22 70 to 200 125 Open 0.1µF Figure 38. Differential Transformer-Coupled Configuration Single-Ended Input Configuration The signal characteristics must be considered when selecting A single-ended input can provide adequate performance in a transformer. Most RF transformers saturate at frequencies cost-sensitive applications. In this configuration, SFDR and below a few megahertz (MHz). Excessive signal power can also distortion performance degrade due to the large input common- cause core saturation, which leads to distortion. mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 39 At input frequencies in the second Nyquist zone and above, the shows a typical single-ended input configuration. noise performance of most amplifiers is not adequate to achieve 10µF AVDD the true SNR performance of the AD9266. For applications above 1kΩ ~10 MHz where SNR is a key parameter, differential double balun R VIN+ coupling is the recommended input configuration (see Figure 40). 1V p-p 0.1µF 49.9Ω 1kΩ AVDD C ADC An alternative to using a transformer-coupled input at frequencies 1kΩ R in the second Nyquist zone is to use the AD8352 differential driver. VIN– 10µF 0.1µF 1kΩ An example is shown in Figure 41. See the AD8352 data sheet for more information. Figure 39. Single-Ended Input Configuration 0.1µF 0.1µF R VIN+ 2V p-p 25Ω P S S P C A ADC 0.1µF 25Ω 0.1µF R VCM VIN– Figure 40. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+ 2 200Ω C ADC R R AD8352 C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN– 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 41. Differential Input Configuration Using the AD8352 Rev. 0 | Page 18 of 32 08678-008 08678-010 08678-011 08678-009 AD9266 0 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the –0.5 AD9266. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. –1.0 The various reference modes are summarized in the sections that INTERNAL V = 0.995V REF follow. The Reference Decoupling section describes the best –1.5 practices for PCB layout of VREF. –2.0 Internal Reference Connection A comparator within the AD9266 detects the potential at the –2.5 SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the –3.0 reference amplifier switch is connected to the internal resistor 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 divider (see Figure 42), setting VREF to 1.0 V. LOAD CURRENT (mA) Figure 43. V Accuracy vs. Load Current REF VIN+ VIN– External Reference Operation The use of an external reference may be necessary to enhance ADC the gain accuracy of the ADC or improve thermal drift charac- CORE teristics. Figure 44 shows the typical drift characteristics of the internal reference in 1.0 V mode. VREF 4 1.0µF 0.1µF SELECT 3 LOGIC 2 SENSE V ERROR (mV) REF 1 0.5V 0 ADC –1 –2 Figure 42. Internal Reference Configuration –3 If the internal reference of the AD9266 is used to drive multiple –4 converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 43 shows –5 how the internal reference voltage is affected by loading. –6 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 44. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 28). The internal buffer generates the posi- tive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. 0 | Page 19 of 32 08678-012 REFERENCE VOLTAGE ERROR (%) V ERROR (mV) REF 08678-052 08678-014 AD9266 The back-to-back Schottky diodes across the transformer/ CLOCK INPUT CONSIDERATIONS balun secondary limit clock excursions into the AD9266 to For optimum performance, clock the AD9266 sample clock inputs, approximately 0.8 V p-p differential. CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or This limit helps prevent the large voltage swings of the clock capacitors. These pins are biased internally (see Figure 45) and from feeding through to other portions of the AD9266 while require no external bias. preserving the fast rise and fall times of the signal that are critical to a low jitter performance. AVDD If a low jitter clock source is not available, another option is to 0.9V ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 48. The AD9510/AD9511/AD9512/ CLK+ CLK– AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 2pF 2pF 0.1µF 0.1µF CLOCK CLK+ Figure 45. Equivalent Clock Input Circuit INPUT AD951x 100Ω ADC Clock Input Options PECL DRIVER 0.1µF 0.1µF CLOCK CLK– The AD9266 has a very flexible clock input structure. The clock INPUT 240Ω 240Ω 50kΩ 50kΩ input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is Figure 48. Differential PECL Sample Clock (Up to 625 MHz) of great concern, as described in the Jitter Considerations section. A third option is to ac couple a differential LVDS signal to the Figure 46 and Figure 47 show two preferred methods for clock- sample clock input pins, as shown in Figure 49. The AD9510/ ing the AD9266 (at clock rates up to 625 MHz when using the AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 internal clock divider). A low jitter clock source is converted from clock drivers offer excellent jitter performance. a single-ended signal to a differential signal using either an RF transformer or an RF balun. 0.1µF 0.1µF CLOCK CLK+ ® Mini-Circuits INPUT ADT1-1WT, 1:1 Z AD951x 100Ω ADC 0.1µF 0.1µF LVDS DRIVER 0.1µF XFMR 0.1µF CLOCK CLK+ CLOCK CLK– INPUT INPUT 100Ω 50Ω ADC 50kΩ 50kΩ 0.1µF CLK– SCHOTTKY Figure 49. Differential LVDS Sample Clock (Up to 625 MHz) 0.1µF DIODES: HSMS2822 In some applications, it may be acceptable to drive the sample Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz) clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see 1nF 0.1µF Figure 50). CLOCK CLK+ INPUT 50Ω ADC V CC 0.1µF 1nF CLK– OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω SCHOTTKY CLOCK CLK+ CMOS DRIVER DIODES: INPUT 1 1kΩ 50Ω HSMS2822 ADC Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz) CLK– 0.1µF The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- 1 50Ω RESISTOR IS OPTIONAL. mended for clock frequencies from 10 MHz to 200 MHz. Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. 0 | Page 20 of 32 08678-016 08678-018 08678-017 08678-021 08678-020 08678-019 AD9266 Input Clock Divider Jitter Considerations The AD9266 contains an input clock divider with the ability High speed, high resolution ADCs are sensitive to the quality of to divide the input clock by integer values between 1 and 8. the clock input. The degradation in SNR from the low frequency Optimum performance can be obtained by enabling the internal SNR (SNRLF) at a given input frequency (fINPUT) due to jitter duty cycle stabilizer (DCS) when using divide ratios other than (tJRMS) can be calculated by 1, 2, or 4. (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS Clock Duty Cycle In the previous equation, the rms aperture jitter represents the Typical high speed ADCs use both clock edges to generate clock input jitter specification. IF undersampling applications a variety of internal timing signals and, as a result, may be are particularly sensitive to jitter, as illustrated in Figure 52. sensitive to clock duty cycle. Commonly, a ±5% tolerance is 80 required on the clock duty cycle to maintain dynamic performance characteristics. 75 0.05ps The AD9266 contains a duty cycle stabilizer (DCS) that retimes 70 the nonsampling (falling) edge, providing an internal clock 0.2ps signal with a nominal 50% duty cycle. This allows the user to 65 provide a wide range of clock input duty cycles without affecting 60 0.5ps the performance of the AD9266. Noise and distortion perform- ance are nearly flat for a wide range of duty cycles with the DCS on, 55 1.0ps as shown in Figure 51. 1.5ps 80 50 DCS OFF 2.0ps 79 DCS ON 3.0ps 2.5ps 45 78 1 10 100 1k FREQUENCY (MHz) 77 Figure 52. SNR vs. Input Frequency and Jitter 76 The clock input should be treated as an analog signal when 75 aperture jitter may affect the dynamic range of the AD9266. To 74 avoid modulating the clock signal with digital noise, keep power 73 supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best 72 clock sources. If the clock is generated from another type of source 71 (by gating, dividing, or another method), it should be retimed by 70 the original clock at the last step. 30 35 40 45 50 55 60 65 70 POSITIVE DUTY CYCLE (%) For more information, see the AN-501 Application Note and Figure 51. SNR vs. DCS On/Off the AN-756 Application Note available at www.analog.com. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. Rev. 0 | Page 21 of 32 SNR (dBFS) 08678-064 SNR (dBFS) 08678-022 AD9266 down mode and then must be recharged when returning to normal POWER DISSIPATION AND STANDBY MODE operation. As a result, wake-up time is related to the time spent As shown in Figure 53, the analog core power dissipated by the in power-down mode, and shorter power-down cycles result in AD9266 is proportional to its sample rate. The digital power proportionally shorter wake-up times. dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows The maximum DRVDD current (IDRVDD) can be calculated as the user to keep the internal reference circuitry powered when IDRVDD = V × C × f × N DRVDD LOAD CLK faster wake-up times are required. See the Memory Map section for more details. where N is the number of output bits (nine, in the case of the AD9266). DIGITAL OUTPUTS This maximum current occurs when every output bit switches The AD9266 output drivers can be configured to interface with on every clock cycle, that is, a full-scale square wave at the Nyquist 1.8 V to 3.3 V CMOS logic families. Output data can also be frequency of f /2. In practice, the DRVDD current is estab- CLK multiplexed onto a single output bus to reduce the total number lished by the average number of output bits switching, which of traces required. is determined by the sample rate and the characteristics of the The CMOS output drivers are sized to provide sufficient output analog input signal. current to drive a wide variety of logic families. However, large Reducing the capacitive load presented to the output drivers can drive currents tend to cause current glitches on the supplies and minimize digital power consumption. The data in Figure 53 was may affect converter performance. taken using the same operating conditions as those used for the Applications requiring the ADC to drive large capacitive loads Typical Performance Characteristics, with a 5 pF load on each or large fanouts may require external buffers or latches. output driver. The output data format can be selected to be either offset binary 115 or twos complement by setting the SCLK/DFS pin when operating AD9266-80 in the external pin mode (see Table 11). 105 AD9266-65 As detailed in the AN-877 Application Note, Interfacing to High 95 Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. 85 Table 11. SCLK/DFS and SDIO/PDWN Mode Selection 75 AD9266-40 (External Pin Mode) 65 Voltage at Pin SCLK/DFS SDIO/PDWN AD9266-20 AGND Offset binary (default) Normal operation 55 (default) DRVDD Twos complement Outputs disabled 45 10 20 30 40 50 60 70 80 CLOCK RATE (MSPS) Digital Output Enable Function (OEB) Figure 53. Analog Core Power vs. Clock Rate When using the SPI interface, the data outputs and DCO can be In SPI mode, the AD9266 can be placed in power-down mode independently three-stated by using the programmable external directly via the SPI port, or by using the programmable external MODE pin. The MODE pin (OEB) function is enabled via Bits[6:5] MODE pin. In non-SPI mode, power-down is achieved by assert- of Register 0x08. ing the PDWN pin high. In this state, the ADC typically dissipates If the MODE pin is configured to operate in traditional OEB 500 μW. During power-down, the output drivers are placed in mode and the MODE pin is low, the output data drivers and a high impedance state. Asserting PDWN low (or the MODE pin DCOs are enabled. If the MODE pin is high, the output data in SPI mode) returns the AD9266 to its normal operating mode. drivers and DCOs are placed in a high impedance state. This Note that PDWN is referenced to the digital output driver OEB function is not intended for rapid access to the data bus. supply (DRVDD) and should not exceed that supply voltage. Note that the MODE pin is referenced to the digital output Low power dissipation in power-down mode is achieved by driver supply (DRVDD) and should not exceed that supply shutting down the reference, reference buffer, biasing networks, voltage. and clock. Internal capacitors are discharged when entering power- Rev. 0 | Page 22 of 32 ANALOG CORE POWER (mW) 08678-067 AD9266 The lowest typical conversion rate of the AD9266 is 3 MSPS. At TIMING clock rates below 3 MSPS, dynamic performance may degrade. The AD9266 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation Data Clock Output (DCO) delay (tPD) after the rising edge of the clock signal. The AD9266 provides a data clock output (DCO) signal that is intended for capturing the data in an external register. The CMOS Minimize the length of the output data lines and loads placed data outputs are valid on the rising edge of DCO, unless the DCO on them to reduce transients within the AD9266. These clock polarity has been changed via the SPI. See Figure 2 for transients can degrade converter dynamic performance. a graphical timing description. Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 0000 1000 0000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111 1 Rev. 0 | Page 23 of 32 AD9266 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9266 includes a built-in test feature that is designed to Bit 0 of Register 0x24 is automatically cleared. The PN sequence enable verification of the integrity of the datapath, as well as to can be continued from its last value by writing a 0 in Bit 2 of facilitate board-level debugging. A built-in self-test (BIST) feature Register 0x0E. However, if the PN sequence is not reset, the that verifies the integrity of the digital datapath of the AD9266 signature calculation does not equal the predetermined value is included. Various output test options are also provided to place at the end of the test. At that point, the user must rely on predictable values on the outputs of the AD9266. verifying the output data. BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES The BIST is a thorough test of the digital portion of the selected The output test options are described in Table 16 at Address 0x0D. AD9266 signal path. Perform the BIST test after a reset to ensure When an output test mode is enabled, the analog section of the that the part is in a known state. During BIST, data from an internal ADC is disconnected from the digital back end blocks and the pseudorandom noise (PN) source is driven through the digital test pattern is run through the output formatting block. Some of datapath, starting at the ADC block output. At the datapath the test patterns are subject to output formatting, and some are output, CRC logic calculates a signature from the data. The not. The PN generators from the PN sequence tests can be reset BIST sequence runs for 512 cycles and then stops. Once by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be completed, the BIST compares the signature results with performed with or without an analog signal (if present, the a predetermined value. If the signatures match, the BIST sets Bit 0 analog signal is ignored), but they do require an encode clock. of Register 0x24, signifying the test passed. If the BIST test failed, For more information, see the AN-877 Application Note, Bit 0 of Register 0x24 is cleared. The outputs are connected during Interfacing to High Speed ADCs via SPI. this test, so the PN sequence can be observed as it runs. Writing 0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST, Rev. 0 | Page 24 of 32 AD9266 SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of The AD9266 serial port interface (SPI) allows the user to con- SCLK, determines the start of the framing. An example of the figure the converter for specific functions or operations through serial timing and its definitions can be found in Figure 54 and a structured register space provided inside the ADC. The SPI gives Table 5. the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can Other modes involving the CSB pin are available. CSB can be be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are this is called streaming. CSB can stall high between bytes to documented in the Memory Map section. For more detailed allow for additional external timing. When CSB is tied high, operational information, see the AN-877 Application Note, SPI functions are placed in high impedance mode. This mode Interfacing to High Speed ADCs via SPI. turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: SCLK, SDIO, and CSB by the W0 and W1 bits, as shown in Figure 54. (see Table 13). The SCLK (a serial clock) is used to synchronize All data is composed of 8-bit words. The first bit of the first byte in the read and write data presented from and to the ADC. SDIO a multibyte serial data transfer frame indicates whether a read (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. command or a write command is issued. This allows the serial The CSB (chip select bar) is an active-low control that enables data input/output (SDIO) pin to change direction from an input or disables the read and write cycles. to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines Table 13. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial clock. The serial shift clock input, which is used to the contents of the on-chip memory. If the instruction is a readback synchronize serial interface reads and writes. operation, performing a readback causes the serial data input/ SDIO Serial data input/output. A dual-purpose pin that output (SDIO) pin to change direction from an input to an output typically serves as an input or an output, depending on the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip select bar. An active-low control that gates the read first is the default on power-up and can be changed via the SPI and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 54. Serial Port Interface Timing Diagram Rev. 0 | Page 25 of 32 08678-023 AD9266 lines for the power-down and output data format feature control. HARDWARE INTERFACE In this mode, connect the CSB chip select to DRVDD, which The pins described in Table 13 constitute the physical interface disables the serial port interface. between the programming device of the user and the serial port of the AD9266. The SCLK pin and the CSB pin function as inputs Table 14. Mode Selection when using the SPI interface. The SDIO pin is bidirectional, External functioning as an input during write phases and as an output Pin Voltage Configuration during readback. SDIO/PDWN DRVDD Chip power-down mode AGND (default) Normal operation (default) The SPI interface is flexible enough to be controlled by either SCLK/DFS DRVDD Twos complement enabled FPGAs or microcontrollers. One method for SPI configuration AGND (default) Offset binary enabled is described in detail in the AN-812 Application Note, Micro- controller-Based Serial Port Interface (SPI) Boot Circuit. SPI ACCESSIBLE FEATURES The SPI port should not be active during periods when the full Table 15 provides a brief description of the general features that dynamic performance of the converter is required. Because the are accessible via the SPI. These features are described in detail SCLK signal, the CSB signal, and the SDIO signal are typically in the AN-877 Application Note, Interfacing to High Speed ADCs asynchronous to the ADC clock, noise from these signals can via SPI. The AD9266 part-specific features are described in degrade converter performance. If the on-board SPI bus is used for detail in Table 16. other devices, it may be necessary to provide buffers between this bus and the AD9266 to prevent these signals from transi- Table 15. Features Accessible Using the SPI tioning at the converter inputs during critical sampling periods. Feature Description Modes Allows the user to set either power-down mode SDIO/PDWN and SCLK/DFS serve a dual function when the or standby mode SPI interface is not being used. When the pins are strapped to Clock Allows the user to access the DCS via the SPI DRVDD or ground during device power-on, they are associated Offset Allows the user to digitally adjust the converter with a specific function. The Digital Outputs section describes offset the strappable functions supported on the AD9266. Test I/O Allows the user to set test modes to have known CONFIGURATION WITHOUT THE SPI data on output bits Output Mode Allows the user to set up outputs In applications that do not interface to the SPI control registers, Output Phase Allows the user to set the output clock polarity the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone Output Delay Allows the user to vary the DCO delay CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control Rev. 0 | Page 26 of 32 AD9266 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) After the AD9266 is reset, critical registers are loaded with contains eight bit locations. The memory map is roughly default values. The default values for the registers are given in divided into four sections: the chip configuration registers the memory map register table (see Table 16). (Address 0x00 to Address 0x02); the device index and transfer Logic Levels register (Address 0xFF); the program registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x2A); and the AD9266-specific customer SPI control register (Address 0x101). • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 16 documents the default hexadecimal value for each hexa- • “Clear a bit” is synonymous with “bit is set to Logic 0” or decimal address shown. The column with the heading Bit 7 (MSB) “writing Logic 0 for the bit.” is the start of the default hexadecimal value given. For example, Address 0x2A, the OR/MODE select register, has a hexadecimal Transfer Register Map default value of 0x01. This means that in Address 0x2A, Address 0x08 to Address 0x18 are shadowed. Writes to these Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE addresses do not affect part operation until a transfer command setting. The default value results in the programmable external is issued by writing 0x01 to Address 0xFF, setting the transfer bit. MODE/OR pin (Pin 23) functioning as an out-of-range digital This allows these registers to be updated internally and simulta- output. For more information on this function and others, see the neously when the transfer bit is set. The internal update takes AN-877 Application Note, Interfacing to High Speed ADCs via SPI. place when the transfer bit is set, and then the bit autoclears. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x101, is documented in the Memory Map Register Descriptions section that follows Table 16. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these loca- tions is required only when part of an address location is open (for example, Address 0x2A). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. 0 | Page 27 of 32 AD9266 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft 1 1 Soft LSB first 0 0x18 The nibbles are configuration first reset reset mirrored so that LSB- or MSB-first mode registers correctly, regardless of shift mode. 0x01 Chip ID 8-bit chip ID, Bits[7:0] Read Unique chip ID AD9266 = 0x78 only used to differentiate devices; read only. 0x02 Chip grade Open Speed grade ID, Bits[6:4] (identify Open Read Unique speed device variants of chip ID) only grade ID used to differentiate 20 MSPS = 000 devices; read only. 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Device Index and Transfer Register 0xFF Transfer Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave. Program Registers 0x08 Modes External External Pin 23 Open 00 = chip run 0x00 Determines various Pin 23 mode function when high generic modes of 01 = full power-down input enable chip operation. 00 = full power- 10 = standby down 11 = chip wide digital 01 = standby reset 10 = normal mode: output disabled 11 = normal mode: output enabled 0x09 Clock Open Duty cycle 0x01 Enable internal stabilize duty cycle stabilizer (DCS). 0x0B Clock divide Open Clock divider, Bits[2:0] 0x00 The divide ratio is Clock divide ratio: the value plus 1. 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0D Test mode User test mode Reset PN Reset PN Output test mode, Bits[3:0] (local) 0x00 When set, the test long gen short gen data is placed on 00 = single 0000 = off (default) the output pins in 0001 = midscale short 01 = alternate place of normal data. 0010 = positive FS 10 = single once 0011 = negative FS 11 = alternate once 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle 1000 = user input 1001 = 1/0 bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x0E BIST enable Open BIST Open BIST 0x00 When Bit 0 is set, INIT enable the built-in self-test function is initiated. 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) 0x00 Device offset trim. Offset adjust in LSBs from +127 to −128 (twos complement format) Rev. 0 | Page 28 of 32 AD9266 Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x14 Output mode 00 = 3.3 V CMOS Open Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS disable invert 01 = twos complement outputs and the 10 = gray code format of the data. 11 = offset binary 0x15 Output adjust 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data drive strength 0x22 Determines CMOS drive strength drive strength drive strength output drive 00 = 1 stripe strength properties. 00 = 1 stripe (default) 00 = 1 stripe 00 = 1 stripe (default) 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes (default) 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes 10 = 3 stripes 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 Output phase DCO output Open Input clock phase adjust, Bits[2:0] 0x00 On devices that use polarity global clock divide, (Value is number of input clock 0 = normal determines which cycles of phase delay) 1 = inverted phase of the divider 000 = no delay output is used to 001 = 1 input clock cycle supply the output 010 = 2 input clock cycles clock; internal 011 = 3 input clock cycles latching is 100 = 4 input clock cycles unaffected. 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 Output delay Open Open DCO/data delay[2:0] 0x00 Enable DCO Enable Sets the fine delay data output delay of the 000 = 0.56 ns delay output clock but 001 = 1.12 ns does not change 010 = 1.68 ns internal timing. 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 0x24 BIST signature LSB BIST signature, Bits[7:0] 0x00 Least significant byte of BIST signature, read only. 0x2A OR/MODE select Open 0 = MODE 0x01 Selects I/O functionality in 1 = OR conjunction with (default) Address 0x08 for MODE (input) or OR (output) on External Pin 23. AD9266-Specific Customer SPI Control Register 0x10USR2 Open Enable Run Open Disable 0x08 Enables internal 1 GCLK GCLK SDIO pull- oscillator for clock detect down rates of <5 MHz. Rev. 0 | Page 29 of 32 AD9266 MEMORY MAP REGISTER DESCRIPTIONS Bit 2—Run GCLK For additional information about functions that are controlled This bit enables the GCLK oscillator. For some applications in Register 0x00 to Register 0xFF, see the AN-877 Application with encode rates below 10 MSPS, it may be preferable to set Note, Interfacing to High Speed ADCs via SPI at www.analog.com. this bit high to supersede the GCLK detector. USR2 (Register 0x101) Bit 0—Disable SDIO Pull-Down Bit 3—Enable GCLK Detect This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when Normally set high, this bit enables a circuit that detects encode many devices are connected to the SPI bus. rates below about 5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled, ensuring the proper operation of several circuits. If set low, the detector is disabled. Rev. 0 | Page 30 of 32 AD9266 APPLICATIONS INFORMATION To maximize the coverage and adhesion between the ADC and DESIGN GUIDELINES the PCB, a silkscreen should be overlaid to partition the continuous Before starting design and layout of the AD9266 as a system, plane on the PCB into several uniform sections. This provides it is recommended that the designer become familiar with these several tie points between the ADC and the PCB during the reflow guidelines, which discuss the special circuit connections and process. Using one continuous plane with no partitions guarantees layout requirements needed for certain pins. only one tie point between the ADC and the PCB. For detailed Power and Ground Recommendations information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and When connecting power to the AD9266, it is strongly recom- Manufacturing Guide for the Lead Frame Chip Scale Package mended that two separate supplies be used. Use one 1.8 V supply (LFCSP) at www.analog.com. for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and Encode Clock DRVDD supply must be used, the AVDD and DRVDD domains For optimum dynamic performance, a low jitter encode clock must be isolated with a ferrite bead or filter choke and separate source with a 50% duty cycle ± 5% should be used to clock the decoupling capacitors. Several different decoupling capacitors AD9266. can be used to cover both high and low frequencies. Locate VCM these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. A single PCB ground plane should be sufficient when using the AD9266. With proper decoupling and smart partitioning of the RBIAS PCB analog, digital, and clock sections, optimum performance The AD9266 requires that a 10 kΩ resistor be placed between is easily achieved. the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for Reference Decoupling the AD9266; therefore, it must be connected to analog ground Externally decouple the VREF pin to ground with a low ESR, (AGND) on the customer’s PCB. To achieve the best electrical 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic and thermal performance, mate an exposed (no solder mask) capacitor. continuous copper plane on the PCB to the AD9266 exposed SPI Port paddle, Pin 0. The SPI port should not be active during periods when the full The copper plane should have several vias to achieve the dynamic performance of the converter is required. Because the lowest possible resistive thermal path for heat dissipation to SCLK, CSB, and SDIO signals are typically asynchronous to the flow through the bottom of the PCB. Fill or plug these vias ADC clock, noise from these signals can degrade converter with nonconductive epoxy. performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9266 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 31 of 32 AD9266 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC * 3.75 EXPOSED PAD 3.60 SQ 3.55 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9266BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-12 AD9266-80EBZ Evaluation Board AD9266-65EBZ Evaluation Board AD9266-40EBZ Evaluation Board AD9266-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08678-0-4/10(0) Rev. 0 | Page 32 of 32 PIN 1 INDICATOR 02-05-2009-B