ANALOG DEVICES AD9265

16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9265 FEATURES PRODUCT HIGHLIGHTS SNR = 79.0 dBFS @ 70 MHz and 125 MSPS 1. On-chip dither option for improved SFDR performance SFDR = 93 dBc @ 70 MHz and 125 MSPS with low power analog input. Low power: 373 mW @ 125 MSPS 2. Proprietary differential input that maintains excellent SNR 1.8 V analog supply operation performance for input frequencies up to 300 MHz. 1.8 V CMOS or LVDS output supply 3. Operation from a single 1.8 V supply and a separate digital Integer 1-to-8 input clock divider output driver supply accommodating 1.8 V CMOS or IF sampling frequencies to 300 MHz LVDS outputs. −154.3 dBm/Hz small signal input noise with 200 Ω input 4. Standard serial port interface (SPI) that supports various impedance @ 70 MHz and 125 MSPS product features and functions, such as data formatting Optional on-chip dither (offset binary, twos complement, or gray coding), enabling Programmable internal ADC voltage reference the clock duty cycle stabilizer, DCS, power-down, test Integrated ADC sample-and-hold inputs modes, and voltage reference mode. Flexible analog input range: 1 V p-p to 2 V p-p 5. Pin compatibility with the AD9255, allowing a simple Differential analog inputs with 650 MHz bandwidth migration from 16 bits down to 14 bits. ADC clock duty cycle stabilizer Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM SENSE RBIAS PDWN AGND AVDD (1.8V) LVDS LVDS_RS REFERENCE VREF AD9265 VCM DRVDD (1.8V) VIN+ TRACK-AND-HOLD VIN– OUTPUT ADC STAGING 16 16 16-BIT DITHER CMOS OR D15 TO D0 CORE LVDS (DDR) CLK+ CLOCK OR MANAGEMENT CLK– SYNC SERIAL PORT DCO SVDD SCLK/ SDIO/ CSB DFS DCS Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08502-001 AD9265 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 28  Applications ....................................................................................... 1  Clock Input Considerations ...................................................... 29  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 31  Functional Block Diagram .............................................................. 1  Digital Outputs ........................................................................... 32  Revision History ............................................................................... 2  Timing ......................................................................................... 32  General Description ......................................................................... 3  Built-In Self-Test (BIST) and Output Test .................................. 33  Specif ica t ions ..................................................................................... 4  Built-In Self-Test (BIST) ............................................................ 33  ADC DC Specifications ............................................................... 4  Output Test Modes ..................................................................... 33  ADC AC Specifications ................................................................. 5  Serial Port Interface (SPI) .............................................................. 34  Digital Specifications ................................................................... 6  Configuration Using the SPI ..................................................... 34  Switching Specifications ................................................................ 8  Hardware Interface ..................................................................... 34  Timing Specifications .................................................................. 9  Configuration Without the SPI ................................................ 35  Absolute Maximum Ratings .......................................................... 10  SPI Accessible Features .............................................................. 35  Thermal Characteristics ............................................................ 10  Memory Map .................................................................................. 36  ESD Caution ................................................................................ 10  Reading the Memory Map Register Table ............................... 36  Pin Configurations and Function Descriptions ......................... 11  Memory Map Register Table ..................................................... 37  Typical Performance Characteristics ........................................... 15  Memory Map Register Descriptions ........................................ 39  Equivalent Circuits ......................................................................... 23  Applications Information .............................................................. 40  Theory of Operation ...................................................................... 25  Design Guidelines ...................................................................... 40  ADC Architecture ...................................................................... 25  Outline Dimensions ....................................................................... 41  Analog Input Considerations .................................................... 25  Ordering Guide .......................................................................... 41  REVISION HISTORY 1/10—Rev. 0 to Rev. A Changes to Worst Other (Harmonic or Spur) Parameter, Table 2 ................................................................................................ 5 Changes to Figure 77 ...................................................................... 29 Changes to Input Clock Divider Section ..................................... 30 Changes to Table 17 ........................................................................ 37 Updated Outline Dimensions ....................................................... 41 10/09—Revision 0: Initial Version Rev. A | Page 2 of 44 AD9265 GENERAL DESCRIPTION The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter A differential clock input controls all internal conversion cycles. A (ADC). The AD9265 is designed to support communications duty cycle stabilizer provides the means to compensate for vari- applications where high performance combined with low cost, ations in the ADC clock duty cycle, allowing the converters to small size, and versatility is desired. maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design consid- The ADC core features a multistage, differential pipelined erations. architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees The ADC output data format is either parallel 1.8 V CMOS or no missing codes over the full operating temperature range. LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic. The ADC features a wide bandwidth differential sample-and- hold analog input amplifier supporting a variety of user-selectable Programming for setup and control is accomplished using a 3-wire input ranges. It is suitable for multiplexed systems that switch SPI-compatible serial interface. Flexible power-down options full-scale voltage levels in successive channels and for sampling allow significant power savings, when desired. An optional on- single-channel inputs at frequencies well beyond the Nyquist rate. chip dither function is available to improve SFDR performance Combined with power and cost savings over previously available with low power analog input signals. ADCs, the AD9265 is suitable for applications in communications, The AD9265 is available in a Pb-free, 48-lead LFCSP and is speci- instrumentation and medical imaging. fied over the industrial temperature range of −40°C to +85°C. Rev. A | Page 3 of 44 AD9265 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. 1 1 1 AD9265BCPZ-80 AD9265BCPZ-105 AD9265BCPZ-125 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.25 ±0.05 ±0.25 ±0.05 ±0.25 % FSR Gain Error Full ±0.2 ±2.5 ±0.2 ±2.5 ±0.4 ±2.5 % FSR 2 Differential Nonlinearity (DNL) Full −1.0 +1.25 −1.0 +1.25 −1.0 +1.25 LSB 25°C ±0.6 ±0.65 ±0.7 LSB 2 Integral Nonlinearity (INL) Full ±2.5 ±3.5 ±4.5 LSB 25°C ±1.5 ±2.0 ±3.0 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full +8 ±12 +8 ±12 +8 ±12 mV Load Regulation @ 1.0 mA Full 3 3 3 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 2.17 2.26 2.17 LSB rms ANALOG INPUT 22 Input Span, VREF = 1.0 V Full 2 V p-p 3 88 Input Capacitance Full 8 pF 0.9 0.9 Input Common-Mode Voltage Full 0.9 V 66 REFERENCE INPUT RESISTANCE Full 6 kΩ POWER SUPPLIES Supply Voltage 1.7 1.8 1.9 1.7 1.8 1.9 AVDD Full 1.7 1.8 1.9 V 1.7 1.8 1.9 1.7 1.8 1.9 DRVDD Full 1.7 1.8 1.9 V 1.7 3.51.7 3.51.7 3.5 SVDD Full V Supply Current 2 126 131 169 176 IAVDD Full 194 202 mA 2 IDRVDD 14 20 1.8 V CMOS Full 24 mA 43 46 1.8 V LVDS Full 49 mA POWER CONSUMPTION 241 258 323 343 DC Input Full 373 392 mW 2 Sine Wave Input DRVDD = 1.8 V 254 341 CMOS Output Mode Full 394 mW 308 391 LVDS Output Mode Full 439 mW 4 54 54 Standby Power Full 54 mW 0.05 0.15 0.05 0.15 Power-Down Power Full 0.05 .015 mW 1 The suffix following the part number refers to the model found in the Ordering Guide section. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). Rev. A | Page 4 of 44 AD9265 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. 2 2 2 AD9265BCPZ-80 AD9265BCPZ-105 AD9265BCPZ-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz 25°C 80.2 79.7 79.0 dBFS fIN = 70 MHz 25°C 79.7 79.2 79.0 dBFS Full 78.7 78.2 77.3 dBFS f = 140 MHz 25°C 78.4 78.3 77.5 dBFS IN f = 200 MHz 25°C 77.1 76.9 75.6 dBFS IN SIGNAL-TO-NOISE-AND DISTORTION (SINAD) f = 2.4 MHz 25°C 79.6 79.4 78.7 dBFS IN f = 70 MHz 25°C 79.6 78.8 78.7 dBFS IN Full 78.6 77.9 77.0 dBFS fIN = 140 MHz 25°C 77.3 77.5 77.0 dBFS 76.0 75.7 74.4 fIN = 200 MHz 25°C dBFS EFFECTIVE NUMBER OF BITS (ENOB) 25°C 12.9 12.9 12.8 Bits fIN = 2.4 MHz 25°C 12.9 12.8 12.8 Bits fIN = 70 MHz 25°C 12.5 12.6 12.5 Bits f = 140 MHz IN 25°C 12.3 12.3 12.1 Bits f = 200 MHz IN WORST SECOND OR THIRD HARMONIC 25°C dBc f = 2.4 MHz −88 −90 −88 IN 25°C dBc f = 70 MHz −94 −89 −93 IN Full −92 −88 −85 dBc 25°C dBc fIN = 140 MHz −82 −86 −89 25°C dBc fIN = 200 MHz −81 −81 −80 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 25°C dBc fIN = 2.4 MHz 88 90 88 25°C dBc fIN = 70 MHz 94 89 93 Full 92 dBc 88 85 25°C dBc f = 140 MHz 82 86 89 IN 25°C dBc f = 200 MHz 81 81 80 IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN @ −23 dBFS) f = 2.4 MHz 25°C 103 98 96 dBFS IN 25°C dBFS fIN = 70 MHz 103 96 98 25°C dBFS fIN = 140 MHz 104 96 98 25°C dBFS fIN = 200 MHz 102 101 97 With On-Chip Dither (AIN @ −23 dBFS) 25°C dBFS f = 2.4 MHz 110 108 108 IN 25°C dBFS fIN = 70 MHz 110 109 110 25°C dBFS fIN = 140 MHz 110 109 109 25°C dBFS fIN = 200 MHz 110 109 109 Rev. A | Page 5 of 44 AD9265 2 2 2 AD9265BCPZ-80 AD9265BCPZ-105 AD9265BCPZ-125 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER (HARMONIC OR SPUR) Without Dither 25°C dBc fIN = 2.4 MHz −106 −105 −101 25°C dBc fIN = 70 MHz −106 −104 −103 Full −97 −95 dBc −92 25°C dBc f = 140 MHz −104 −103 −104 IN 25°C dBc f = 200 MHz −102 −103 −100 IN With On-Chip Dither 25°C dBc fIN = 2.4 MHz −106 −105 −102 25°C dBc fIN = 70 MHz −106 −105 −103 Full −97 −99 dBc −98 25°C dBc f = 140 MHz −104 −103 −104 IN 25°C dBc fIN = 200 MHz −101 −101 −100 TWO-TONE SFDR Without Dither 25°C 93 90 dBc fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 95 25°C 80 78 dBc fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 79 25°C 650 650 MHz ANALOG INPUT BANDWIDTH 650 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 The suffix following the part number refers to the model found in the Ordering Guide section. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ Rev. A | Page 6 of 44 AD9265 Parameter Temperature Min Typ Max Unit 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUT/OUTPUT (SDIO/DCS) High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF High Level Output Voltage Full 1.70 V Low Level Output Voltage Full 0.2 V 2 LOGIC INPUTS (OEB, PDWN, DITHER, LVDS, LVDS_RS) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (DRVDD = 1.8 V) CMOS Mode High Level Output Voltage IOH = 50 μA Full 1.79 V I = 0.5 mA Full 1.75 V OH Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V LVDS Mode ANSI Mode Differential Output Voltage (V) Full 290 345 400 mV OD Output Offset Voltage (V) Full 1.15 1.25 1.35 V OS Reduced Swing Mode Differential Output Voltage (VOD) Full 160 200 230 mV Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V 1 Pull-up. 2 Pull-down. Rev. A | Page 7 of 44 AD9265 SWITCHING SPECIFICATIONS −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. 1 1 1 AD9265BCPZ-80 AD9265BCPZ-105 AD9265BCPZ-125 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 2 Conversion Rate DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 8 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns Divide-by-1 Mode, DCS Disabled 5.9 6.25 6.6 4.5 4.75 5.0 3.8 4 4.2 ns Divide-by-3 Mode, Divide-by-5 Mode, and Full 0.8 0.8 0.8 ns 3 Divide-by-7 Mode, DCS Enabled Divide-by-2 Mode, Divide-by-4 Mode, Divide- Full 0.8 0.8 0.8 ns by-6 Mode and Divide-by-8 Mode, DCS 3 Enabled or DCS Disabled Aperture Delay(t) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.07 0.07 0.07 ps rms J DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (t) Full 2.4 2.8 3.4 2.4 2.8 3.4 2.4 2.8 3.4 ns PD 4 DCO Propagation Delay (tDCO) Full 2.7 3.4 4.2 2.7 3.4 4.2 2.7 3.4 4.2 ns DCO to Data Skew (tSKEW) Full 0.3 0.6 0.9 0.3 0.6 0.9 0.3 0.6 0.9 ns Pipeline Delay (Latency) Full 12 12 12 Cycles LVDS Mode Data Propagation Delay (t) Full 2.6 3.4 4.2 2.6 3.4 4.2 2.6 3.4 4.2 ns PD 4 DCO Propagation Delay (tDCO) Full 3.3 3.8 4.3 3.3 3.8 4.3 3.3 3.8 4.3 ns DCO to Data Skew (tSKEW) Full −0.3 0.4 1.2 −0.3 0.4 1.2 −0.3 0.4 1.2 ns Pipeline Delay (Latency) Full 12.5 12.5 12.5 Cycles 5 Wake-Up Time Full 500 500 500 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 The suffix following the part number refers to the model found in the Ordering Guide section. 2 Conversion rate is the clock rate after the divider. 3 See the Input Clock Divider section for additional information on using the DCS with the input clock divider. 4 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. A | Page 8 of 44 AD9265 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.30 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t t CH CL t CLK CLK+ CLK– t DCO DCO/DCO+ DCO– t SKEW LVDS (DDR) MODE t PD D0/1+ TO D14/D15+ DEx DOx DEx DOx DEx DOx DEx DOx DEx DOx – 12 – 12 – 11 – 11 – 10 – 10 – 9 – 9 – 8 – 8 D0/1– TO D14/D15– CMOS MODE D0 TO D15 Dx – 12 Dx – 11 Dx – 10 Dx – 9 Dx – 8 NOTES 1. DEx DENOTES EVEN BIT. 2. DOx DENOTES ODD BIT. Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Input Timing Requirements Rev. A | Page 9 of 44 08502-104 08502-002 AD9265 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 6. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to AGND −0.3 V to +2.0V maximum rating conditions for extended periods may affect SVDD to AGND −0.3 V to +3.6 V device reliability. VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V THERMAL CHARACTERISTICS CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V The exposed paddle must be soldered to the ground plane for VREF to AGND −0.3 V to AVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the customer SENSE to AGND −0.3 V to AVDD + 0.2 V board increases the reliability of the solder joints and maximizes VCM to AGND −0.3 V to AVDD + 0.2 V the thermal capability of the package. RBIAS to AGND −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground CSB to AGND −0.3 V to SVDD +0.3 V plane. As shown, airflow improves heat dissipation, which SCLK/DFS to AGND −0.3 V to SVDD +0.3 V reduces θJA. In addition, metal in direct contact with the package SDIO/DCS to AGND −0.3V to SVDD + 0.3 V leads from metal traces, through holes, ground, and power OEB to AGND −0.3 V to DRVDD + 0.2 V planes, reduces the θ . JA PDWN to AGND −0.3 V to DRVDD + 0.2 V Table 7. Thermal Resistance LVDS to AGND −0.3 V to AVDD + 0.2 V Airflow LVDS_RS to AGND −0.3 V to AVDD + 0.2 V Velocity DITHER to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 Package Type (m/s) θJA θJC θJB Unit D0 through D15 to AGND −0.3 V to DRVDD + 0.2 V 0 24.5 1.3 12.7 °C/W 48-Lead LFCSP DCO to AGND −0.3 V to DRVDD + 0.2 V (CP-48-8) 1.0 21.4 °C/W Environmental 2.5 19.2 °C/W Operating Temperature Range −40°C to +85°C 1 (Ambient) Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Maximum Junction Temperature 150°C 3 Per MIL-Std 883, Method 1012.1. Under Bias 4 Per JEDEC JESD51-8 (still air). Storage Temperature Range −65°C to +150°C ESD CAUTION (Ambient) Rev. A | Page 10 of 44 AD9265 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SYNC 1 36 AVDD PIN 1 CLK+ 2 INDICATOR 35 DITHER 34 AVDD CLK– 3 AVDD 4 33 SVDD AVDD 5 32 CSB AD9265 OEB 6 31 SCLK/DFS PARALLEL DNC 7 30 SDIO/DCS CMOS DCO 8 29 DRVDD TOP VIEW (Not to Scale) D0 (LSB) 9 28 DNC 27 OR D1 10 D2 11 26 D15 (MSB) D3 12 25 D14 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE INPUT. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. LFCSP Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal). 33 SVDD Supply SPI Input/Output Voltage. 7, 28, 39, 40 DNC Do Not Connect. 0 AGND Ground Analog Ground. The exposed thermal pad on the bottom of the package provides the analog ground for the input. This exposed pad must be connected to ground for proper operation. ADC Analog 42 VIN+ Input Differential Analog Input Pin (+). 43 VIN− Input Differential Analog Input Pin (−). 38 VREF Input/output Voltage Reference Input/Output. 37 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 47 RBIAS Input/output External Reference Bias Resistor. 46 VCM Output Common-Mode Level Bias Output for Analog Inputs. 2 CLK+ Input ADC Clock Input—True. 3 CLK− Input ADC Clock Input—Complement. Digital Input 1 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 9 D0 (LSB) Output CMOS Output Data. 10 D1 Output CMOS Output Data. 11 D2 Output CMOS Output Data. 12 D3 Output CMOS Output Data. 14 D4 Output CMOS Output Data. 15 D5 Output CMOS Output Data. 16 D6 Output CMOS Output Data. 17 D7 Output CMOS Output Data. 18 D8 Output CMOS Output Data. Rev. A | Page 11 of 44 DRVDD 13 48 PDWN D4 14 47 RBIAS D5 15 46 VCM D6 16 45 AVDD D7 17 44 LVDS 43 VIN– D8 18 D9 19 42 VIN+ DRVDD 20 41 LVDS_RS D10 21 40 DNC D11 22 39 DNC D12 23 38 VREF D13 24 37 SENSE 08502-003 AD9265 Pin No. Mnemonic Type Description 19 D9 Output CMOS Output Data. 21 D10 Output CMOS Output Data. 22 D11 Output CMOS Output Data. 23 D12 Output CMOS Output Data. 24 D13 Output CMOS Output Data. 25 D14 Output CMOS Output Data. 26 D15 (MSB) Output CMOS Output Data. 27 OR Output Overrange Output. 8 DCO Output Data Clock Output. SPI Control 31 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 30 SDIO/DCS Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 32 CSB Input SPI Chip Select (Active Low). ADC Configuration 6 OEB Input Output Enable Input (Active Low). 35 DITHER Input In external pin mode, this pin sets dither to on (active high). Pull low for control via SPI in SPI mode. 41 LVDS_RS Input In external pin mode, this pin sets LVDS reduced swing output mode (active high). Pull low for control via SPI in SPI mode. 44 LVDS Input In external pin mode, this pin sets LVDS output mode (active high). Pull low for control via SPI in SPI mode. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 12 of 44 AD9265 SYNC 1 36 AVDD PIN 1 CLK+ 2 INDICATOR 35 DITHER CLK– 3 34 AVDD 33 SVDD AVDD 4 AVDD 5 32 CSB AD9265 OEB 6 31 SCLK/DFS INTERLEAVED DCO– 7 30 SDIO/DCS LVDS DCO+ 8 29 DRVDD TOP VIEW D0/1– (Not to Scale) 28 OR+ 9 D0/1+ 10 27 OR– D2/3– 11 26 D14/15+ 25 D2/3+ 12 D14/15– NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 5. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal). 33 SVDD Supply SPI Input/Output Voltage. 39, 40 DNC Do Not Connect. 0 AGND Ground Analog Ground. The exposed thermal pad on the bottom of the package provides the analog ground for the input. This exposed pad must be connected to ground for proper operation. ADC Analog 42 VIN+ Input Differential Analog Input Pin (+). 43 VIN− Input Differential Analog Input Pin (−). 38 VREF Input/output Voltage Reference Input/Output. 37 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 47 RBIAS Input/output External Reference Bias Resistor. 46 VCM Output Common-Mode Level Bias Output for Analog Inputs. 2 CLK+ Input ADC Clock Input—True. 3 CLK− Input ADC Clock Input—Complement. Digital Input 1 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 10 D0/1+ Output LVDS Output Data Bit 0/Bit 1 (LSB)—True. 9 D0/1− Output LVDS Output Data Bit 0/Bit 1 (LSB)—Complement. 12 D2/3+ Output LVDS Output Data Bit 2/Bit 3—True. 11 D2/3− Output LVDS Output Data Bit 2/Bit 3—Complement. 15 D4/5+ Output LVDS Output Data Bit 4/Bit 5—True. 14 D4/5− Output LVDS Output Data Bit 4/Bit 5—Complement. 17 D6/7+ Output LVDS Output Data Bit 6/Bit 7—True. 16 D6/7− Output LVDS Output Data Bit 6/Bit 7—Complement. 19 D8/9+ Output LVDS Output Data Bit 8/Bit 9 —True. 18 D8/9− Output LVDS Output Data Bit 8/Bit 9—Complement. Rev. A | Page 13 of 44 DRVDD 13 48 PDWN D4/5– 14 47 RBIAS D4/5+ 15 46 VCM D6/7– 16 45 AVDD D6/7+ 17 44 LVDS 43 VIN– D8/9– 18 D8/9+ 19 42 VIN+ DRVDD 20 41 LVDS_RS D10/11– 21 40 DNC D10/11+ 22 39 DNC D12/13– 23 38 VREF D12/13+ 24 37 SENSE 08502-004 AD9265 Pin No. Mnemonic Type Description 22 D10/11+ Output LVDS Output Data Bit 10/Bit 11—True. 21 D10/11− Output LVDS Output Data Bit 10/Bit 11—Complement. 24 D12/13+ Output LVDS Output Data Bit 12/Bit 13—True. 23 D12/13− Output LVDS Output Data Bit 12/Bit 13—Complement. 26 D14/15+ Output LVDS Output Data Bit 14/Bit 15 (MSB)—True. 25 D14/15− Output LVDS Output Data Bit 14/Bit 15 (MSB)—Complement. 28 OR+ Output LVDS Overrange Output—True. 27 OR− Output LVDS Overrange Output—Complement. 8 DCO+ Output LVDS Data Clock Output—True. 7 DCO− Output LVDS Data Clock Output—Complement. SPI Control 31 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 30 SDIO/DCS Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 32 CSB Input SPI Chip Select (Active Low). ADC Configuration 6 OEB Input Output Enable Input (Active Low). 35 DITHER Input In external pin mode, this pin sets dither to on (active high). Pull low for control via SPI in SPI mode. 41 LVDS_RS Input In external pin mode, this pin sets LVDS reduced swing output mode (active high). Pull low for control via SPI in SPI mode. 44 LVDS Input In external pin mode, this pin sets LVDS output mode (active high). Pull low for control via SPI in SPI mode. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 14 of 44 AD9265 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, sample rate = 125 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted. 0 0 80MSPS 80MSPS 2.4MHz @ –1dBFS 200.3MHz @ –1dBFS SNR = 79.2dB (80.2dBFS) SNR = 76.5dB (77.5dBFS) –20 –20 SFDR = 88.2dBc SFDR = 81.2dBc –40 –40 –60 –60 THIRD SECOND HARMONIC HARMONIC THIRD –80 –80 HARMONIC SECOND HARMONIC –100 –100 –120 –120 –140 –140 0 10203040 0 10203040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9265-80 Single-Tone FFT with f = 2.4 MHz Figure 9. AD9265-80 Single-Tone FFT with f = 200.3 MHz IN IN 0 0 80MSPS 80MSPS 70.1MHz @ –1dBFS 70.1MHz @ –6dBFS SNR = 78.7dB (79.7dBFS) SNR = 74.0dB (80.0dBFS) –20 –20 SFDR = 93.8dBc SFDR = 100dBc –40 –40 –60 –60 THIRD HARMONIC SECOND –80 –80 HARMONIC THIRD SECOND HARMONIC HARMONIC –100 –100 –120 –120 –140 –140 0 10203040 0 10203040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD9265-80 Single-Tone FFT with f = 70.1 MHz Figure 10. AD9265-80 Single-Tone FFT with f = 70.1 MHz @ −6 dBFS with IN IN Dither Enabled 0 120 80MSPS SFDR (dBFS) 140.1MHz @ –1dBFS SNR = 77.7dB (78.7dBFS) –20 100 SFDR = 82.2dBc SNR (dBFS) –40 80 THIRD –60 HARMONIC 60 SECOND HARMONIC SFDR (dBc) –80 40 –100 SNR (dBc) 20 –120 0 –140 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10203040 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 8. AD9265-80 Single-Tone FFT with f = 140.1 MHz Figure 11. AD9265-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with IN fIN = 98.12 MHz Rev. A | Page 15 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-108 08502-107 08502-106 SNR/SFDR (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-111 08502-110 08502-109 AD9265 120 450,000 2.17 LSB RMS SFDRFS (DITHER ON) 400,000 110 350,000 300,000 100 250,000 SFDRFS (DITHER OFF) 200,000 90 150,000 SNRFS (DITHER OFF) 100,000 80 SNRFS (DITHER ON) 50,000 70 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 15. AD9265-80 Grounded Input Histogram Figure 12. AD9265-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz With and Without Dither Enabled 100 4 INL WITHOUT DITHER INL WITH DITHER 3 95 SFDR @ +25°C SFDR @ +85°C 2 90 1 85 SNR @ –40°C 0 80 SFDR @ –40°C –1 75 SNR @ +25°C –2 SNR @ +85°C 70 –3 65 –4 0 50 100 150 200 250 300 0 10,000 20,000 30,000 40,000 50,000 60,000 INPUT FREQUENCY (MHz) OUTPUT CODE Figure 13. AD9265-80 Single-Tone SNR/SFDR vs. Figure 16. AD9265-80 INL with fIN = 12.5 MHz Input Frequency (fIN) and Temperature with 2 V p-p Full Scale 105 1.00 0.75 100 0.50 95 0.25 SFDR 90 0 –0.25 85 –0.50 SNR 80 –0.75 75 –1.00 25 30 35 40 45 50 55 60 65 70 75 80 0 10,000 20,000 30,000 40,000 50,000 60,000 SAMPLE RATE (MSPS) OUTPUT CODE Figure 14. AD9265-80 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 17. AD9265-80 DNL with f = 12.5 MHz IN with fIN = 70.1 MHz Rev. A | Page 16 of 44 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS) 08502-112 08502-114 08502-113 NUMBER OF HITS DNL ERROR (LSB) INL ERROR (LSB) N – 11 N – 10 N – 9 N – 8 N –7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N +9 N + 10 N + 11 08502-116 08502-117 08502-115 AD9265 0 0 105MSPS 105MSPS 2.4MHz @ –1dBFS 200.3MHz @ –1dBFS –20 SNR = 78.8dB (79.8dBFS) –20 SNR = 75.9dB (76.9dBFS) SFDR = 91dBc SFDR = 82dBc –40 –40 –60 –60 THIRD HARMONIC SECOND SECOND HARMONIC HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 1020304050 0 1020304050 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9265-105 Single-Tone FFT with fIN = 2.4 MHz Figure 21. AD9265-105 Single-Tone FFT with fIN = 200.3 MHz 0 0 105MSPS 105MSPS 70.1MHz @ –1dBFS 70.1MHz @ –6dBFS –20 SNR = 78.3dB (79.3dBFS) –20 SNR = 73.7dB (79.7dBFS) SFDR = 89dBc SFDR = 92dBc –40 –40 –60 –60 SECOND THIRD HARMONIC SECOND HARMONIC –80 –80 THIRD HARMONIC HARMONIC –100 –100 –120 –120 –140 –140 0 1020304050 0 1020304050 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. AD9265-105 Single-Tone FFT with fIN = 70.1 MHz Figure 22. AD9265-105 Single-Tone FFT with fIN = 70.1 MHz @ −6dBFS with Dither Enabled 120 0 105MSPS SFDR (dBFS) 140.1MHz @ –1dBFS –20 SNR = 77.3dB (78.3dBFS) 100 SFDR = 86dBc SNR (dBFS) –40 80 –60 THIRD SECOND 60 HARMONIC HARMONIC SFDR (dBc) –80 40 –100 SNR (dBc) 20 –120 0 –140 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 1020304050 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 23. AD9265-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with Figure 20. AD9265-105 Single-Tone FFT with fIN = 140.1 MHz fIN = 98.12 MHz Rev. A | Page 17 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-120 08502-119 08502-118 SNR/SFDR (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-122 08502-121 08502-123 AD9265 120 400,000 SFDRFS (DITHER ON) 2.28 LSB RMS 350,000 110 300,000 250,000 100 SFDRFS (DITHER OFF) 200,000 90 150,000 SNRFS (DITHER OFF) 100,000 80 SNRFS (DITHER ON) 50,000 70 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 27. AD9265-105 Grounded Input Histogram Figure 24. AD9265-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz with and without Dither Enabled 100 4 SFDR @ +25°C INL WITHOUT DITHER SFDR @ –40°C INL WITH DITHER 3 95 SFDR @ +85°C 2 90 1 85 SNR @ –40°C 0 80 –1 75 SNR @ +25°C –2 SNR @ +85°C 70 –3 65 –4 0 50 100 150 200 250 300 0 10,000 20,000 30,000 40,000 50,000 60,000 INPUT FREQUENCY (MHz) OUTPUT CODE Figure 25. AD9265-105 Single-Tone SNR/SFDR vs. Figure 28. AD9265-105 INL with fIN = 12.5 MHz Input Frequency (fIN) and Temperature with 2 V p-p Full Scale 105 1.00 0.75 100 0.50 SFDR 95 0.25 90 0 –0.25 85 –0.50 SNR 80 –0.75 75 –1.00 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 0 10,000 20,000 30,000 40,000 50,000 60,000 SAMPLE RATE (MSPS) OUTPUT CODE Figure 26. AD9265-105 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 29. AD9265-105 DNL with f = 12.5 MHz IN with fIN = 70.1 MHz Rev. A | Page 18 of 44 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS) 08502-124 08502-126 08502-125 NUMBER OF HITS DNL ERROR (LSB) INL ERROR (LSB) N – 11 N – 10 N – 9 N – 8 N –7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N +9 N + 10 N + 11 08502-128 08502-129 08502-127 AD9265 0 0 125MSPS 125MSPS 2.4MHz @ –1dBFS 140.1MHz @ –1dBFS –20 SNR = 78.0dB (79.0dBFS) –20 SNR = 76.6dB (77.6dBFS) SFDR = 88dBc SFDR = 89dBc –40 –40 –60 –60 SECOND HARMONIC SECOND THIRD HARMONIC HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 102030 40 5060 0 102030 40 5060 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. AD9265-125 Single-Tone FFT with fIN = 2.4 MHz Figure 33. AD9265-125 Single-Tone FFT with fIN = 140.1 MHz 0 0 125MSPS 125MSPS 30.3MHz @ –1dBFS 200.3MHz @ –1dBFS –20 SNR = 78.6dB (79.6dBFS) –20 SNR = 74.7dB (75.7dBFS) SFDR = 95dBc SFDR = 80dBc –40 –40 THIRD –60 –60 HARMONIC THIRD SECOND HARMONIC SECOND HARMONIC –80 –80 HARMONIC –100 –100 –120 –120 –140 –140 0 102030 40 5060 0 102030 40 5060 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. AD9265-125 Single-Tone FFT with fIN = 30.3 MHz Figure 34. AD9265-125 Single-Tone FFT with fIN = 200.3 MHz 0 0 125MSPS 125MSPS 70.1MHz @ –1dBFS 220.1MHz @ –1dBFS –20 SNR = 78.0dB (79.0dBFS) –20 SNR = 74.3dB (75.3dBFS) SFDR = 94dBc SFDR = 80dBc –40 –40 THIRD –60 –60 HARMONIC SECOND HARMONIC SECOND THIRD –80 HARMONIC HARMONIC –80 –100 –100 –120 –120 –140 –140 0 102030 40 5060 0 102030 40 5060 FREQUENCY (MHz) FREQUENCY (MHz) Figure 32. AD9265-125 Single-Tone FFT with fIN = 70.1 MHz Figure 35. AD9265-125 Single-Tone FFT with fIN = 220.1 MHz Rev. A | Page 19 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-132 08502-131 08502-130 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-135 08502-134 08502-133 AD9265 0 120 125MSPS SFDR (dBFS) 70.1MHz @ –6dBFS –20 SNR = 73.5dB (79.5dBFS) 100 SFDR = 98dBc SNR (dBFS) –40 80 –60 60 SFDR (dBc) –80 SECOND THIRD HARMONIC HARMONIC 40 –100 SNR (dBc) 20 –120 –140 0 0 102030 40 5060 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 36. AD9265-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS with Figure 39. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with Dither Enabled fIN = 2.4 MHz 120 125MSPS 0 SFDR (dBFS) 70.1MHz @ –23dBFS SNR = 57.3dBc (80.3dBFS) –15 SFDR = 75.1dBc 100 –30 SNR (dBFS) –45 80 –60 60 –75 SFDR (dBc) –90 2 5 40 3 –105 + 6 4 SNR (dBc) –120 20 –135 0 6 12 18 24 30 36 42 48 54 60 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 37. AD9265-125 Single-Tone FFT with f = 70.1 MHz @ −23 dBFS with IN Figure 40. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with Dither Disabled, 1M Sample fIN = 98.12 MHz 120 125MSPS 0 70.1MHz @ –23dBFS SFDRFS (DITHER ON) SNR = 56.8dBc (79.8dBFS) –15 SFDR = 86.8dBc 110 –30 –45 100 –60 –75 SFDRFS (DITHER OFF) –90 90 –105 2 + 4 5 3 SNRFS (DITHER OFF) 6 –120 80 SNRFS (DITHER ON) –135 70 6 12 18 24 30 36 42 48 54 60 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 38. AD9265-125 Single-Tone FFT with f = 70.1 MHz @ −23 dBFS with Figure 41. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude (A ) with IN IN Dither Enabled, 1M Sample f = 30 MHz With and Without Dither Enabled IN Rev. A | Page 20 of 44 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-138 08502-137 08502-136 SNR/SFDR (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 08502-141 08502-140 08502-139 AD9265 100 0 SFDR @ –40°C SFDR (dBc) 95 –20 SFDR @ +25°C 90 –40 SFDR @ +85°C IMD3 (dBc) 85 –60 SNR @ –40°C 80 –80 SFDR (dBFS) 75 –100 SNR @ +25°C SNR @ +85°C 70 –120 IMD3 (dBFS) 65 –140 0 50 100 150 200 250 300 –90 –78 –66 –54 –42 –30 –18 –6 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 42. AD9265-125 Single-Tone SNR/SFDR vs. Figure 45. AD9265-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Input Frequency (fIN) and Temperature with 2 V p-p Full Scale with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 125 MSPS 100 0 125MSPS 29.1MHz @ –7dBFS 95 –20 32.1MHz @ –7dBFS SFDR = 94.9dBc (101.9dBFS) SFDR 90 –40 85 –60 80 –80 75 –100 SNR 70 –120 65 –140 0 50 100 150 200 250 300 0 102030 40 5060 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 43. AD9265-125 Single-Tone SNR/SFDR vs. Figure 46. AD9265-125 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Input Frequency (fIN) with 1 V p-p Full Scale 0 0 125MSPS 169.1MHz @ –7dBFS SFDR (dBc) –20 172.1MHz @ –7dBFS –20 SFDR = 79.4dBc (86.4dBFS) –40 –40 IMD3 (dBc) –60 –60 –80 –80 SFDR (dBFS) –100 –100 –120 –120 IMD3 (dBFS) –140 –140 –90 –78 –66 –54 –42 –30 –18 –6 0 102030 40 5060 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 44. AD9265-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN Figure 47. AD9265-125 Two-Tone FFT with f = 169.1 MHz and IN1 with f = 29.1 MHz, f = 32.1 MHz, f = 125 MSPS IN1 IN2 S f = 172.1 MHz IN2 Rev. A | Page 21 of 44 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) SFDR/IMD3 (dBc AND dBFS) 08502-144 08502-143 08502-142 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 08502-147 08502-146 08502-145 AD9265 105 1.00 0.75 100 0.50 95 SFDR 0.25 90 0 –0.25 85 –0.50 SNR 80 –0.75 75 –1.00 25 35 45 55 65 75 85 95 105 115 125 0 10,000 20,000 30,000 40,000 50,000 60,000 SAMPLE RATE (MSPS) OUTPUT CODE Figure 51. AD9265-125 DNL with fIN = 9.7 MHz Figure 48. AD9265-125 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 70.1 MHz 450,000 100 2.13 LSB RMS SFDR 400,000 90 350,000 SNR 300,000 80 250,000 70 200,000 150,000 60 100,000 50 50,000 0 40 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 INPUT COMMON-MODE VOLTAGE (V) OUTPUT CODE Figure 49. AD9265-125 Grounded Input Histogram Figure 52. AD9265-125 SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30 MHz 4 INL WITHOUT DITHER INL WITH DITHER 3 2 1 0 –1 –2 –3 –4 0 10,000 20,000 30,000 40,000 50,000 60,000 OUTPUT CODE Figure 50. AD9265-125 INL with fIN = 9.7 MHz Rev. A | Page 22 of 44 NUMBER OF HITS SNR/SFDR (dBFS/dBc) INL ERROR (LSB) N – 11 N – 10 N – 9 N – 8 N –7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N +9 N + 10 N + 11 08502-150 08502-148 08502-149 SNR/SFDR (dBFS AND dBc) DNL ERROR (LSB) 08502-151 08502-152 AD9265 EQUIVALENT CIRCUITS AVDD VIN+ OR VIN– VREF 6kΩ Figure 53. Equivalent Analog Input Circuit Figure 57. Equivalent VREF Circuit AVDD SVDD 0.9V 26kΩ 10kΩ 10kΩ 350Ω CLK+ CLK– SDIO/DCS Figure 54. Equivalent Clock Input Circuit Figure 58. Equivalent SDIO/DCS Circuit DRVDD SVDD 350Ω SCLK/DFS PAD 26kΩ Figure 59. Equivalent SCLK/DFS Input Circuit Figure 55. Digital Output SVDD AVDD 26kΩ 350Ω 350Ω SENSE CSB Figure 56. Equivalent SENSE Circuit Figure 60. Equivalent CSB Input Circuit Rev. A | Page 23 of 44 08502-005 08502-007 08502-010 08502-006 08502-012 08502-011 08502-009 08502-008 AD9265 AVDD DITHER, 350Ω 350Ω LVDS OR PDWN LVDS_RS 26kΩ 26kΩ Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit Figure 61. Equivalent PDWN Circuit DRVDD 26kΩ 350Ω OEB Figure 62. Equivalent OEB Input Circuit Rev. A | Page 24 of 44 08502-061 08502-062 08502-063 AD9265 THEORY OF OPERATION A small resistor in series with each input can help reduce the With the AD9265, the user can sample any fS/2 frequency peak transient current required from the output stage of the segment from dc to 200 MHz, using appropriate low-pass or driving source. A shunt capacitor can be placed across the band-pass filtering at the ADC inputs with little loss in ADC inputs to provide dynamic charging currents. This passive performance. Operation to 300 MHz analog input is permitted, network creates a low-pass filter at the ADC input; therefore, but it occurs at the expense of increased ADC noise and distortion. the precise values are dependent on the application. Synchronization capability is provided to allow synchronized In intermediate frequency (IF) undersampling applications, any timing between multiple devices. shunt capacitors should be reduced. In combination with the Programming and control of the AD9265 are accomplished driving source impedance, the shunt capacitors limit the input using a 3-wire SPI-compatible serial interface. bandwidth. Refer to AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; AN-827 Application Note, ADC ARCHITECTURE A Resonant Approach to Interfacing Amplifiers to Switched- The AD9265 architecture consists of a front-end sample-and- Capacitor ADCs; and the Analog Dialogue article, “Transformer- hold input network, followed by a pipelined, switched-capacitor Coupled Front-End for Wideband A/D Converters,” for more ADC. The quantized outputs from each stage combine into a information on this subject (see www.analog.com). final 16-bit result in the digital correction logic. The pipelined BIAS architecture permits the first stage to operate on a new input S sample and the remaining stages to operate on the preceding S C C samples. Sampling occurs on the rising edge of the clock. S FB VIN+ Each stage of the pipeline, excluding the last, consists of a low C C PAR1 PAR2 resolution flash ADC connected to a switched-capacitor digital- H S S to-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between C S VIN– the reconstructed DAC output and the flash input for the next C C C FB PAR1 PAR2 S stage in the pipeline. One bit of redundancy is used in each stage S to facilitate digital correction of flash errors. The last stage simply BIAS consists of a flash ADC. Figure 64. Switched Capacitor Input The input stage can be ac- or dc-coupled in differential or For best dynamic performance, the source impedances driving single-ended modes. The output staging block aligns the data, VIN+ and VIN− should be matched, and the inputs should be corrects errors, and passes the data to the output buffers. The differentially balanced. output buffers are powered from a separate supply, allowing An internal differential reference buffer creates positive and adjustment of the output voltage swing. During power-down, negative reference voltages that define the input span of the ADC the output buffers go into a high impedance state. core. The span of the ADC core is set by this buffer to 2 × VREF. ANALOG INPUT CONSIDERATIONS Input Common Mode The analog input to the AD9265 is a differential switched- The analog inputs of the AD9265 are not internally dc biased. capacitor network that has been designed to give optimum In ac-coupled applications, the user must provide this bias performance while processing a differential input signal. externally. Setting the device so that VCM = 0.5 × AVDD is The clock signal alternatively switches between sample mode recommended for optimum performance, but the device and hold mode (see Figure 64). When the input is switched into functions over a wider range with reasonable performance (see sample mode, the signal source must be capable of charging the Figure 52). An on-board common-mode voltage reference is sample capacitors and settling within 1/2 of a clock cycle. included in the design and is available from the VCM pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Rev. A | Page 25 of 44 08502-037 AD9265 Dither Static Linearity The AD9265 has an optional dither mode that can be selected Dithering also removes sharp local discontinuities in the INL either through the SPI bus or by using the DITHER pin. Dithering transfer function of the ADC and reduces the overall peak-to- is the act of injecting a known but random amount of white noise, peak INL. commonly referred to as dither, into the input of the ADC. In receiver applications, utilizing dither helps to reduce DNL errors Dithering has the effect of improving the local linearity at that cause small signal gain errors. Often this issue is overcome various points along the ADC transfer function. Dithering by setting the input noise 5 dB to 10 dB above the converter can significantly improve the SFDR when quantizing small noise. By utilizing dither within the converter to correct the signal inputs, typically when the input level is below −6 dBFS. DNL errors, the input noise requirement can be reduced. As shown in Figure 65, the dither that is added to the input of Differential Input Configurations the ADC through the dither DAC is precisely subtracted out Optimum performance is achieved while driving the AD9265 in a digitally to minimize SNR degradation. When dithering is enabled, differential input configuration. For baseband applications, the the dither DAC is driven by a pseudorandom number generator AD8138, ADA4937-2, and ADA4938-2 differential drivers provide (PN gen). In the AD9265, the dither DAC is precisely calibrated excellent performance and a flexible interface to the ADC. to result in only a very small degradation in SNR and SINAD. The typical SNR and SINAD degradation values, with dithering The output common-mode voltage of the ADA4938 is easily set enabled, are only 1 dB and 0.8 dB, respectively. with the VCM pin of the AD9265 (see Figure 66), and the driver can be configured in the filter topology shown to provide band limiting of the input signal. VIN ADC CORE DOUT 15pF 200Ω 33Ω 15Ω 90Ω VIN– DITHER AVDD 76.8Ω VIN DAC 5pF ADC ADA4938-2 0.1µF 33Ω 15Ω PN GEN DITHER ENABLE VCM VIN+ 120Ω 15pF Figure 65. Dither Block Diagram 200Ω Large Signal FFT Figure 66. Differential Input Configuration Using the ADA4938-2 In most cases, dithering does not improve SFDR for large signal For baseband applications where SNR is a key parameter, inputs close to full scale, for example, with a −1 dBFS input. For differential transformer coupling is the recommended input large signal inputs, the SFDR is typically limited by front-end configuration. An example is shown in Figure 67. To bias the sampling distortion, which dithering cannot improve. However, analog input, the VCM voltage can be connected to the center even for such large signal inputs, dithering may be useful for tap of the secondary winding of the transformer. certain applications because it makes the noise floor whiter. C2 As is common in pipeline ADCs, the AD9265 contains small R2 VIN+ DNL errors caused by random component mismatches that R1 produce spurs or tones that make the noise floor somewhat 2V p-p 49.9Ω C1 ADC randomly colored part-to-part. Although these tones are R1 R2 VCM VIN– typically at very low levels and do not limit SFDR when the ADC is quantizing large signal inputs, dithering converts these 0.1µF C2 tones to noise and produces a whiter noise floor. Figure 67. Differential Transformer-Coupled Configuration Small Signal FFT The signal characteristics must be considered when selecting For small signal inputs, the front-end sampling circuit typically a transformer. Most RF transformers saturate at frequencies contributes very little distortion, and, therefore, the SFDR is likely below a few megahertz (MHz). Excessive signal power can also to be limited by tones caused by DNL errors due to random com- cause core saturation, which leads to distortion. ponent mismatches. Therefore, for small signal inputs (typically, those below −6 dBFS), dithering can significantly improve At input frequencies in the second Nyquist zone and above, the SFDR by converting these DNL tones to white noise. noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9265. For applications in Rev. A | Page 26 of 44 08502-038 08502-040 08502-039 AD9265 which SNR is a key parameter, differential double balun coupling Table 10. Example RC Network is the recommended input configuration (see Figure 68). In this Frequency Range R1 Series C1 Differential R2 Series C2 Shunt configuration, the input is ac-coupled and the CML is provided (MHz) (Ω Each) (pF) (Ω Each) (pF Each) to each input through a 33 Ω resistor. These resistors compensate 0 to 100 15 18 15 Open for losses in the input baluns to provide a 50 Ω impedance to 100 to 300 10 10 10 10 the driver. An alternative to using a transformer-coupled input at fre- In the double balun and transformer configurations, the value of quencies in the second Nyquist zone and higher is to use the the input capacitors and resistors is dependent on the input fre- ADL5562 differential driver. The ADL5562 provides three quency and source impedance and may need to be reduced or selectable gain options up to 15.5 dB. An example circuit is removed. Table 10 displays recommended values to set the RC shown in Figure 69; additional filtering between the ADL5562 network. However, these values are dependent on the input output and the AD9265 input may be required to reduce out-of- signal and should be used only as a starting guide. band noise. See the ADL5562 data sheet for more information. C2 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– C2 Figure 68. Differential Double Balun Input Configuration V CC 10pF 0.1µF 0.1µF 0Ω 5, 6, 7, 8 2 0.1µF ANALOG INPUT 20Ω 15Ω 15Ω 11 VIN+ 1 100Ω 5pF AD9265 ADL5562 100Ω 0.1µF 4 10 15Ω 15Ω VCM VIN– 3 20Ω 9 ANALOG INPUT 0Ω 0.1µF 0.1µF 10pF 0.1µF Figure 69. Differential Input Configuration Using the ADL5562 Rev. A | Page 27 of 44 08502-041 08502-042 AD9265 the reference amplifier in a noninverting mode with the VREF VOLTAGE REFERENCE output defined as follows: A stable and accurate voltage reference is built into the AD9265. R2   The input range can be adjusted by varying the reference voltage VREF 0.5 1   R1 applied to the AD9265, using either the internal reference or an   externally applied reference voltage. The input span of the ADC The input range of the ADC always equals twice the voltage at tracks reference voltage changes linearly. The various reference the reference pin for either an internal or an external reference. modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of VIN+ VIN– the reference. Internal Reference Connection ADC A comparator within the AD9265 detects the potential at the CORE SENSE pin and configures the reference into four possible modes, which are summarized in Table 11. If SENSE is grounded, the VREF reference amplifier switch is connected to the internal resistor 1.0µF 0.1µF R2 SELECT divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full- LOGIC SENSE scale input. In this mode, with SENSE grounded, the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of 0.5V R1 Register 0x18. These bits can be used to change the full scale to 1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p, ADC as shown in Table 17. Figure 71. Programmable Reference Configuration Connecting the SENSE pin to the VREF pin switches the reference amplifier output to the SENSE pin, completing the loop and pro- If the internal reference of the AD9265 is used to drive multiple viding a 0.5 V reference output for a 1 V p-p full-scale input. converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows VIN+ VIN– how the internal reference voltage is affected by loading. 0 ADC CORE –0.5 VREF = 0.5V VREF –1.0 1.0µF 0.1µF SELECT VREF = 1V LOGIC –1.5 SENSE 0.5V –2.0 ADC –2.5 Figure 70. Internal Reference Configuration –3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 If a resistor divider is connected external to the chip, as shown LOAD CURRENT (mA) in Figure 71, the switch again sets to the SENSE pin. This puts Figure 72. VREF Accuracy vs. Load Table 11. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × external reference Internal Fixed Reference VREF 0.5 1.0 R2   Programmable Reference 0.2 V to VREF 0.5 1 (see Figure 71) 2 × VREF   R1   Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. A | Page 28 of 44 08502-043 REFERENCE VOLTAGE ERROR (%) 08502-044 08502-045 AD9265 External Reference Operation The RF balun configuration is recommended for clock frequencies at 625 MHz and the RF transformer is recommended for clock The use of an external reference may be necessary to enhance frequencies from 10 MHz to 200 MHz. The back-to-back Schottky the gain accuracy of the ADC or improve thermal drift charac- diodes across the transformer/balun secondary limit clock excur- teristics. Figure 73 shows the typical drift characteristics of the sions into the AD9265 to approximately 0.8 V p-p differential. internal reference in 1.0 V mode. 2.0 This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9265 while 1.5 preserving the fast rise and fall times of the signal that are critical VREF = 1.0V 1.0 to low jitter performance. 0.5 ® Mini-Circuits ADC ADT1-1WT, 1:1Z AD9265 0 0.1µF 0.1µF XFMR CLOCK CLK+ INPUT –0.5 100Ω 50Ω 0.1µF CLK– –1.0 SCHOTTKY 0.1µF DIODES: –1.5 HSMS2822 Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz) –2.0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 73. Typical VREF Drift Update Figure ADC AD9265 1nF 0.1µF When the SENSE pin is tied to AVDD, the internal reference is CLOCK CLK+ INPUT disabled, allowing the use of an external reference. An internal 50Ω 0.1µF reference buffer loads the external reference with an equivalent 1nF CLK– 6 kΩ load (see Figure 57). The internal buffer generates the SCHOTTKY DIODES: HSMS2822 positive and negative full-scale references for the ADC core. Figure 76. Balun-Coupled Differential Clock (625 MHz) Therefore, the external reference must be limited to a maximum of 1.0 V. If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input CLOCK INPUT CONSIDERATIONS pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ For optimum performance, the AD9265 sample clock inputs, AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/ CLK+ and CLK−, should be clocked with a differential signal. AD9522 clock drivers offer excellent jitter performance. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 74) and require no external bias. 0.1µF 0.1µF CLOCK CLK+ AVDD INPUT ADC AD95xx 100Ω PECL DRIVER AD9265 0.1µF 0.1µF CLOCK CLK– 0.9V INPUT 240Ω 240Ω 50kΩ 50kΩ CLK+ CLK– Figure 77. Differential PECL Sample Clock (Up To Rated Sample Rate) 4pF 4pF A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ Figure 74. Equivalent Clock Input Circuit AD9518/AD9520/AD9522 clock drivers offer excellent jitter Clock Input Options performance. The AD9265 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 75 and Figure 76 show two preferred methods for clocking the AD9265. A low jitter clock source is converted from a single- ended signal to a differential signal using either an RF transformer or an RF balun. Rev. A | Page 29 of 44 REFERENCE VOLTAGE ERROR (mV) 08502-047 08502-046 08502-049 08502-048 08502-050 AD9265 The DCS is enabled by setting the SDIO/DCS pin high when operating in the external pin mode (see Table 12). If the SPI 0.1µF 0.1µF CLOCK CLK+ mode is enabled, the DCS is enabled by default and can be INPUT ADC AD95xx disabled by writing a 0x00 to Address 0x09. 100Ω LVDS DRIVER AD9265 0.1µF 0.1µF CLOCK Input Clock Divider CLK– INPUT 50kΩ 50kΩ The AD9265 contains an input clock divider with the ability to divide the input clock by integer values between 2 and 8. For Figure 78. Differential LVDS Sample Clock (Up to Rated Sample Rate) clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (DCS) In some applications, it may be acceptable to drive the sample is not required because the output of the divider inherently clock inputs with a single-ended CMOS signal. In such applica- produces a 50% duty cycle. Enabling the DCS with the clock tions, drive the CLK+ pin directly from a CMOS gate, and bypass divider in these divide modes may cause a slight degradation the CLK− pin to ground with a 0.1 μF capacitor (see Figure 79). in SNR; therefore, disabling the DCS is recommended. For other divide ratios, divide-by-3, divide-by-5, and divide-by-7, V CC the duty cycle output from the clock divider is related to the OPTIONAL 0.1µF 0.1µF 1kΩ 100Ω AD95xx input clock’s duty cycle. In these modes, if the input clock has CLOCK CLK+ CMOS DRIVER INPUT a 50% duty cycle, the DCS is again not required. However, if a 1 ADC 1kΩ 50Ω AD9265 50% duty cycle input clock is not available, the DCS must be CLK– enabled for proper part operation. 0.1µF The AD9265 clock divider can be synchronized using an external 1 50Ω RESISTOR IS OPTIONAL. sync signal applied to the SYNC pin input. Bit 1 and Bit 2 of Reg- Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) ister 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register Clock Duty Cycle is written. A valid signal at the SYNC pin causes the clock divider Typical high speed ADCs use both clock edges to generate to reset to its initial state. This synchronization feature allows a variety of internal timing signals and, as a result, may be multiple parts to have their clock dividers aligned to guarantee sensitive to clock duty cycle. Commonly, a ±5% tolerance is simultaneous input sampling. If the SYNC pin is not used, it required on the clock duty cycle to maintain dynamic should be tied to AGND. performance characteristics. Jitter Considerations The AD9265 contains a duty cycle stabilizer (DCS) that retimes High speed, high resolution ADCs are sensitive to the quality the nonsampling (falling) edge, providing an internal clock signal of the clock input. The degradation in SNR from the low frequency with a nominal 50% duty cycle. This allows the user to provide a SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) wide range of clock input duty cycles without affecting the perfor- can be calculated by mance of the AD9265. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled. (SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS Jitter in the rising edge of the input is still of paramount concern In the equation, the rms aperture jitter represents the clock input and is not easily reduced by the internal stabilization circuit. jitter specification. IF undersampling applications are particularly The duty cycle control loop does not function for clock rates sensitive to jitter, as illustrated in Figure 80. less than 20 MHz nominally. The loop has a time constant 80 associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 0.05ps 75 1.5 μs to 5 μs is required after a dynamic clock frequency increase MEASURED or decrease before the DCS loop is relocked to the input signal. 70 During the time period that the loop is not locked, the DCS loop is 0.20ps bypassed, and the internal device timing is dependent on the duty 65 cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. The DCS can also be 0.50ps 60 disabled in some cases when using the input clock divider circuit, see the Input Clock Divider section for additional information. In 55 1.00ps all other applications, enabling the DCS circuit is recommended 1.50ps to maximize ac performance. 50 1 10 100 1k INPUT FREQUENCY (MHz) Figure 80. SNR vs. Input Frequency and Jitter Rev. A | Page 30 of 44 08502-052 08502-051 SNR (dBc) 08502-053 AD9265 0.5 0.20 Treat the clock input as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9265. To avoid modulating the clock signal with digital noise, separate 0.4 0.16 power supplies for clock drivers from the ADC output driver IAVDD supplies. Low jitter, crystal controlled oscillators make the best 0.3 0.12 clock sources. If the clock is generated from another type of source TOTAL POWER (by gating, dividing, or another method), the output clock should 0.2 0.08 be retimed by the original clock at the last step. Refer to AN-501 Application Note, Aperture Uncertainty and 0.1 0.04 ADC System Performance, and AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter IDRVDD (see www.analog.com) for more information about jitter perfor- 0 0 25 35 45 55 65 75 85 95 105 mance as it relates to ADCs. CLOCK FREQUENCY (MSPS) POWER DISSIPATION AND STANDBY MODE Figure 82. AD9265-105 Power and Current vs. Sample Rate As shown in Figure 81, the power dissipated by the AD9265 is 0.5 0.15 proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the 0.4 0.12 digital drivers and the load on each output bit. IAVDD The maximum DRVDD current (IDRVDD) can be 0.3 0.09 approximately calculated as TOTAL POWER IDRVDD = VDRVDD × C × f × N LOAD CLK 0.2 0.06 where N is the number of output bits (16 data bits plus 1 DCO, in the case of the AD9265). 0.1 0.03 This maximum current occurs when every output bit switches on IDRVDD every clock cycle, that is, a full-scale square wave at the Nyquist 0 0 frequency of fCLK/2. In practice, the DRVDD current is established 25 35 45 55 65 75 ENCODE FREQUENCY (MSPS) by the average number of output bits switching, which is Figure 83. AD9265-80 Power and Current vs. Sample Rate determined by the sample rate and the characteristics of the analog input signal. By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9265 is placed in power-down mode. Reducing the capacitive load presented to the output drivers can In this state, the ADC typically dissipates 0.05 mW. During power- minimize digital power consumption. The data shown in Figure 81, down, the output drivers are placed in a high impedance state. Figure 82, and Figure 83 were taken using a 70 MHz analog input Asserting the PDWN pin low returns the AD9265 to its normal signal with a 5 pF load on each output driver. operating mode. 0.5 0.20 Low power dissipation in power-down mode is achieved by IAVDD shutting down the reference, reference buffer, biasing networks, 0.4 0.16 and clock. Internal capacitors are discharged when entering power- down mode and then must be recharged when returning to normal 0.3 0.12 TOTAL operation. POWER When using the SPI port interface, the user can place the ADC 0.2 0.08 in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when 0.1 0.04 faster wake-up times are required. In addition, when using the SPI mode, the user can change the function of the external PDWN pin IDRVDD to either place the part in power-down or standby mode. See the 0 0 25 50 75 100 125 Memory Map Register Description section for more details. CLOCK FREQUENCY (MSPS) Figure 81. AD9265-125 Power and Current vs. Sample Rate Rev. A | Page 31 of 44 TOTAL POWER (W) SUPPLY CURRENT (A) 08502-179 TOTAL POWER (W) TOTAL POWER (W) SUPPLY CURRENT (A) SUPPLY CURRENT (A) 08502-181 08502-180 AD9265 Digital Output Enable Function (OEB) DIGITAL OUTPUTS The AD9265 has a flexible three-state ability for the digital output The AD9265 output drivers can be configured to interface with pins. The three-state mode is enabled using the OEB pin or 1.8 V CMOS logic families. The AD9265 can also be configured through the SPI interface. If the OEB pin is low, the output data for LVDS outputs using a DRVDD supply voltage of 1.8 V. The drivers and DCOs are enabled. If the OEB pin is high, the output AD9265 defaults to CMOS output mode but can be placed into data drivers and DCOs are placed in a high impedance state. This LVDS mode either by setting the LVDS pin high or by using the SPI OEB function is not intended for rapid access to the data bus. port to place the part into LVDS mode. Because most users do not Note that OEB is referenced to the output driver supply (DRVDD) toggle between CMOS and LVDS mode during operation, use of and should not exceed that supply voltage. the LVDS pin is recommended to avoid any power-up loading issues on the CMOS configured outputs. When using the SPI interface, the data and DCO outputs can be three-stated by using the output enable bar bit in Register 0x14. In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. TIMING However, large drive currents tend to cause current glitches on The AD9265 provides latched data with a pipeline delay of the supplies, which may affect converter performance. Applications 12 clock cycles (12.5 clock cycles in LVDS mode). Data outputs requiring the ADC to drive large capacitive loads or large are available one propagation delay (tPD) after the rising edge of fanouts may require external buffers or latches. the clock signal. In LVDS output mode two output drive levels can be selected, Minimize the length of the output data lines and loads placed either ANSI LVDS or reduced swing LVDS mode. Using the on them to reduce transients within the AD9265. These reduced swing LVDS mode lowers the DRVDD current and transients can degrade converter dynamic performance. reduces power consumption. The reduced swing LVDS mode The lowest typical conversion rate of the AD9265 is 10 MSPS. can be selected by asserting the LVDS_RS pin or by selecting At clock rates below 10 MSPS, dynamic performance can degrade. this mode via the SPI port. The output data format is selected for either offset binary or Data Clock Output (DCO) twos complement by setting the SCLK/DFS pin when operating in The AD9265 provides a single data clock output (DCO) pin in the external pin mode (see Table 12). CMOS output mode and two differential data clock output (DCO) pins in LVDS mode intended for capturing the data in an external As detailed in AN-877 Application Note, Interfacing to High register. In CMOS output mode, the data outputs are valid on the Speed ADCs via SPI, the data format can be selected for offset rising edge of DCO, unless the DCO clock polarity has been binary, twos complement, or gray code when using the SPI control. changed via the SPI. In LVDS output mode, data is output as Table 12. SCLK/DFS Mode Selection (External Pin Mode) double data rate with the even numbered output bits transitioning Voltage at near the rising edge of DCO and the odd numbered output bits Pin SCLK/DFS SDIO/DCS transitioning near the falling edge of DCO. See Figure 2 for a AGND Offset binary (default) DCS disabled graphical timing description. SVDD Twos complement DCS enabled (default) Table 13. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 0000 1000 0000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111 1 Rev. A | Page 32 of 44 AD9265 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9265 includes built-in test features designed to enable The outputs are not disconnected during this test, so the PN verification of the integrity of the part as well as facilitate board sequence can be observed as it runs. The PN sequence can be level debugging. A BIST (built-in self-test) feature is included that continued from its last value or reset from the beginning, based verifies the integrity of the digital datapath of the AD9265. Various on the value programmed in Register 0x0E, Bit 2. The BIST output test options are also provided to place predictable values on signature result varies based on the part configuration. the outputs of the AD9265. OUTPUT TEST MODES BUILT-IN SELF-TEST (BIST) The output test options are shown in Table 17. When an output The BIST is a thorough test of the digital portion of the selected test mode is enabled, the analog section of the ADC is discon- AD9265 signal path. When enabled, the test runs from an internal nected from the digital back end blocks and the test pattern is run pseudorandom noise (PN) source through the digital datapath through the output formatting block. Some of the test patterns are starting at the ADC block output. The BIST sequence runs for subject to output formatting, and some are not. The seed value for 512 cycles and stops. The BIST signature value is placed in the PN sequence tests can be forced if the PN reset bits are used Register 0x24 and Register 0x25. to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. A | Page 33 of 44 AD9265 SERIAL PORT INTERFACE (SPI) The AD9265 serial port interface (SPI) allows the user to configure All data is composed of 8-bit words. The first bit of the first byte the converter for specific functions or operations through a in a multibyte serial data transfer frame indicates whether a read structured register space provided inside the ADC. The SPI command or a write command is issued. This allows the serial gives the user added flexibility and customization, depending on data input/output (SDIO) pin to change direction from an input the application. Addresses are accessed via the serial port and to an output. can be written to or read from via the port. Memory is organized In addition to word length, the instruction phase determines into bytes that can be further divided into fields, which are docu- whether the serial frame is a read or write operation, allowing mented in the Memory Map section. For detailed operational the serial port to be used both to program the chip and to read information, see AN-877 Application Note, Interfacing to High the contents of the on-chip memory. If the instruction is a readback Speed ADCs via SPI. operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output CONFIGURATION USING THE SPI at the appropriate point in the serial frame. Three pins define the SPI of this ADC: the SCLK/DFS pin, the Data can be sent in MSB-first mode or in LSB-first mode. MSB SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS first is the default on power-up and can be changed via the SPI (a serial clock) is used to synchronize the read and write data port configuration register. For more information about this presented from and to the ADC. The SDIO/DCS (serial data and other features, see AN-877 Application Note, Interfacing to input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The High Speed ADCs via SPI. CSB (chip select bar) is an active low control that enables or HARDWARE INTERFACE disables the read and write cycles. The pins described in Table 14 comprise the physical interface Table 14. Serial Port Interface Pins between the user programming device and the serial port of the Pin Mnemonic Function AD9265. The SCLK pin and the CSB pin function as inputs SCLK/DFS Serial clock. The SCLK function of the pin is for when using the SPI interface. The SDIO pin is bidirectional, the serial shift clock input, which is used to functioning as an input during write phases and as an output synchronize serial interface reads and writes. during readback. SDIO/DCS SDIO is the serial data input/output function The AD9265 has a separate supply pin for the SPI interface, of the pin. A dual-purpose pin that typically serves as an input or an output, depending on SVDD. The SVDD pin can be set at any level between 1.8 V the instruction being sent and the relative and 3.3 V to enable operation with a SPI bus at these voltages position in the timing frame. without requiring level translation. If the SPI port is not used, CSB Chip select bar. An active low control that SVDD can be tied to the DRVDD voltage. gates the read and write cycles. The SPI interface is flexible enough to be controlled by either The falling edge of the CSB, in conjunction with the rising edge FPGAs or microcontrollers. One method for SPI configuration of the SCLK, determines the start of the framing. See Figure 84 is described in detail in AN-812 Application Note, Microcontroller- and Table 5 for an example of the serial timing and its Based Serial Port Interface (SPI) Boot Circuit. definitions. The SPI port should not be active during periods when the full Other modes involving the CSB are available. The CSB can be dynamic performance of the converter is required. Because the held low indefinitely, which permanently enables the device; SCLK signal, the CSB signal, and the SDIO signal are typically this is called streaming. The CSB can stall high between bytes to asynchronous to the ADC clock, noise from these signals can allow for additional external timing. When CSB is tied high at degrade converter performance. If the on-board SPI bus is used for power-up, SPI functions are placed in high impedance mode. other devices, it may be necessary to provide buffers between This mode turns on any SPI pin secondary functions. When this bus and the AD9265 to prevent these signals from transi- CSB is toggled low after power-up, the part remains in SPI tioning at the converter inputs during critical sampling periods. mode and does not revert back to pin mode. Some pins serve a dual function when the SPI interface is not During an instruction phase, a 16-bit instruction is transmitted. being used. When the pins are tied to AVDD or ground during Data follows the instruction phase, and its length is determined device power-on, they are associated with a specific function. by the W0 and W1 bits. The Digital Outputs section describes those alternate functions that are supported on the AD9265. Rev. A | Page 34 of 44 AD9265 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, Table 16 provides a brief description of the general features that the SDIO/DCS pin and the SCLK/DFS pin serve as standalone are accessible via the SPI. These features are described in detail CMOS-compatible control pins. When the device is powered in AN-877 Application Note, Interfacing to High Speed ADCs via up, it is assumed that the user intends to use the pins as static SPI. The AD9265 part-specific features are described in detail control lines for the duty cycle stabilizer and output data format following Table 17, the external memory map register table. feature control. In this mode, connect the CSB chip select to Table 16. Features Accessible Using the SPI AVDD, which disables the serial port interface. Feature The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS Name Description pin, and the PDWN pin are active control lines in both external Mode Allows the user to set either power-down mode or pin mode and SPI mode. The input from these pins or the SPI standby mode register setting is used to determine the mode of operation for Clock Allows the user to access the DCS, set the clock the part. divider, set the clock divider phase, and enable the SYNC input Table 15. Mode Selection Offset Allows the user to digitally adjust the converter offset External Pin Voltage Configuration Test I/O Allows the user to set test modes to have known data on output bits SDIO/DCS SVDD (default) Duty cycle stabilizer enabled Output Mode Allows the user to set the output mode AGND Duty cycle stabilizer disabled Output Phase Allows the user to set the output clock polarity SCLK/DFS SVDD Twos complement enabled Output Delay Allows the user to vary the DCO delay AGND (default) Offset binary enabled VREF Allows the user to set the reference voltage OEB DRVDD Outputs in high impedance AGND (default) Outputs enabled PDWN AVDD Chip in power-down or standby mode AGND (default) Normal operation LVDS AGND (default) CMOS output mode AVDD LVDS output mode LVDS_RS AGND (default) ANSI LVDS output levels AVDD Reduced swing LVDS output levels DITHER AGND (default) Dither disabled AVDD Dither enabled t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 84. Serial Port Interface Timing Diagram Rev. A | Page 35 of 44 08502-055 AD9265 MEMORY MAP open (for example, Address 0x18). If the entire address location READING THE MEMORY MAP REGISTER TABLE is open (for example, Address 0x13), this address location should Each row in the memory map register table has eight bit locations. not be written. The memory map is roughly divided into four sections: the chip Default Values configuration registers (Address 0x00 to Address 0x02); the After the AD9265 is reset, critical registers are loaded with transfer register (Address 0xFF); the ADC functions registers, default values. The default values for the registers are given in including setup, control, and test (Address 0x08 to Address 0x30); and the digital feature control register (Address 0x100). the memory map register table, Table 17. The memory map register table (see Table 17) documents the Logic Levels default hexadecimal value for each hexadecimal address shown. An explanation of logic level terminology follows: The column with the heading, Bit 7 (MSB), is the start of the  “Bit is set” is synonymous with “bit is set to Logic 1” or default hexadecimal value given. For example, Address 0x18, “writing Logic 1 for the bit.” the VREF select register, has a hexadecimal default value of 0xC0.  “Clear a bit” is synonymous with “bit is set to Logic 0” or This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. “writing Logic 0 for the bit.” This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this Transfer Register Map function and others, see AN-877 Application Note, Interfacing to Address 0x08 to Address 0x18 are shadowed. Writes to these High Speed ADCs via SPI. This document details the functions addresses do not affect part operation until a transfer command controlled by Register 0x00 to Register 0xFF. The remaining is issued by writing 0x01 to Address 0xFF, setting the transfer bit. register, Register 0x100, is documented in the Memory Map This allows these registers to be updated internally and simulta- Register Description section. neously when the transfer bit is set. The internal update takes Open Locations place when the transfer bit is set, and the bit autoclears. All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is Rev. A | Page 36 of 44 AD9265 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Default Addr. Register Value Default Notes/ (Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB 0 0x18 The nibbles are configuration first mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit Chip ID[7:0], AD9265 = 0x64 (default) 0x64 Read only 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade ID used to 01 = 125 MSPS differentiate 10 = 105 MSPS devices; read 11 = 80 MSPS only Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Functions Registers 0x08 Power 1 Open External Open Open Open Internal 0x80 Determines modes power-down power-down various generic pin function mode modes of chip operation 0 = power- 00 = normal down operation 1 = standby 01 = full power- down 10 = standby 11 = normal operation 0x09 Global clock Open Open Open Open Open Open Open Duty 0x01 cycle stabilizer (default) 0x0D Test mode Open Open Reset PN23 Reset PN9 Open Output test mode 0x00 When this generator generator register is set, 000 = off (default) the test data is 001 = midscale short placed on the 010 = positive FS output pins in 011 = negative FS place of normal data 100 = alternating checkerboard 101 = PN 23 sequence 110 = PN 9 sequence 111 = one/zero word toggle 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST 0x04 sequence enable Rev. A | Page 37 of 44 AD9265 Default Addr. Register Value Default Notes/ (Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Comments 0x14 Output Drive Output Open Output Open Output Output 0x00 Configures the mode strength type enable invert format outputs and bar the format of 0 = ANSI LVDS 0 = CMOS 00 = offset binary the data 1 = reduced 1 = LVDS 01 = twos LVDS complement 01 = gray code 11 = offset binary 0x16 Clock phase Invert DCO Open Open Open Open Input clock divider phase adjust 0x00 Allows control clock selection of 000 = no delay clock delays 001 = 1 input clock cycle into the input 010 = 2 input clock cycles clock divider 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 DCO output Open Open Open DCO clock delay 0x00 delay (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps … 11110 = 2419 ps 11111 = 2500 ps 0x18 VREF select Reference voltage selection Open Open Open Open Open Open 0xC0 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) 0x24 BIST BIST Signature[7:0] 0x00 Read only signature LSB 0x25 BIST BIST Signature[15:8] 0x00 Read only signature MSB 0x30 Dither Open Open Open Dither Open Open Open Open 0x00 enable enable Digital Feature Control Register 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x00 divider divider sync next sync sync enable only enable Rev. A | Page 38 of 44 AD9265 and to ignore the rest. The clock divider sync enable bit (Address MEMORY MAP REGISTER DESCRIPTIONS 0x100, Bit 1) resets after it syncs. For additional information about functions controlled in Bit 1—Clock Divider Sync Enable Register 0x00 to Register 0xFF, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Bit 1 gates the sync pulse to the clock divider. The sync signal is Sync Control (Register 0x100) enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bits[7:3]—Reserved Bit 0—Master Sync Enable These bits are reserved. Bit 0 must be high to enable any of the sync functions. If the Bit 2—Clock Divider Next Sync Only sync capability is not used, this bit should remain low to If the master sync enable bit (Address 0x100, Bit 0) and the conserve power. clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives Rev. A | Page 39 of 44 AD9265 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the lowest DESIGN GUIDELINES possible resistive thermal path for heat dissipation to flow through Before starting design and layout of the AD9265 as a system, the bottom of the PCB. Fill or plug these vias with nonconductive it is recommended that the designer become familiar with these epoxy. guidelines, which discuss the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements that are needed for certain pins. the PCB, overlay a silkscreen to partition the continuous plane on Power and Ground Recommendations the PCB into several uniform sections. This provides several tie When connecting power to the AD9265, it is recommended that points between the ADC and the PCB during the reflow process. two separate 1.8 V supplies be used. Use one supply for analog Using one continuous plane with no partitions guarantees only one (AVDD); use a separate supply for the digital outputs (DRVDD). tie point between the ADC and the PCB. For detailed information Several different decoupling capacitors can be used to cover both about packaging and PCB layout of chip scale packages, see high and low frequencies. Locate these capacitors close to the AN-772 Application Note, A Design and Manufacturing Guide point of entry at the PCB level and close to the pins of the part, for the Lead Frame Chip Scale Package (LFCSP), at with minimal trace length. The power supply for the SPI port, www.analog.com. SVDD, should not contain excessive noise and should also be VCM bypassed close to the part. Decouple the VCM pin to ground with a 0.1 μF capacitor, as A single PCB ground plane should be sufficient when using the shown in Figure 67. AD9265. With proper decoupling and smart partitioning of the RBIAS PCB analog, digital, and clock sections, optimum performance The AD9265 requires that a 10 kΩ resistor be placed between is easily achieved. the RBIAS pin and ground. This resistor sets the master current LVDS Operation reference of the ADC core and should have at least a 1% tolerance. The AD9265 can be configured for CMOS or LVDS output mode Reference Decoupling on power-up using the LVDS pin, Pin 44. If LVDS operation is desired, connect Pin 44 to AVDD. LVDS operation can also be Decouple the VREF pin externally to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic enabled through the SPI port. If CMOS operation is desired, capacitor. connect Pin 44 to AGND. Exposed Paddle Thermal Heat Slug Recommendations SPI Port It is mandatory that the exposed paddle on the underside of the The SPI port should not be active during periods when the full ADC be connected to the analog ground (AGND) to achieve dynamic performance of the converter is required. Because the the best electrical and thermal performance. A continuous, SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter per- exposed (no solder mask) copper plane on the PCB should mate to the AD9265 exposed paddle, Pin 0. formance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9265 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. A | Page 40 of 44 AD9265 OUTLINE DIMENSIONS 7.10 0.30 0.60 MAX 7.00 SQ 0.23 6.90 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 1 36 PIN 1 INDICATOR 0.50 6.85 REF * 5.65 6.75 SQ EXPOSED 5.50 SQ 6.65 PAD 5.35 (BOTTOM VIEW) 25 12 24 13 0.50 0.25 MIN TOP VIEW 0.40 5.50 REF 0.30 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 85. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9265BCPZ-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265BCPZRL7-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265BCPZ-105 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265BCPZRL7-105 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265BCPZ-80 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265BCPZRL7-80 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9265-125EBZ Evaluation Board AD9265-105EBZ Evaluation Board AD9265-80EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 41 of 44 120109-B AD9265 NOTES Rev. A | Page 42 of 44 AD9265 NOTES Rev. A | Page 43 of 44 AD9265 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08502-0-1/10(A) Rev. A | Page 44 of 44