ANALOG DEVICES AD9262

16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC AD9262 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input ORA SFDR: −87 dBc to 10 MHz input VIN+A SAMPLE D15A LOW-PASS CT Σ-Δ DC CMOS DECIMATION RATE Noise figure: 15 dB MODULATOR CORRECT BUFFER FILTER CONVERTER VIN–A D0A Input impedance: 1 kΩ GAIN Power: 600 mW QUADRATURE ADJ ERROR VREF ESTIMATE 1.8 V analog supply operation PHASE AD9262 ADJ CFILT 1.8 V to 3.3 V output supply DCO Selectable bandwidth VIN–B D15B LOW-PASS SAMPLE CT Σ-Δ DC CMOS DECIMATION RATE MODULATOR CORRECT 2.5 MHz/5 MHz/10 MHz real BUFFER FILTER CONVERTER VIN+B D0B 5 MHz/10 MHz/20 MHz complex CLK+ PHASE- SERIAL ORB LOCKED INTERFACE Output data rate: 30 MSPS to 160 MSPS CLK– LOOP Integrated dc and quadrature correction AGND SDIO SCLK CSB DGND Integrated decimation filters Figure 1 Integrated sample rate converter The AD9262 incorporates an integrated dc correction and On-chip PLL clock multiplier quadrature estimation block that corrects for gain and phase On-chip voltage reference mismatch between the two channels. This functional block Offset binary, Gray code, or twos complement data format proves invaluable in complex signal processing applications Serial control interface (SPI) such as direct conversion receivers. APPLICATIONS The digital output data is presented in offset binary, Gray code, Baseband quadrature receivers: CDMA2000, W-CDMA, or twos complement format. A data clock output (DCO) is multicarrier GSM/EDGE, 802.16x, and LTE provided to ensure proper timing with the receiving logic. The Quadrature sampling instrumentation AD9262 has the added feature of interleaving Channel A and Medical equipment Channel B data onto one 16-bit bus, simplifying on-board routing. Radio detection and ranging (RADAR) The ADC is available in three different bandwidth options of GENERAL DESCRIPTION 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. The AD9262 is a dual channel, 16-bit analog-to-digital conver- The AD9262 is available in a 64-lead LFCSP and is specified ter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ) over the industrial temperature range (−40°C to +85°C). architecture that achieves −87 dBc of dynamic range over a 10 MHz input bandwidth. The integrated features and characteris- PRODUCT HIGHLIGHTS tics unique to the continuous time Σ-Δ architecture significantly 1. Continuous time Σ-Δ architecture efficiently achieves high simplify its use and minimize the need for external components. dynamic range and wide bandwidth. The AD9262 has a resistive input impedance that relaxes the 2. Passive input structure reduces or eliminates the require- requirements of the driver amplifier. In addition, a 32× oversam- ments for a driver amplifier. pled fifth-order continuous time loop filter significantly attenuates 3. An oversampling ratio of 32× and high order loop filter out-of-band signals and aliases, reducing the need for external provide excellent alias rejection reducing or eliminating the filters at the input. need for antialiasing filters. 4. An integrated decimation filter, sample rate converter, PLL An external clock input or the integrated integer-N PLL provides clock multiplier, and voltage reference provide ease of use. the 640 MHz internal clock needed for the oversampled conti- 5. Integrated dc correction and quadrature error correction. nuous time Σ-Δ modulator. On-chip decimation filters and sample 6. Operates from a single 1.8 V analog power supply and rate converters reduce the modulator data rate from 640 MSPS to a 1.8 V to 3.3 V output supply. user-defined output data rate between 30 MSPS and 160 MSPS, enabling a more efficient and direct interface. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07772-001 AD9262 TABLE OF CONTENTS Features .............................................................................................. 1  AD9262BCPZ-10 ....................................................................... 12  Applications ....................................................................................... 1  Equivalent Circuits ......................................................................... 15  General Description ......................................................................... 1  Theory of Operation ...................................................................... 16  Functional Block Diagram .............................................................. 1  Analog Input Considerations ................................................... 16  Product Highlights ........................................................................... 1  Clock Input Considerations ...................................................... 18  Revision History ............................................................................... 2  Power Dissipation and Standby Mode .................................... 20  Specif ica t ions ..................................................................................... 3  Digital Engine ............................................................................. 21  DC Specifications ......................................................................... 3  DC and Quadrature Error Correction (QEC) ........................ 23  AC Specifications .......................................................................... 4  Digital Outputs ........................................................................... 24  Digital Decimation Filtering Characteristics ............................ 5  Timing ......................................................................................... 25  Digital Specifications ................................................................... 6  Serial Port Interface (SPI) .............................................................. 26  Switching Specifications .............................................................. 7  Configuration Using the SPI ..................................................... 26  Absolute Maximum Ratings ............................................................ 8  Hardware Interface ..................................................................... 27  Thermal Resistance ...................................................................... 8  Applications Information .............................................................. 28  ESD Caution .................................................................................. 8  Filtering Requirement ................................................................ 28  Pin Configuration and Function Descriptions ............................. 9  Memory Map .................................................................................. 30  Typical Performance Characteristics ........................................... 10  Memory Map Definitions ......................................................... 30  AD9262BCPZ ............................................................................. 10  Outline Dimensions ....................................................................... 32  AD9262B CP Z-5 .......................................................................... 11  Ordering Guide .......................................................................... 32  REVISION HISTORY 2/10—Rev. 0 to Rev. A Changes to Figure 61 ...................................................................... 28 1/10—Revision 0: Initial Version Rev. A | Page 2 of 32 AD9262 SPECIFICATIONS DC SPECIFICATIONS 1 All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 1. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ANALOG INPUT BANDWIDTH 2.5 5 10 MHz ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.025 ±0.2 ±0.025 ±0.2 ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±3.0 ±0.7 ±3.0 ±0.7 ±3.0 % FSR 2 Integral Nonlinearity (INL) 25°C ±1.5 ±1.5 ±1.5 LSB MATCHING CHARACERISTICS Offset Error Full ±0.035 ±0.2 ±0.035 ±0.2 ±0.035 ±0.2 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ±1.5 ±1.5 ppm/°C Gain Error Full ±50 ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 490 500 510 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 2 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Input Resistance Full 1 1 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 1.7 1.8 3.6 1.7 1.8 3.6 V Supply Current 2 I Full 146 165 146 165 146 165 mA AVDD 2 I PLL Enabled Full 57 65 57 65 57 65 mA CVDD 2 ICVDD PLL Disabled Full 8.1 8.8 8.1 8.8 8.1 8.8 mA 2 IDVDD Full 108 117 141 152 169 182 mA 2 IDRVDD (1.8 V) Full 8.3 8.6 8.7 9.1 10 12.7 mA 2 I (3.3 V) Full 17 18 22 mA DRVDD POWER CONSUMPTION 2 Sine Wave Input PLL Disabled Full 487 538.5 547 601.5 600 660 mW 2 Sine Wave Input PLL Enabled Full 576 640 636 703 688 762 mW Power-Down Power Full 23 23 23 mW 2 Standby Power Full 10 10 10 mW Sleep Power Full 3 4 3 4 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. A | Page 3 of 32 AD9262 AC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 2. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) 2 fIN = 600 kHz Full 86 89 dB 3 fIN = 1.2 MHz Full 89 83 86 dB 4 fIN = 2.4 MHz Full 89 86 81 83 dB fIN = 4.2 MHz 25°C 86 83 dB fIN = 8.4 MHz 25°C 83 dB EFFECTIVE NUMBER OF BITS (ENOB) f = 600 kHz 25°C Bits IN f = 1.2 MHz 25°C 14.5 Bits IN f = 2.4 MHz 25°C 14.5 14 Bits IN f = 4.2 MHz 25°C 14 13.5 Bits IN fIN = 8.4 MHz 25°C 13.5 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) 2 f = 600 kHz Full −87 −80 dBc IN 3 f = 1.2 MHz Full −87 −87 −80 dBc IN 4 f = 2.4 MHz Full <−120 −87 −87 −80 dBc IN f = 4.2 MHz 25°C <−120 −87 dBc IN f = 8.4 MHz 25°C <−120 dBc IN NOISE SPECTRAL DENSITY (NSD) AIN = −2 dBFS Full −154.3 −152 −155 −152 −155 −153 dBFS/Hz AIN = −40 dBFS Full −155.4 −154 −156 −154.5 −156 −154.5 dBFS/Hz 5 NOISE FIGURE 25°C 15.6 15 15 dB TWO-TONE SFDR f = 1.8 MHz @ −8 dBFS, f = 2.1 MHz @ −8 dBFS 25°C −92 dBc IN1 IN2 f = 2.1 MHz @ −8 dBFS, f = 2.4 MHz @ −8 dBFS 25°C −93 −93 dBc IN1 IN2 f = 3.7 MHz @ −8 dBFS, f = 4.2 MHz @ −8 dBFS 25°C −92.5 dBc IN1 IN2 f = 7.2 MHz @ −8 dBFS, f = 8.4 MHz @ −8 dBFS 25°C −92.5 dBc IN1 IN2 6 CROSSTALK 25°C −110 −110 −110 dB ANALOG INPUT BANDWIDTH 25°C 2.5 5 10 MHz APERTURE JITTER 25°C 1 1 1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data guaranteed over the full temperature range for the AD9262BCPZ only. 3 Data guaranteed over the full temperature range for the AD9262BCPZ-5 only. 4 Data guaranteed over the full temperature range for the AD9262BCPZ-10 only. 5 Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. 6 Crosstalk measured with an input signal on both channels at different frequencies and the leakage of one on to the other. Rev. A | Page 4 of 32 AD9262 DIGITAL DECIMATION FILTERING CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 3. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 1 Parameter Min Typ Max Min Typ Max Min Typ Max Unit Pass-Band Transition 2.5 3.75 5 6.5 10 13 MHz Pass-Band Ripple <0.1 <0.1 <0.1 dB Stop Band 3.75 MHz − f /2 6.5 MHz − f/2 13 MHz − f/2 MHz S S S Stop Band Attenuation >85 >85 >85 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. A | Page 5 of 32 AD9262 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 4. 1 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVPECL Differential Input Voltage Full 0.4 0.8 2 V p-p Input Common-Mode Range Full 0.3 0.450 0.5 V High Level Input Current Full −60 +60 μA Low Level Input Current Full −60 +60 μA Input Resistance Full 20 kΩ Input Capacitance Full 1 pF LOGIC INPUTS (SCLK) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO, CSB, RESET) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (V , I = 50 μA) Full 3.29 V OH OH High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V DRVDD = 1.8 V High Level Output Voltage (V , I = 50 μA) Full 1.79 V OH OH High Level Output Voltage (V , I = 0.5 mA) Full 1.75 V OH OH Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. A | Page 6 of 32 AD9262 SWITCHING SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS unless otherwise noted. Table 5. 1 Parameter Temp Min Typ Max Unit CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate Full 30 160 MSPS CLK± Period Full 6.25 33 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT (DIRECT CLOCKING) Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.49 1.5625 1.64 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS Output Data Rate Full 20 160 MSPS 2 DCO to Data Skew (tSKEW) Full 3 ns 3 4 Sample Latency Full 960 Cycles 5 WAKE-UP TIME Power-Down Power Full 3 μs Standby Power Full 9 μs Sleep Power Full 15 μs 3 4 OUT-OF-RANGE RECOVERY TIME Full 960 Cycles 6 SERIAL PORT INTERFACE SCLK Period Full 40 ns SCLK Pulse Width High Time (t) Full 16 ns SHIGH SCLK Pulse Width Low Time (t) Full 16 ns SLOW SDIO to SCLK Setup Time (t) Full 5 ns SDS SDIO to SCLK Hold Time (tSDH) Full 2 ns CSB to SCLK Setup Time (tSS) Full 5 ns CSB to SCLK Hold Time (tSH) Full 2 ns 1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load. 3 Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively. 4 Cycles refers to modulator clock cycles. 5 Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT. 6 See Figure 60 and the Serial Port Interface (SPI) section. Timing Diagram DCO t SKEW D0x TO D15x Figure 2. Timing Diagram Rev. A | Page 7 of 32 07772-002 AD9262 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB Electrical increases the reliability of the solder joints, maximizing the AVDD to AGND −0.3 V to +2.0 V thermal capability of the package. DVDD to DGND −0.3 V to +2.0 V DRVDD to DGND −0.3 V to +3.9 V Table 7. Thermal Resistance AGND to DGND −0.3 V to +0.3 V Package Type θJA θJC Unit AVDD to DRVDD −3.9 V to +2.0 V 64-Lead LFCSP (CP-64-4) 21.2 1.1 °C/W CVDD to CGND −0.3 V to +2.0 V CGND to DGND −0.3 V to +0.3 V Typical θJA and θJC are specified for a 4-layer board in still air. D0A to D15A to DGND −0.3 V to +2.0 V Airflow increases heat dissipation, effectively reducing θJA. In D0B to D15B to DGND −0.3 V to +2.0 V addition, metal in direct contact with the package leads from DCO to DGND −0.3 V to +2.0 V metal traces, through holes, ground, and power planes reduces ORA, ORB to DGND −0.3 V to +2.0 V the θ . JA SDIO to DGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V ESD CAUTION SCLK to AGND −0.3 V to +3.9 V VIN+A/VIN−A, VIN+B/VIN−B to AGND −0.3 V to +2.5 V CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 Sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 32 AD9262 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK– 1 PIN 1 48 SCLK INDICATOR CVDD 2 47 SDIO D0B 3 46 ORA D1B 4 45 D15A D2B 5 44 D14A AD9262 DVDD 6 43 DVDD DGND 7 CMOS OUTPUTS 42 DGND DRVDD 8 41 DRVDD TOP VIEW D3B 9 40 D13A (Not to Scale) D4B 10 39 D12A D5B 11 38 D11A 37 D10A D6B 12 36 D7B 13 D9A D8B 14 35 D8A D9B 15 34 D7A D10B 16 33 D6A NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 to 5, 9 to 21 D0B to D15B Channel B Data Output Pins. D0B is the LSB and D15B is the MSB. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Overrange Indicator. 26 DCO Data Clock Output. 27 to 40, 44, 45 D0A to D15A Channel A Data Output Pins. D0A is the LSB and D15A is the MSB. 46 ORA Channel A Overrange Indicator. 47 SDIO Serial Port Interface Data Input/Output. 48 SCLK Serial Port Interface Clock. 49 CSB Serial Port Interface Chip Select Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53 VIN+A Channel A Analog Input (+). 54 VIN−A Channel A Analog Input (−). 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59 VIN+B Channel B Analog Input (+). 60 VIN−B Channel B Analog Input (−). 63 CGND Clock Ground. 64 CLK+ Clock Input (+). 65 (EPAD) Exposed pad (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed pad must be soldered to ground. Rev. A | Page 9 of 32 D11B 17 64 CLK+ D12B 18 63 CGND D13B 19 62 AGND D14B 20 61 AVDD D15B 21 60 VIN–B ORB 22 59 VIN+B DRVDD 58 AVDD 23 DGND 24 57 CFILT DVDD 25 56 VREF DCO 26 55 AVDD D0A 27 54 VIN–A D1A 28 53 VIN+A D2A 29 52 AVDD D3A 30 51 AGND D4A 31 50 RESET D5A 32 49 CSB 07772-003 AD9262 TYPICAL PERFORMANCE CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, TA = 25°C, output data rate 40 MSPS, unless otherwise noted. AD9262BCPZ 0 120 BANDWIDTH: 2.5MHz DATA RATE: 40MSPS SFDR (dBFS) –20 f : 600kHz AT –2dBFS IN 100 SNR: 87.9dB –40 SFDR: 88.2dBc 80 –60 SNR (dBFS) –80 60 SFDR (dBc) –100 40 –120 SNR (dB) 20 –140 –160 0 0 2 4 6 8 10 121416 1820 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 7. AD9262BCPZ Single-Tone SNR and SFDR vs. Input Amplitude Figure 4. AD9262BCPZ Single-Tone FFT with f = 600 kHz IN with f = 600 kHz IN 0 0 BANDWIDTH: 2.5MHz BANDWIDTH: 2.5MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 1.2MHz AT –2dBFS f : 1.8MHz AT –8dBFS IN IN1 SNR: 87.7dB f : 2.1MHz AT –8dBFS IN2 SFDR: 87.1dBc SFDR: –91.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 121416 18 20 0 2 4 6 8 10 121416 1820 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9262BCPZ Single-Tone FFT with f = 1.2 MHz Figure 8. AD9262BCPZ Two-Tone FFT with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz IN 0 0 BANDWIDTH: 2.5MHz DATA RATE: 40MSPS –20 f : 2.4MHz AT –2dBFS IN –20 SNR: 87.8dB SFDR: 106.6dBc –40 –40 –60 SFDR (dBc) –80 –60 –100 –80 –120 SFDR (dBFS) –100 –140 –160 –120 0 2 4 6 8 10 12 1416 1820 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 6. AD9262BCPZ Single-Tone FFT with f = 2.4 MHz IN Figure 9. AD9262BCPZ Two-Tone SFDR/IMD3 vs. Input Amplitude with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz Rev. A | Page 10 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07772-063 07772-062 07772-061 AMPLITUDE (dBFS) SNR/SFDR SFDR 07772-077 07772-087 07772-070 AD9262 AD9262BCPZ-5 0 120 BANDWIDTH: 5MHz SFDR (dBFS) DATA RATE: 40MSPS –20 f : 1.2MHz AT –2dBFS IN 100 SNR: 85.3dB SFDR: 87.1dBc –40 80 –60 SNR (dBFS) 60 –80 SFDR (dBc) –100 SNR (dB) 40 –120 20 –140 0 –160 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 2 4 6 8 10 12 1416 1820 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 10. AD9262BCPZ-5 Single-Tone FFT with f = 1.2 MHz IN Figure 13. AD9262BCPZ-5 Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 1.2 MHz 0 0 BANDWIDTH: 5MHz BANDWIDTH: 5MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 2.4MHz AT –2dBFS f : 1.8MHz AT –8dBFS IN IN1 SNR: 85.7dB f : 2.1MHz AT –8dBFS IN2 SFDR: 87.4dBc SFDR: –92.8dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 121416 1820 0 2 4 6 8 10 12 1416 1820 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. AD9262BCPZ-5 Single-Tone FFT with f = 2.4 MHz IN Figure 14. AD9262BCPZ-5 Two-Tone FFT with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz 0 0 BANDWIDTH: 5MHz DATA RATE: 40MSPS –20 f : 4.2MHz AT –2dBFS IN –20 SNR: 85.7dB SFDR: 104.9dBc –40 SFDR (dBc) –40 –60 –60 –80 –100 –80 –120 SFDR (dBFS) –100 –140 –120 –160 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 2 4 6 8 10 121416 1820 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 15. AD9262BCPZ-5 Two-Tone SFDR/IMD3 vs. Input Amplitude Figure 12. AD9262BCPZ-5 Single-Tone FFT with fIN = 4.2 MHz with f = 2.1 MHz, f = 2.4 MHz IN1 IN2 Rev. A | Page 11 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07772-065 07772-064 07772-066 AMPLITUDE (dBFS) SFDR SNR/SFDR 07772-092 07772-078 07772-057 AD9262 AD9262BCPZ-10 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 2.1MHz AT –8dBFS IN1 f : 2.4MHz AT –2dBFS IN f : 2.4MHz AT –8dBFS IN2 SNR: 82.8dB SFDR: –93dBc SFDR: 87.7dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 121416 1820 0 2 4 6 8 10 12 1416 1820 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. AD9262BCPZ-10 Single-Tone FFT with fIN = 2.4 MHz Figure 19. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 4.2MHz AT –2dBFS f : 3.6MHz AT –8dBFS IN IN1 SNR: 82.7dB f : 4.2MHz AT –8dBFS IN2 SFDR: 86.7dBc SFDR: –92.5dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 1416 1820 0 2 4 6 8 10 121416 1820 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. AD9262BCPZ-10 Single-Tone FFT with fIN = 4.2 MHz Figure 20. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 3.6 MHz, fIN2 = 4.2 MHz 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 7.2MHz AT –8dBFS IN1 f : 8.4MHz AT –2dBFS IN f : 8.4MHz AT –8dBFS IN2 SNR: 82.6dB SFDR: –92.5dBc –40 –40 SFDR: 104.1dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 1416 1820 0 2 4 6 8 10 121416 1820 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9262BCPZ-10 Single-Tone FFT with fIN = 8.4 MHz Figure 21. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 7.2 MHz, fIN2 = 8.4 MHz Rev. A | Page 12 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07772-068 07772-067 07772-069 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07772-060 07772-059 07772-058 AD9262 120 110 SFDR (dBFS) 100 105 80 100 SNR (dBFS) 60 95 SFDR (dBc) SFDR (dBc) 40 90 SNR (dB) SNR (dB) 20 85 0 80 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 01 23 45 67 89 10 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 22. AD9262BCPZ-10 Single-Tone SNR/SFDR vs. Input Amplitude Figure 25. AD9262BCPZ-10 SNR/SFDR vs. Input Frequency with fIN = 2.4 MHz 0 92 91 1.9 V –20 90 SFDR 1.8V 89 –40 88 1.7V SFDR (dBc) 87 –60 86 85 –80 84 SFDR (dBFS) SNR 1.9V 83 –100 1.8V 1.7V 82 –120 81 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 –60 –40 –20 0 20 40 60 80 100 INPUT AMPLITUDE (dBFS) TEMPERATURE (°C) Figure 23. AD9262BCPZ-10 Two-Tone SFDR/IMD3 vs. Input Amplitude Figure 26. AD9262BCPZ-10 SFDR/SNR vs. Temperature with fIN = 2.4 MHz with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz 89 84.0 83.8 SFDR (dBc) 88 83.6 87 83.4 83.2 86 83.0 85 82.8 82.6 84 SNR (dB) 82.4 83 82.2 82 82.0 0 20 40 60 80 100 120 140 160 180 1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.875 1.900 OUTPUT DATA RATE (MSPS) COMMON-MODE VOLTAGE (V) Figure 24. AD9262BCPZ-10 SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz Figure 27. AD9262BCPZ-10 SNR vs. Input Common-Mode Voltage with fIN = 2.4 MHz Rev. A | Page 13 of 32 SFDR SNR/SFDR SNR/SFDR 07772-093 07772-079 07772-076 SNR (dB) SNR (dB)/SFDR (dBc) SNR/SFDR 07772-090 07772-081 07772-091 AD9262 83.0 0.5 f = 2.4MHz 82.5 IN 0 82.0 –0.5 81.5 f = 8.4MHz IN 81.0 –1.0 80.5 –1.5 80.0 79.5 –2.0 79.0 –2.5 78.5 –3.0 78.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 1.0 4.5 6.0 7.5 8.5 10.0 12.0 14.0 16.0 21.0 4.0 5.0 7.0 8.0 9.0 10.5 12.5 15.0 17.0 OUTPUT CODE PLL DIVIDE RATIO Figure 28. AD9262BCPZ-10 Single-Tone SNR vs. PLL Divide Ratio Figure 29. AD9262BCPZ-10 INL Rev. A | Page 14 of 32 SNR (dB) 07772-080 INL ERROR (LSB) 07772-096 AD9262 EQUIVALENT CIRCUITS AVDD 26kΩ 1kΩ CSB 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 30. Equivalent Analog Input Circuit Figure 34. Equivalent CSB Input Circuit CVDD DRVDD CLK+ CLK– 10kΩ 10kΩ 90kΩ 30kΩ CVDD DGND Figure 35. Equivalent Digital Output Circuit Figure 31. Equivalent Clock Input Circuit DRVDD 2.85kΩ 8.5kΩ 10kΩ 0.5V 1kΩ SDIO 10µF 3.5kΩ TO CURRENT GENERATOR Figure 36. Equivalent VREF Circuit Figure 32. Equivalent SDIO Input Circuit 1kΩ SCLK 30kΩ Figure 33. Equivalent SCLK Input Circuit Rev. A | Page 15 of 32 07772-005 07772-006 07772-008 07772-004 07772-009 07772-010 07772-007 AD9262 THEORY OF OPERATION DIGITAL FILTER CUTOFF FREQUENCY The AD9262 uses a continuous time Σ-Δ modulator to convert the analog input to a digital word. The digital word is processed by the decimation filter and rate-adjusted by the sample rate converter (see Figure 37). The modulator consists of a continuous f /32 f /16 time loop filter preceding a quantizer that samples at f = MOD MOD MOD BAND OF INTEREST 640 MSPS. This produces an oversampling ratio (OSR) of 32 for Figure 40. Digital Filter Cutoff Frequency a 10 MHz input bandwidth. The output of the quantizer is fed back to a DAC that ideally cancels the input signal. The incom- plete input cancellation residue is filtered by the loop filter and is used to form the next quantizer sample. MODULATOR f /2 f f /16 OUT OUT MOD DECIMATION SAMPLE RATE BAND OF INTEREST LOOP FILTER FILTER CONVERTER QUANTIZER Figure 41. Sample Rate Converter + SRC H(f) ADC – ANALOG INPUT CONSIDERATIONS The continuous time modulator removes the need for an anti- alias filter at the input to the AD9262. A discrete time converter Figure 37. Σ-Δ Modulator Overview aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 42). Therefore, an external The quantizer produces a nine-level digital word. The quantization antialias filter is needed to reject these signals. noise is spread uniformly over the Nyquist band (see Figure 38), DESIRED UNDESIRED but the feedback loop causes the quantization noise present in INPUT SIGNAL the nine-level output to have a nonuniform spectral shape. This noise-shaping technique (see Figure 39) pushes the in-band f f /2 S S noise out of band; therefore, the amount of quantization noise ADC in the frequency band of interest is minimal. Figure 42. Discrete Time Converter The digital decimation filter that follows the modulator removes the large out-of-band quantization noise (see Figure 40), while In contrast, the continuous time Σ-Δ modulator used within the also reducing the data rate from f to f /16. If the internal MOD MOD AD9262 has inherent antialiasing. The antialiasing property PLL is enabled, the sample rate converter generates samples at results from sampling occurring at the output of the loop filter the same frequency as the input clock frequency. If the internal (see Figure 43), and thus aliasing occurs at the same point in the PLL is disabled, the sample rate converter can be programmed loop as quantization noise is injected; aliases are shaped by the to give an output frequency that is a divide ratio of the modulator same mechanism as quantization noise. The quantization noise clock. The sample rate converter is designed to attenuate images transfer function, NTF(f), has zeros in the band of interest and in outside the band of interest (see Figure 41). all alias bands because NTF(f) is a discrete time transfer function, whereas the loop filter transfer function, LF(f), is a continuous time transfer function, which introduces poles only in the band of interest. The signal transfer function, being the product of QUANTIZATION NOISE NTF(f) and LF(f), only has zeros in alias bands and therefore f /2 MOD suppresses all aliases. BAND OF INTEREST LF(f) Figure 38. Quantization Noise LOOP FILTER INPUT LF(f) QUANTIZATION f MOD NOISE f MOD NOISE SHAPING OUTPUT H(z) f /2 MOD NTF(f) BAND OF INTEREST Figure 39. Noise Shaping f f MOD Figure 43. Continuous Time Converter Rev. A | Page 16 of 32 DAC 07772-035 07772-034 07772-033 07772-038 07772-037 07772-036 07772-039 AD9262 Input Common Mode 2V p-p VIN+x 50Ω 1:1 The analog inputs of the AD9262 are not internally dc biased. In R T V AD9262 S 50Ω ac-coupled applications, the user must provide this bias externally. SIGNAL VIN–x Setting the device such that VCM = AVDD is recommended for SOURCE AVDD optimum performance. The analog inputs are 500 Ω resistors, 0.1µF and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 44). With 0 V differential input, Figure 46. Differential Transformer Configuration the driver sources 1 mA into each analog input. Voltage Reference AVDD – 0.5V A stable and accurate 0.5 V voltage reference is built into the 500Ω VIN+x AD9262. The reference voltage should be decoupled to minimize V =AVDD TO LOOP FILTER CM V p-p = 2V STAGE 2 IN the noise bandwidth using a 10 μF capacitor. The reference is VIN–x 500Ω used to generate a bias current into a matched resistor such that, when used to bias the current in the feedback DAC, a voltage DAC of AVDD − 0.5 V is developed at the internal side of the input resistors (see Figure 47). The current bias circuit should also be FROM QUANTIZER decoupled on the CFILT pin with a 10 μF capacitor. For this Figure 44. Input Common Mode reason, the VREF voltage should always be 0.5 V. Differential Input Configurations AVDD – 0.5V The AD9262 can also be configured for differential inputs. The V =AVDD CM ADA4937-2 differential driver provides excellent performance V p-p = 2V 500Ω IN VIN+x and a flexible interface to the ADC. The output common-mode 500Ω 0.5V VIN–x voltage of the ADA4937-2 is easily set by connecting AVDD to TO LOOP VREF 10kΩ FILTER the VOCM2 pin of the ADA4937-2 (see Figure 45). The noise and AVDD REF STAGE 2 10µF linearity of the ADA4937-2 need important consideration because AVDD – 0.5V 500Ω the system performance may be limited by the ADA4937-2. +5V +1.8V 0.1µF CFILT 0.1µF 10µF VIN–x 200Ω AVDD Figure 47. Voltage Reference Loop 9 2V p-p 50Ω 200Ω 6 13 Internal Reference Connection V OCM211 ADA4937-2 AD9262 V R S T 7 60.4 To minimize thermal noise, the internal reference on the AD9262 12 SIGNAL is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor, 15 SOURCE 200Ω which, when externally decoupled with a 10 μF capacitor, limits VIN+x 0.1µF 49.9Ω 60.4Ω the noise (see Figure 48). The unbuffered reference should not be used to drive any external circuitry. The internal reference is 0.1µF –5V used by default and when Serial Register 0x18[6] is reset. Figure 45. Differential Input Configuration Using the ADA4937-2 For frequencies offset from dc, where SNR is a key parameter, differential transformer coupling is the recommended input 2.85kΩ 8.5kΩ configuration. An example is shown in Figure 46. The center 10kΩ 0.5V tap of the secondary winding of the transformer is connected to 10µF 3.5kΩ AVDD to bias the analog input. The signal characteristics must be considered when selecting a TO CURRENT GENERATOR transformer. Most RF transformers saturate at frequencies Figure 48. Internal Reference Configuration below a couple of megahertz (MHz), and excessive signal power can cause core saturation, which leads to distortion. Rev. A | Page 17 of 32 07772-041 07772-040 07772-044 07772-042 07772-043 AD9262 External Reference Operation width. The input range of the clock is limited to 640 MHz ± 5%. In situations where the AD9262 loses its clock and then later If an external reference is desired, the internal reference can be regains it, it is important that the sample rate converter be reset disabled by setting Serial Register 0x18[6] high. Figure 49 shows and reprogrammed before the desired output data rate is an application using the ADR130B as a stable external reference. achieved. 0.5V AVDD ADR130B 10kΩ Direct Clocking 0.1µF 10µF The default configuration of the AD9262 is for direct clocking TO CURRENT where the PLL is bypassed. Figure 50 shows one preferred method GENERATOR for clocking the AD9262. A low jitter clock source is converted Figure 49. External Reference Configuration from a single-ended signal to a differential signal using an RF CLOCK INPUT CONSIDERATIONS transformer. The back-to-back Schottky diodes across the secondary side of the transformer limits clock excursions into the The AD9262 offers two modes of sourcing the ADC sample AD9262 to approximately 0.8 V p-p differential. This helps clock (CLK+ and CLK−). The first mode uses an on-chip clock prevent the large voltage swings of the clock from feeding multiplier that accepts a reference clock operating at the lower through to other portions of the AD9262 while preserving the input frequency. The on-chip phase-locked loop (PLL) then fast rise and fall times of the signal, which are critical to multiplies the reference clock to a higher frequency, which is achieving low jitter. then used to generate all the internal clocks required by the ADC MINI-CIRCUITS The clock multiplier provides a high quality clock that meets TC1-1-13M+, 1:1 the performance requirements of most applications. Using the 0.1µF 0.1µF XFMR CLK+ CLOCK on-chip clock multiplier removes the burden of generating and INPUT ADC AD9262 distributing the high speed clock. 50Ω 0.1µF CLK– The second mode bypasses the clock multiplier circuitry and SCHOTTKY DIODES: allows the clock to be directly sourced. This mode enables the 0.1µF HSM2812 user to source a very high quality clock directly to the Σ-Δ Figure 50. Transformer-Coupled Differential Clock modulator. Sourcing the ADC clock directly may be necessary in demanding applications that require the lowest possible ADC If a differential clock is not available, the AD9262 can be driven output noise. See Figure 28, which shows the degradation in by a single-ended signal into the CLK+ terminal with the CLK− SNR performance for the various PLL settings. terminal ac-coupled to ground. Figure 51 shows the circuit configuration. In either case, when using the on-chip clock multiplier or sourcing the high speed clock directly, it is necessary that the clock source have low jitter to maximize the ADC noise performance. 0.1µF CLK+ CLOCK High speed, high resolution ADCs are sensitive to the quality of INPUT ADC the clock input. As jitter increases, the SNR performance of the AD9262 50Ω CLK– AD9262 degrades from that specified in Table 2. The jitter SCHOTTKY inherent in the part due to the PLL root sum squares with any DIODES: 0.1µF HSM2812 external clock jitter, thereby degrading performance. To prevent jitter from dominating the performance of the AD9262, the input Figure 51. Single-Ended Clock clock source should be no greater than 1 ps rms of jitter. Another option is to ac couple a differential LVPECL signal to The CLK± inputs are self-biased to 450 mV (see Figure 31); the sample clock input pins, as shown in Figure 52. The AD951x if the inputs are dc-coupled, it is important to maintain the family of clock drivers is recommended because it offers excellent specified 450 mV input common-mode voltage. Each input pin jitter performance. can safely swing from 200 mV p-p to 1 V p-p single-ended about the 450 mV common-mode voltage. The recommended 0.1µF 0.1µF clock inputs are CMOS or LVPECL. CLOCK CLK+ CLK INPUT AD951x ADC The specified clock rate of the Σ-Δ modulator, f , is 640 MHz. MOD LVPECL 100Ω AD9262 DRIVER CLK– CLOCK The clock rate possesses a direct relationship to the available INPUT CLK 0.1µF 0.1µF input bandwidth of the ADC. 240Ω 240Ω 1 1 50Ω 50Ω Bandwidth = fMOD ÷ 64 In either case, using the on-chip clock multiplier to generate the 1 50Ω RESISTORS ARE OPTIONAL. Σ-Δ modulator clock rate or directly sourcing the clock, any Figure 52. Differential LVPECL Sample Clock deviation from 640 MHz results in a change in input band- Rev. A | Page 18 of 32 07772-045 07772-047 07772-046 07772-048 AD9262 Internal PLL Clock Distribution PLL Autoband Select The alternative clocking option available on the AD9262 is to apply The PLL VCO has a wide operating range that is covered by a low frequency reference clock and use the on-chip clock multip- overlapping frequency bands. For any desired VCO output lier to generate the high frequency fMOD rate. The internal clock frequency, there are multiple valid PLL band select values. The architecture is shown in Figure 53. AD9262 possesses an automatic PLL band select feature on chip that determines the optimal PLL band setting. This feature can CLK+/CLK– PHASE LOOP be enabled by writing to Register 0x0A[6]and is the recommended VCO DETECTOR FILTER configuration with the PLL clocking option. When the device is PLL taken out of sleep or standby mode, Register 0x0A[6] must be DIVIDER toggled to reinitiate the autoband detect. See Table 9 for informa- tion about enabling the autoband select along with configuring the PLL. PLL MULT ÷2 MODULATOR 0x0A[5:0] CLOCK Table 10. PLL Multiplication Factors 640MSPS 0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N) PLLENABLE 1 8 33 32 0x09[2] 2 8 34 34 Figure 53. Internal Clock Architecture 3 8 35 34 The clock multiplication circuit operates such that the VCO 4 8 36 34 outputs a frequency, fVCO, equal to the reference clock input 5 8 37 34 multiplied by N. 6 8 38 34 fVCO = (CLK±) × (N) 7 8 39 34 8 8 40 34 where N is the PLL multiplication (PLLMULT) factor. 9 9 41 34 The Σ-Δ modulator clock frequency, f , is equal to MOD 10 10 42 42 f = f ÷ 2 11 10 43 42 MOD VCO 12 12 44 42 The reference clock, CLK±, is limited to 30 MHz to 160 MHz 13 12 45 42 when configured to use the on-chip clock multiplier. Given the 14 14 46 42 input range of the reference clock and the available multiplication 15 15 47 42 factors, the fVCO is approximately 1280 MHz. This results in the 16 16 48 42 desired fMOD rate of 640 MHz with a 50% duty cycle. 17 17 49 42 Before the PLL enable register bit (PLLENABLE) is set, the PLL 18 18 50 42 multiplication factor should be programmed into Register 19 18 51 42 0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and 20 20 52 42 reports a locked state in Register 0x0A[7]. If the PLL multiplica- 21 21 53 42 tion factor is changed, the PLL enable bit should be reset and set 22 21 54 42 again. Some common clock multiplication factors are shown in 23 21 55 42 Table 11. 24 24 56 42 The recommended sequence for enabling and programming the 25 25 57 42 on-chip clock multiplier is shown in Table 9. 26 25 58 42 27 25 59 42 Table 9. Sequence for Enabling and Programming the PLL 28 28 60 42 Step Procedure 29 28 61 42 1 Apply a reference clock to the CLK± pins. 30 30 62 42 2 Program the PLL multiplication factor in 31 30 63 42 Register 0x0A[5:0]. See Table 10. 32 32 64 42 3 Enable the PLL; Register 0x09 = 04 (decimal). 4 Enable PLL autoband select. 5 Initiate an SRC reset; Register 0x101[5:0] = 0. 6 Set SRC to desired value via Register 0x101[5:0]. Rev. A | Page 19 of 32 ÷N 07772-049 AD9262 POWER DISSIPATION AND STANDBY MODE Table 11. Common Modulator Clock Multiplication Factors The AD9262 power consumption can be further reduced by CLK± 0x0A[5:0] fVCO fMOD BW configuring the chip in channel power-down, standby, or sleep (MHz) (PLLMULT) (MHz) (MHz) (MHz) mode. The low power modes turn off internal blocks of the chip, 30.72 42 1290.24 645.12 10.08 including the reference. As a result, the wake-up time is depen- 39.3216 32 1258.29 629.15 9.83 dent on the amount of circuitry that is turned off. Fewer internal 52.00 25 1300.00 650.00 10.16 circuits that are powered down result in proportionally shorter 21 1290.24 645.12 10.08 61.44 wake-up time. The low power modes are shown in Table 12. 17 1305.60 652.80 10.20 76.80 In the standby mode, all clock related activity and the output 78.00 17 1326.00 663.00 10.36 channels are disabled. Only the references and CMOS outputs 78.6432 16 1258.29 629.15 9.83 remain powered up to ensure a short recovery and link integr- 89.60 15 1344.00 672.00 10.50 ity. During sleep mode, all internal circuits are powered down, 92.16 14 1290.24 645.12 10.08 putting the device into its lowest power mode, and the CMOS 10 1228.80 614.40 9.60 122.88 outputs are disabled. 10 1344.00 672.00 10.50 134.40 153.60 8 1228.80 614.40 9.60 Each ADC channel can be independently powered down or 157.2864 8 1258.29 629.15 9.83 both channels can be set simultaneously by writing to the channel index, Register 0x05[1:0]. Jitter Considerations Table 12. Low Power Modes The aperture jitter requirements for continuous time Σ-Δ conver- ters may be more forgiving than Nyquist rate converters. The Mode 0x08[1:0] Analog Circuitry Clock Ref continuous time Σ-Δ architecture is an oversampled system Normal 0x0 On On On and to accurately represent the analog input signal to the ADC, Power-Down 0x1 Off On On a large number of output samples must be averaged together. As Standby 0x2 Off Off On a result, the jitter contribution from each sample is root sum Sleep 0x3 Off Off Off squared, resulting in a more subtle impact on noise perfor- mance as compared to Nyquist converters where aperture jitter has a direct impact on each sampled output. In the block diagram of the continuous time Σ-Δ modulator (see Figure 37), the two building blocks most susceptible to jitter are the quantizer and the DAC. The error introduced through the sampling process is reduced by the loop gain and shaped in the same way as the quantization noise and, therefore, its effect can be neglected. On the contrary, the jitter error associated with the DAC directly adds to the input signal, thus increasing the in-band noise power and degrading the modulator performance. The SNR degradation due to jitter can be represented by the following equation. SNR = −20 log (2πfanalogtjitter_rms) dB where fanalog is the analog input frequency and tjitter_rms is the jitter. The SNR performance of the AD9262 remains constant within the input bandwidth of the converter, from DC to 10 MHz. Therefore, the minimal jitter specification is determined at the highest input frequency. From the calculation, the aperture jitter of the input clock must be no greater than 1 ps to achieve optimal SNR performance. Rev. A | Page 20 of 32 AD9262 Table 14. DEC4 Filter Coefficients DIGITAL ENGINE Coefficient Coefficient Bandwidth Selection Number Coefficient Number Coefficient The digital engine (see Figure 54) selects the decimation signal C0, C22 −21 C6, C16 1121 3 bandwidth by cascading third-order sinc (sinc ) decimate-by-2 C1, C21 0 C7, C15 0 filters. For a 10 MHz signal band, no filters are cascaded; for a C2, C20 122 C8, C14 −2796 5 MHz signal band, a single filter is used; and for a 2.5 MHz C3, C19 0 C9, C13 0 signal band, the 5 MHz filter is cascaded with a second filter. C4, C18 −418 C10, C12 10,184 Depending on the signal bandwidth, this drops the data rate C5, C17 0 C11 16,384 into the fixed decimation filter. As a result, lower signal bandwidth options result in lower power. Bandwidth selection is determined Table 15. LPF/EQZ Filter Coefficients by setting Serial Register 0x0F[6:5]. Table 13 summarizes the Coefficient Coefficient available bandwidth options. Number Coefficient Number Coefficient C0, C62 17 C16, C46 694 Table 13. Output Bandwidth Options C1, C61 31 C17, C45 −744 BW[1:0] AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 C2, C60 −15 C18, C44 −677 0x0 2.5 MHz 5 MHz 10 MHz C3, C59 −52 C19, C43 1271 0x1 2.5 MHz 5 MHz 5 MHz C4, C58 36 C20, C42 450 0x2 2.5 MHz 2.5 MHz 2.5 MHz C5, C57 78 C21, C41 −1909 0x3 2.5 MHz 2.5 MHz 2.5 MHz C6, C56 −84 C22, C40 103 Decimation Filters C7, C55 −98 C23, C39 2612 C8, C54 170 C24, C38 −1147 The fixed decimation filters reduce the sample rate from 640 MSPS C9, C53 97 C25, C37 −3326 to 40 MSPS. A fixed frequency low-pass filter is used to define C10, C52 −291 C26, C36 3022 the signal band. This filter incorporates magnitude equalization C11, C51 −42 C27, C35 4051 for the droop of the preceding sinc decimation filters and the sinc filters of the sample rate converter. Table 14 and Table 15 C12, C50 441 C28, C34 −6870 detail the coefficients for the DEC4 and LPF/EQZ filters. Sinc filter C13, C49 −98 C29, C33 −5305 implementation for all sinc filters is standard. C14, C48 −592 C30, C32 21,141 C15, C47 353 C31 38,956 BANDWIDTH SELECTION DECIMATION FILTERS 10MHz 10MHz DEC1 DEC2 DEC3 DEC4 LPF/EQZ DEC01 5MHz 5MHz 4 3 4 4 6 FIR SINC 2 SINC 2 SINC 2 SINC 2 HB 2 Σ-Δ 2.5MHz 2.5MHz OUTPUT DEC02 3 INT1 INT2 INT3 INT4 SINC 2 10MHz 16 5MHz 5 5 2 SINC HB 2 HB 2 SINC 4 8 DATA 2.5MHz OUTPUT SAMPLE RATE CONVERTER NCO Figure 54. Digital Engine Rev. A | Page 21 of 32 07772-050 AD9262 Sample Rate Converter If the main clocking source of the AD9262 is provided by the The sample rate converter (SRC) allows the flexibility of a PLL, it is important, once the PLL has been programmed and user-defined output sample rate, enabling a more efficient locked, to initiate an SRC reset before programming the desired and direct interface to the digital receiver blocks. KOUT factor. This is done by first writing 0x101[5:0] = 0 and then rewriting to the same register with the appropriate KOUT The sample rate converter performs an interpolation and value. In addition, if the AD9262 loses its clock source and then resampling procedure to provide an output data rate of later regains it, an SRC reset should be initiated. 20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coefficients for the INT1 and INT2 filters. The sinc filters Table 18. SRC Conversion Factors are a standard implementation. 0x101[5:0] K 0x101[5:0] K 0x101[5:0] K OUT OUT OUT The relationship between the output sample rate and the Σ-Δ 0 SRC reset 22 11 44 22 1 4 23 11.5 45 22.5 modulator clock rate is expressed as follows: 2 4 24 12 46 23 fOUT = fMOD ÷ KOUT 3 4 25 12.5 47 23.5 Table 18 shows the available KOUT conversion factors. 4 4 26 13 48 24 5 4 27 13.5 49 24.5 Table 16. INT1 Filter Coefficients 6 4 28 14 50 25 Coefficient Coefficient 7 4 29 14.5 51 25.5 Number Coefficient Number Coefficient 8 4 30 15 52 26 9 4.5 31 15.5 53 26.5 C0, C26 15 C7, C19 0 10 5 32 16 54 27 C1, C25 0 C8, C18 2450 11 5.5 33 16.5 55 27.5 C2, C24 −97 C9, C17 0 12 6 34 17 56 28 C3, C23 0 C10, C16 −5761 13 6.5 35 17.5 57 28.5 C4, C22 361 C11, C15 0 14 7 36 18 58 29 C5, C21 0 C12, C14 20,433 15 7.5 37 18.5 59 29.5 C6, C20 −1017 C13 32,768 16 8 38 19 60 30 17 8.5 39 19.5 61 30.5 Table 17. INT2 Filter Coefficients 18 9 40 20 62 31 19 9.5 41 20.5 63 31.5 Coefficient Coefficient Number Coefficient Number Coefficient 20 10 42 21 21 10.5 43 21.5 C0, C14 −27 C4, C10 −1032 C1, C13 0 C5, C9 0 C2, C12 227 C6, C8 4928 C3, C11 0 C7 8192 Rev. A | Page 22 of 32 AD9262 Cascaded Filter Responses DC AND QUADRATURE ERROR CORRECTION (QEC) The cascaded filter responses for the three signal bandwidth In direct conversion or other quadrature systems, mismatches settings are for a 160 MSPS output data rate, as shown in Figure 55, between the real (I) and imaginary (Q) signal paths cause Figure 56, and Figure 57. frequencies in the positive spectrum to image into the negative spectrum and vice versa. From an RF point of view, this is 0 0.08 equivalent to information above the LO frequency interfering –20 0.04 with information below the LO frequency, and vice versa. These –40 0 mismatches may occur from gain and/or phase mismatches in the analog quadrature demodulator or in any components in –60 –0.04 the ADC signal chain itself. In a single-carrier zero-IF system –0.08 –80 where the carrier has been placed symmetrically around dc, this 02 4 6 8 10 FREQUENCY (MHz) –100 causes self-distortion of the carrier as the two sidebands fold onto one another and degrade the EVM of the signal. –120 In a multicarrier communication system, this can be even more –140 problematic because carriers of widely different power levels –160 can interfere with one another. For example, a large carrier 0 102030 40506070 80 centered at +f1 can have an image appear at –f1 that can be FREQUENCY (MHz) larger than the desired carrier at this frequency. Figure 55. 10 MHz Signal Bandwidth, 160 MSPS The integrated quadrature error correction (QEC) algorithm of 0 the AD9262 attempts to measure and correct the amplitude and 0.08 –20 phase imbalances of the I and Q signal paths to achieve higher 0.04 levels of image suppression than is achievable by analog means –40 0 alone. These errors can be corrected in an adapted manner –60 –0.04 where the I and Q gain and quadrature phase mismatches are –0.08 –80 constantly estimated and corrected. This allows changes in the 01 2 3 4 5 mismatches due to slow supply and temperature changes to be FREQUENCY (MHz) –100 constantly tracked. –120 The quadrature errors are corrected in a frequency independent –140 manner on the AD9262; therefore, systems with significant mismatch in the baseband chain may have reduced image –160 suppression. The AD9262 QEC still corrects the systematic 0 102030 40506070 80 FREQUENCY (MHz) imbalances. Figure 56. 5 MHz Signal Bandwidth, 160 MSPS The convergence time of the QEC algorithm is dependent on the statistics of the input signal. For large signals and large 0 0.08 imbalance errors, this convergence time is typically less than –20 0.04 two million samples of the AD9262 output data rate. –40 0 LO Leakage (DC) Correction –60 –0.04 In a direct conversion receiver subsystem, LO to RF leakage of –0.08 –80 the quadrature modulator shows up as dc offsets at baseband. 0.5 1.5 2.5 FREQUENCY (MHz) These offsets are added to dc offsets in the baseband signal –100 paths, and both contribute to a carrier at dc. In a zero-IF receiver, –120 this dc energy can cause problems because it appears in band of a desired channel. As part of the AD9262 QEC function, the dc –140 offset is suppressed by applying a low frequency notch filter to –160 form a null around dc. The 3 dB bandwidth of this notch filter 0 102030 40506070 80 vs. the AD9262 output data rates is shown in Figure 58. FREQUENCY (MHz) Figure 57. 2.5 MHz Signal Bandwidth, 160 MSPS Rev. A | Page 23 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07772-053 07772-052 07772-051 AD9262 60 Interleaved Outputs The AD9262 has the added feature of interleaving Channel A 50 and Channel B data onto one 16-bit bus. This feature is availa- ble for integer values of KOUT greater than 8 and does not apply 40 to half values of KOUT. The interleave function can be accessed by writing to Register 0x14[5]. The data from both Channel A 30 and Channel B are interleaved and presented on the Channel A bus, whereas the Channel B bus is internally grounded. Channel 20 A is sampled on the falling edge of DCO and Channel B on the rising edge. The output of Channel A and Channel B can be 10 interchanged by inverting the DCO clock, Register 0x16[7]. In this case, Channel B is sampled on the falling edge and Channel A 0 30 50 70 90 110 130 150 on the rising edge. OUTPUT DATA RATE (MSPS) DCO Figure 58. DC Correction Low Frequency Notch Filter 3 dB Bandwidth vs. Output Data Rate DCO In applications where constant tracking of the dc offsets and BUS A A BABA quadrature errors are not needed, the algorithms can be independently frozen to save power. When frozen, the image BUS B and LO leakage (dc) correction are still performed, but changes Figure 59. Interleaved Output Mode are no longer tracked. Register 0x112[5:3] disables the Overrange (OR) Condition respective correction when frozen. The ORA and ORB (ORx) pins serve as indicators for an overrange The quadrature gain, quadrature phase, and dc correction condition. The ORx pins are triggered by in-band signals that algorithms can also be disabled independently for system exceed the full-scale range of the ADC. In addition, the AD9262 debugging or to save power by setting Register 0x112[2:0]. possesses out-of-band gain above 10 MHz. Therefore, a large The default configuration on the AD9262 has the QEC and dc out-of-band signal may trip an overrange condition. correction blocks disabled, and Register 0x101[6] must be The ORx pins are synchronous outputs that are updated at the pulled high to enable the correction blocks. After the QEC is output data rate. Ideally, ORx should be latched on the falling enabled and a correction value has been calculated, the value edge of DCO to ensure proper setup-and-hold time. However, remains active as long as any one of the QEC functions (DC, because an overrange condition typically extends well beyond one gain, or phase correction) is used. clock cycle (that is, it does not toggle at the DCO rate) data can QEC and DC Correction Range usually be successfully detected on the rising edge of DCO or Table 19 gives the minimum and maximum correction ranges monitored asynchronously. of the algorithms on the AD9262 If the mismatches are greater The AD9262 has two trip points that can trigger an overrange than these ranges, an imperfect correction results. condition: analog and digital. The analog trip point is located in the modulator ,and the second trip point is in the digital engine. Table 19. QEC and DC Correction Range In normal operation, it is possible for the analog trip point to Parameter Min Max toggle the ORx pin for a number of clock cycles as the analog Gain −1.1 dB +1.0 dB input approaches full scale. Because the ORx pin is a pulse-width Phase −1.79 degrees +1.79 degrees modulated (PWM) signal, as the analog input increases in ampli- DC −6 % +6% tude, the duration of overrange pin toggling increases. Eventually, DIGITAL OUTPUTS when the ORx pin is high for an extended period of time, the Digital Output Format ADC is overloaded, whereby there is little correspondence The AD9262 offers a variety of digital output formats for ease of between analog input and digital output. system integration. The digital output on each channel consists The second trip point is in the digital block. If the input signal is of 16 data bits and an output clock signal (DCO) for data latching. large enough to cause the data bits to clip to its maximum full- The data bits can be configured for offset binary, twos comple- scale level, an overrange condition occurs. The overrange trip ment, or Gray code by writing to Register 0x14[1:0]. In addition, point can be adjusted by specifying a threshold level. the voltage swing of the digital outputs can be configured to 3.3 V TTL levels or a reduced voltage swing of 1.8 V by accessing Register 0x14[7]. When 3.3 V voltage levels are desirable, the DRVDD power supply must be set to 3.3 V. Rev. A | Page 24 of 32 3dB BANDWIDTH (Hz) 07772-072 07772-094 AD9262 Table 20 shows the corresponding threshold level in dBFS vs. occurs, the modulator resets itself after 16 consecutive clock register setting. If the input signal crosses this level, the ORx pin cycles of overrange. is set. In the case where 0x111[5:0] is set to all 0s, the threshold If the AD9262 is used in a system that incorporates automatic level is set to the maximum code of 32,76710. This feature pro- gain control (AGC), the ORx signal can be used to indicate that vides a means of reporting the instantaneous amplitude as it the signal amplitude should be reduced. This may be particularly crosses a user-provided threshold. This gives the user a sense effective for use in maximizing the signal dynamic range if the of the signal level without needing to perform a full power signal includes high occurrence components that occasionally measurement. exceed full scale by a small amount. The user has the ability to select how the overrange conditions TIMING are reported, and this is controlled through Register 0x111 via The AD9262 provides a data clock out (DCO) pin to assist in AUTORST, OR_IND, and ORTHRESH (see Table 21). By capturing the data in an external register. The data outputs are enabling the AUTORST bit, Register 0x111[7], if an overrange valid on the rising edge of DCO, unless changed by setting occurs, the ADC automatically resets itself. The ORx pins remain Serial Register 0x16[7] (see the Serial Port Interface (SPI) high until the automatic reset has completed. If an analog trip section). See Figure 2 for a graphical timing description. Table 20. OR Threshold Levels 0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS) 1 −36.12 16 −9.28 2B −3.45 2 −30.10 17 −8.89 2C −3.25 3 −26.58 18 −8.52 2D −3.06 4 −24.08 19 −8.16 2E −2.87 5 −22.14 1A −7.82 2F −2.68 6 −20.56 1B −7.50 30 −2.50 7 −19.22 1C −7.18 31 −2.32 8 −18.06 1D −6.88 32 −2.14 9 −17.04 1E −6.58 33 −1.97 A −16.12 1F −6.30 34 −1.80 B −15.29 20 −6.02 35 −1.64 C −14.54 21 −5.75 36 −1.48 D −13.84 22 −5.49 37 −1.32 E −13.20 23 −5.24 38 −1.16 F −12.60 24 −5.00 39 −1.00 10 −12.04 25 −4.76 3A −0.86 11 −11.51 26 −4.53 3B −0.71 12 −11.02 27 −4.30 3C −0.56 13 −10.56 28 −4.08 3D −0.42 14 −10.10 29 −3.87 3E −0.28 15 −9.68 2A −3.66 3F −0.14 Table 21. ORx Conditions ORx Conditions AUTORST OR_IND ORTHRESH[5:0] ORTHRESH[4:0] Description Normal, Reset Off 0 0 0 00000 Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0 Digital Threshold, 0 0 >0 Digital threshold: if 16-bit output > ORTHRESH, ORx = 1, Reset Off else ORx = 0 Full Overrange, 0 1 0 X If analog trip or digital trip, ORx = 1, else ORx = 0 Reset Off Data Valid, No Reset 0 1 1 X If analog trip or digital trip or calibration, ORx = 0, else ORx = 1 Normal, Reset On 1 0 0 00000 Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0 Digital Threshold, 1 0 >0 Digital threshold: if 16-bit output > ORTHRESH, ORx = 1, Reset On else ORx = 0 Full Overrange, 1 1 0 X If analog trip or digital trip ORx = 1 else ORx = 0 Reset On Data Valid, 1 1 1 X If analog trip or digital trip or calibration, ORx = 0 else ORx = 1 Reset On Rev. A | Page 25 of 32 AD9262 SERIAL PORT INTERFACE (SPI) During an instruction phase, a 16-bit instruction is transmitted. The AD9262 serial port interface (SPI) allows the user to configure Data follows the instruction phase, and the length is determined the converter for specific functions or operations through a by the W0 bit and the W1 bit. All data is composed of 8-bit words. structured register space provided inside the ADC. This provides The first bit of each individual byte of serial data indicates whether the user added flexibility and customization depending on the a read or write command is issued. This allows the serial data application. Addresses are accessed via the serial port and can input/output (SDIO) pin to change direction from an input to be written to or read from via the port. Memory is organized an output. into bytes that are further divided into fields, as documented in the Memory Map section. For detailed operational information, In addition to word length, the instruction phase determines if see the AN-877 Application Note, Interfacing to High Speed the serial frame is a read or write operation, allowing the serial ADCs via SPI. port to be used to both program the chip and to read the contents of the on-chip memory. If the instruction is a readback opera- CONFIGURATION USING THE SPI tion, performing a readback causes the serial data input/output As summarized in Table 22, three pins define the SPI of this ADC. (SDIO) pin to change direction from an input to an output at the The SCLK pin synchronizes the read and write data presented appropriate point in the serial frame. to the ADC. The SDIO pin allows data to be sent and read from Data can be sent in MSB-first or in LSB-first mode. MSB first is the internal ADC memory map registers. The CSB pin is an active the default setting on power-up and can be changed via the low control that enables or disables the read and write cycles. configuration register. For more information, see the AN-877 Table 22. Serial Port Interface Pins Application Note, Interfacing to High Speed ADCs via SPI. Pin Name Description Table 23. SPI Timing Diagram Specifications SCLK SCLK (serial clock) is the serial shift clock. SCLK Parameter Description synchronizes serial interface reads and writes. t Setup time between data and rising edge of SCLK SDIO SDIO (serial data input/output) is an input and SDS output depending on the instruction being sent tSDH Hold time between data and rising edge of SCLK and the relative position in the timing frame. tSCLK Period of the clock CSB (chip select bar) is an active low control that CSB tSS Setup time between CSB and SCLK gates the read and write cycles. t Hold time between CSB and SCLK SH The falling edge of CSB in conjunction with the rising edge of t Minimum period that SCLK should be in a logic SHIGH SCLK determines the start of the framing. Figure 60 and Table 23 high state provide an example of the serial timing and its definitions. tSLOW Minimum period that SCLK should be in a logic low state Other modes involving CSB are available. CSB can be held low indefinitely to permanently enable the device (this is called streaming). CSB can stall high between bytes to allow for addi- tional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. t t t t SDS SHIGH SCLK SH t t SS SDH t SLOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 60. Serial Port Interface Timing Diagram Rev. A | Page 26 of 32 07772-054 AD9262 The SPI interface is flexible enough to be controlled by either HARDWARE INTERFACE PROM or PIC microcontrollers. This provides the user with the The pins described in Table 22 comprise the physical interface ability to use an alternate method to program the ADC. One between the programming device of the user and the serial port such method is described in detail in the AN-812 Application of the AD9262. The SCLK and CSB pins function as inputs Note, MicroController-Based Serial Port Interface (SPI) Boot when using the SPI interface. The SDIO pin is bidirectional, Circuit. functioning as an input during write phases and as an output during readback. Rev. A | Page 27 of 32 AD9262 APPLICATIONS INFORMATION Figure 61 shows the gain profile of the AD9262, and this can be FILTERING REQUIREMENT interpreted as the level at which the signal power should be The need for antialias protection often requires one or two scaled back to prevent an overload condition. This is the ulti- octaves for a transition band, which reduces the usable band- mate trip point and before this point is reached, the in-band width of a Nyquist converter to between 25% and 50% of the noise (IBN) slowly degrades. As a result, it is recommended that available bandwidth. A CT Σ-Δ converter maximizes the availa- the low-pass filter be designed to match the profile of Figure 62, ble signal bandwidth by forgoing the need for an anti-aliasing which shows the maximum input signal for a 3 dB degradation filter because the architecture possesses inherent anti-aliasing. of in-band noise. The input signal is attenuated to allow only Although a high order, sharp cutoff antialiasing filter may not 3 dB of noise degradation over frequency. be necessary because of the unique characteristics of the The noise performance is normalized to a −2 dBFS in-band architecture, a low order filter may still be required to precede signal. The AD9262 STF and NTF are flat within the band of the ADC for out-of-band signal handling. interest and should result in almost no change in input level Depending on the application and the system architecture, this and IBN. Beyond the bandwidth of the AD9262, out-of-band low order filter may or may not be necessary. The signal trans- peaking adds gain to the system, therefore requiring the input fer function (STF) of a continuous time feedforward ADC power to be scaled back to prevent in-band noise degradation. usually contains out-of-band peaks. Because these STF peaks The input power is scaled back to a point where only 3 dB of are typically one or two octaves above the pass-band edge, they noise degradation is allowed, therefore resulting in the response are not problematic in applications where the bulk of the signal shown in Figure 62. energy is in or near the pass band. However, in applications 5 with large far-out interferers, it is necessary to either add a filter to attenuate these problematic signals or to allocate some of the 0 ADC dynamic range to accommodate them. Figure 61 shows the normalized STF of the AD9262 CT Σ-Δ –5 converter. The figure shows out-of-band peaking beyond the –40°C band edge of the ADC. Within the 10 MHz band of interest, the –10 STF is maximally flat with less than 0.1 dB of gain. Maximum –15 peaking occurs at 60 MHz with 10 dB of gain. To put this into +85°C perspective, for a fixed input power, a 5 MHz in-band signal +25°C –20 CHEBYSHEVII appears at −5 dBFS, a 25 MHz tone appears at −2 dBFS and FILTER RESPONSE 60 MHz tone at +5 dBFS. Because the maximum input to the –25 ADC is −2 dBFS, large out-of-band signals can quickly saturate 0 1020 3040 5060 708090 100 the system. This implies that, under these conditions, the digital FREQUENCY (MHz) outputs of the ADC no longer accurately represent the input. Figure 62. Maximum Input Level for 3 dB Noise Degradation See the Overrange (OR) Condition section for details on over- An example third-order, low-pass Chebyshev II type filter is range detection and recovery. shown in Figure 63. Table 24 summarizes the components 15 and manufacturers used to build the circuit. 13 L1 180nH 11 9 VIN+ C2 7 390pF C3 C1 AD9262 150pF 1kΩ 18pF CT-Σ-Δ 5 L1 180nH VIN– 3 1 C2 390pF –1 Figure 63. Third-Order, Low-Pass Chebyshev II Filter –3 –5 0 102030405060708090 100 FREQUENCY (MHz) Figure 61. STF Rev. A | Page 28 of 32 GAIN (dB) 07772-073 AMPLITUDE (dB) 07772-095 07772-074 AD9262 Table 24. Chebyshev II Filter Components In addition to matching the profile of Figure 62, group delay and channel matching are important filter design criteria. Low Parameter Value Unit Manufacturer tolerance components are highly recommended for improved C1 18 pF Murata GRM188 series, 0603 channel matching, which translates to minimal degradation in L1 180 nH Coil Craft 0603 LS, 2% image rejection for quadrature systems. C2 390 pF Murata GRM188 series, 0603 C3 150 pF Murata GRM188 series, 0603 Rev. A | Page 29 of 32 AD9262 MEMORY MAP Table 25. Memory Map Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Port Config 0x00 0 LSBFIRST SOFTRESET 1 1 SOFTRESET LSBFIRST 0 Chip ID 0x01 CHIPID[7:0] Chip Grade 0x02 1 CHILDID[2:0] Channel Index 0x05 Channel[1:0] Power Modes 0x08 PWRDWN[1:0] PLLENABLE 0x09 PLLENABLE PLL 0x0A PLLLOCKED PLLAUTO PLLMULT[5:0] Analog Input 0x0F BW[1:0] Output Modes 0x14 DRVSTD Interleave OUTENB OUTINV Format[1:0] Output Adjust 0x15 DRVSTR33[1:0] DRVSTR18[1:0] Output Clock 0x16 DCOINV Reference 0x18 EXTREF Output Data 0x101 QEC KOUT[5:0] Overrange 0x111 AUTORST OR_IND ORTHRESH[5:0] QEC1 0x112 DCFRZ PHASEFRZ GAINFRZ DCENB PHASEENB GAINENB QEC2 0x113 DCFRC PHASEFRC GAINFRC MEMORY MAP DEFINITIONS Table 26. Memory Map Definitions Register Address Bit(s) Mnemonic Default Description SPI Port Config 0x00 6, 1 LSBFIRST 0 0: serial interface uses MSB first format 1: serial interface uses LSB first format 5, 2 SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A Chip ID 0x01 [7:0] CHIPID 0x22 0x22: AD9262 Chip Grade 0x02 [5:4] CHILDID 0 0x00: 10 MHz bandwidth 0x10: 5 MHz bandwidth 0x20: 2.5 MHz bandwidth Channel Index 0x05 [1:0] Channel 0 0: both channels addressed simultaneously 1: Channel A only addressed 2: Channel B only addressed 3: both channels addressed simultaneously Power Modes 0x08 [1:0] PWRDWN 0 0x0: normal operation 0x1: power-down (local) 0x2: standby (everything except reference circuits) 0x3: sleep PLLENABLE 0x09 2 PLLENABLE 0 1: enable PLL PLL 0x0A 7 PLLLOCKED 0 0: PLL is not locked 1: PLL is locked 6 PLLAUTO 0 1: PLL autoband enabled [5:0] PLLMULT 0 See Table 10 Analog Input 0x0F [6:5] BW 0 See Table 13 Rev. A | Page 30 of 32 AD9262 Register Address Bit(s) Mnemonic Default Description Output Modes 0x14 7 DRVSTD 0 0: 3.3 V 1: 1.8 V 5 Interleave 0 1: interleave both channels onto D[15:0]A 4 OUTENB 0 1: data outputs tristated 2 OUTINV 0 1: data outputs bitwise inverted [1:0] Format 0 0: offset binary 1: twos complement 2: Gray code 3: offset binary Output Adjust 0x15 [3:2] DRVSTR33 0 Typical output sink current to DGND 0: 33 mA 1: 63 mA 2: 93 mA 3: 120 mA [1:0] DRVSTR18 2 Typical output sink current to DGND 0: 10 mA 1: 20 mA 2: 30 mA 3: 39 mA Output Clock 0x16 7 DCOINV 0 1: invert DCO Reference 0x18 6 EXTREF 0 1: use external reference Output Data 0x101 6 QEC 0 1: enable quadrature error correction [5:0] KOUT 0 Output data rate, see Table 18 Overrange 0x111 7 AUTORST 0 1: enable loop filter reset indicator on ORx pin 6 OR_IND 0 Refer to Table 21 [5:0] ORTHRESH 0 Refer to Table 20 QEC1 0x112 5 DCFRZ 0 1: freeze dc correction coefficients 4 PHASEFRZ 0 1: freeze phase correction coefficients 3 GAINFRZ 0 1: freeze gain correction coefficients 2 DCENB 0 1: disable dc correction 1 PHASEENB 0 1: disable phase correction 0 GAINENB 0 1: disable gain correction QEC2 0x113 2 DCFRC 0 1: force dc correction coefficients to initial static values 1 PHASEFRC 0 1: force phase correction coefficients to initial static values 0 GAINFRC 0 1: force gain correction coefficients to initial static values Rev. A | Page 31 of 32 AD9262 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 64. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9262BCPZ-10 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9262BCPZ-5 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9262BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9262EBZ Evaluation Board AD9262-5EBZ Evaluation Board AD9262-10EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07772-0-2/10(A) Rev. A | Page 32 of 32 091707-C