ANALOG DEVICES AD9261

16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC AD9261 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input OR SFDR: 87 dBc to 10 MHz input VIN+ SAMPLE D15 Noise figure: 15 dB LOW-PASS Σ-Δ CMOS RATE DECIMATION MODULATOR BUFFER Input impedance: 1 kΩ FILTER CONVERTER VIN– D0 Power: 340 mW PLL_ LOCKED 1.8 V analog supply operation PHASE 1.8 V to 3.3 V output supply CLK+ LOCKED VREF AD9261 CLK– LOOP Selectable bandwidth 2.5 MHz/5 MHz/10 MHz SERIAL DCO CFILT INTERFACE Output data rate: 30 MSPS to 160 MSPS Integrated decimation filters AGND SDIO SCLK CSB DGND Integrated sample rate converter Figure 1. On-chip PLL clock multiplier On-chip voltage reference Offset binary, Gray code, or twos complement data format Serial control interface (SPI) APPLICATIONS Data acquisition Automated test equipment Instrumentation Medical imaging GENERAL DESCRIPTION The AD9261 is a single 16-bit analog-to-digital converter The digital output data is presented in offset binary, Gray code, (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ) or twos complement format. A data clock output (DCO) is architecture that achieves 87 dBc of dynamic range over a 10 MHz provided to ensure proper timing with the receiving logic. input bandwidth. The integrated features and characteristics The AD9261 operates on a 1.8 V analog supply and a 1.8 V unique to the continuous time Σ-Δ architecture significantly to 3.3 V digital supply, consuming 340 mW. The AD9261 is simplify its use and minimize the need for external components. available in a 48-lead LFCSP and is specified over the industrial The AD9261 has a resistive input impedance that relaxes the temperature range (−40°C to +85°C). requirements of the driver amplifier. In addition, a 32× oversam- PRODUCT HIGHLIGHTS pled fifth-order continuous time loop filter significantly attenuates 1. Continuous time Σ-Δ architecture efficiently achieves high out-of-band signals and aliases, reducing the need for external dynamic range and wide bandwidth. filters at the input. 2. Passive input structure reduces or eliminates the require- An external clock input or the integrated integer-N PLL provides ments for a driver amplifier. the 640 MHz internal clock needed for the oversampled conti- 3. An oversampling ratio of 32× and high order loop filter nuous time Σ-Δ modulator. On-chip decimation filters and sample provide excellent alias rejection reducing or eliminating the rate converters reduce the modulator data rate from 640 MSPS to a need for antialiasing filters. user-defined output data rate from 30 MSPS to 160 MSPS, 4. An integrated decimation filter, sample rate converter, PLL enabling a more efficient and direct interface. clock multiplier, and voltage reference provide ease of use. 5. This part operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07803-001 AD9261 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................9  Applications ....................................................................................... 1  Equivalent Circuits ......................................................................... 13  Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 14  General Description ......................................................................... 1  Analog Input Considerations ................................................... 14  Product Highlights ........................................................................... 1  Clock Input Considerations ...................................................... 16  Revision History ............................................................................... 2  Power Dissipation and Standby Mode .................................... 18  Specif ica t ions ..................................................................................... 3  Digital Engine ............................................................................. 19  DC Specifications ......................................................................... 3  Digital Outputs ........................................................................... 21  AC Specifications .......................................................................... 4  Timing ......................................................................................... 21  Digital Decimation Filtering Characteristics ............................ 4  Serial Port Interface (SPI) .............................................................. 23  Digital Specifications ................................................................... 5  Configuration Using the SPI ..................................................... 23  Switching Specifications .............................................................. 6  Hardware Interface ..................................................................... 24  Absolute Maximum Ratings ............................................................ 7  Memory Map .................................................................................. 25  Thermal Resistance ...................................................................... 7  Memory Map Definitions ......................................................... 25  ESD Caution .................................................................................. 7  Outline Dimensions ....................................................................... 27  Pin Configuration and Function Descriptions ............................. 8  Ordering Guide .......................................................................... 27  REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9261 SPECIFICATIONS DC SPECIFICATIONS 1 All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 1. Parameter Temp Min Typ Max Unit RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.02 ±0.15 % FSR Gain Error Full ±0.7 ±3.0 % FSR 2 Integral Nonlinearity (INL) Full ±1.5 LSB TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 V Input Resistance Full 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 V Supply Current 2 IAVDD Full 74 83 mA 2 I PLL Enabled Full 57 654 mA CVDD 2 I PLL Disabled Full 8.0 8.8 mA CVDD 2 I Full 100 108 mA DVDD 2 IDRVDD (1.8 V) Full 5.5 5.8 mA 2 IDRVDD (3.3 V) Full 10 mA POWER CONSUMPTION 2 Sine Wave Input PLL Disabled Full 340 370 mW 2 Sine Wave Input PLL Enabled Full 425 465 mW Power-Down Power Full 20 mW 2 Standby Power Full 7 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. 0 | Page 3 of 28 AD9261 AC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 2. 1 Parameter Temp Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 81 83 dB fIN = 4.2 MHz 25°C 83 dB f = 8.4 MHz 25°C 83 dB IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 13.5 Bits f = 4.2 MHz 25°C 13.5 Bits IN f = 8.4 MHz 25°C 13.5 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz Full 87 80 dBc IN f = 4.2 MHz 25°C 87 dBc IN fIN = 8.4 MHz 25°C <120 dBc NOISE SPECTRAL DENSITY (NSD) AIN= −2 dBFS Full −155 −153 dB/Hz AIN = −40 dBFS Full −156 −154.5 dB/Hz 2 NOISE FIGURE 25°C 15 dB TWO-TONE SFDR f = 2.1 MHz at −8 dBFS, f = 2.4 MHz at −8 dBFS 25°C 93 dBc IN1 IN2 f = 3.6 MHz at −8 dBFS, f = 4.2 MHz at −8 dBFS 25°C 92.5 dBc IN1 IN2 f = 7.2 MHz at −8 dBFS, f = 8.4 MHz at −8 dBFS 25°C 92.5 dBc IN1 IN2 ANALOG INPUT BANDWIDTH 25°C 10 MHz APERTURE JITTER 25°C 1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. DIGITAL DECIMATION FILTERING CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 3. 2.5 MHz BW 5 MHZ BW 10 MHz BW 1 Parameter Min Typ Max Min Typ Max Min Typ Max Unit Pass-Band Transition 2.5 3.75 5 6.5 10 13 MHz Pass-Band Ripple <0.1 <0.1 <0.1 dB Stop Band 3.75 MHz − fS/2 6.5 MHz − fS/2 13 MHz − fS/2 MHz Stop Band Attenuation >85 >85 >85 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 4 of 28 AD9261 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 4. 1 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVPECL Differential Input Voltage Full 0.4 0.8 2 V p-p Input Common-Mode Range Full 0.3 0.450 0.5 V High Level Input Current Full −60 +60 μA Low Level Input Current Full −60 +60 μA Input Resistance Full 20 kΩ Input Capacitance Full 1 pF LOGIC INPUTS (SCLK) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO, CSB, RESET) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (V , I = 50 μA) Full 3.29 V OH OH High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V DRVDD = 1.8 V High Level Output Voltage (V , I = 50 μA) Full 1.79 V OH OH High Level Output Voltage (V , I = 0.5 mA) Full 1.75 V OH OH Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 28 AD9261 SWITCHING SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 5. 1 Parameter Temp Min Typ Max Unit CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate Full 30 160 MSPS CLK± Period Full 6.25 33 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT (DIRECT CLOCKING) Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.49 1.5625 1.64 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS Output Data Rate Full 20 168 MSPS 2 DCO to Data Skew (tSKEW) Full 3 ns Sample Latency Full 960 Cycles 3 WAKE-UP TIME Full Power Down Power Full 3 μs Standby Power Full 9 μs Sleep Power Full 15 μs OUT-OF-RANGE RECOVERY TIME Full 960 Cycles 4 SERIAL PORT INTERFACE SCLK Period Full 40 ns SCLK Pulse Width High Time (t) Full 16 ns SHIGH SCLK Pulse Width Low Time (t) Full 16 ns SLOW SDIO to SCLK Setup Time (t) Full 5 ns SDS SDIO to SCLK Hold Time (tSDH) Full 2 ns CSB to SCLK Setup Time (tSS) Full 5 ns CSB to SCLK Hold Time (tSH) Full 2 ns 1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT. 4 See Figure 50 and the Serial Port Interface (SPI) section. Timing Diagram DCO t SKEW D0 TO D15 Figure 2. Timing Diagram Rev. 0 | Page 6 of 28 07803-002 AD9261 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB Electrical increases the reliability of the solder joints, maximizing the AVDD to AGND −0.3 V to +2.0 V thermal capability of the package. DVDD to DGND −0.3 V to +2.0 V DRVDD to DGND −0.3 V to +3.9 V Table 7. Thermal Resistance AGND to DGND −0.3 V to +0.3 V Package Type θJA θJB θJC Unit AVDD to DRVDD −3.9 V to +2.0 V 48-Lead LFCSP (CP-48-1) 27.7 11.8 1.1 °C/W CVDD to CGND −0.3 V to +2.0 V CGND to DGND −0.3 V to +0.3 V Typical θJA and θJC are specified for a 4-layer board in still air. D0 to D15 to DGND −0.3 V to +2.0 V Airflow increases heat dissipation, effectively reducing θJA. In DCO to DGND −0.3 V to +2.0 V addition, metal in direct contact with the package leads from OR to DGND −0.3 V to +2.0 V metal traces, through holes, ground, and power planes reduces PDWN to GND −0.3 V to +2.0 V the θ . JA PLLMULTx to DGND −0.3 V to +2.0 V SDIO to DGND −0.3 V to +3.9 V ESD CAUTION CSB to AGND −0.3 V to +3.9 V SCLK to AGND −0.3 V to +3.9 V VIN+, VIN− to AGND −0.3 V to +2.5 V CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 Sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 28 AD9261 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK– 1 36 PLLMULT0/SCLK PIN 1 CVDD 2 35 PLLMULT1/SDIO INDICATOR PDWN 3 34 PLLMULT2 33 PLLMULT3 DVDD 4 DGND 5 32 PLLMULT4 AD9261 DRVDD 6 31 DVDD PLL_LOCKED 7 30 DGND TOP VIEW (Not to Scale) 29 DRVDD DCO 8 D0 9 28 OR D1 10 27 D15 D2 11 26 D14 D3 12 25 D13 NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 PDWN External Power-Down Pin. 4, 19, 31 DVDD Digital Supply (1.8 V). 5, 18, 30 DGND Digital Ground. 6, 17, 29 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 7 PLL_LOCKED PLL Lock Indicator. 8 DCO Data Clock Output. 9 to 16, 20 to 27 D0 to D15 Data Output Bits. D0 is the LSB and D15 is the MSB. 28 OR Overrange Indicator. 32, 33, 34 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 35 PLLMULT1/SDIO PLL Mode Selection Pin/Serial Port Interface Data Input/Output. 36 PLLMULT0/SCLK PLL Mode Selection Pin/Serial Port Interface Clock. 37 CSB Serial Port Interface Chip Select. Active low. 38, 46 AGND Analog Ground. 39, 42, 45 AVDD Analog Supply (1.8 V). 40 VREF Voltage Reference Input/Output. 41 CFILT Noise Limiting Filter Capacitor. 43 VIN+ Analog Input (+). 44 VIN– Analog Input (−). 47 CGND Clock Ground. 48 CLK+ Clock Input (+). 49 EPAD Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package. Rev. 0 | Page 8 of 28 48 CLK+ D4 13 D5 14 47 CGND D6 15 46 AGND D7 16 45 AVDD DRVDD 17 44 VIN– DGND 18 43 VIN+ DVDD 19 42 AVDD D8 20 41 CFILT D9 40 VREF 21 D10 22 39 AVDD D11 23 38 AGND CSB D12 24 37 07803-003 AD9261 TYPICAL PERFORMANCE CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, TA = 25°C, unless otherwise noted. 0 0 BANDWIDTH: 2.5MHz BANDWIDTH: 2.5MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 600kHz AT –2dBFS f : 2.1MHz AT –8dBFS IN IN1 f : 2.5MHz AT –8dBFS SNR: 88.8dB IN2 –40 –40 SFDR: 90dBc SFDR: 90.6dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 141618 20 0 2 4 6 8 10 12 141618 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.5 MHz, and BW = 2.5 MHz Figure 4. Single-Tone FFT with fIN = 600 kHz and BW = 2.5 MHz 0 0 BANDWIDTH: 5MHz BANDWIDTH: 5MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 2.1MHz AT –8dBFS f : 1.2MHz AT –2dBFS IN1 IN f : 2.4MHz AT –8dBFS SNR: 86dB IN2 –40 –40 SFDR: 91.9dBc SFDR: 90.3dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 141618 20 0 2 4 6 8 10 12 141618 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Single-Tone FFT with f = 1.2 MHz and BW = 5 MHz IN Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz and BW = 5 MHz Rev. 0 | Page 9 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07803-015 07803-011 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07803-053 07803-052 AD9261 All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, 10 MHz bandwidth, output data rate 40 MSPS, T = 25°C, unless otherwise noted. A 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 2.4MHz AT –2dBFS : 2.1MHz AT –8dBFS f IN IN1 SNR: 83.2dB f : 2.4MHz AT –8dBFS IN2 –40 –40 SFDR: 92.6dBc SFDR: 91.2dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 141618 20 0 2 4 6 8 10 12 141618 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Single-Tone FFT with f = 2.4 MHz IN Figure 11. Two-Tone FFT with f = 2.1 MHz and f = 2.4 MHz IN1 IN2 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 3.6MHz AT –8dBFS f : 4.2MHz AT –2dBFS IN1 IN f : 4.2MHz AT –8dBFS IN2 SNR: 83.1dB –40 –40 SFDR: 92.2dBc SFDR: 91.5dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 141618 20 0 2 4 6 8 10 12 141618 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Single-Tone FFT with fIN = 4.2 MHz Figure 12. Two-Tone FFT with f = 3.6 MHz and f = 4.2 MHz IN1 IN2 0 0 BANDWIDTH: 10MHz BANDWIDTH: 10MHz DATA RATE: 40MSPS DATA RATE: 40MSPS –20 –20 f : 8.4MHz AT –2dBFS f : 7.2MHz AT –8dBFS IN IN1 f : 8.4MHz AT –8dBFS SNR: 83dB IN2 –40 –40 SFDR: 105.7dBc SFDR: 93dBc –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2 4 6 8 10 12 141618 20 0 2 4 6 8 10 12 141618 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Single-Tone FFT with f = 8.4 MHz Figure 13. Two-Tone FFT with f = 7.2 MHz and f = 8.4 MHz IN IN1 IN2 Rev. 0 | Page 10 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07803-020 07803-019 07803-018 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07803-056 07803-055 07803-054 AD9261 120 110 SFDR (dBFS) 105 100 SNR (dBFS) 100 80 60 95 SFDR (dBc) SFDR (dB) 40 90 SNR (dB) 20 85 SNR (dB) 80 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 01 2 3 4 5 6 7 8 9 10 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 14. Single-Tone SNR and SFDR vs. Input Amplitude with f = 2.4 MHz Figure 17. SNR/SFDR vs. Input Frequency IN –40 92 91 1.9V –50 SFDR 90 –60 1.8V 89 SFDR (dBc) –70 88 1.7V 87 –80 86 –90 85 SNR –100 84 1.9V SFDR (dB) 1.8V 83 –110 1.7V 82 –120 81 –60 –50 –40 –30 –20 –10 –60 –40 –20 0 20 40 60 80 100 INPUT AMPLITUDE (dBFS) TEMPERATURE (°C) Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude Figure 18. SFDR/SNR vs. Temperature with fIN = 2.4 MHz with f = 2.1 MHz and f = 2.4 MHz IN1 IN2 94 84.0 SFDR (dBc) 83.8 92 83.6 90 83.4 83.2 88 83.0 86 82.8 82.6 84 SNR (dBc) 82.4 82 82.2 80 82.0 20 40 60 80 100 120 140 160 1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.875 1.900 OUTPUT DATA RATE (MSPS) COMMON-MODE VOLTAGE (V) Figure 16: SNR/SFDR vs. Output Data Rate with f = 2.4 MHz Figure 19. SNR vs. Input Common Mode Voltage with f = 2.4 MHz IN IN Rev. 0 | Page 11 of 28 SNR/SFDR (dBc) SFDR (dBc AND dB) SNR/SFDR (dBFS AND dB) 07803-025 07803-024 07803-057 SNR (dB) SNR (dB)/SFDR (dBc) AMPLITUDE (dBFS) 07803-023 07803-059 07803-058 AD9261 1.0 84 83 0.5 2.4MHz 82 0 8.4MHz 81 –0.5 80 –1.0 79 –1.5 78 77 –2.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 1182 9 10 12 14 156 17 18 20 21 245 28 30 32 34 42 OUTPUT CODE PLL DIVIDE RATIO Figure 21. INL with f = 2.4 MHz Figure 20. Single-Tone SNR vs. PLL Divide Ratio IN Rev. 0 | Page 12 of 28 SNR (dB) 07803-026 INL ERROR (LSB) 07803-021 AD9261 EQUIVALENT CIRCUITS AVDD 26kΩ 1kΩ CSB 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 22. Equivalent Analog Input Circuit Figure 26. Equivalent CSB Input Circuit CVDD DRVDD CLK+ CLK– 10kΩ 10kΩ 90kΩ 30kΩ CVDD DRGND Figure 27. Equivalent Digital Output Circuit Figure 23. Equivalent Clock Input Circuit DRVDD 2.85kΩ 8.5kΩ 10kΩ 0.5V 1kΩ SDIO 10µF 3.5kΩ TO CURRENT GENERATOR Figure 28. Equivalent VREF Circuit Figure 24. Equivalent SDIO Input Circuit 1kΩ SCLK 30kΩ Figure 25. Equivalent SCLK Input Circuit Rev. 0 | Page 13 of 28 07803-005 07803-006 07803-007 07803-004 07803-008 07803-010 07803-009 AD9261 THEORY OF OPERATION DIGITAL FILTER CUTOFF FREQUENCY The AD9261 uses a continuous time Σ-Δ modulator to convert the analog input to a digital word. The digital word is processed by the decimation filter and rate-adjusted by the sample rate converter (see Figure 29). The modulator consists of a continuous f /32 f /16 time loop filter preceding a quantizer that samples at f = MOD MOD MOD BAND OF INTEREST 640 MSPS. This produces an oversampling ratio (OSR) of 32 for Figure 32. Digital Filter Cutoff Frequency a 10 MHz input bandwidth. The output of the quantizer is fed back to a DAC that ideally cancels the input signal. The incom- plete input cancellation residue is filtered by the loop filter and is used to form the next quantizer sample. MODULATOR f /2 f f /16 OUT OUT MOD DECIMATION SAMPLE RATE BAND OF INTEREST LOOP FILTER FILTER CONVERTER QUANTIZER Figure 33. Sample Rate Converter + SRC H(f) ADC – ANALOG INPUT CONSIDERATIONS The continuous time modulator removes the need for an anti- alias filter at the input to the AD9261. A discrete time converter Figure 29. Σ-Δ Modulator Overview aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 34). Therefore, an external The quantizer produces a nine-level digital word. The quantization antialias filter is needed to reject these signals. noise is spread uniformly over the Nyquist band (see Figure 30), DESIRED UNDESIRED but the feedback loop causes the quantization noise present in INPUT SIGNAL the nine-level output to have a nonuniform spectral shape. This noise-shaping technique (see Figure 31) pushes the in-band f f /2 S S noise out of band; therefore, the amount of quantization noise ADC in the frequency band of interest is minimal. Figure 34. Discrete Time Converter The digital decimation filter that follows the modulator removes the large out-of-band quantization noise (see Figure 32), while In contrast, the continuous time Σ-Δ modulator used within the also reducing the data rate from f to f /16. If the internal MOD MOD AD9261 has inherent antialiasing. The antialiasing property PLL is enabled, the sample rate converter generates samples at results from sampling occurring at the output of the loop filter the same frequency as the input clock frequency. If the internal (see Figure 35), and thus aliasing occurs at the same point in the PLL is disabled, the sample rate converter can be programmed loop as quantization noise is injected; aliases are shaped by the to give an output frequency that is a divide ratio of the modulator same mechanism as quantization noise. The quantization noise clock. The sample rate converter is designed to attenuate images transfer function, NTF(f), has zeros in the band of interest and in outside the band of interest (see Figure 33). all alias bands because NTF(f) is a discrete time transfer function, whereas the loop filter transfer function, LF(f), is a continuous time transfer function, which introduces poles only in the band of interest. The signal transfer function, being the product of QUANTIZATION NOISE NTF(f) and LF(f), only has zeros in alias bands and therefore f /2 MOD suppresses all aliases. BAND OF INTEREST LF(f) Figure 30. Quantization Noise LOOP FILTER INPUT LF(f) QUANTIZATION f MOD NOISE f MOD NOISE SHAPING OUTPUT H(z) f /2 MOD NTF(f) BAND OF INTEREST Figure 31. Noise Shaping f f MOD Figure 35. Continuous Time Converter Rev. 0 | Page 14 of 28 DAC 07803-031 07803-030 07803-029 07803-034 07803-033 07803-032 07803-035 AD9261 Input Common Mode 2V p-p VIN+ 50Ω 1:1 The analog inputs of the AD9261 are not internally dc biased. In R T V AD9261 S 50Ω ac-coupled applications, the user must provide this bias externally. SIGNAL VIN– Setting the device such that VCM = AVDD is recommended for SOURCE AVDD optimum performance. The analog inputs are 500 Ω resistors, 0.1µF and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 36). With 0 V differential input, Figure 38. Differential Transformer Configuration the driver sources 1 mA into each analog input. Voltage Reference AVDD – 0.5V A stable and accurate 0.5 V voltage reference is built into the 500Ω VIN+ AD9261. The reference voltage should be decoupled to minimize V =AVDD TO LOOP FILTER CM V p-p = 2V STAGE 2 IN the noise bandwidth using a 10 μF capacitor. The reference is VIN– 500Ω used to generate a bias current into a matched resistor such that, when used to bias the current in the feedback DAC, a voltage DAC of AVDD − 0.5 V is developed at the internal side of the input resistors (see Figure 39). The current bias circuit should also be FROM QUANTIZER decoupled on the CFILT pin with a 10 μF capacitor. For this Figure 36. Input Common Mode reason, the VREF voltage should always be 0.5 V. Differential Input Configurations AVDD – 0.5V The AD9261 can also be configured for differential inputs. The V =AVDD CM ADA4937-1 differential driver provides excellent performance V p-p = 2V 500Ω IN VIN+ and a flexible interface to the ADC. The output common-mode 500Ω VIN– 0.5V voltage of the ADA4937-1 is easily set by connecting AVDD to TO LOOP VREF 10kΩ FILTER the VOCM pin of the ADA4937-1 (see Figure 37). The noise and AVDD REF STAGE 2 10µF linearity of the ADA4937-1 needs important consideration because AVDD – 0.5V 500Ω the system performance may be limited by the ADA4937-1. +5V +1.8V 0.1µF CFILT 0.1µF 10µF VIN– 200Ω AVDD 8 Figure 39. Voltage Reference Loop 2V p-p 50Ω 200Ω 2 11 V Internal Reference Connection OCM 9 ADA4937-1 AD9261 V R S T 3 60.4Ω To minimize thermal noise, the internal reference on the AD9261 10 SIGNAL is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor, 15 SOURCE 200Ω which, when externally decoupled with a 10 μF capacitor, limits VIN+ 0.1µF 49.9Ω 60.4Ω the noise (see Figure 40). The unbuffered reference should not 0.1µF be used to drive any external circuitry. The internal reference is –5V used by default. Figure 37. Differential Input Configuration Using the ADA4937-1 For frequencies offset from dc, where SNR is a key parameter, differential transformer coupling is the recommended input 2.85kΩ 8.5kΩ configuration. An example is shown in Figure 38. The center 10kΩ 0.5V tap of the secondary winding of the transformer is connected to 10µF 3.5kΩ AVDD to bias the analog input. The signal characteristics must be considered when selecting a TO CURRENT GENERATOR transformer. Most RF transformers saturate at frequencies Figure 40. Internal Reference Configuration below a couple of megahertz (MHz), and excessive signal power can cause core saturation, which leads to distortion. Rev. 0 | Page 15 of 28 07803-036 07803-037 07803-040 07803-038 07803-039 AD9261 External Reference Operation In either case, using the on-chip clock multiplier to generate the Σ-Δ modulator clock rate or directly sourcing the clock, any If an external reference is desired, the internal reference can be deviation from 640 MHz results in a change in input bandwidth. disabled by setting Register 0x18[6] high. Figure 41 shows an The input range of the clock is limited to 640 MHz ± 5%. application using the ADR130B as a stable external reference. 0.5V Direct Clocking AVDD ADR130B 10kΩ 0.1µF 10µF The default configuration of the AD9261 is for direct clocking where the PLL is bypassed. Figure 42 shows one preferred method TO CURRENT for clocking the AD9261. A low jitter clock source is converted GENERATOR from a single-ended signal to a differential signal using an RF Figure 41. External Reference Configuration transformer. The back-to-back Schottky diodes across the CLOCK INPUT CONSIDERATIONS secondary side of the transformer limits clock excursions into the AD9261 to approximately 0.8 V p-p differential. This helps The AD9261 offers two modes of sourcing the ADC sample prevent the large voltage swings of the clock from feeding clock (CLK+ and CLK−). The first mode uses an on-chip clock through to other portions of the AD9261 while preserving the multiplier that accepts a reference clock operating at the lower fast rise and fall times of the signal, which are critical to input frequency. The on-chip phase-locked loop (PLL) then achieving low jitter. multiplies the reference clock up to a higher frequency, which is then used to generate all the internal clocks required by the ADC ® MINI-CIRCUITS TC1-1-13M+, 1:1 The clock multiplier provides a high quality clock that meets 0.1µF 0.1µF XFMR CLK+ CLOCK the performance requirements of most applications. Using the ADC INPUT AD9261 on-chip clock multiplier removes the burden of generating and 50Ω 0.1µF CLK– distributing the high speed clock. SCHOTTKY DIODES: The second mode bypasses the clock multiplier circuitry and 0.1µF HSM2812 allows the clock to be directly sourced. This mode enables the Figure 42. Transformer-Coupled Differential Clock user to source a very high quality clock directly to the Σ-Δ modulator. Sourcing the ADC clock directly may be necessary If a differential clock is not available, the AD9261 can be driven in demanding applications that require the lowest possible ADC by a single-ended signal into the CLK+ terminal with the CLK− output noise. Refer to Figure 20, which shows the degradation terminal ac-coupled to ground. Figure 43 shows the circuit in SNR performance for the various PLL settings. configuration. In either case, when using the on-chip clock multiplier or sourcing the high speed clock directly, it is necessary that the 0.1µF CLK+ clock source have low jitter to maximize the ADC noise CLOCK ADC INPUT performance. High speed, high resolution ADCs are sensitive to AD9261 50Ω CLK– the quality of the clock input. As jitter increases, the SNR SCHOTTKY performance of the AD9261 degrades from that specified in DIODES: 0.1µF Table 2. The jitter inherent to the part due to the PLL root sum HSM2812 squares with any external clock jitter, thereby degrading Figure 43. Single-Ended Clock performance. To prevent jitter from dominating the performance Another option is to ac couple a differential LVPECL signal to of the AD9261, the input clock source should be no greater than 1 ps rms of jitter. the sample clock input pins, as shown in Figure 44. The AD951x family of clock drivers is recommended because it offers excellent The CLK± inputs are self-biased to 450 mV (see Figure 23); if jitter performance. dc-coupled, it is important to maintain the specified 450 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p single-ended about the 450 mV 0.1µF 0.1µF CLOCK CLK+ CLK common-mode voltage. The recommended clock inputs are INPUT ADC AD951x CMOS or LVPECL. LVPECL 100Ω AD9261 DRIVER CLK– CLOCK CLK The specified clock rate of the Σ-Δ modulator, f , is 640 MHz. INPUT MOD 0.1µF 0.1µF 240Ω 240Ω The clock rate possesses a direct relationship with the available 1 1 50Ω 50Ω input bandwidth of the ADC. Bandwidth = fMOD ÷ 64 1 50Ω RESISTORS ARE OPTIONAL. Figure 44. Differential LVPECL Sample Clock Rev. 0 | Page 16 of 28 07803-041 07803-043 07803-042 07803-044 AD9261 Internal PLL Clock Distribution Table 10. Internal PLL Multiplication Factors 0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N) The alternative clocking option available on the AD9261 is to apply 1 8 33 32 a low frequency reference clock and use the on-chip clock multip- 2 8 34 34 lier to generate the high frequency fMOD rate. The internal clock 3 8 35 34 architecture is shown in Figure 45. 4 8 36 34 CLK+/CLK– PHASE LOOP 1.28GHz 5 8 37 34 DETECTOR FILTER VCO 6 8 38 34 PLL 7 8 39 34 DIVIDER 8 8 40 34 ÷N 9 9 41 34 10 10 42 42 ÷2 PLL MULT MODULATOR 0x0A[5:0] 11 10 43 42 CLOCK 640MSPS 12 12 44 42 13 12 45 42 PLLENABLE 0x09[2] 14 14 46 42 Figure 45. Internal Clock Architecture 15 15 47 42 16 16 48 42 The clock multiplication circuit operates such that the VCO 17 17 49 42 outputs a frequency, f , equal to the reference clock input VCO 18 18 50 42 multiplied by N 19 18 51 42 f = (CLK±) × (N) VCO 20 20 52 42 where N is the PLL multiplication (PLLMULT) factor. 21 21 53 42 22 21 54 42 The Σ-Δ modulator clock frequency, fMOD, is equal to 23 21 55 42 fMOD = fVCO ÷ 2 24 24 56 42 The reference clock, CLK±, is limited to 30 MHz to 160 MHz 25 25 57 42 when configured to use the on-chip clock multiplier. Given the 26 25 58 42 input range of the reference clock and the available multiplication 27 25 59 42 factors, the f is approximately 1280 MHz. This results in the VCO 28 28 60 42 desired f rate of 640 MHz with a 50% duty cycle. MOD 29 28 61 42 30 30 62 42 Before the PLL enable (PLLENABLE) register bit is set, the PLL 31 30 63 42 multiplication factor should be programmed into Register 32 32 64 42 0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and reports a locked state in Register 0x0A[7]. If the PLL multiplica- External PLL Control tion factor is changed, the PLL enable bit should be reset and set At power-up, the serial interface is disabled until the first serial again. Some common clock multiplication factors are shown in port access. If the serial interface is disabled, the PLLMULTx Table 11. pins control the PLL multiplication factor. The five PLLMULTx The recommended sequence for enabling and programming the pins (Pin 32 to Pin 36) offer all the available multiplication on-chip clock multiplier is summarized in Table 9. factors. If all PLLMULTx pins are tied high, the PLL is disabled and the AD9261 assumes the high frequency modulator clock Table 9. Sequence for Enabling and Programming the PLL rate that is applied to the CLK± pins. Table 12 shows the relation- Step Procedure ship between PLLMULTx pins and the PLL multiplication factor. 1 Apply a reference clock to the CLK± pins. 2 Program the PLL multiplication factor in Register 0x0A[5:0]. See Table 10. 3 Enable the PLL; Register 0x09 = 04 (decimal). 4 Enable the PLL autoband select. 5 Initiate an SRC reset; Register 0x101[5:0] = 0. 6 Set SRC to the desired value via Register 0x101[5:0]. Rev. 0 | Page 17 of 28 07803-045 AD9261 Jitter Considerations PLL Autoband Select The aperture jitter requirements for continuous time Σ-Δ conver- The PLL VCO has a wide operating range that is covered by ters may be more forgiving than Nyquist rate converters. The overlapping frequency bands. For any desired VCO output continuous time Σ-Δ architecture is an oversampled system, frequency, there are multiple valid PLL band select values. The and to accurately represent the analog input signal to the ADC, AD9261 possesses an automatic PLL band select feature on chip a large number of output samples must be averaged together. As a that determines the optimal PLL band setting. This feature can be result, the jitter contribution from each sample is root sum enabled by writing to Register 0x0A[6] and is the recommended squared, resulting in a more subtle impact on noise perfor- configuration with the PLL clocking option. Follow the sequence mance as compared to Nyquist converters where aperture jitter shown in Table 9 for enabling the autoband select and configur- has a direct impact on each sampled output. ing the PLL. In the block diagram of the continuous time Σ-Δ modulator When the device is taken out of sleep or standby mode, Register (see Figure 29), the two building blocks most susceptible to 0x0A[6] must be toggled to reinitiate the autoband detect. jitter are the quantizer and the DAC. The error introduced Table 11. Common Modulator Clock Multiplication Factors through the sampling process or quantizer is reduced by the CLK± 0x0A[5:0] f BW MOD loop gain and shaped in the same way as the quantization noise (MHz) (PLLMULT) fVCO (MHz) (MHz) (MHz) and, therefore, its effect can be neglected. On the contrary, the 30.72 42 1290.24 645.12 10.08 jitter error associated to the DAC directly adds to the input 39.3216 32 1258.29 629.15 9.83 signal, thus increasing the in-band noise power and degrading 25 1300.00 650.00 10.16 52.00 the modulator performance. The SNR degradation due to jitter 21 1290.24 645.12 10.08 61.44 can be represented by the following equation: 76.80 17 1305.60 652.80 10.20 SNR = −20 log (2πfanalogtjitter_rms) dB 78.00 17 1326.00 663.00 10.36 where f is the analog input frequency and t is the jitter. 78.6432 16 1258.29 629.15 9.83 analog jitter_rms 15 1344.00 672.00 10.50 89.60 The SNR performance of the AD9261 remains constant within 14 1290.24 645.12 10.08 92.16 the input bandwidth of the converter, from dc to 10 MHz. 122.88 10 1228.80 614.40 9.60 Therefore, the minimal jitter specification is determined at the 134.40 10 1344.00 672.00 10.50 highest input frequency. From the calculation, the aperture 153.60 8 1228.80 614.40 9.60 jitter of the input clock must be no greater than 1 ps to achieve 157.2864 8 1258.29 629.15 9.83 optimal SNR performance. POWER DISSIPATION AND STANDBY MODE Table 12. External PLLMULTx Pins and PLL Multiplication Factor The AD9261 power consumption can be further reduced by PLLMULTx[4:0] Pins PLL Multiplication Factors (N) configuring the chip in channel power-down, standby, or sleep 0 8 mode. The low power modes turn off internal blocks of the chip 1 9 including the reference. As a result, the wake-up time is depen- 2 10 dent on the amount of circuitry that is turned off. Fewer internal 3 12 circuits that are powered down result in proportionally shorter 4 14 wake-up time. The different low power modes are shown in 5 15 Table 13. In the standby mode, all clock related activity and the 6 16 output channels are disabled. Only the references and CMOS 7 17 outputs remain powered up to ensure a short recovery and link 8 18 integrity. During sleep mode, all internal circuits are powered 9 20 down, putting the device into its lowest power mode, and the 10 21 CMOS outputs are disabled. 11 24 If the serial port interface is not available, the AD9261 can be 12 25 configured in power-down mode by connecting Pin 3 (PDWN) 13 28 to AVDD. 14 30 15 32 16 34 17 to 30 42 31 Direct clocking Rev. 0 | Page 18 of 28 AD9261 Table 13. Low Power Modes Table 14. DEC4 Filter Coefficients Mode 0x08[1:0] Analog Circuitry Clock Ref Coefficient Coefficient Normal 0x0 On On On Number Coefficient Number Coefficient Power-Down 0x1 Off On On C0, C22 −21 C6, C16 1121 Standby 0x2 Off Off On C1, C21 0 C7, C15 0 Sleep 0x3 Off Off Off C2, C20 122 C8, C14 −2796 C3, C19 0 C9, C13 0 DIGITAL ENGINE C4, C18 −418 C10, C12 10,184 Bandwidth Selection C5, C17 0 C11 16,384 The digital engine (see Figure 46) selects the decimation signal 3 Table 15. LPF/EQZ Filter Coefficients bandwidth by cascading third-order sinc (sinc ) decimate-by-2 Coefficient Coefficient filters. For a 10 MHz signal band, no filters are cascaded; for a Number Coefficient Number Coefficient 5 MHz signal band, a single filter is used; and for a 2.5 MHz C0, C62 17 C16, C46 694 signal band, the 5 MHz filter is cascaded with a second filter. C1, C61 31 C17, C45 −744 Depending on the signal bandwidth, this drops the data rate C2, C60 −15 C18, C44 −677 into the fixed decimation filter. As a result, lower signal bandwidth C3, C59 −52 C19, C43 1271 options result in lower power. Bandwidth selection is determined C4, C58 36 C20, C42 450 by setting Register 0x0F[6:5]. C5, C57 78 C21, C41 −1909 Decimation Filters C6, C56 −84 C22, C40 103 A fixed frequency low-pass filter is used to define the signal C7, C55 −98 C23, C39 2612 band. This filter incorporates magnitude equalization for the C8, C54 170 C24, C38 −1147 droop of the preceding sinc decimation filters and the sinc C9, C53 97 C25, C37 −3326 filters of the sample rate converter. Table 14 and Table 15 detail C10, C52 −291 C26, C36 3022 the coefficients for the DEC4 and LPF/EQZ filters. The preceding C11, C51 −42 C27, C35 4051 sinc decimation filters are a standard sinc filter implementation. C12, C50 441 C28, C34 −6870 C13, C49 −98 C29, C33 −5305 C14, C48 −592 C30, C32 21,141 C15, C47 353 C31 38,956 BANDWIDTH SELECTION DECIMATION FILTERS 10MHz 10MHz DEC1 DEC2 DEC3 DEC4 LPF/EQZ DEC01 5MHz 5MHz 4 3 4 4 6 FIR SINC 2 SINC 2 SINC 2 SINC 2 HB 2 Σ-Δ 2.5MHz 2.5MHz OUTPUT DEC02 3 INT1 INT2 INT3 INT4 SINC 2 10MHz 16 5MHz 5 5 HB 2 HB 2 SINC 2 SINC 4 8 DATA 2.5MHz OUTPUT SAMPLE RATE CONVERTER NCO Figure 46. Digital Engine Rev. 0 | Page 19 of 28 07803-046 AD9261 Sample Rate Converter Table 18. SRC Conversion Factors The sample rate converter (SRC) allows the flexibility of a user- 0x101[5:0] K 0x101[5:0] K 0x101[5:0] K OUT OUT OUT defined output sample rate, enabling a more efficient and direct 0 SRC reset 22 11 44 22 1 4 23 11.5 45 22.5 interface to the digital receiver blocks. 2 4 24 12 46 23 The sample rate converter performs an interpolation and 3 4 25 12.5 47 23.5 resampling procedure to provide an output data rate of 4 4 26 13 48 24 20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coeffi- 5 4 27 13.5 49 24.5 cients for the INT1 and INT2 filters. The sinc filters are a 6 4 28 14 50 25 standard implementation. 7 4 29 14.5 51 25.5 8 4 30 15 52 26 Table 16. INT1 Filter Coefficients 9 4.5 31 15.5 53 26.5 Coefficient Coefficient 10 5 32 16 54 27 Number Coefficient Number Coefficient 11 5.5 33 16.5 55 27.5 C0, C26 15 C7, C19 0 12 6 34 17 56 28 13 6.5 35 17.5 57 28.5 C1, C25 0 C8, C18 2450 14 7 36 18 58 29 C2, C24 −97 C9, C17 0 15 7.5 37 18.5 59 29.5 C3, C23 0 C10, C16 −5761 16 8 38 19 60 30 C4, C22 361 C11, C15 0 17 8.5 39 19.5 61 30.5 C5, C21 0 C12, C14 20433 18 9 40 20 62 31 C6, C20 −1017 C13 32768 19 9.5 41 20.5 63 31.5 20 10 42 21 21 10.5 43 21.5 Table 17. INT2 Filter Coefficients Cascaded Filter Responses Coefficient Coefficient Number Coefficient Number Coefficient The cascaded filter responses for the three signal bandwidth C0, C14 −27 C4, C10 −1032 settings are for a 160 MSPS output data rate, as shown in Figure 47, C1, C13 0 C5, C9 0 Figure 48, and Figure 49. C2, C12 227 C6, C8 4928 0 C3, C11 0 C7 8192 0.08 –20 0.04 The relationship between the output sample rate and the Σ-Δ –40 modulator clock rate is expressed as follows: 0 –60 –0.04 fOUT = fMOD ÷ KOUT –0.08 –80 Table 18 shows the available K conversion factors. OUT 02 4 6 8 10 FREQUENCY (MHz) –100 If the main clocking source of the AD9261 is provided by the PLL, it is important that once the PLL has been programmed –120 and locked, to initiate an SRC reset before programming the –140 desired KOUT factor. This is done by first writing 0x101[5:0] = 0 –160 and then rewriting to the same register with the appropriate KOUT value. In addition, if the AD9261 loses its clock source and 0 102030 40506070 80 FREQUENCY (MHz) then later regains it, an SRC reset should be initiated. Figure 47. 10 MHz Signal Bandwidth, 160 MSPS Rev. 0 | Page 20 of 28 AMPLITUDE (dBFS) 07803-047 AD9261 0 an overrange condition typically extends well beyond one clock 0.08 cycle—that is, it does not toggle at the DCO rate—data can –20 0.04 usually be successfully detected on the rising edge of DCO or –40 0 monitored asynchronously. –60 –0.04 The AD9261 has two trip points that can trigger an overrange –0.08 –80 condition: analog and digital. The analog trip point is located 01 2 3 4 5 FREQUENCY (MHz) in the modulator, and the second trip point is in the digital –100 engine. In normal operation, it is possible for the analog trip –120 point to toggle the OR pin for a number of clock cycles as the –140 analog input approaches full scale. Because the OR pin is a pulse- width modulated (PWM) signal, as the analog input increases –160 in amplitude, the duration of overrange pin toggling increases. 0 102030 40506070 80 FREQUENCY (MHz) Eventually, when the OR pin is high for an extended period of Figure 48. 5 MHz Signal Bandwidth, 160 MSPS time, the ADC is overloaded, and there is little correspondence between analog input and digital output. 0 0.08 The second trip point is in the digital block. If the input signal –20 0.04 is large enough to cause the data bits to clip to the maximum –40 0 full-scale level, an overrange condition occurs. The overrange –60 –0.04 trip point can be adjusted by specifying a threshold level. –0.08 –80 Table 19 shows the corresponding threshold level in dBFS vs. 0.5 1.5 2.5 FREQUENCY (MHz) register setting. If the input signal crosses this level, the OR pin –100 is set. In the case where 0x111[5:0] is set to all 0s, the threshold –120 level is set to the maximum code of 32,767 . This feature 10 –140 provides a means of reporting the instantaneous amplitude as it crosses a user-provided threshold. This gives the user a sense –160 for the signal level without needing to perform a full power 0 102030 40506070 80 measurement. FREQUENCY (MHz) Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS The user has the ability to select how the overrange conditions are reported, and this is controlled through Register 0x111 via DIGITAL OUTPUTS AUTORST, OR_IND, and ORTHRESH (see Table 20). By Digital Output Format enabling the AUTORST bit, Register 0x111[7], if an overrange The AD9261 offers a variety of digital output formats for ease of occurs, the ADC automatically resets itself. The OR pin remains system integration. The digital output consists of 16 data bits and high until the automatic reset has completed. If an analog trip an output clock signal (DCO) for data latching. The data bits can occurs, the modulator resets itself after 16 consecutive clock be configured for offset binary, twos complement, or Gray code cycles of overrange. by writing to Register 0x14[1:0]. In addition, the voltage swing of If the AD9261 is used in a system that incorporates automatic the digital outputs can be configured to 3.3 V TTL levels or a gain control (AGC), the OR signal can be used to indicate that reduced voltage swing of 1.8 V by accessing Register 0x14[7]. the signal amplitude should be reduced. This may be particularly When 3.3 V voltage levels are desirable, the DRVDD power effective for use in maximizing the signal dynamic range if the supply must be set to 3.3 V. signal includes high occurrence components that occasionally Overrange (OR) Condition exceed full scale by a small amount. The OR pin serves as an indicator for an overrange condition. The TIMING OR pin is triggered by in-band signals that exceed the full-scale The AD9261 provides a data clock out (DCO) pin to assist range of the ADC. In addition, the AD9261 possesses out-of- in capturing the data in an external register. The data outputs band gain above 10 MHz; therefore, a large out-of-band signal are valid on the rising edge of DCO, unless changed by setting may trip an overrange condition. Register 0x16[7]. See Figure 2 for a graphical timing description. The OR pin is a synchronous output that is updated at the out- put data rate. Ideally, OR should be latched on the falling edge of DCO to ensure proper setup-and-hold time. However, because Rev. 0 | Page 21 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07803-049 07803-048 AD9261 Table 19. OR Threshold Levels 0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS) 1 −36.12 16 −9.28 2B −3.45 2 −30.10 17 −8.89 2C −3.25 3 −26.58 18 −8.52 2D −3.06 4 −24.08 19 −8.16 2E −2.87 5 −22.14 1A −7.82 2F −2.68 6 −20.56 1B −7.50 30 −2.50 7 −19.22 1C −7.18 31 −2.32 8 −18.06 1D −6.88 32 −2.14 9 −17.04 1E −6.58 33 −1.97 A −16.12 1F −6.30 34 −1.80 B −15.29 20 −6.02 35 −1.64 C −14.54 21 −5.75 36 −1.48 D −13.84 22 −5.49 37 −1.32 E −13.20 23 −5.24 38 −1.16 F −12.60 24 −5.00 39 −1.00 10 −12.04 25 −4.76 3A −0.86 11 −11.51 26 −4.53 3B −0.71 12 −11.02 27 −4.30 3C −0.56 13 −10.56 28 −4.08 3D −0.42 14 −10.10 29 −3.87 3E −0.28 15 −9.68 2A −3.66 3F −0.14 Table 20. OR Conditions OR Conditions AUTORST OR_IND ORTHRESH[5:0] ORTHRESH[4:0] Description Normal, Reset Off 0 0 0 00000 Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0 Digital Threshold, 0 0 >0 Digital threshold: If 16-bit output > ORTHRESH, OR = 1, Reset Off else OR = 0 1 Full Overrange, 0 1 0 X If analog trip or digital trip, OR = 1, else OR = 0 Reset Off 1 Data Valid, No Reset 0 1 1 X If analog trip or digital trip or calibration, OR = 0, else OR = 1 Normal, Reset On 1 0 0 00000 Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0 Digital Threshold, 1 0 >0 Digital threshold: if 16-bit output > ORTHRESH, OR = 1, Reset On else OR = 0 1 Full Overrange, 1 1 0 X If analog trip or digital trip, OR = 1, else OR = 0 Reset On 1 Data Valid, 1 1 1 X If analog trip or digital trip or calibration, OR = 0 else OR = 1 Reset On 1 X = don’t care. Rev. 0 | Page 22 of 28 AD9261 SERIAL PORT INTERFACE (SPI) During an instruction phase, a 16-bit instruction is transmitted. The AD9261 serial port interface (SPI) allows the user to configure Data follows the instruction phase and the length is determined the converter for specific functions or operations through a by the W0 bit and the W1 bit. All data is composed of 8-bit words. structured register space provided inside the ADC. This provides The first bit of each individual byte of serial data indicates whether the user added flexibility and customization depending on the a read or write command is issued. This allows the serial data application. Addresses are accessed via the serial port and can input/output (SDIO) pin to change direction from an input to be written to or read from via the port. Memory is organized an output. into bytes that are further divided into fields, as documented in the Memory Map section. For detailed operational information, In addition to word length, the instruction phase determines if see the AN-877 Application Note, Interfacing to High Speed the serial frame is a read or write operation, allowing the serial ADCs via SPI. port to be used to both program the chip as well as to read the contents of the on-chip memory. If the instruction is a readback CONFIGURATION USING THE SPI operation, performing a readback causes the serial data input/ As summarized in Table 21, three pins define the SPI of this ADC. output (SDIO) pin to change direction from an input to an output The SCLK pin synchronizes the read and write data presented at the appropriate point in the serial frame. to the ADC. The SDIO pin allows data to be sent and read from Data can be sent in MSB-first or in LSB-first mode. MSB first is the internal ADC memory map registers. The CSB pin is an active the default setting on power-up and can be changed via the low control that enables or disables the read and write cycles. configuration register. For more information, see the AN-877 Table 21. Serial Port Interface Pins Application Note, Interfacing to High Speed ADCs via SPI. Pin Name Description Table 22. SPI Timing Diagram Specifications SCLK SCLK (serial clock) is the serial shift clock. SCLK Parameter Description synchronizes serial interface reads and writes. t Setup time between data and rising edge of SCLK SDIO SDIO (serial data input/output) is an input and SDS output depending on the instruction being sent tSDH Hold time between data and rising edge of SCLK and the relative position in the timing frame. tSCLK Period of the clock CSB (chip select bar) is an active low control that CSB tSS Setup time between CSB and SCLK gates the read and write cycles. t Hold time between CSB and SCLK SH The falling edge of CSB in conjunction with the rising edge of t Minimum period that SCLK should be in a logic SHIGH SCLK determines the start of the framing. Figure 50 and Table 22 high state provide an example of the serial timing and its definitions. tSLOW Minimum period that SCLK should be in a logic low state Other modes involving CSB are available. CSB can be held low indefinitely to permanently enable the device (this is called streaming). CSB can stall high between bytes to allow for addi- tional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. t t t t SDS SHIGH SCLK SH t t SS SDH t SLOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 50. Serial Port Interface Timing Diagram Rev. 0 | Page 23 of 28 07803-050 AD9261 HARDWARE INTERFACE The pins described in Table 21 comprise the physical interface such method is described in detail in the AN-812 Application between the programming device of the user and the serial port Note, MicroController-Based Serial Port Interface (SPI) Boot of the AD9261. The SCLK and CSB pins function as inputs Circuit. when using the SPI interface. The SDIO pin is bidirectional, When the SPI interface is not used, some pins serve a dual functioning as an input during write phases and as an output function. When strapped to AVDD or ground during device during readback. power-on, the pins are associated with a specific function. The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user with the ability to use an alternate method to program the ADC. One Rev. 0 | Page 24 of 28 AD9261 MEMORY MAP Table 23. Memory Map Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Port Config 0x00 0 LSBFIRST SOFTRESET 1 1 SOFTRESET LSBFIRST 0 Chip ID 0x01 CHIPID[7:0] Chip Grade 0x02 CHILDID[2:0] Power Modes 0x08 PWRDWN[1:0] PLLENABLE 0x09 PLLENABLE PLL 0x0A PLLLOCKED PLLAUTO PLLMULT[5:0] Analog Input 0x0F BW[1:0] Output Modes 0x14 DRVSTD Interleave OUTENB OUTINV Format[1:0] Output Adjust 0x15 DRVSTR33[1:0] DRVSTR18[1:0] Output Clock 0x16 DCOINV Reference 0x18 EXTREF Output Data 0x101 KOUT[5:0] Overrange 0x111 AUTORST OR_IND ORTHRESH[5:0] MEMORY MAP DEFINITIONS Table 24. Memory Map Definitions Register Address Bit(s) Mnemonic Default Description SPI Port Config 0x00 6, 1 LSBFIRST 0 0: serial interface uses MSB first format 1: serial interface uses LSB first format 5, 2 SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A Chip ID 0x01 [7:0] CHIPID 0x26 0x26: AD9261 Chip Grade 0x02 [5:4] CHILDID 0 0x00: 10 MHz bandwidth Power Modes 0x08 [1:0] PWRDWN 0 0x0: normal operation 0x1: power-down (local) 0x2: standby (everything except reference circuits) 0x3: sleep PLLENABLE 0x09 2 PLLENABLE 0 1: enable PLL PLL 0x0A 7 PLLLOCKED 0 0: PLL is not locked 1: PLL is locked 6 PLLAUTO 0 1: PLL autoband enabled [5:0] PLLMULT 0 See Table 10 Analog Input 0x0F [6:5] BW 0 0x0: 10 MHz 0x1: 5 MHz 0x2: 2.5 MHz 0x3: 10 MHz Output Modes 0x14 7 DRVSTD 0 0: 3.3 V 1: 1.8 V 5 Interleave 0 1: interleave both channels onto D[15:0] 4 OUTENB 0 1: data outputs tristated 2 OUTINV 0 1: data outputs bitwise inverted [1:0] Format 0 0: offset binary 1: twos complement 2: Gray code 3: offset binary Rev. 0 | Page 25 of 28 AD9261 Register Address Bit(s) Mnemonic Default Description Output Adjust 0x15 [3:2] DRVSTR33 0 Typical output sink current to DGND 0: 33 mA 1: 63 mA 2: 93 mA 3: 120 mA [1:0] DRVSTR18 2 Typical output sink current to DGND 0: 10 mA 1: 20 mA 2: 30 mA 3: 39 mA Output Clock 0x16 7 DCOINV 0 1: invert DCO Reference 0x18 6 EXTREF 0 1: use external reference Output Data 0x101 [5:0] K 0 Output data rate, see Table 18 OUT Overrange 0x111 7 AUTORST 0 1: enable loop filter reset indicator on OR pin 6 OR_IND 0 See Table 20 [5:0] ORTHRESH 0 See Table 19 Rev. 0 | Page 26 of 28 AD9261 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY 0.50 BSC SECTION OF THIS DATA SHEET. 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 51. 48-Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9261BCPZ-10 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD9261BCPZRL7-10 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD9261-10EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 080108-A AD9261 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07803-0-4/10(0) Rev. 0 | Page 28 of 28