ANALOG DEVICES AD9260

High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 FUNCTIONAL BLOCK DIAGRAM FEATURES Monolithic 16-bit, oversampled A/D converter 8× oversampling mode, 20 MSPS clock RESET/ SYNC DVSS DVDD 2.5 MHz output word rate 1.01 MHz signal passband with 0.004 dB ripple VINA MULTIBIT DIGITAL OTR Signal-to-noise ratio: 88.5 dB SIGMA-DELTA DEMODULATOR MODULATOR Total harmonic distortion: –96 dB VINB 12-BIT: 20MHz Spurious-free dynamic range: 100 dB STAGE 1:2X 16-BIT: Input referred noise: 0.6 LSB DECIMATION 10MHz FILTER Selectable oversampling ratio: 1×, 2×, 4×, 8× AD9260 BIT1– Selectable power dissipation: 150 mW to 585 mW BIT16 STAGE 2:2X 16-BIT: 85 dB stop-band attenuation DECIMATION 5MHz REF TOP FILTER 0.004 dB pass-band ripple REF REFERENCE BOTTOM BUFFER Linear phase COMMON STAGE 3:2X 16-BIT: MODE Single 5 V analog supply, 5 V/3 V digital supply DECIMATION 2.5MHz FILTER Synchronize capability for parallel ADC interface VREF DAV BANDGAP Twos complement output data SENSE BIAS CLOCK MODE READ REFERENCE CIRCUIT BUFFER REGISTER 44-lead MQFP REFCOM PRODUCT DESCRIPTION BIAS ADJUST CLK MODE CS The AD9260 is a 16-bit, high-speed oversampled analog-to- Figure 1. digital converter (ADC) that offers exceptional dynamic range over a wide bandwidth. The AD9260 is manufactured on an tion levels as low as 150 mW at reduced clock and data rates. advanced CMOS process. High dynamic range is achieved with The AD9260 is available in a 44-lead MQFP package and is an oversampling ratio of 8× through the use of a proprietary specified to operate over the industrial temperature range. technique that combines the advantages of sigma-delta and PRODUCT HIGHLIGHTS pipeline converter technologies. The AD9260 is a switched- The AD9260 is fabricated on a very cost effective CMOS capacitor ADC with a nominal full-scale input range of 4 V. It process. High speed, precision, mixed-signal analog circuits are offers a differential input with 60 dB of common-mode rejec- combined with high density digital filter circuits. The AD9260 tion of common-mode signals. The signal range of each differ- offers a complete single-chip 16-bit sampling ADC with a 2.5 ential input is ±1 V centered on a 2.0 V common-mode level. MHz output data rate in a 44-lead MQFP. The on-chip decimation filter is configured for maximum Selectable Internal Decimation Filtering—The AD9260 performance and flexibility. A series of three half-band FIR provides a high performance decimation filter with 0.004 dB filter stages provide 8× decimation filtering with 85 dB of stop- pass-band ripple and 85 dB of stop-band attenuation. The filter band attenuation and 0.004 dB of pass-band ripple. An onboard is configurable with options for 1×, 2×, 4×, and 8× decimation. digital multiplexer allows the user to access data from the various stages of the decimation filter. The on-chip Power Scaling—The AD9260 consumes a low 585 mW of programmable reference and reference buffer amplifier are power at 16-bit resolution and 2.5 MHz output data rate. Its configured for maximum accuracy and flexibility. An external power can be scaled down to as low as 150 mW at reduced reference can also be chosen to suit the user’s specific dc clock rates. accuracy and drift requirements. Single Supply—Both the analog and digital portions of the The AD9260 operates on a single +5 V supply, typically AD9260 can operate off of a single +5 V supply, simplifying consuming 585 mW of power. A power scaling circuit is system power supply design. The digital logic will also provided allowing the AD9260 to operate at power consump- accommodate a single +3 V supply for reduced power. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AVDD AVSS AVDD AVSS AVDD AVSS OUTPUT MODE MULTIPLEXER DRVDD OUTPUT REGISTER DRVSS 00581-C-001 AD9260 TABLE OF CONTENTS Specifications..................................................................................... 3 Theory of Operation ...................................................................... 23 Clock Input Frequency Range .................................................... 3 Analog Input and Reference Overview ....................................... 24 DC Specifications ......................................................................... 3 Input Span ................................................................................... 24 AC Specifications.......................................................................... 4 Input Compliance Range........................................................... 24 Digital Filter Characteristics ....................................................... 6 Analog Input Operation............................................................ 24 Digital Filter Characteristics ....................................................... 7 Driving the Input........................................................................ 25 Digital Specifications ................................................................... 9 Reference Operation ...................................................................... 28 Switching Specifications ............................................................ 10 Digital Inputs and Outputs ........................................................... 30 Absolute Maximum Ratings.......................................................... 11 Digital Outputs ........................................................................... 30 Thermal Characteristics ............................................................ 11 Mode Operation ......................................................................... 31 ESD Caution................................................................................ 11 Bias Pin Operation ..................................................................... 32 Terminology .................................................................................... 12 Power Dissipation Considerations............................................... 33 Pin Configuration and Function Descriptions........................... 13 Digital Output Driver Considerations (DRVDD) ................. 33 Typical Performance Characteristics ........................................... 14 Grounding and Decoupling...................................................... 34 Typical AC Characterization Curves Evaluation Board General Description ....................................... 36 vs. Decimation Mode................................................................. 15 Features and User Controls....................................................... 36 Typical AC Characterization Curves for 8× Mode ................ 16 Shipment Configuration............................................................ 37 Typical AC Characterization Curves for 4× Mode ................ 17 Quick Setup................................................................................. 37 Typical AC Characterization Curves for 2× Mode ................ 18 Application Information ........................................................... 38 Typical AC Characterization Curves for 1× Mode ................ 19 Outline Dimensions ....................................................................... 43 Typical AC Characterization Curves ....................................... 20 Ordering Guide .......................................................................... 43 Additional AC Characterization Curves ................................. 21 REVISION HISTORY 7/04—Changed from Rev. B to Rev. C Changed “trimpot” to “variable resistor” ..................... Universal Updated Format................................................................ Universal Updated Outline Dimensions ......................................................43 Changes to Ordering Guide .........................................................43 5/00—Changed from Rev. A to Rev. B. 1/98—Changed from Rev. 0 to Rev. A. Rev. C | Page 2 of 44 AD9260 SPECIFICATIONS CLOCK INPUT FREQUENCY RANGE Table 1. Parameter—Decimation Factor (N) AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit CLOCK INPUT (Modulator Sample Rate, fCLOCK) 1 1 1 1 kHz min 20 20 20 20 MHz max OUTPUT WORD RATE (FS = fCLOCK/N) 0.125 0.250 0.500 1 kHz min 2.5 5 10 20 MHz max DC SPECIFICATIONS AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, f = 20 MSPS, V = +2.5 V, Input CML = 2.0 V T to T unless otherwise noted, CLOCK REF MIN MAX R = 2 kΩ. BIAS Table 2. Parameter—Decimation Factor (N) AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit RESOLUTION 16 16 16 12 Bits min INPUT REFERRED NOISE (TYP) 1.0 V Reference 1.40 2.4 6.0 1.3 LSB rms typ 1 2.5 V Reference 0.68 (90.6) 1.2 (86) 3.7 (76) 1.0 (63.2) LSB rms typ (dB typ) ACCURACY Integral Nonlinearity (INL) ± 0.75 ± 0.75 ± 0.75 ± 0.3 LSB typ Differential Nonlinearity (DNL) ± 0.50 ± 0.50 ± 0.50 ± 0.25 LSB typ No Missing Codes 16 16 16 12 Bits Guaranteed Offset Error 0.9 (0.5) (0.5) (0.5) (0.5) % FSR max (typ @ +25°C) 2 Gain Error 2.75 (0.66) (0.66) (0.66) (0.66) % FSR max (typ @ +25°C) 3 Gain Error 1.35 (0.7) (0.7) (0.7) (0.7) % FSR max (typ @ +25°C) TEMPERATURE DRIFT Offset Error 2.5 2.5 2.5 2.5 ppm/°C typ 2 Gain Error 22 22 22 22 ppm/°C typ 3 Gain Error 7.0 7.0 7.0 7.0 ppm/°C typ POWER SUPPLY REJECTION AVDD, DVDD, DRVDD (+5 V ±0.25 V) 0.06 0.06 0.06 0.06 % FSR max ANALOG INPUT Input Span VREF= 1.0 V 1.6 1.6 1.6 1.6 V p p Diff. max VREF= 2.5 V 4.0 4.0 4.0 4.0 V p p Diff. max Input (VINA or VINB) Range +0.5 +0.5 +0.5 +0.5 V min +AVDD –0.5 +AVDD –0.5 +AVDD –0.5 +AVDD –0.5 V max Input Capacitance 10.2 10.2 10.2 10.2 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1 1 1 1 V typ Output Voltage Error (1 V Mode) ± 14 ± 14 ± 14 ± 14 mV max Output Voltage (2.5 V Mode) 2.5 2.5 2.5 2.5 V typ Output Voltage Error (2.5 V Mode) ± 35 ± 35 ± 35 ± 35 mV max 4 Load Regulation 1 V REF 0.5 0.5 0.5 0.5 mV max 2.5 V REF 2.0 2.0 2.0 2.0 mV max REFERENCE INPUT RESISTANCE 8 8 8 8 kΩ POWER SUPPLIES Supply Voltages AVDD +5 +5 +5 +5 V (± 5%) Rev. C | Page 3 of 44 AD9260 Parameter—Decimation Factor (N) AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit DVDD and DRVDD +5.5 +5.5 +5.5 +5.5 V max +2.7 +2.7 +2.7 +2.7 V min Supply Current IAVDD 115 115 115 115 mA typ 134 mA max IDVDD 12.5 10.3 6.5 2.4 mA typ 3.5 mA max IDRVDD 0.450 0.850 1.7 2.6 mA typ POWER CONSUMPTION 613 608 600 585 mW typ 630 mW max 1 VINA and VINB connect to DUT CML. 2 Including Internal 2.5 V reference. 3 Excluding Internal 2.5 V reference. 4 Load regulation with 1 mA load current (in addition to that required by AD9260). AC SPECIFICATIONS AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX unless otherwise noted, R = 2 kΩ. BIAS Table 3. Parameter—Decimation Factor (N) AD9260(8) AD9260(4) AD9260(2) AD9260(1) Unit DYNAMIC PERFORMANCE INPUT TEST FREQUENCY: 100 kHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 88.5 82 74 63 dB typ Input Amplitude = –6.0 dBFS 82.5 78 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 87.5 82 74 63 dB typ Input Amplitude = –6.0 dBFS 82 77.5 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –96 –96 –97 –98 dB typ Input Amplitude = –6.0 dBFS –93 –98 –96 –98 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 100 98 98 88 dB typ Input Amplitude = –6.0 dBFS 94 100 94 84 dB typ INPUT TEST FREQUENCY: 500 kHz Signal to Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 86.5 82 74 63 dB typ 80.5 dB min Input Amplitude = –6.0 dBFS 82.5 77 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 86.0 81 74 63 dB typ 80.0 dB min Input Amplitude = –6.0 dBFS 82.0 77 68 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –97.0 –92 –89 –86 dB typ –90.0 dB max Input Amplitude = –6.0 dBFS –95.5 –96 –89 –86 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 99.0 92 91 88 dB typ 90.0 dB max Rev. C | Page 4 of 44 AD9260 Parameter—Decimation Factor (N) AD9260(8) AD9260(4) AD9260(2) AD9260(1) Unit Input Amplitude = –6.0 dBFS 98 100 91 82 dB typ INPUT TEST FREQUENCY: 1.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 85 82 74 63 dB typ Input Amplitude = –6.0 dBFS 80 76 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 84.5 81 74 63 dB typ Input Amplitude = –6.0 dBFS 80 76 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –102 –96 –82 –79 dB typ Input Amplitude = –6.0 dBFS –96 –94 –84 –77 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 105 98 83 80 dB typ Input Amplitude = –6.0 dBFS 98 96 87 80 dB typ INPUT TEST FREQUENCY: 2.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 82 74 63 dB typ Input Amplitude = –6.0 dBFS 76 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 81 73 62 dB typ Input Amplitude = –6.0 dBFS 76 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –101 –80 –75 dB typ Input Amplitude = –6.0 dBFS –95 –80 –76 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 104 80 78 dB typ Input Amplitude = –6.0 dBFS 100 83 79 dB typ INPUT TEST FREQUENCY: 5.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 59 dB typ Input Amplitude = –6.0 dBFS 57 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 58 dB typ Input Amplitude = –6.0 dBFS 57 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –58 dB typ Input Amplitude = –6.0 dBFS –67 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 59 dB typ Input Amplitude = –6.0 dBFS 70 dB typ INTERMODULATION DISTORTION fIN1 = 475 kHz, fIN2 = 525 kHz –93 –91 –91 –83 dBFS typ f 1 = 950 kHz, f 2 = 1.050 MHz –95 –86 –85 –83 dBFS typ IN IN DYNAMIC CHARACTERISTICS Full Power Bandwidth 75 75 75 75 MHz typ Small Signal Bandwidth (A = –20 dBFS) 75 75 75 75 MHz typ IN Aperture Jitter 2 2 2 2 ps rms typ Rev. C | Page 5 of 44 AD9260 DIGITAL FILTER CHARACTERISTICS Table 4. Parameter AD9260 Unit 8× DECIMATION (N = 8) Pass-Band Ripple 0.00125 dB max Stop-Band Attenuation 82.5 dB min Pass-Band 0 MHz min 0.605 × (f /20 MHz) MHz max CLOCK Stop-Band 1.870 × (f /20 MHz) MHz min CLOCK 18.130 × (f /20 MHz) MHz max CLOCK Pass-Band/Transition Band Frequency (–0.1 dB Point) 0.807 × (fCLOCK/20 MHz) MHz max (–3.0 dB Point) 1.136 × (fCLOCK/20 MHz) MHz max 1 Absolute Group Delay 13.55 × (20 MHz/f ) µs max CLOCK Group Delay Variation 0 µs max 1 Settling Time (to ± 0.0007%) 24.2 × (20 MHz/f ) µs max CLOCK 4× DECIMATION (N = 4) Pass-Band Ripple 0.001 dB max Stop-Band Attenuation 82.5 dB min Pass-Band 0 MHz min 1.24 × (fCLOCK/20 MHz) MHz max Stop-Band 3.75 × (f /20 MHz) MHz min CLOCK 16.25 × (f /20 MHz) MHz max CLOCK Pass-Band/Transition Band Frequency (–0.1 dB Point) 1.61 × (fCLOCK/20 MHz) MHz max (–3.0 dB Point) 2.272 × (fCLOCK/20 MHz) MHz max 1 Absolute Group Delay 2.90 × (20 MHz/fCLOCK) µs max Group Delay Variation 0 µs max 1 Settling Time (to ± 0.0007%) 5.05 × (20 MHz/f ) µs max CLOCK 2× DECIMATION (N = 2) Pass-Band Ripple 0.0005 dB max Stop-Band Attenuation 85.5 dB min Pass-Band 0 MHz min 2.491 × (fCLOCK/20 MHz) MHz max Stop-Band 7.519 × (fCLOCK/20 MHz) MHz min 12.481 × (f /20 MHz) MHz max CLOCK Pass-Band/Transition Band Frequency (–0.1 dB Point) 3.231 × (f /20 MHz) MHz max CLOCK (–3.0 dB Point) 4.535 × (fCLOCK/20 MHz) MHz max 1 Absolute Group Delay 0.80 × (20 MHz/fCLOCK) µs max Group Delay Variation 0 µs max 1 Settling Time (to ± 0.0007%) 1.40 × (20 MHz/f ) µs max CLOCK 1× DECIMATION (N = 1) Propagation Delay: tPROP 13 ns max Absolute Group Delay (225 × (20 MHz/f )) + t ns max CLOCK PROP 1 To determine overall Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1 ×decimation. Rev. C | Page 6 of 44 AD9260 DIGITAL FILTER CHARACTERISTICS 0 1.0 0.8 –20 0.6 –40 0.4 –60 0.2 –80 0 –100 –0.2 –120 –0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 0 100 200 300 400 500 600 FREQUENCY (NORMALIZED TOπ) CLOCK PERIODS (RELATIVE TO CLK) Figure 2. 8x FIR Filter Frequency Response Figure 5. 8x FIR Filter Impulse Response 0 1.0 –20 0.8 –40 0.6 –60 0.4 –80 0.2 –100 0 –120 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 10 20304050 60 708090 100 110 FREQUENCY (NORMALIZED TOπ) CLOCK PERIODS (RELATIVE TO CLK) Figure 3. 4x FIR Filter Frequency Response Figure 6. 4x FIR Filter Impulse Response 0 1.0 –20 0.8 –40 0.6 –60 0.4 –80 0.2 –100 0 –120 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 FREQUENCY (NORMALIZED TOπ) CLOCK PERIODS (RELATIVE TO CLK) Figure 4. 2x FIR Filter Frequency Response Figure 7. 2x FIR Filter Impulse Response Rev. C | Page 7 of 44 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 00581-C-004 00581-C-003 00581-C-002 NORMALIZED OUTPUT RESPONSE NORMALIZED OUTPUT RESPONSE NORMALIZED OUTPUT RESPONSE 00581-C-007 00581-C-006 00581-C-005 AD9260 Table 5. Integer Filter Coefficients for First Stage Table 7. Integer Filter Coefficients for Third Stage Decimation Filter (23-Tap Half-Band FIR Filter) Decimation Filter (107-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient Integer Value Lower Coefficient Upper Coefficient Integer Value H(1) H(23) –1 H(1) H(107) –1 H(2) H(22) 0 H(2) H(106) 0 H(3) H(21) 13 H(3) H(105) 2 H(4) H(20) 0 H(4) H(104) 0 H(5) H(19) –66 H(5) H(103) –2 H(6) H(18) 0 H(6) H(102) 0 H(7) H(17) 224 H(7) H(101) 3 H(8) H(16) 0 H(8) H(100) 0 H(9) H(15) –642 H(9) H(99) –3 H(10) H(14) 0 H(10) H(98) 0 H(11) H(13) 2496 H(11) H(97) 1 H(12) 4048 H(12) H(96) 0 H(13) H(95) 3 H(14) H(94) 0 Table 6. Integer Filter Coefficients for Second Stage H(15) H(93) –12 Decimation Filter (43-Tap Half-Band FIR Filter) H(16) H(92) 0 H(17) H(91) 27 Lower Coefficient Upper Coefficient Integer Value H(18) H(90) 0 H(1) H(43) 3 H(19) H(89) –50 H(2) H(42) 0 H(20) H(88) 0 H(3) H(41) –12 H(21) H(87) 85 H(4) H(40) 0 H(22) H(86) 0 H(5) H(39) 35 H(23) H(85) –135 H(6) H(38) 0 H(24) H(84) 0 H(7) H(37) –83 H(25) H(83) 204 H(8) H(36) 0 H(26) H(82) 0 H(9) H(35) 172 H(27) H(81) –297 H(10) H(34) 0 H(28) H(80) 0 H(11) H(33) –324 H(29) H(79) 420 H(12) H(32) 0 H(30) H(78) 0 H(13) H(31) 572 H(31) H(77) –579 H(14) H(30) 0 H(32) H(76) 0 H(15) H(29) –976 H(33) H(75) 784 H(16) H(28) 0 H(34) H(74) 0 H(17) H(27) 1680 H(35) H(73) –1044 H(18) H(26) 0 H(36) H(72) 0 H(19) H(25) –3204 H(37) H(71) 1376 H(20) H(24) 0 H(38) H(70) 0 H(21) H(23) 10274 H(39) H(69) –1797 H(22) 16274 H(40) H(68) 0 NOTE: The composite filter undecimated coefficients (i.e., H(41) H(67) 2344 impulse response) in the 4× decimation mode can be H(42) H(66) 0 determined by convolving the first stage filter taps with a H(43) H(65) –3072 H(44) H(64) 0 “zero stuffed” version of the second stage filter taps (i.e., insert H(45) H(63) 4089 one zero between samples). Similarly, the composite filter H(46) H(62) 0 coefficients in the 8× decimation mode can be determined by H(47) H(61) –5624 convolving the taps of the composite 4× decimation mode (as H(48) H(60) 0 previously determined) with a “zero stuffed” version of the third H(49) H(59) 8280 stage filter taps (i.e., insert three zeros between samples). H(50) H(58) 0 H(51) H(57) –14268 H(52) H(56) 0 H(53) H(55) 43520 H(54) 68508 Rev. C | Page 8 of 44 AD9260 DIGITAL SPECIFICATIONS AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted. Table 8. Parameter AD9260 Unit 1 CLOCK AND LOGIC INPUTS High Level Input Voltage (DVDD = +5 V) +3.5 V min (DVDD = +3 V) +2.1 V max Low Level Input Voltage (DVDD = +5 V) +1.0 V min (DVDD = +3 V) +0.9 V max High Level Input Current (VIN = DVDD) ± 10 µA max Low Level Input Current (VIN = 0 V) ± 10 µA max Input Capacitance 5 pF typ LOGIC OUTPUTS (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) +4.5 V min High Level Output Voltage (I = 0.5 mA) +2.4 V min OH 2 Low Level Output Voltage (I = 0.3 mA) +0.4 V max OL Low Level Output Voltage (I = 50 µA) +0.1 V max OL Output Capacitance 5 pF typ LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (I = 50 µA) +2.4 V min OH Low Level Output Voltage (IOL = 50 µA) +0.7 V max 1 Since CLK is referenced to AVDD, +5 V logic input levels only apply. 2 The AD9260 is not guaranteed to meet VOL = 0.4 V max for standard TTL load of IOL = 1.6 mA. S1 S2 t C ANALOG INPUT t CL t CH INPUT CLOCK t t DI DS DATA OUTPUT t OE t H DAV t t OD DAV READ CS Figure 8. Timing Diagram Rev. C | Page 9 of 44 00581-C-008 AD9260 t t RES-DAV CLK-DAV INPUT CLOCK RESET DAV RESET Figure 9. Timing Diagram SWITCHING SPECIFICATIONS AVDD = +5 V, DVDD = +5 V, CL = 20 pF, TMIN to TMAX unless otherwise noted. Table 9. Parameters Symbol AD9260 Unit Clock Period t 50 ns min C Data Available (DAV) Period tDAV tC ×Mode ns min Data Invalid tDI 40% tDAV ns max Data Set-Up Time tDS tDAV –tH –tDI ns min Clock Pulse-Width High t 22.5 ns min CH Clock Pulse-Width Low t 22.5 ns min CL Data Hold Time tH 3.5 ns min RESET t 10 ns typ to DAV Delay RES–DAV CLOCK to DAV Delay tCLK–DAV 15 ns typ Three-State Output Disable Time t 8 ns typ OD Three-State Output Enable Time t 45 ns typ OE Rev. C | Page 10 of 44 00581-C-009 AD9260 ABSOLUTE MAXIMUM RATINGS Table 10. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AVDD to AVSS –0.3 V to +6.5 V rating only; functional operation of the device at these or any DVDD to DVSS –0.3 V to +6.5 V other conditions above those indicated in the operational AVSS to DVSS –0.3 V to +0.3 V sections of this specification is not implied. Exposure to AVDD to DVDD –6.5 V to +6.5 V absolute maximum ratings for extended periods may affect DRVDD to DRVSS –0.3 V to +6.5 V device reliability. DRVSS to AVSS –0.3 V to +0.3 V THERMAL CHARACTERISTICS REFCOM to AVSS –0.3 V to +0.3 V Thermal Resistance CS RESET –0.3 V to DVDD + 0.3 V CLK, MODE, READ, , and to 44-Lead MQFP DVSS θ = 53.2°C/W JA Digital Outputs to DRVSS –0.3 V to DRVDD + 0.3 V θ = 19°C/W JC VINA, VINB, CML, and BIAS to AVSS –0.3 V to AVDD + 0.3 V VREF to AVSS –0.3 V to AVDD + 0.3 V SENSE to AVSS –0.3 V to AVDD + 0.3 V CAPB and CAPT to AVSS –0.3 V to AVDD + 0.3 V Junction Temperature 150°C Storage Temperature –65°C to +150°C Lead Temperature (10 s) 300°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 11 of 44 AD9260 TERMINOLOGY Integral Nonlinearity (INL) Aperture Jitter INL refers to the deviation of each individual code from a line Aperture jitter is the variation in aperture delay for successive drawn from “negative full scale” through “positive full scale.” samples and is manifested as noise on the input to the A/D. The point used as “negative full scale” occurs 1/2 LSB before the Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio first code transition. “Positive full scale” is defined as a level 1 S/N+D is the ratio of the rms value of the measured input signal 1/2 LSB beyond the last code transition. The deviation is to the rms sum of all other spectral components below the measured from the middle of each particular code to the true Nyquist frequency, including harmonics but excluding dc. The straight line. value for S/N+D is expressed in decibels. Differential Nonlinearity (DNL, No Missing Codes) Effective Number of Bits (ENOB) An ideal ADC exhibits code transitions that are exactly 1 LSB For a sine wave, SINAD can be expressed in terms of the apart. DNL is the deviation from this ideal value. Guaranteed number of bits. Using the following formula, it is possible to get no missing codes to 14-bit resolution indicates that all 16384 a measure of performance expressed as N, the effective number codes, respectively, must be present over all operating ranges. of bits: NOTE: Conventional INL and DNL measurements don’t really N = (SINAD − 1.76)/6.02 apply to ∑∆ converters: the DNL looks continually better if longer data records are taken. For the AD9260, INL and DNL Thus, effective number of bits for a device for sine wave inputs numbers are given as representative. at a given input frequency can be calculated directly from its measured SINAD. Zero Error The major carry transition should occur for an analog value 1/2 Total Harmonic Distortion (THD) LSB below VINA = VINB. Zero error is defined as the deviation THD is the ratio of the rms sum of the first six harmonic of the actual transition from that point. components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Gain Error The first code transition should occur at an analog value 1/2 Signal-to-Noise Ratio (SNR) LSB above negative full scale. The last transition should occur at SNR is the ratio of the rms value of the measured input signal to an analog value 1 1/2 LSB below the nominal full scale. Gain the rms sum of all other spectral components below the Nyquist error is the deviation of the actual difference and the ideal frequency, excluding the first six harmonics and dc. The value difference between first and last code transitions. for SNR is expressed in decibels. Temperature Drift Spurious-Free Dynamic Range (SFDR) The temperature drift for zero error and gain error specifies the SFDR is the difference in dB between the rms amplitude of the maximum change from the initial (+25°C) value to the value at input signal and the peak spurious signal. T or T . MIN MAX Two-Tone SFDR Power Supply Rejection The ratio of the rms value of either input tone to the rms value The specification shows the maximum change in full scale from of the peak spurious component. The peak spurious component the value with the supply at the minimum limit to the value may or may not be an IMD product. May be reported in dBc with the supply at its maximum limit. (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Rev. C | Page 12 of 44 AD9260 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 DVSS 1 REFCOM PIN 1 AVSS 2 IDENTIFIER 32 VREF 3 31 DVDD SENSE AVDD 4 30 RESET 5 29 DRVSS AVSS AD9260 DRVDD 6 28 AVDD TOP VIEW (Not to Scale) 27 CLK 7 CS 8 26 DAV READ 25 (LSB) BIT16 9 OTR 10 24 BIT1 (MSB) BIT15 23 BIT14 11 BIT2 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT Figure 10. Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Description 1 DVSS Digital Ground. 2, 29, 38 AVSS Analog Ground. 3 DVDD +3 V to +5 V Digital Supply. 4, 28, 44 AVDD +5 V Analog Supply. 5 DRVSS Digital Output Driver Ground. 6 DRVDD +3 V to +5 V Digital Output Driver Supply. 7 CLK Clock Input. 8 READ Part of DSP Interface—Pull Low to Disable Output Bits. 9 BIT16 Least Significant Data Bit (LSB). 10–23 BIT15–BIT2 Data Output Bit. 24 BIT1 Most Significant Data Bit (MSB). 25 OTR Out of Range—Set When Converter or Filter Overflows. 26 DAV Data Available. 27 CS Chip Select (CS): Active LOW. 30 RESET RESET : Active LOW. 31 SENSE Reference Amplifier SENSE: Selects REF Level. 32 VREF Input Span Select Reference I/O. 33 REFCOM Reference Common. 34 MODE Mode Select—Selects Decimation Mode. 35 BIAS Power Bias. 36 CAPB Noise Reduction Pin—Decouples Reference Level. 37 CAPT Noise Reduction Pin—Decouples Reference Level. 39 CML Common-Mode Level (AVDD/2.5). 40, 43 NC No Connect (Ground for Shielding Purposes). 41 VINA Analog Input Pin (+). 42 VINB Analog Input Pin (–). Rev. C | Page 13 of 44 BIT13 AVDD BIT12 NC BIT11 VINB BIT10 VINA BIT9 NC BIT8 CML BIT7 AVSS BIT6 CAPT BIT5 CAPB BIAS BIT4 BIT3 MODE 00581-C-010 AD9260 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = DRVDD = +5.0 V, 4 V Input Span, Differential DC Coupled Input with CML = 2.0 V, fCLOCK = 20 MSPS, Full Bias. 0 0 100kHz INPUT 100kHz INPUT 20MHz CLOCK 20MHz CLOCK –20 –20 8× DECIMATION 1× DECIMATION THD: –96dB THD: –98dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 1 23 45 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, Figure 14. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, 8x OSR (2.5 MHz Output Data Rate) Undecimated (20 MHz Output Data Rate) 0 110 100kHz INPUT 20MHz CLOCK –12dBFS/TONE –20 4× DECIMATION 106 THD: –98dB –40 102 –60 –6.5dBFS/TONE 98 –80 –26dBFS/TONE –46dBFS/TONE –100 94 –120 90 0 0.5 1.0 1.5 2.0 2.5 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, Figure 15. Dual-Tone SFDR vs. Input Frequency (F1 = F2, Span = 10% Center 4x OSR (5 MHz Output Data Rate) Frequency, Mode = 8x) 0 0 100kHz INPUT DUAL-TONE TEST 20MHz CLOCK f1 = 1.0MHz –20 –20 2× DECIMATION f2 = 975kHz THD: –98dB 20MHz CLOCK 8× DECIMATION –40 –40 IM3: –94dB –60 –60 –80 –80 –100 –100 –120 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, Figure 16. Two-Tone Spectral Performance of the AD9260 Given Inputs at 2x OSR (10 MHz Output Data Rate) 975 kHz and 1.0 MHz, 20 MHz Clock, 8x Decimation Rev. C | Page 14 of 44 dB BELOW FULL SCALE dB BELOW FULL SCALE dB BELOW FULL SCALE 00581-C-013 00581-C-012 00581-C-011 dB BELOW FULL SCALE dB BELOW FULL SCALE WORST CASE SPUR (dBFS) 00581-C-016 00581-C-014 00581-C-015 AD9260 TYPICAL AC CHARACTERIZATION CURVES VS. DECIMATION MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, AIN = 0.5 dBFS Full Bias. 90 90 8× MODE 85 8× MODE 85 4× MODE 4× MODE 80 80 75 75 2× MODE 2× MODE 70 70 65 65 1× MODE 60 60 1× MODE 55 55 50 50 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 17. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) 8x SINAD performance limited by noise contribution of input differential Figure 20. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) op amp driver –50 –70 1× MODE 1× MODE –75 –60 –80 –85 –70 –90 –80 –95 2× MODE –100 2× MODE 8× MODE 4× MODE –90 –105 4× MODE –110 –100 8× MODE –115 –110 –120 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 18. THD vs. Input Frequency (f = 20 MSPS) CLOCK Figure 21. THD vs. Input Frequency (f = 10 MSPS) CLOCK –50 –70 1× MODE –75 1× MODE –60 –80 –85 –70 –90 –80 –95 2× MODE 4× MODE –100 2× MODE –90 8× MODE –105 –110 –100 4× MODE –115 8× MODE –110 –120 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 19. SFDR vs. Input Frequency (f = 20 MSPS) CLOCK Figure 22. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 15 of 44 SINAD (dBFS) SFDR (dBFS) THD (dBFS) 00581-C-019 00581-C-018 00581-C-017 SFDR (dBFS) THD (dBFS) SINAD (dBFS) 00581-C-022 00581-C-021 00581-C-020 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 8× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 90 90 –0.5dBFS 85 –0.5dBFS 85 80 –6.0dBFS 80 –6.0dBFS 75 75 70 70 –20dBFS –20dBFS 65 65 60 60 0.1 1.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 23. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) SINAD performance Figure 26. SINAD vs. Input Frequency (fCLOCk- = 10 MSPS) limited by noise contribution of input differential op amp driver. –70 –70 –75 –75 –20dBFS –80 –80 –20dBFS –85 –85 –0.5dBFS –90 –90 –6.0dBFS –95 –100 –95 –6.0dBFS –105 –100 –0.5dBFS –110 –105 0.1 1.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 24. THD vs. Input Frequency (f = 20 MSPS) CLOCK Figure 27. THD vs. Input Frequency (fCLOCK = 10 MSPS) 105 105 100 100 –6.0dBFS –6.0dBFS 95 95 –0.5dBFS –0.5dBFS 90 90 85 85 –20dBFS –20dBFS 80 80 0.1 1.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 25. SFDR vs. Input Frequency (f = 20 MSPS) CLOCK Figure 28. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 16 of 44 THD (dB) SFDR (dBc) SINAD (dB) 00581-C-025 00581-C-024 00581-C-023 THD (dB) SFDR (dBc) SINAD (dB) 00581-C-028 00581-C-027 00581-C-026 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 4× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 90 90 85 85 –0.5dBFS 80 –0.5dBFS –6.0dBFS 80 75 –6.0dBFS 70 75 65 –20dBFS 70 60 65 55 –20dBFS 50 60 0.1 1.0 10.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 29. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 32. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –70 –70 –75 –75 –20dBFS –80 –80 –0.5dBFS –85 –85 –0.5dBFS –20dBFS –90 –90 –95 –95 –6.0dBFS –6.0dBFS –100 –100 –105 –105 –110 –110 0.1 1.0 10.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 30. THD vs. Input Frequency (f = 20 MSPS) Figure 33. THD vs. Input Frequency (f = 10 MSPS) CLOCK CLOCK 110 110 105 105 –0.5dBFS 100 100 –6.0dBFS –6.0dBFS 95 95 –20dBFS 90 90 –0.5dBFS 85 85 –20dBFS 80 80 0.1 1.0 10.0 0.1 1.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 31. SFDR vs. Input Frequency (f = 20 MSPS) Figure 34. SFDR vs. Input Frequency (f = 10 MSPS) CLOCK CLOCK Rev. C | Page 17 of 44 THD (dB) SINAD (dB) SFDR (dBc) 00581-C-031 00581-C-030 00581-C-029 THD (dB) SFDR (dBc) SINAD (dB) 00581-C-034 00581-C-033 00581-C-032 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 2× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 80 80 75 75 –0.5dBFS –0.5dBFS 70 70 –6.0dBFS –6.0dBFS 65 65 60 60 –20dBFS 55 55 –20dBFS 50 50 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 35. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 38. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –60 –60 –65 –65 –70 –70 –20dBFS –75 –75 –0.5dBFS –80 –80 –20dBFS –85 –85 –90 –90 –0.5dBFS –6.0dBFS –6.0dBFS –95 –95 –100 –100 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 36. THD vs. Input Frequency (f = 20 MSPS) Figure 39. THD vs. Input Frequency (f = 10 MSPS) CLOCK CLOCK 100 100 95 95 –6.0dBFS 90 90 –0.5dBFS –6.0dBFS 85 85 –20dBFS –0.5dBFS 80 80 75 75 –20dBFS 70 70 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 37. SFDR vs. Input Frequency (f = 20 MSPS) Figure 40. SFDR vs. Input Frequency (f = 10 MSPS) CLOCK CLOCK Rev. C | Page 18 of 44 THD (dB) SFDR (dBc) SINAD (dB) 00581-C-037 00581-C-036 00581-C-035 THD (dB) SFDR (dBc) SINAD (dB) 00581-C-040 00581-C-039 00581-C-038 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 1× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 70 70 65 65 –0.5dBFS –0.5dBFS 60 60 –6.0dBFS –6.0dBFS 55 55 50 50 45 45 –20dBFS –20dBFS 40 40 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 41. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 44. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –55 –55 –0.5dBFS –60 –60 –20dBFS –65 –65 –20dBFS –70 –70 –6.0dBFS –75 –75 –80 –80 –0.5dBFS –85 –85 –90 –90 –6.0dBFS –95 –95 –100 –100 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 42. THD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 45. THD vs. Input Frequency (fCLOCK = 10 MSPS) 100 100 95 95 –0.5dBFS –0.5dBFS 90 90 85 85 –6.0dBFS 80 –6.0dBFS 80 75 75 70 70 –20dBFS 65 65 –20dBFS 60 60 55 55 50 50 0.1 1.0 10.0 0.1 1.0 10.0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 43. SFDR vs. Input Frequency (f = 20 MSPS) Figure 46. SFDR vs. Input Frequency (f = 10 MSPS) CLOCK CLOCK Rev. C | Page 19 of 44 SDFR (dBc) THD (dB) SINAD (dB) 00581-C-043 00581-C-042 00581-C-041 SDFR (dBc) THD (dBc) SINAD (dB) 00581-C-046 00581-C-045 00581-C-044 AD9260 TYPICAL AC CHARACTERIZATION CURVES AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V. 100 –60 95 FULL BIAS –65 90 –70 85 –75 80 HALF BIAS F = 1MHz, 2× MODE IN –80 75 70 QUARTER BIAS –85 65 –90 F = 100kHz, 8× MODE IN 60 –95 55 –100 50 01 5 01520 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 COMMON MODE INPUT LEVEL (V) CLOCK FREQUENCY (MHz) Figure 50. THD vs. Common-Mode Input Level (CML) Figure 47. SFDR vs. Clock Rate (f = 100 kHz in 8x Mode) IN –40 100 FULL BIAS –50 80 HALF BIAS F = 20MHz S –60 60 F = 10MHz S QUARTER BIAS –70 40 F = 5MHz S –80 20 0 –90 5 10 15 20 25 1k 10k 100k 1M 10M 100M CLOCK FREQUENCY (MHz) INPUT FREQUENCY (Hz) Figure 48. SFDR vs. Clock Rate (fIN = 500 kHz in 4x Mode) Figure 51. CMR vs. Input Frequency (VCML = 2 V p-p, 1x Mode) 100 100 FULL BIAS 95 80 4V SPAN SFDR-2× MODE 90 60 HALF BIAS 4V SPAN SNR-8× MODE 40 85 QUARTER BIAS 1.6V SPAN SNR-8× MODE 20 80 1.6V SPAN SFDR-2× MODE 0 5 10 15 20 25 75 01 0.2 0.4 0.6 0.8.01.21.41.6 CLOCK FREQUENCY (MHz) FREQUENCY (MHz) Figure 52. 4 V vs. 1.6 V Span SNR/SFDR (fCLOCK = 20 MSPS) Figure 49. SFDR vs. Clock Rate (fIN = 1.0 MHz in 2x Mode) Rev. C | Page 20 of 44 SFDR (dBFS) SFDR (dBFS) SFDR (dBFS) 00581-C-049 00581-C-048 00581-C-047 THD (dBc) SFDR (dBFS) CMR (dB) 00581-C-052 00581-C-051 00581-C-050 AD9260 ADDITIONAL AC CHARACTERIZATION CURVES AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V, Full Bias, unless otherwise noted. 120 120 20 MSPS (dBFS) FULL BIAS 115 20 MSPS 110 FULL BIAS 110 10 MSPS (dBFS) 10 MSPS 100 HALF BIAS FULL BIAS 105 20 MSPS (dBc) 90 FULL BIAS 100 80 20 MSPS 95 HALF BIAS 10 MSPS (dBc) 70 HALF BIAS 90 10 MSPS HALF BIAS 60 85 80 50 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –60 –50 –40 –30 –20 –10 0 A (dBFS) A (dBFS) IN IN Figure 53. Single-Tone SFDR vs. Amplitude (fIN = 100 kHz, 8x Mode) Figure 56. Two-Tone SFDR (F1 = 475 kHz, F2 = 525 MHz, 8x Mode) 110 120 FULL BIAS (dBFS) 110 105 10 MSPS FULL BIAS 100 HALF BIAS (dBFS) 100 90 FULL BIAS (dBc) 95 10 MSPS 80 20 MSPS HALF BIAS FULL BIAS 90 70 HALF BIAS (dBc) 85 60 80 50 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –60 –50 –40 –30 –20 –10 0 A (dBFS) A (dBFS) IN IN Figure 54. Single-Tone SFDR vs. Amplitude (f = 1.0 MHz) Figure 57. Two-Tone SFDR (F = 0.95 kHz, F = 1.05 MHz, 8x Mode, 20 MSPS) IN 1 2 110 120 10 MSPS 110 105 HALF BIAS dBFS 100 100 dBc 20 MSPS FULL BIAS 90 95 10 MSPS 80 FULL BIAS 90 70 85 60 80 50 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –60 –50 –40 –30 –20 –10 0 A (dBFS) A (dBFS) IN IN Figure 55. Single-Tone SFDR vs. Amplitude (fIN = 500 kHz, 2x Mode) Figure 58. Two-Tone SFDR (F1 = 1.9 MHz, F2 = 2.1 MHz, 4x Mode 20 MSPS) Rev. C | Page 21 of 44 SFDR (dBFS) SFDR (dBFS) SFDR (dBFS) 00581-C-055 00581-C-054 00581-C-053 WORST SPUR (dBc AND dBFS) WORST SPUR (dBc AND dBFS) WORST SPUR (dBc AND dBFS) 00581-C-058 00581-C-057 00581-C-056 AD9260 + 16 + 4 + 4 – – – 5B 5B 3B 3B 3B 3B 4B V + + INT1 INT2 IN – – ADC DAC ADC DAC ADC DAC ADC PIPELINE CORRECTION LOGIC 5B 5B DAC1 DAC2 8 LSBs M OUT LSB –D SHUFFLE Z ++ DIFFERENTIATOR C OUT CONTROL/TEST HALF-BAND LOGIC DECIMATION FILTER STAGE 1 BANDGAP HALF-BAND REFERENCE DECIMATION FILTER STAGE 2 REFERENCE HALF-BAND BUFFER DECIMATION FILTER STAGE 3 OUTPUT BITS Figure 59. Simplified Block Diagram Rev. C | Page 22 of 44 00581-C-059 AD9260 THEORY OF OPERATION antialiasing filter for the analog input path. The decimation The AD9260 utilizes a new analog-to-digital converter filters are integrated with symmetric FIR filter structures, architecture to combine sigma-delta techniques with a high providing a linear phase response and excellent passband speed, pipelined A/D converter. This topology allows the flatness. The digital output driver register of the AD9260 AD9260 to offer the high dynamic range associated with sigma- features both READ and CHIP SELECT pins to allow easy delta converters while maintaining very wide input signal interfacing. The digital supply of the AD9260 is designed to bandwidth (1.25 MHz) at a very modest 8 oversampling ratio. operate over a 2.7 V to 5.25 V supply range, though 3 V supplies Figure 59 provides a block diagram of the AD9260. The are recommended to minimize digital noise on the board. A differential analog input is fed into a second order, multibit DATA AVAILABLE pin allows the user to easily synchronize to sigma-delta modulator. This modulator features a 5-bit flash the converter’s decimated output data rate. OUT-OF-RANGE quantizer and 5-bit feedback. In addition, a 12-bit pipelined (OTR) indication is given for an overflow in the pipelined A/D A/D quantizes the input to the 5-bit flash to greater accuracy. A converter or digital filters. A RESETB function is provided to special digital modulation loop combines the output of the 12- synchronize the converter’s decimated data and clear any bit pipelined A/D with the delayed output of the 5-bit flash to overflow condition in the analog integrators. produce the equivalent response of a second order loop with a 12-bit quantizer and 12-bit feedback. The combination of a An on-chip reference and reference buffer are included on the second order loop and multibit feedback provides inherent AD9260. The reference can be configured in either a 2.5 V stability: the AD9260 is not prone to the idle tones or full-scale mode (providing a 4 V p-p differential input full scale), a 1 V idiosyncrasies sometimes associated with higher order single bit mode (providing a 1.6 V p-p differential input full scale), or sigma-delta modulators. programmed with an external resistor divider to provide any voltage level between 1 V and 2.5 V. However, optimum noise The output of this 12-bit modulator is fed into the digital and distortion performance for the AD9260 can only be achieved decimation filter. The voltage level on the MODE pin with a 2.5 V reference, as shown in Figure 52. establishes the configuration for the digital filter. The user may bring the data out undecimated (at the clock rate), or at a For users who want to operate the part at reduced clock decimation factor of 2×, 4×, or a full 8×. The spectra for these frequencies, the bias current of the AD9260 is designed to be four cases are shown in Figure 11, Figure 12, Figure 13, and scalable. This scaling is accomplished through use of the proper Figure 14, all for a 100 kHz full-scale input and 20 MHz clock. external resistor tied to the BIAS pin: the power can be reduced The spectra of the undecimated output clearly shows the second roughly proportionately to clock frequency by as much as 75% order shaping characteristic of the quantization noise as it rises (for clock rates of 5 MHz). Refer to Figure 47 to Figure 49 and at frequencies above 1.25 MHz. Figure 53 to Figure 57 for characterization curves showing performance tradeoffs. The on-chip decimation filter provides excellent stopband rejection to suppress any stray input signal between 1.25 MHz and 18.75 MHz, substantially easing the requirements on any Rev. C | Page 23 of 44 AD9260 ANALOG INPUT AND REFERENCE OVERVIEW AVSS+ 0.5V< VINA< AVDD− 0.5V Figure 60, a simplified model of the AD9260, highlights the (3) relationship between the analog inputs, VINA, VINB and the AVSS+ 0.5V< VINB< AVDD+ 0.5V reference voltage VREF. Like the voltage applied to the top of where AVSS is nominally 0 V and AVDD is nominally +5 V, the resistor ladder in a flash A/D converter, the value VREF defines this requirement. Thus the valid inputs for VINA and defines the maximum input voltage to the A/D converter. An VINB are any combination that satisfies both Equations 2 and 3. internal reference buffer in the AD9260 scales the reference Note that the clock clamping method used in the differential voltage VREF before it is applied internally to the AD9260 A/D driver circuit shown in Figure 63 is sufficient for protecting the core. The scale factor of this reference buffer is 0.8. AD9260 in an undervoltage condition. Consequently, the maximum input voltage to the A/D core is +0.8 × VREF. The minimum input voltage to the A/D core is For additional information showing the relationships between automatically defined to be –0.8 × VREF. With this scale factor, VINA, VINB, VREF, and the digital output of the AD9260, see the maximum differential input span of 4 V p-p is obtained Table 13. with a VREF voltage of 2.5 V. A smaller differential input span may be obtained by using a VREF voltage of less than 2.5 V at Refer to Table 12 for a summary of the various analog input and the expense of ac performance (refer to Figure 52). reference configurations. ANALOG INPUT OPERATION +0.8× VREF The analog input structure of the AD9260 is optimized to meet VINA the performance requirements for some of the most demanding 16 + A/D CORE Σ communication and data acquisition applications. This input – structure is composed of a switched-capacitor network that VINB samples the input signal applied to pins VINA and VINB on –0.8× VREF every rising edge of the CLK pin. The input switched capacitors Figure 60. Simplified Input Model are charged to the input voltage during each period of CLK. The resulting charge, q, on these capacitors is equal to C × V , IN INPUT SPAN where C is the input capacitor. The change in charge on these The AD9260 is implemented with a differential input structure. capacitors, delta q, as the capacitors are charged from a previous This structure allows the common-mode level (average voltage sample of the input signal to the next sample, is approximated of the two input pins) of the input signal to be varied in the following equation, independently of the input span of the converter over a wide range, as shown in Figure 50. Specifically, the input to the A/D delta q ~ C×deltaV = C×(V −V ) (4) N N N−2 core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation, where V represents the present sample of the input signal and N V represents the sample taken two clock cycles earlier. The N–2 VCORE= VINA−VINB (1) average current flow into the input (provided from an external source) is given in the following equation, defines the output of the differential input stage and provides the input to the A/D core. I= delta q/T ~ C×(V −V )× f (5) N N−2 CLOCK The voltage, VCORE, must satisfy the condition, where T represents the period of CLK and fCLOCK represents the frequency of CLK. Equations 4 and 5 provide simplifying −0.8×VREF≤ VCORE≤+0.8×VREF (2) approximations of the operation of the analog input structure of where VREF is the voltage at the VREF pin. the AD9260. A more exact, detailed description and analysis of the input operation follows. INPUT COMPLIANCE RANGE In addition to the limitations on the differential span of the input signal indicated in Equation 2, an additional limitation is placed on the inputs by the analog input structure of the AD9260. The analog input structure bounds the valid operating range for VINA and VINB. The condition, Rev. C | Page 24 of 44 00581-C-060 AD9260 SS3 circuitry must provide additional charge, qdelta, to capacitors CS1 and CS2, which is the difference between the precharged SS1 CS1 SH1 value, Q(n–1), and the new value, Q(n), as given in the VINA CPA1 CPB1 following equation, SS4 ANALOG MODULATOR SS2 CS2 Qdelta= Q(n)−Q(n−1) (8) SH2 VINB CPA2 CPB2 Qdelta= CS×[VCORE−VCORE() delay +Vdelta] (9) SH3 DRIVING THE INPUT SH4 Transient Response Figure 61. Detailed Analog Input Structure The charge glitch occurs once at the beginning of every period Figure 61 illustrates the analog input structure of the AD9260. of the input CLK (falling edge), and the sample is taken on For the moment, ignore the presence of the parasitic capacitors capacitors CS1 and CS2 exactly one-half period later (rising CPA and CPB. The effects of these parasitic capacitors will be edge). Figure 62 presents a typical input waveform applied to discussed near the end of this section. The switched capacitors, input Pins VINA and VINB of the AD9260. CS1 and CS2, sample the input voltages applied on pins VINA TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE and VINB. These capacitors are connected to input pins VINA and VINB when CLK is low. When CLK rises, a sample of the CLOCK input signal is taken on capacitors CS1 and CS2. When CLK is high, capacitors CS1 and CS2 are connected to the Analog Modulator. The modulator precharges capacitors CS1 and CS2 VINA-VINB to minimize the amount of charge required from any circuit used in combination with the AD9260 to drive input pins VINA and VINB. This reduces the input drive requirements of the analog circuitry driving pins VINA and VINB. The Analog Modulator precharges the voltages across capacitors CS1 and Figure 62. Typical Input Waveform CS2, approximately equal to a delayed version of the input Figure 62 illustrates the effect of the charge glitch when a source signal. When capacitors CS1 and CS2 are connected to input with nonzero output impedance is used to drive the input pins. pins VINA and VINB, the differential charge, Q(n), on these This source must be capable of settling from the charge glitch in capacitors is given in the following equation, one-half period of the CLK. Unfortunately, the MOS switches used in any CMOS-switched capacitor circuit (including those Q(n)= q1− q2= CS×VCORE (6) in the AD9260) include nonlinear parasitic junction where q1 and q2 are the individual charges stored on capacitors capacitances connected to their terminals. Figure 61 also CS1 and CS2 respectively, and CS is the capacitance value of illustrates the parasitic capacitances, Cpa1, Cpb1, Cpa2, and CS1 and CS2. When capacitors CS1 and CS2 are connected to Cpb2, associated with the input switches. the Analog Modulator during the preceding precharge clock Parasitic capacitor Cpa1 and Cpa2 are always connected to Pins phase, the capacitors are precharged equal to an approximation VINA and VINB and therefore do not contribute to the glitch of a previous sample of the input signal. Consequently the energy. Parasitic capacitors Cpb1 and Cpb2, on the other hand, differential charge on these capacitors while CLK is high is cause a charge glitch that adds to that of input capacitors CS1 given in the following equation, and CS2 when they are connected to input Pins VINA and Q(n−1)= CS×VCORE() delay + CS×Vdelta (7) VINB. The nonlinear junction capacitance of Cpb1 and Cpb2 cause charge glitch energy that is nonlinearily related to the where VCORE(delay) is the value of VCORE sampled during a input signal. Therefore, linear settling is difficult to achieve previous period of CLK, and Vdelta is the sigma-delta error unless the input source completely settles during one-half voltage left on the capacitors. Vdelta is a natural artifact of the period of CLK. A portion of the glitch impulse energy kicked sigma-delta feedback techniques utilized in the Analog back at the source is not linearly related to the input signal. Modulator of the AD9260. It is a small random voltage term Therefore, the best way to ensure that the input signal settles that changes every clock period and varies from 0 to ±0.05 linearly is to use wide bandwidth circuitry, which settles as ×VREF. completely as possible from the glitch during one-half period of the CLK. The analog circuitry used to drive the input pins of the AD9260 must respond to the charge glitch that occurs when capacitors The AD9260 utilizes a proprietary clock-boosted boot- CS1 and CS2 are connected to input pins VINA and VINB. This strapping technique to reduce the nonlinear parasitic Rev. C | Page 25 of 44 00581-C-061 00581-C-062 AD9260 capacitances of the internal CMOS switches. This technique 499Ω 499Ω 50Ω VIN VINA improves the linearity of the input switches and reduces the +5V C S nonlinear parasitic capacitance. Thus, this technique reduces 100pF the nonlinear glitch energy. The capacitance values for the input AD9260 AD8138 capacitors and parasitic capacitors for the input structure of the AD9260, as illustrated in Figure 61, are listed as follows. 50Ω VINB 499Ω CS = 3.2 pF, Cpa = 6 pF, Cpb = 1 pF (where CS is the C 499Ω S 100pF capacitance value of capacitors CS1 and CS2, Cpa is the value of VREF capacitors Cpa1 and Cpa2, and Cpb is the value of capacitors Cpb1 and Cpb2). The total capacitance at each input pin is C 10µF 0.1µF IN = CS + Cpa + Cpb = 10.2 pF. Figure 63. AD8138 Single-Ended Differential ADC Driver Input Driver Considerations The second driver circuit, shown in Figure 64, can provide The optimum noise and distortion performance of the AD9260 slightly enhanced noise performance relative to the AD8138, can ONLY be achieved when the AD9260 is driven differentially assuming low noise, high speed op amps are used. This with a 4 V input span. Since not all applications have a signal differential op amp driver circuit is configured to convert and preconditioned for differential operation, there is often a need level-shift a 2 V p-p single-ended, ground-referenced signal to a to perform a single-ended-to-differential conversion. In the 4 V p-p differential signal centered at the common-mode level case of the AD9260, a single-ended-to-differential conversion is of the AD9260. The circuit is based on two op amps that are best realized using a differential op amp driver. Although a configured as matched unity gain difference amplifiers. The transformer will perform a similar function for ac signals, its single-ended input signal is applied to opposing inputs of the usefulness is precluded by its inability to directly drive the difference amplifiers, thus providing differential outputs. The AD9260 and thus the additional requirement of an active low common-mode offset voltage is applied to the noninverting noise, low distortion buffer stage. resistor leg of each difference amplifier providing the required Single-Ended-to-Differential Op Amp Driver offset voltage. This offset voltage is derived from the common- There are two single-ended-to-differential op amp driver mode level (CML) pin of the AD9260 via a low output circuits useful for driving the AD9260. The first circuit, shown impedance buffer amplifier capable of driving a 1 µF capacitive in Figure 63, uses the AD8138 and represents the best choice in load. The common-mode offset can be varied over a 1.8 V to most applications. The AD8138 is a low distortion differential 2.5 V span without any serious degradation in distortion ADC driver designed to convert a ground-referenced single- performance as shown in Figure 50, thus providing some ended input signal to a differential output signal with a flexibility in improving output compression distortion from specified common-mode level for dc-coupling applications. It is some ±5 op amps with limited positive voltage swing. capable of maintaining the typical THD and SFDR performance To protect the AD9260 from an undervoltage fault condition of the AD9260 with only a slight degradation in its noise from op amps specified for ±5 V operation, two 50 Ω series performance in the 8 mode (i.e., SNR of 85 dB–86 dB). resistors and a diode to AGND are inserted between each op In this application, the AD8138 is configured for unity gain and amp output and the AD9260 inputs. The AD9260 will its common-mode output level is set to 2.5 V, functioning like inherently be protected against any overvoltage condition if the the VREF of the AD9260, to maximize its output headroom op amps share the same positive power supply (AVDD) as the while operating from a single supply. Note that the single- AD9260. Note, the gain accuracy and common-mode rejection supply operation has the benefit of not requiring an input of each difference amplifier in this driver circuit can be protection network for the AD9260 in dc-coupled applications. enhanced by using a matched thin-film resistor network A simple R-C network at the output is used to filter out high (Ohmtek ORNA5000F) for the op amps. Resistor values should frequency noise from the AD8138. Recall, the AD9260’s small be 500 Ω or less to maintain the lowest possible noise. signal bandwidth is 75 MHz. Therefore, any noise falling within The noise performance of each unity gain differential driver the baseband bandwidth of the AD9260 defined by its sample circuit is limited by its inherent noise gain of two. For unity gain and decimation rate, as well as images of its baseband response op amps only, the noise gain can be reduced from two to one occurring at multiples of the sample rate, will degrade its overall noise performance. Rev. C | Page 26 of 44 00581-C-063 AD9260 R (1 dB–2 dB) when compared to the OPA642. Note that the V -VIN CML majority of the AD9260 test and characterization data presented R 50Ω 50Ω in this data sheet was taken using the AD9632 op amp in this VINA R C R C dc-coupled driver circuit. This driver circuit is also provided on VIN 100pF C AD9260 the AD9260 evaluation board since the AD8138 was unreleased F C at that time. D V -VIN CML 100pF C F 50Ω R 50Ω The outputs of each op amp are ac coupled via a small series VINB R resistor and capacitor (i.e., 50 Ω and 0.1 µF) to the respective C C 100pF inputs of the AD9260. Similar to the dc coupled driver, further R R out-of-band noise reduction can be realized with the addition of 100 pF single-ended and differential capacitors, C and C . The AD817 S D lower cutoff frequency of this ac-coupled circuit is determined CML by RC and CC in which RC is tied to the common-mode level pin, 1.0µF 0.1µF CML, of the AD9260 for proper biasing of the inputs. Although Figure 64. DC-Coupled Differential Driver with Level-Shifting the OPA642 was found to provide the lowest overall noise and beyond the input signals passband by adding a shunt capacitor, distortion performance (88.8 dB and 96 dB THD @ 100 kHz), C , across the feedback resistor of each op amp. This will F the AD8055, or dual AD8056, suffered only a 0.5 dB to 1.5 dB essentially establish a low-pass filter which reduces the noise degradation in overall performance. It is worth noting that gain to one beyond the filter’s f–3 dB while simultaneously given the high level of performance attainable by the AD9260, bandlimiting the input signal to f–3 dB. Note that the pole special consideration must be given to both the quality of the established by this filter can also be used as the real pole of an test equipment and test set-up in its evaluation. antialiasing filter. Since the noise contribution of two op amps Common-Mode Level from the same product family are typically equal but The CML pin is an internal analog bias point used internally by uncorrelated, the total output-referred noise of each op amp the AD9260. This pin must be decoupled to analog ground with will add root-sum square leading to a further 3 dB degradation at least a 0.1 µF capacitor as shown in Figure 65. The dc level of in the circuit’s noise performance. Further out-of-band noise CML is approximately AVDD/2.5. This voltage should be reduction can be realized with the addition of single-ended and buffered if it is to be used for any external biasing. differential capacitors, CS and CD. Note: the common-mode voltage of the input signal applied to The distortion and noise performance of the two op amps the AD9260 need not be at the exact same level as CML. While within the signal path are critical in achieving optimum this level is recommended for optimal performance, the performance in the AD9260. Low noise op amps capable of AD9260 is tolerant of a range of input common-mode voltages providing greater than 85 dB THD at 1 MHz while swinging around AVDD/2.5. over a 1 V to 3 V range are a rare commodity, yet these parts are the only ones that should be considered. The AD9632 op amp CML was found to provide superb distortion performance in this 0.1µF circuit due to its ability to maintain excellent distortion AD9260 performance over a wide bandwidth while swinging over a 1 V to 3 V range. Since the AD9632 is gain-of-two or greater stable, Figure 65. CML Decoupling the use of the noise reduction shunt capacitors discussed above was prohibited, thus degrading its noise performance slightly Rev. C | Page 27 of 44 00581-C-064 00581-C-065 AD9260 REFERENCE OPERATION SENSE and another resistor (R2) connected between SENSE The AD9260 contains an on-board band gap reference and and REFCOM. The other comparator controls internal circuitry internal reference buffer amplifier. The onboard reference that will disable the reference amplifier if the SENSE pin is tied provides a pin-strappable option to generate either a 1 V or 2.5 to AVDD. Disabling the reference amplifier allows the VREF V output. With the addition of two external resistors, the user pin to be driven by an external voltage reference. can generate reference voltages other than 1 V and 2.5 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See TO A/D Table 12 for a summary of the pin-strapping options for the 5kΩ CAPT AD9260 reference configurations. Note, the optimum noise and 6.25kΩ distortion can only be achieved with a 2.5 V reference. 6.25kΩ A2 Figure 66 shows a simplified model of the internal voltage 5kΩ CAPB reference of the AD9260. A pin-strappable reference amplifier buffers a 1 V fixed reference. The output from the reference DISABLE LOGIC A2 amplifier, A1, appears on the VREF pin and must be decoupled with 0.1 µF and 10 µF capacitor to REFCOM. The voltage on – + the VREF pin determines the full-scale input span of the A/D. A1 VREF 1V This input span equals: 7.5k 7.5kΩ Full - Scale Input Span= 1.6×VREF AD9260 SENSE The voltage appearing at the VREF pin, as well as the state of 5kΩ LOGIC the internal reference amplifier, A1, is determined by the DISABLE A1 voltage appearing at the SENSE pin. The logic circuitry contains REFCOM two comparators that monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of Figure 66. Simplified Reference A1. If the SENSE pin is tied to REFCOM, the switch is The reference buffer circuit level shifts the reference to an connected to the internal resistor network, thus providing a appropriate common-mode voltage for use by the internal VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a circuitry. The on-chip buffer provides the low impedance short or resistor, the switch is connected to the SENSE pin. A necessary for driving the internal switched capacitor circuits short will provide a VREF of 1.0 V while an external resistor and eliminates the need for an external buffer op amp. network will provide an alternative VREF SPAN between 1.0 V and 2.5 V. The external resistor network, for example, may be implemented as a resistor divider circuit. This divider circuit could consist of a resistor (R1) connected between VREF and Table 12. Reference Configuration Summary Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To INTERNAL 1.6 1 SENSE VREF INTERNAL 4.0 2.5 SENSE REFCOM INTERNAL 1.6 ≤ SPAN ≤ 4.0 and 1 ≤ VREF ≤ 2.5 and R1 VREF and SENSE SPAN = 1.6 × VREF VREF = (1+R1/R2) R2 SENSE and REFCOM EXTERNAL 1.6 ≤ SPAN ≤4.0 1 ≤ VREF ≤2.5 SENSE AVDD VREF EXT. REF. Rev. C | Page 28 of 44 00581-C-066 AD9260 bandlimits the noise contribution from the reference. The turn- The actual reference voltages used by the internal circuitry of on time of the reference voltage appearing between CAPT and the AD9260 appear on the CAPT and CAPB pins. If VREF is CAPB is approximately 15 ms and should be evaluated in any configured for 2.5 V, thus providing a 4 V full-scale input span, power-down mode of operation. the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V respectively. For proper operation when using the internal or an AD9260 0.1µF external reference, it is necessary to add a capacitor network to V CAPT REF decouple the CAPT and CAPB pins. Figure 67 shows the + + 0.1µF 10µF SENSE 0.1µF 10µF recommended decoupling network. This capacitive network performs the following three functions: (1) along with the REFCOM CAPB 0.1µF reference amplifier, A2, it provides a low source impedance over Figure 67. Recommended Reference Decoupling Network a large frequency range to drive the A/D internal circuitry; (2) it provides the necessary compensation for A2; and (3) it Rev. C | Page 29 of 44 00581-C-067 AD9260 DIGITAL INPUTS AND OUTPUTS Table 14. CS and READ Pin Functionality DIGITAL OUTPUTS CS READ Condition of Data Output Pins The AD9260 output data is presented in a twos complement Low Low Data Output Pins in Hi-Z State format. Table 13 indicates the output data formats for various Low High ADC Data on Output Pins input ranges and decimation modes. A straight binary output High Low Data Output Pins in Hi-Z State data format can be created by inverting the MSB. High High Data Output Pins in Hi-Z State Table 13. Output Data Format Input (V) Condition (V) Digital Output 8× Decimation Mode DAV Pin VINA–VINB < –0.8 ×VREF 1000 0000 0000 0000 The DAV pin indicates when the output data of the AD9260 is VINA–VINB = –0.8 ×VREF 1000 0000 0000 0000 valid. Digital output data is updated on the rising edge of DAV. VINA–VINB = 0 0000 0000 0000 0000 The data hold time (tH) is dependent on the external loading of VINA–VINB = +0.8 ×VREF – 1 LSB 0111 1111 1111 1111 DAV and the digital data output pins (BIT1–BIT16) as well as VINA–VINB >= + 0.8 ×VREF 0111 1111 1111 1111 the particular decimation mode. The internal DAV driver is 4× Decimation Mode sized to be larger than the drivers pertaining to the digital data VINA–VINB < –0.825 ×VREF 1000 0001 0001 1100 outputs to ensure that rising edge of DAV occurs before the data VINA–VINB = –0.825 ×VREF 1000 0001 0000 1100 transitions under similar loading conditions (i.e., fanout) VINA–VINB = 0 0000 0000 0000 0000 regardless of mode. Note that minimum data hold (tH) of 3.5 ns VINA–VINB = +0.825 ×VREF –1 LSB 0111 1110 1110 0011 is specified in the Figure 4 timing diagram from the 50% point VINA–VINB >= + 0.825 ×VREF 0111 1110 1110 0011 of DAV’s rising edge to the 50% of data transition using a 2× Decimation Mode capacitive load of 20 pF for DAV and BIT1–BIT16. Applications VINA–VINB < –0.825 ×VREF 1000 0000 0100 0001 interfacing to TTL logic and/or having larger capacitive loading VINA–VINB = –0.825 ×VREF 1000 0000 0100 0001 for DAV than BIT1–BIT16 should consider latching data on the VINA–VINB = 0 0000 0000 0000 0000 falling edge of DAV since the falling edge of DAV occurs well VINA–VINB = +0.825 ×VREF –1 LSB 0111 1111 1011 1110 after the data has transitioned in the case of the 2×, 4×, and 8× VINA–VINB >= + 0.825 ×VREF 0111 1111 1011 1110 modes. The duty cycle of DAV is approximately 50% and it The slightly different ± full-scale input voltage conditions and CS remains active independent of and READ. their corresponding digital output code for the 4× and RESET 2× decimation modes can be attributed to the different digital Pin scaling factors applied to each AD9260 FIR decimation stage for The RESET pin is an asynchronous digital input that is active filter optimization purposes. Thus, a + full-scale reading of low. Upon asserting RESET low, the clocks in the digital 0111 1111 1111 1111 and – full-scale reading of 1000 0000 0000 decimation filters are disabled, the DAV pin goes low and the 0000 is unachievable in the 2× and 4× decimation modes. As a data on the digital output data pins (Bit 1–Bit 16) is invalid. In result, a digital overrange condition can never exist in the 2× or addition, the analog modulator in the AD9260 and internal the 4× decimation mode and thus OTR being set high indicates clock dividers used in the decimation filters are reset and will an overrange condition in the analog modulator. RESET remain reset as long as is maintained low. In the 2×, 4×, RESET or 8× mode, the must remain low for at least a clock The output data format in 1× decimation differs from that in 2×, 4× and 8× decimation modes. In 1× decimation mode the period to ensure all the clock dividers and analog modulator output data remains in a twos complement format, but the are reset. Upon bringing RESET high, the internal clock digital numbers are scaled by a factor of 7/128. This factor of dividers will begin to count again on the next falling edge of 7/128 is the product of an internal scale factor of 7/8 in the CLK and DAV will go high approximately 15 ns after this analog modulator and a 1/16 scale factor caused by LSB falling edge, resuming normal operation. Refer to Figure 9 for justification of the 12-bit modulator data. a timing diagram. CS and Read Pins The state of the internal decimation filters in the AD9260 CS RESET The and READ pins control the state of the output data pins remains unchanged when is asserted low. Consequently, CS (BIT1–BIT16) on the AD9260. The pin is active low and the when RESET is pulsed low, this resets the analog modulator but CS READ pin is active high. When and READ are both active does not clear all the data in the digital filters. The data in the filters is corrupted by the effect of resetting the analog the ADC data is driven on the output data pins, otherwise the modulator (this causes an abrupt change at the input of the output data pins are in a high-impedance (Hi-Z) state. Table 14 digital filter and this change is unrelated to the signal at the indicates the relationship between the CS and READ pins and input of the A/D converter). Similarly, in multiplexed the state of Pins Bit 1 to Bit 16. Rev. C | Page 30 of 44 AD9260 applications in which the input of the A/D converters sees an internally clipping. A long duration overrange condition will abrupt change, the data in the analog modulator and digital cause the digital filter data to exceed full scale. For this reason, filter will be corrupted. the OTR signal is generated using two separate internal out-of- range detectors. For this reason, following a pulse on the RESET pin, or change The first of these out-of-range detectors is placed at the output in channels (i.e., multiplexed applications only), the decimation of the analog modulator and indicates whether the modulator filters must be flushed of their data. These filters have a output signal has extended 3% beyond the full-scale range of memory length, hence delay, equal to the number of filter taps the converter. If the modulator output signal exceeds 3% times the clock rate of the converter. This memory length may beyond full scale, the digital data is hard-limited (i.e., clipped) be interpreted in terms of a number of samples stored in the to a number that is 3% larger than full scale. Due to the delay of decimation filter. For example, if the part is in 8× decimation the switched capacitor analog modulator, the OTR signal is mode, the delay is 321/f . This corresponds to 321 samples CLOCK delayed 3 1/2 clock cycles relative to the clock edge in which the stored in the decimation filter. These 321 samples must be overranged analog input signal was sampled. flushed from the AD9260 after RESET is pulsed high prior to reusing the data from the AD9260. That is, the AD9260 should The second out-of-range detector is placed at the output of the be allowed to clock for 321 samples as the corrupted data is stage three decimation filter and detects whether the low pass flushed from the filters. If the part is in 4× or 2× decimation filtered data has exceeded full scale. When this occurs, the filter mode, then the relatively smaller group delays of the 4× and 2× output data is hard limited to full scale. The OTR signal is a decimation filters result fewer samples that must be flushed logical OR function of the signals from these two internal out- from the filters (108 samples and 23 samples respectively). of-range detectors. If either of these detectors produces an out- of-range signal, the OTR pin goes high and the data may be In 2×, 4×, or 8× mode, RESET may be used to synchronize seriously corrupted. multiple AD9260s clocked with the same clock. The decimation filters in the AD9260 are clocked with an internal clock divider. If the AD9260 is used in a system that incorporates automatic The state of this clock divider determines when the output data gain control (AGC), the OTR signal may be used to indicate becomes available (relative to CLK). In order to synchronize that the signal amplitude should be reduced. This may be multiple AD9260s clocked with the same clock, it is necessary particularly effective for use in maximizing the signal dynamic that the clock dividers in each of the individual AD9260s are all range if the signal includes high-frequency components that reset to the same state. When RESET is asserted low, these clock occasionally exceed full scale by a small amount. If, on the other dividers are cleared. On the next falling edge of CLK following hand, the signal includes large amplitude low frequency the rising edge of RESET, the clock dividers begin counting and components that cause the digital filters to overrange, this may the clock is applied to the digital decimation filters. cause the low pass digital filter to overrange. In this case the data may become seriously corrupted and the digital filters may OTR Pin RESET need to be flushed. See the pin function description The OTR pin is a synchronous output that is updated each CLK above for an explanation of the requirements for flushing the period. It indicates that an overrange condition has occurred digital filters. within the AD9260. Ideally, OTR should be latched on the falling edge of CLK to ensure proper setup-and-hold time. OTR should be sampled with the falling edge of CLK. This However, since an overrange condition typically extends well signal is invalid while CLK is HIGH. beyond one clock cycle (i.e., does not toggle at the CLK rate). OTR typically remains high for more than a clock cycle, MODE OPERATION allowing it to be successfully detected on the rising edge of CLK The Mode Select Pin (MODE) allows the user to select one of or monitored asynchronously. four available digital filter modes using a single pin. Each mode configures the internal decimation filter to decimate at: 1×, 2×, An overrange condition must be carefully handled because of 4×, or 8×. Refer to Table 15 for mode pin ranges. the group delays in the low-pass digital decimation filters in the output stages of the AD9260. When the input signal exceeds the The mode selection is performed by using a set of internal full-scale range of the converter, this can have a variety of comparators, as illustrated in Figure 68, so that each mode effects upon the operation of the AD9260, depending on the corresponds to a voltage range on the input of the MODE pin. duration and amplitude of this overrange condition. A short The output of the comparators are fed into encoding logic duration overrange condition (<< filter group delay) may cause where, on the falling edge of the clock, the encoded data the analog modulator to briefly overrange without causing the is latched. data in the low pass digital filters to exceed full scale. The analog modulator is actually capable of processing signals slightly (3%) beyond the full-scale range of the AD9260 without Rev. C | Page 31 of 44 AD9260 Table 15. Recommended Mode Pin Ranges AVDD and Configurations Mode Pin Range Typical Mode Pin Decimation Mode 4R 0 V–0.5 V GND 8× 0.5 V–1.5 V VREF/2 2× 3R 1.5 V–3.0 V CML 4× MODE PIN 3.0 V–5.0 V AVDD 1× LATCH ENCODED MODE 2R BIAS PIN OPERATION The Bias Select Pin (BIAS) gives the user, who is able to operate the AD9260 at a slower clock rate, the added flexibility of CLOCK running the device in a lower, power consumption mode when R it is clocked at less than 20 MHz. This is accomplished by scaling the bias current of the AD9260 AVSS as illustrated in Figure 69. The bias amplifier drives a source Figure 68. Simplified Mode Pin Circuitry follower and forces 1 V across R , which sets the bias current. BIAS CURRENT EXT This effectively adjusts the bias current in the modulator amplifiers and FLASH preamplifiers. When a large value of REXT 1V is used, a smaller bias current is available to the internal amplifier circuitry. As a result these amplifiers need more time to settle, thus dictating the use of a slower clock as the power BIAS PIN is reduced. Refer to the characterization curves shown in Figure REXT 47 to Figure 54 revealing the performance tradeoffs. The scaling is accomplished by properly attaching an external Figure 69. Simplified Bias Pin Circuitry resistor to the BIAS pin of the AD9260 as shown in Table 17. REXT is normally 2 kΩ for a clock speed of 20 MHz and scales inversely with clock rate. Because BIAS is an external pin, minimization of capacitance to this pin is recommended in order to prevent instability of the bias pin amplifier. Rev. C | Page 32 of 44 ENCODER 00581-C-069 00581-C-068 AD9260 POWER DISSIPATION CONSIDERATIONS 30 The power dissipation of the AD9260 is dependent on its 4× MODE application specific configuration and operating conditions. 25 8× MODE The analog power dissipation as shown in Figure 70 is primarily a function of its power bias setting and sample rate. It remains 20 insensitive to the particular input waveform being digitized or 1× MODE digital filter MODE setting. The digital power dissipation is 15 primarily a function of the digital supply setting (i.e., +3 V to 2× MODE +5 V), the sample rate and, to a lesser extent, the MODE setting 10 and input waveform. Figure 71 and Figure 72 show the total current dissipation of the combined digital (DVDD) and digital 5 driver supply (DRVDD) for +3 V and +5 V supplies. Note, DVDD and DRVDD are typically derived from the same supply 0 51 105 20 bus since no degradation in performance results. A 1 MHz full- SAMPLE RATE (MSPS) scale sine wave was used to ensure maximum digital activity in Figure 72. I /I vs. Sample Rate (DVDD = DRVDD = 5 V, f = 1 DVDD DRVDD IN the digital filters and the digital drivers had a fanout of one. MHz) Note also that a twofold decrease in digital supply current DIGITAL OUTPUT DRIVER CONSIDERATIONS results when the digital supply is reduced form +5 V to +3 V. (DRVDD) 130 The AD9260 output drivers can be configured to interface with FULL BIAS [2kΩ] +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V, 110 respectively. The AD9260 output drivers in each mode are appropriately sized to provide sufficient output current to drive 90 a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD HALF BIAS [4kΩ] performance. Applications requiring the AD9260 to drive large 70 capacitive loads or large fanout may require additional decoupling capacitors on DRVDD. The addition of external 50 buffers or latches helps reduce output loading while providing QUARTER BIAS [8kΩ] effective isolation from the data bus. 30 Clock Input and Considerations 51 105 20 SAMPLE RATE (MSPS) The AD9260 internal timing uses the two edges of the clock Figure 70. IAVDD vs. Sample Rate (AVDD = +5V, Mode 1x-4x) input to generate a variety of internal timing signals. The clock 16 8× MODE input must meet or exceed the minimum specified pulse width 14 high and low (tCH and tCL) specifications for the given A/D as 4× MODE defined in the Switching Specifications at the beginning of the 12 data sheet to meet the rated performance specifications. For 1× MODE 10 example, the clock input to the AD9260 operating at 20 MSPS 2× MODE may have a duty cycle between 45% and 55% to meet this 8 timing requirement since the minimum specified t and t is CH CL 6 22.5 ns. For clock rates below 20 MSPS, the duty cycle may deviate from this range to the extent that both tCH and tCL are 4 satisfied. All high speed, high resolution A/Ds are sensitive to 2 the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f ) due to only aperture jitter IN 0 5 1015 20 (t ) can be calculated with the following equation: A SAMPLE RATE (MSPS) SNR= 20 log [1/(2π f t )] 10 IN A Figure 71. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD = 3 V, f = 1 MHz) IN In the equation, the rms aperture jitter, t , represents the A rootsum square of all the jitter sources which include the clock input, analog input signal, and A/D aperture jitter specification. For example, if a 500 kHz full-scale sine wave is sampled by an Rev. C | Page 33 of 44 I /I (mA) I (mA) DVDD DRVDD AVDD 00581-C-071 00581-C-070 I /I (mA) DVDD DRVDD 00581-C-072 AD9260 A/D with a total rms jitter of 15 ps, the SNR performance of the Analog and Digital Supply Decoupling A/D will be limited to 86.5 dB. The AD9260 features separate analog, digital, and driver supply and ground pins, helping to minimize digital corruption of The clock input should be treated as an analog signal in cases sensitive analog signals. where aperture jitter may affect the dynamic range of the AD9260. In fact, the CLK input buffer is internally powered Figure 73 shows the power supply rejection ratio vs. frequency from the AD9260’s analog supply, AVDD. Thus the CLK for a 200 mV p-p ripple applied to AVDD, DVDD, and logic high and low input voltage levels are +3.5 V and DAVDD. +1.0 V, respectively. 90 Supplies for clock drivers should be separated from the A/D 85 DVDD AND DRVDD output driver supplies to avoid modulating the clock signal with 80 digital noise. Low jitter crystal controlled oscillators make the 75 best clock sources. If the clock is generated from another type of 70 source (by gating, dividing, or other method), it should be 65 retimed by the original clock at the last step. 60 AVDD GROUNDING AND DECOUPLING 55 Analog and Digital Grounding 50 Proper grounding is essential in any high speed, high resolution 45 system. Multilayer printed circuit boards (PCBs) are 40 recommended to provide optimal grounding and power 1 2 3 4 01 100 10 10 schemes. The use of ground and power planes offers FREQUENCY (kHz) distinct advantages: Figure 73. AD9260 PSRR vs. Frequency (8x Mode) In general, AVDD, the analog supply, should be decoupled to 1. The minimization of the loop area encompassed by a signal AVSS, the analog common, as close to the chip as physically and its return path. possible. Figure 74 shows the recommended decoupling for the 2. The minimization of the impedance associated with analog supplies; 0.1 µF ceramic chip capacitors should provide ground and power paths. adequately low impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9260 to 3. The inherent distributed capacitor formed by the power simplify the layout of the decoupling capacitors and provide the plane, PCB insulation, and ground plane. shortest possible PCB trace lengths. The AD9260/EB power plane layout, shown in Figure 84 depicts a typical arrangement These characteristics result in both a reduction of using a multilayer PCB. electromagnetic interference (EMI) and an overall improvement in performance. 4 AVDD AVDD 44 0.1µF 0.1µF It is important to design a layout that prevents noise from 3 AVSS 38 AVSS coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away AD9260 from the input circuitry. While the AD9260 features separate 28 AVDD analog and digital ground pins, it should be treated as an analog 0.1µF 29 AVSS component. The AVSS, DVSS and DRVSS pins must be joined together directly under the AD9260. A solid ground plane under the A/D is acceptable if the power and ground return currents Figure 74. Analog Supply Decoupling are managed carefully. Alternatively, the ground plane under The digital activity on the AD9260 chip falls into two general the A/D may contain serrations to steer currents in predictable categories: digital logic and output drivers. The internal digital directions where cross-coupling between analog and digital logic draws surges of current, mainly during the clock would otherwise be unavoidable. The AD9260/EB ground transitions. The output drivers draw large current impulses layout, shown in Figure 83, depicts the serrated type of while the output bits are changing. The size and duration of arrangement. The analog and digital grounds are connected by these currents are a function of the load on the output bits: large a jumper below the A/D. capacitive loads are to be avoided. Note that the digital logic of Rev. C | Page 34 of 44 PSRR (dBFS) 00581-C-074 00581-C-073 AD9260 supplies (DRVDD) of the AD9260 from the +5 V power bus. the AD9260 is referenced DVDD while the output drivers are Properly selected ferrite beads can provide more than 40 dB of referenced to DRVDD. Also note that the SNR performance isolation from high frequency switching transients originating of the AD9260 remains independent of the digital or driver from AD9260 supply pins. Further noise immunity from noise supply setting. is provided by the inherent power supply rejection of the The decoupling shown in Figure 75, a 0.1 µF ceramic chip AD9260 as shown in Figure 70. If digital operation at 3 V is capacitor, is appropriate for a reasonable capacitive load on the desirable for power savings and or to provide for a 3 V digital digital outputs (typically 20 pF on each pin). Applications logic interface, a 5 V to 3 V linear regulator can be used to drive involving greater digital loads should consider increasing the DVDD and/or DRVDD. A more complete discussion on this digital decoupling proportionally, and/or using external layout and decoupling scheme can be found in Chapter 7, pages buffers/latches. 7-27 to 7-55 of the High speed Design Techniques seminar book, which is available at: 3 DVDD 6 DRVDD www.analog.com/support/frames/lin_frameset.hml 0.1µF 0.1µF AD9260 1 DVSS 5 DRVSS INSERT 5/3 VOLT LINEAR REGULATOR FOR 3 OR 3.3V DIGITAL OPERATION Figure 75. Digital Supply Decoupling FERRITE A complete decoupling scheme will also include large tantalum BEAD CORE* V A or electrolytic capacitors on the PCB to reduce low frequency 10µF ripple to negligible levels. Refer to the AD9260/EB schematic DVDD DRVDD and layouts in Figure 80 to Figure 84 for more information 0.1µF 0.1µF regarding the placement of decoupling capacitors. DVSS DRVSS V A AD9260 An alternative layout and decoupling scheme is shown in Figure AVDD 76. This layout and decoupling scheme is well suited for 0.1µF AVSS applications in which multiple AD9260s are located on the BITS 1–16, DAV same PC board and/or the AD9260 is part of a multicard BUFFER AVDD mixed-signal system in which grounds are tied back at the LATCH 0.1µF AVSS system supplies (i.e., star ground configuration). In this case, CLK the AD9260 is treated as an analog component in which its AVDD analog (i.e., AVDD) and digital (DVDD and DRVDD) supplies 0.1µF AVSS are derived from the systems +5 V analog supply and all of the AD9260’s ground pins are tied directly to the analog ground plane which resides directly underneath the IC. SAMPLING CLOCK Referring to Figure 76, each supply pin is directly decoupled to GENERATOR their respective ground pin or analog ground plane via a Figure 76. High Frequency Supply Rejection ceramic 0.1 µF chip capacitor. Surface mount ferrite beads are used to isolate the analog (AVDD), digital (DVDD), and driver Rev. C | Page 35 of 44 00581-C-075 00581-C-076 AD9260 EVALUATION BOARD GENERAL DESCRIPTION Table 17. Evaluation Board Recommended Resistance Value The AD9260 Evaluation Board is designed to provide an easy for External Bias Resistor and flexible method of exercising the AD9260 and demonstrate Resistor Value Clock Speed (max) Power Consumption its performance to data sheet specifications. The evaluation 2 kΩ 20 MHz 585 mW board is fabricated in four layers: the component layer, the 4 kΩ 10 MHz 325 mW ground layer, the power layer, and the solder layer. The board is 8 kΩ 5 MHz 200 mW clearly labeled to provide easy identification of components. 16 kΩ 2.5 MHz 150 mW Ample space is provided near the analog and clock inputs to provide additional or alternate signal conditioning. Data Interfacing Controls FEATURES AND USER CONTROLS The data interfacing controls (RESETB, CSB, READ, DAV) are Jumper Controlled Mode/OSR Selection all accessible via SMA connectors (J2–J5) as illustrated in The choice of Mode/OSR can easily be varied by jumping either Figure 78 within the data interfacing control block. The JP1, JP2, JP3, or JP4 as illustrated in Figure 78 within the RESETB, CSB, and READ connections are each supplied with Mode/OSR Control Block. To obtain the desired mode, refer to two sets or resistor pin cups to allow the user to pull-up or pull- Table 16. down each signal to a fixed state. R5, R6, and R30 will terminate to ground, while R7, R28, and R29 terminate to DRVDD. The Table 16. AD9260 Evaluation Board Mode Select DAV and OTR signals are also directly connected to the data Mode/OSR Connect Jumper output connector P1. All interfacing controls are buffered 1× JP4 through the CMOS line driver 74HC541. 2× JP2 Buffered Output Data 4× JP3 8× JP1 The twos complement output data is buffered through two CMOS noninverting bus transceivers (U2 and U3) and made available at pin connector P1 as illustrated in Figure 78 within Selectable Power Bias the data output block. The power consumption of the AD9260 can be scaled down if Jumper Controlled Reference Source the user is able to operate the device at a lower clock frequency. The choice of reference for the AD9260 can easily be varied As illustrated in Figure 78, pin cups are provided for the between 1.0 V, 2.5 V or external by using jumpers JP5, JP6, JP7, external resistor (R2) tied to the BIAS pin of the AD9260. and JP9 as illustrated in Figure 78 within the reference Table 17 defines the recommended resistance for a given clock configuration block. To obtain the desired reference, see speed to obtain the desired power consumption. Table 18. U5 8 1 NC 2.5/3V VCC2 7 2 AD780R NC +VIN 6 R10 3 1KPOT VOUT TEMP 1kΩ 5 4 C18 C19 TRIM GNDS 0.1µF 0.1µF AGND C14 0.1µF R3 R12 VREFEXT 15kΩ 15kΩ JP10 + C12 C13 Q1 R11 AD817R 0.1µF 10µF 2N2222 49.9Ω R9 1V 1kΩ U6 R8 + 390Ω R4 R13 C17 10kΩ 10kΩ 10µF C15 0.1µF AGND VCC2 AGND Figure 77. Evaluation Board External Reference Circuitry Rev. C | Page 36 of 44 00581-C-077 AD9260 Table 18. Evaluation Board Reference Pin Configuration For signal tone input signal: The user would remove jumper (JP8) and use only IN-1 as the input signal connector. Reference Input Voltage Voltage Connect Jumper (p-p FS) Selectable Input Signal Common-Mode Level Source 2.5 V JP7 4.0 V The input signal’s common-mode level (CML) can be set 1.0 V JP6 1.6 V by U10. External JP5, JP9, and JP10 4.0 V To use the Input CML generated by U10: Disconnect jumper The external reference circuitry is illustrated in Figure 77. By JP13 and Connect resistors RX3 and RX4. The CML generated connecting or disconnecting JP10, the external reference can be by U10 is variable and adjustable using the 1 kΩ Variable configured for either 1.0 V or 2.5 V. By connecting JP10, the Resistor R35. external reference will be configured to provide a 2.5 V reference and by disconnecting JP10 reference, it will be SHIPMENT CONFIGURATION configured for 2.5 V. By leaving JP10 open, the external The AD9260 Evaluation Board is configured as follows reference will be configured to provide a 1.0 V reference. when shipped: Flexible DC or AC Coupled External Clock Inputs 1. 2.5 V external reference/4.0 V differential full-scale input: As illustrated in Figure 78, the AD9260 Evaluation Board is designed to allow the user the flexibility of selecting how to JP5, JP9, and JP10 connected, JP6 and JP7 disconnected. connect the external clock source. It is also equipped with a 2. 8× Mode/OSR: JP1 connected, JP2, JP3, and JP4 playpen area for experimenting with optional clock drivers or disconnected. crystals. 3. Full Speed Power Bias: R2 = 2 kΩ and connected. Selecting DC or AC Coupled External Clock: DC Coupled: To directly drive the clock externally via the 4. CSB pulled low: R6 = 49.9 Ω and connected, R29 CLKIN connector, connect JP11 and disconnect JP12. Note: disconnected. 50 Ω terminated by R27. 5. RESETB pulled high: R7 = 10 kΩ and connected, R30 AC Coupled: To ac couple the external clock and level shift it to disconnected. midsupply, connect JP12 and disconnect JP11. Note: 50 Ω terminated by R27. 6. READ pulled high: R28 = 10 kΩ and connected, R5 Flexible Input Signal Configuration Circuitry disconnected. The AD9260 Evaluation Board’s Input Signal Configuration 7. Single Tone Input: JP8 removed, input applied via IN-1 Block is illustrated in Figure 79. It is comprised of an input (J7). signal summing amplifier (U7), a variable input signal common-mode generator (U10), and a pair of amplifiers (U8 8. Input signal common-mode level set by Variable Resistor and U9) that configure the input into a differential signal and R35 to 2.0 V: Jumper JP12 is disconnected and resistors drive it, through a pair of isolation resistors, into the input pins R×4 and R×3 are connected. of AD9260. The user can either input a signal or dual signal into the evaluation board via the two SMA connectors (J6 and J7) 9. AC-Coupled Clock: JP12 connected and JP11 labeled IN-1 or IN-2. disconnected. Note: 50 Ω terminated by R27. The user should refer to the Driving the Input section of the QUICK SETUP data sheet for a detailed explanation of how the inputs are to be 1. Connect the required power supplies to the Evaluation driven and what amplifier requirements are recommended. Board as illustrated in Figure 28: Selecting Single or Dual Signal Input ± 5 VA supplies to P5—Analog Power The input amplifier (U7) can either be configured as a dual +5 VA supply to P4—Analog Power input signal inverting summer or a single tone inverting buffer. +5 VD supply to P3—Digital Power +5 VD supply to P2—Driver Power This flexibility will allow for slightly better noise performance in the single tone mode due to the inherent noise gain 2. Connect a Clock Source to CLKIN (J1): difference in the two amplifier configurations. An optional Note: 50 Ω terminated by R1. feedback capacitor (C9) was added to allow the user additional 3. Connect an Input Signal Source to the IN-1 (J7). out-of band filtering of the input signal if needed. For two-tone input signals: The user would leave jumpers (JP8) 4. Turn on power. connected and use IN-1 and IN-2 (J7 and J6) as the connectors 5. The AD9260 Evaluation Board is now ready for use. for the input signals. Rev. C | Page 37 of 44 AD9260 poor jitter performance. See Note 8 if a crystal-based clock APPLICATION INFORMATION generator is used during FFT testing. 1. The ADC analog input should not be overdriven. Using a signal amplitude slightly lower than FSR will allow a small A low jitter clock may be generated by using a high- amount of headroom so that noise or DC offset voltage will frequency clock source and dividing this frequency down not overrange the ADC and hard limit on signal peaks. with a low noise clock divider to obtain the AD9260 input CLK. Maintaining a large amplitude clock signal may also 2. Two-tone tests can produce signal envelopes that exceed be very beneficial in minimizing the effects of noise in the FSR. Set each test signal to slightly less than –6 dB to digital gates of the clock generation circuitry. prevent hard limiting on peaks. Finally, special care should be taken to avoid coupling 3. Band-pass filtering of test signal generators is absolutely noise into any digital gates preceding the AD9260 CLK pin. necessary for SNR, THD, and IMD tests. Note that a low Short leads are necessary to preserve fast rise times and noise signal generator along with a high Q band-pass filter careful decoupling should be used with these digital gates is often necessary to achieve the attainable noise and the supplies for these digital gates should be connected performance of the AD9260. to the same supplies as that of the internal AD9260 clock circuitry (Pins 44 and 38). 4. Test signal generators must have exceptional noise performance to achieve accurate SNR measurements. 7. Two-tone testing will require isolation between test signal Good generators, together with fifth-order elliptical band- generators to prevent IMD generation in the test generator pass filters, are recommended for SNR tests. Narrow output circuits. bandwidth crystal filters can also be used to filter generator broadband noise, but they should be carefully tested for 8. A very low-side lobe window must be used for FFT operation at high signal levels. calculations if generators cannot be phase-locked and set to exact frequencies. 5. The analog inputs of the AD9260 should be terminated directly at the input pin sockets with the correct filter 9. A well designed, clean PC board layout will assure proper terminating impedance (50 Ω or 75 Ω), or it should be operation and clean spectral response. Proper grounding driven by a low output impedance buffer. Short leads are and bypassing, short lead lengths, separation of analog and necessary to prevent digital noise pickup. digital signals, and the use of ground planes are particularly important for high frequency circuits. 6. A low noise (jitter) clock signal generator is required for Multilayer PC boards are recommended for best good ADC dynamic performance. A poor generator can performance, but if carefully designed, a two-sided PC seriously impair good SNR performance particularly at board with large heavy (20 oz. foil) ground planes can give higher input frequencies. A high frequency generator, excellent results. based on a clock source (e.g., crystal source), is recommended. Frequency-synthesized clock generators 10. Prototype plug-boards or wire-wrap boards will not should generally be avoided because they typically provide be satisfactory. Rev. C | Page 38 of 44 AD9260 Figure 78. Evaluation Board Top Level Schematic Rev. C | Page 39 of 44 RESET CS READ DAV DATA OUTPUT CONTROL BLOCK J2 J5 J4 J3 DRVDD REFERENCE CONFIGURATION U4 BLOCK 20 1 G1 DRVDD VCC 19 10 R7 R5 JP9:EXT REF G2 GND 10kΩ 49.9Ω MDAVDD 2 18 JP7:2.5V REF A1 Y1 P1 33 3 17 R30 R29 R6 R28 A2 Y2 P1 38 4 16 JP6:1V REF 49.9Ω 10kΩ 49.9Ω 10kΩ JP15 A3 Y3 RD MODE/OSR 5 15 A4 Y4 CONTROL BLOCK 6 14 JP5:EXT REF A5 Y5 7 TP8:OTR 13 VREFEXT A6 Y6 8 12 TP1:RD JP4:1× A7 Y7 9 11 MDAVDD Y8 A8 JP3:4× 74HC541 CML + C10 C11 JP2:2× 10µF 0.1µF 1V RESETB JP1:8× TP2 CSBBUE TP6 CT17 P1 39 DRVDD C5 P1 37 R2 U2 0.1µF P1 35 2kΩ TP3 1 20 DIR VCC DRVDD 33 32 31 30 29 28 27 26 25 24 23 2 19 A1 OUT_EN P1 2 3 18 CT1 A2 P1 4 B1 P1 1 C1 34 22 4 17 CT2 MODE P1 6 0.1µF C2 C4 A3 BIT03 B2 P1 3 35 21 P1 8 5 16 CT3 10µF BIAS 0.1µF BIT04 A4 B3 P1 5 TP4:REFB 36 P1 10 20 6 15 CT4 CAPB BIT05 A5 B4 P1 7 P1 12 TP5:REFT 37 19 7 14 CT5 CAPT A6 BIT06 B5 P1 9 P1 14 38 18 8 13 CT6 C3 AVSS A7 P1 16 BIT07 B6 P1 11 39 17 0.1µF 9 12 CT7 P1 18 CML AD9260 A8 BIT08 B7 P1 13 40 16 P1 20 10 11 CT8 NC BIT09 W1 GND B8 P1 15 41 15 P1 22 VINA VINA BIT10 TP7 TP9 TP11 TP12 TP13 TP15 42 P1 24 14 74HC245 VINB VINB BIT11 P1 26 43 13 W2 NC BIT12 P1 28 44 12 INVDD AVDD P1 30 BIT13 CT18 P1 32 DRVDD P1 34 12 3 456 78 91 01 1 AGND P1 38 CML U3 P1 40 1 20 R31 C6 C7 DIR VCC DRVDD 2 19 10µF 0.1µF 1kΩ A1 TP10 OUT_EN 3 18 CT9 A2 P1 17 B1 CT10 4 17 A3 P1 19 CT20 B2 CT11 5 16 P1 21 A4 B3 6 15 CT12 C61 C62 A5 B4 P1 23 10µF 0.1µF 7 14 CT13 CT19 A6 P1 25 B5 DVDD CT14 8 13 A7 P1 27 B6 CT15 9 12 A8 P1 29 B7 JP11 10 11 CT16 C8 GND B8 P1 31 DC COUPLED 0.1µF 74HC245 J1 CLKIN DATA OUTPUT BLOCK JP13 R33 AC COUPLED R27 1kΩ 49.9kΩ 00581-C-078 NC = NO CONNECT DVSS REFCOM VREF AVSS SENSE DVDD DVDD AVDD RESET FLAVDD DRVSS AVSS DRVDD AVDD MDAVDD SHIELDED_TRACE CLK CS RD READ DAV BIT16(LSB) OTR BIT15 BIT01(MSB) BIT14 BIT02 AD9260 R18 390Ω C20 0.1µF VCC2 C9 TBD R19 390Ω 8 U8 R21 R22 3 J6 7 JP8 390Ω 390Ω 6 AD9632 IN-2 4 VEE 2 R1 R17 5 57.6Ω 390Ω C16 R16 J7 100pF 390Ω 5 U7 IN-1 2 4 VEE R20 R46 R47 6 R15 AD9632 JP16 390Ω 50Ω 50Ω 57.6Ω 7 VINA 3 8 R14 VCC2 50Ω R23 C24 390Ω 100pF VCC2 8 R48 R49 U9 3 7 JP17 50Ω 50Ω 6 VINB AD9632 4 2 R24 C26 5 390Ω 100pF R32 390Ω R25 VEE R26 390Ω 390Ω VCC2 CX4 XXX R34 390Ω RX4 7 U10 2 JP12 XXX IKPOT RX3 AD817R 6 9260CML XXX R35 3 4 1kΩ C25 + C23 C22 0.1µF 10µF 0.1µF Figure 79. Evaluation Board Input Configuration Block L3 L6 R41 R51 1 1 P4:+5V FLAVDD P5:+5AUX VCC2 R40 R50 + + C36 C38 C39 C27 10mF 0.1µF 0.01µF 47µF C37 C55 0.1mF 0.1µF 2 P5 L7 R53 1 L4 R43 P5:–5AUX VEE MDAVDD R52 + R42 C56 + C40 C42 C43 47µF 10µF 0.1µF 0.01µF C57 C41 0.1µF 2 0.1µF P5 L2 R37 1 P2:VDD DRVDD L5 R45 INVDD R36 + C28 R44 + 47µF C44 C46 C47 C29 10µF 0.1µF 0.01µF 0.1µF C45 2 P2 0.1µF 2 P4 VCC2 L2 VEE VEE VEE VCC2 VCC2 R39 1 P3:D5 DVDD R38 + C30 C31 C64 C48 C49 C50 C32 C34 C35 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 22µF 0.1µF 0.01µF C33 0.1µF 2 P3 U7 U8 U9 U7 U8 U9 VCC2 DRVDD DRVDD DRVDD EVALUATION BOARD POWER SUPPLY CONFIGURATION C51 C52 C53 C54 0.1µF 0.1µF 0.1µF 0.1µF U10 U2 U3 U4 DEVICE SUPPLY DECOUPLING Figure 80. Evaluation Board Power Supply Configuration and Coupling Rev. C | Page 40 of 44 00581-C-079 00581-C-080 AD9260 Figure 81. Evaluation Board Component Side Layout (Not to Scale) Figure 82. Evaluation Board Solder Side Layout (Not to Scale) Rev. C | Page 41 of 44 AD9260 Figure 83. Evaluation Board Ground Plane Layout (Not to Scale) Figure 84. Evaluation Board Power Plane Layout (Not to Scale) Rev. C | Page 42 of 44 AD9260 OUTLINE DIMENSIONS 13.45 13.20 SQ 1.03 12.95 0.88 2.45 MAX 0.73 33 23 SEATING 34 22 PLANE 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 7° VIEW A 2.20 0° PIN 1 2.00 44 12 0.25 MAX 1.80 0.10 MIN 1 11 COPLANARITY 0.10 0.45 0.80 VIEW A 0.29 BSC ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-022AB - Figure 85.44-Lead MQFP (S-44) Dimensions shown in millimeters and inches ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9260AS –40°C to +85°C 44-Lead MQFP S-44 AD9260ASRL –40°C to +85°C 44-Lead MQFP S-44 2 AD9260ASZ –40°C to +85°C 44-Lead MQFP S-44 2 AD9260ASZRL –40°C to +85°C 44-Lead MQFP S-44 AD9260-EB Evaluation Board 1 S = Metric Quad Flatpack. 2 Z = Pb-free part. Rev. C | Page 43 of 44 AD9260 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00581–0–7/04(C) Rev. C | Page 44 of 44