ANALOG DEVICES AD9259

Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC Data Sheet AD9259 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN 4 ADCs integrated into 1 package DRVDD DRGND 98 mW ADC power per channel at 50 MSPS AD9259 14 SNR = 73 dB (to Nyquist) VIN + A SERIAL D + A PIPELINE T/H D – A ENOB = 12 bits VIN – A LVDS ADC SFDR = 84 dBc (to Nyquist) 14 VIN + B PIPELINE SERIAL D + B Excellent linearity T/H D – B VIN – B ADC LVDS DNL = ±0.5 LSB (typical) 14 VIN + C SERIAL PIPELINE D + C INL = ±1.5 LSB (typical) T/H D – C VIN – C LVDS ADC Serial LVDS (ANSI-644, default) 14 VIN + D Low power, reduced signal option (similar to IEEE 1596.3) SERIAL PIPELINE D + D T/H LVDS D – D VIN – D ADC Data and frame clock outputs VREF 315 MHz full-power analog bandwidth FCO+ SENSE + 2 V p-p input voltage range – 0.5V FCO– DATA RATE 1.8 V supply operation REFT REF MULTIPLIER SERIAL PORT DCO+ REFB SELECT Serial port control INTERFACE DCO– Full-chip and individual-channel power-down modes RBIASAGND CSB SDIO/ODM SCLK/DTP CLK+ CLK– Flexible bit orientation Figure 1. Built-in and custom digital test pattern generation Programmable clock and data alignment The ADC automatically multiplies the sample rate clock for the Programmable output resolution appropriate LVDS serial data rate. A data clock output (DCO) for Standby mode capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel APPLICATIONS power-down is supported and typically consumes less than 2 mW Medical imaging and nondestructive ultrasound when all channels are disabled. Portable ultrasound and digital beam-forming systems Quadrature radio receivers The ADC contains several features designed to maximize Diversity radio receivers flexibility and minimize system cost, such as programmable Tape drives clock and data alignment and programmable digital test pattern Optical networking generation. The available digital test patterns include built-in Test equipment deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). GENERAL DESCRIPTION The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con- specified over the industrial temperature range of −40°C to +85°C. verter (ADC) with an on-chip sample-and-hold circuit designed PRODUCT HIGHLIGHTS for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for 1. Small Footprint. Four ADCs are contained in a small, space- outstanding dynamic performance and low power in applications saving package. where a small package size is critical. 2. Low power of 98 mW/channel at 50 MSPS. 3. Ease of Use. A data clock output (DCO) operates at The ADC requires a single 1.8 V power supply and LVPECL-/ frequencies of up to 350 MHz and supports double data CMOS-/LVDS-compatible sample rate clock for full performance rate (DDR) operation. operation. No external reference or driver components are 4. User Flexibility. The SPI control offers a wide range of flexible required for many applications. features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit). Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 05965-001 AD9259 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 21 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 29 Functional Block Diagram .............................................................. 1 Hardware Interface ..................................................................... 29 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 31 Revision History ............................................................................... 3 Reading the Memory Map Table .............................................. 31 Specifications ..................................................................................... 4 Reserved Locations .................................................................... 31 AC Specifications .......................................................................... 5 Default Values ............................................................................. 31 Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 31 Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 35 Timing Diagrams .......................................................................... 8 Power Supplies ............................................................................ 35 Absolute Maximum Ratings .......................................................... 10 Input Signals................................................................................ 35 Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 35 ESD Caution ................................................................................ 10 Default Operation and Jumper Selection Settings ................. 36 Pin Configuration and Function Descriptions ........................... 11 Alternative Analog Input Drive Configuration...................... 37 Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 51 Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 51 Theory of Operation ...................................................................... 19 Rev. E | Page 2 of 52 Data Sheet AD9259 REVISION HISTORY Changes to Figure 2 to Figure 4 ............................................................... 7 12/11—Rev. D to Rev. E Changes to Figure 10 ............................................................................... 12 Changes to Output Signals Section and Figure 60 ...................... 35 Changes to Figure 15 to Figure 17, Figure 22, and Figure 31 .......... 14 Change to Default Operation and Jumper Selection Settings Changes to Figure 21 and Figure 22 Captions .................................... 15 Section .............................................................................................. 36 Changes to Figure 41 ............................................................................... 19 Change to Figure 63 ........................................................................ 39 Changes to Clock Duty Cycle Considerations Section ..................... 20 Added Endnote 2 in Ordering Guide ........................................... 51 Changes to Power Dissipation and Power-Down Mode Section ... 21 Changes to Figure 50 to Figure 52 Captions ....................................... 23 4/10—Rev. C to Rev. D Change to Table 8 ..................................................................................... 23 Changes to Table 16 ........................................................................ 33 Changes to Table 9 Endnote .................................................................. 24 Updated Outline Dimensions ........................................................ 51 Changes to Digital Outputs and Timing Section ............................... 25 Changes to Ordering Guide ........................................................... 51 Added Table 10 ......................................................................................... 25 Changes to RBIAS Pin Section .............................................................. 26 Deleted Figure 53 and Figure 54 ........................................................... 26 11/09—Rev. B to Rev. C Changes to Figure 56 ............................................................................... 27 Added EPAD Note to Figure 5 ...................................................... 11 Changes to Hardware Interface Section .............................................. 28 Changes to Input Signals Section and Figure 60 ......................... 35 Added Figure 57 ....................................................................................... 29 Updated Outline Dimensions ........................................................ 51 Changes to Table 15 ................................................................................. 29 Changes to Ordering Guide ........................................................... 51 Changes to Reading the Memory Map Table Section ...................... 30 Change to Output Signals Section ........................................................ 34 7/07—Rev. A to Rev. B Changes to Figure 60 ............................................................................... 34 Change to General Description ....................................................... 1 Changes to Default Operation and Changes to Figure 2 and Figure 4 .................................................... 7 Jumper Selection Settings Section ................................................... 35 Changes to the Hardware Interface Section ................................ 29 Changes to Alternative Analog Input Drive Changes to Table 17 ........................................................................ 48 Configuration Section ........................................................................ 36 5/07—Rev. 0 to Rev. A Changes to Figure 63 ............................................................................... 38 Changes to Effective Number of Bits (ENOB) ..................................... 4 Changes to Table 17 ................................................................................. 46 Changes to Logic Output (SDIO/ODM) .............................................. 5 Changes to Ordering Guide ................................................................... 50 Added Endnote 3 to Table 3..................................................................... 5 6/06—Revision 0: Initial Version Change to Pipeline Latency ..................................................................... 6 Rev. E | Page 3 of 52 AD9259 Data Sheet SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter Temperature Min Typ Max Unit RESOLUTION 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±1 ±8 mV Offset Matching Full ±2 ±8 mV Gain Error Full ±0.5 ±2 % FS Gain Matching Full ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.5 ±1.0 LSB Integral Nonlinearity (INL) Full ±1.5 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ppm/°C REFERENCE Output Voltage Error (V = 1 V) Full ±5 ±30 mV REF Load Regulation at 1.0 mA (V = 1 V) Full 3 mV REF Input Resistance Full 6 kΩ ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full AVDD/2 V Differential Input Capacitance Full 7 pF Analog Bandwidth, Full Power Full 315 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V I Full 185 192.5 mA AVDD I Full 32.5 34.7 mA DRVDD Total Power Dissipation (Including Output Drivers) Full 392 409 mW Power-Down Dissipation Full 2 4 mW 2 Standby Dissipation Full 72 mW CROSSTALK Full −100 dB 3 CROSSTALK (Overrange Condition) Full −100 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. E | Page 4 of 52 Data Sheet AD9259 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter Temperature Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 73.5 dB fIN = 19.7 MHz Full 71.0 73.0 dB f = 70 MHz Full 72.8 dB IN SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 72.7 dB f = 19.7 MHz Full 70.2 72.2 dB IN f = 70 MHz Full 72.0 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz Full 11.92 Bits IN f = 19.7 MHz Full 11.5 11.85 Bits IN f = 70 MHz Full 11.8 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz Full 84 dBc IN fIN = 19.7 MHz Full 73 84 dBc fIN = 70 MHz Full 78 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −88 dBc fIN = 19.7 MHz Full −84 −73 dBc fIN = 70 MHz Full −78 dBc WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 dBc fIN = 19.7 MHz Full −90 −80 dBc f = 70 MHz Full −88 dBc IN TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS f = 15 MHz, f = 16 MHz 25°C 80.0 dBc IN1 IN2 f = 70 MHz, f = 71 MHz 25°C 80.0 dBc IN1 IN2 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. Rev. E | Page 5 of 52 AD9259 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF 3 LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (I = 800 μA) Full 1.79 V OH Logic 0 Voltage (IOL = 50 μA) Full 0.05 V DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option) Logic Compliance LVDS Differential Output Voltage (V ) Full 150 250 mV OD Output Offset Voltage (V ) Full 1.10 1.30 V OS Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. Rev. E | Page 6 of 52 Data Sheet AD9259 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. 1, 2 Parameter Temp Min Typ Max Unit 3 CLOCK Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (t ) Full 10 ns EH Clock Pulse Width Low (t ) Full 10 ns EL 3 OUTPUT PARAMETERS Propagation Delay (t ) Full 2.0 2.7 3.5 ns PD Rise Time (t ) (20% to 80%) Full 300 ps R Fall Time (t ) (20% to 80%) Full 300 ps F FCO Propagation Delay (tFCO) Full 2.0 2.7 3.5 ns 4 DCO Propagation Delay (tCPD) Full tFCO + ns (t /28) SAMPLE 4 DCO to Data Delay (t ) Full (t /28) − 300 (t /28) (t /28) + 300 ps DATA SAMPLE SAMPLE SAMPLE 4 DCO to FCO Delay (t ) Full (t /28) − 300 (t /28) (t /28) + 300 ps FRAME SAMPLE SAMPLE SAMPLE Data to Data Skew Full ±50 ±150 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 600 ns Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 8 CLK cycles APERTURE Aperture Delay (t ) 25°C 500 ps A Aperture Uncertainty (Jitter) 25°C <1 ps rms Out-of-Range Recovery Time 25°C 2 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 t /28 is based on the number of bits multiplied by 2; delays are based on half duty cycles. SAMPLE Rev. E | Page 7 of 52 AD9259 Data Sheet TIMING DIAGRAMS N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D – x MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 2. 14-Bit Data Serial Stream, MSB First (Default) N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA D – x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 3. 12-Bit Data Serial Stream, MSB First Rev. E | Page 8 of 52 05965-040 05965-039 Data Sheet AD9259 N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA D – x LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 LSB D0 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 4. 14-Bit Data Serial Stream, LSB First Rev. E | Page 9 of 52 05965-041 AD9259 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Stresses above those listed under Absolute Maximum Ratings ELECTRICAL may cause permanent damage to the device. This is a stress AVDD to AGND −0.3 V to +2.0 V rating only; functional operation of the device at these or any DRVDD to DRGND −0.3 V to +2.0 V other conditions above those indicated in the operational AGND to DRGND −0.3 V to +0.3 V section of this specification is not implied. Exposure to absolute AVDD to DRVDD −2.0 V to +2.0 V maximum rating conditions for extended periods may affect 1 Digital Outputs to DRGND −0.3 V to +2.0 V device reliability. CLK+, CLK− to AGND −0.3 V to +3.9 V THERMAL IMPEDANCE VIN + x, VIN – x to AGND −0.3 V to +2.0 V SDIO/ODM to AGND −0.3 V to +2.0 V Table 6. PDWN, SCLK/DTP, CSB to AGND −0.3 V to +3.9 V 1 Air Flow Velocity (m/sec) θ θ θ Unit JA JB JC REFT, REFB, RBIAS to AGND −0.3 V to +2.0 V 0.0 24 °C/W VREF, SENSE to AGND −0.3 V to +2.0 V 1.0 21 12.6 1.2 °C/W ENVIRONMENTAL 2.5 19 °C/W Operating Temperature −40°C to +85°C Range (Ambient) 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. Maximum Junction 150°C Temperature Lead Temperature 300°C ESD CAUTION (Soldering, 10 sec) Storage Temperature −65°C to +150°C Range (Ambient) 1 Digital outputs include D + x, D − x, DCO+, DCO−, FCO+, FCO−. Rev. E | Page 10 of 52 Data Sheet AD9259 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AVDD 1 36 AVDD AVDD 2 35 AVDD 34 VIN – D 3 VIN – A EXPOSED PADDLE, PIN 0 33 VIN + D 4 VIN + A (BOTTOM OF PACKAGE) AVDD 5 32 AVDD 31 AVDD 6 PDWN AD9259 TOP VIEW 30 7 CLK– CSB 8 29 CLK+ SDIO/ODM 28 AVDD 9 SCLK/DTP 27 AVDD 10 AVDD 11 26 DRGND DRGND 12 25 DRVDD DRVDD NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATIONAL. Figure 5.Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle) 1, 2, 5, 6, 9, 10, 27, 32, AVDD 1.8 V Analog Supply 35, 36, 39, 45, 46 11, 26 DRGND Digital Output Driver Ground 12, 25 DRVDD 1.8 V Digital Output Driver Supply 3 VIN − D ADC D Analog Input Complement 4 VIN + D ADC D Analog Input True 7 CLK− Input Clock Complement 8 CLK+ Input Clock True 13 D − D ADC D Digital Output Complement 14 D + D ADC D Digital Output True 15 D − C ADC C Digital Output Complement 16 D + C ADC C Digital Output True 17 D − B ADC B Digital Output Complement 18 D + B ADC B Digital Output True 19 D − A ADC A Digital Output Complement 20 D + A ADC A Digital Output True 21 FCO− Frame Clock Output Complement 22 FCO+ Frame Clock Output True 23 DCO− Data Clock Output Complement 24 DCO+ Data Clock Output True 28 SCLK/DTP Serial Clock/Digital Test Pattern 29 SDIO/ODM Serial Data I/O/Output Driver Mode Rev. E | Page 11 of 52 13 D – D 48 VIN – C D + D 14 47 VIN + C D – C 15 46 AVDD 16 D + C 45 AVDD D – B 17 44 REFT D + B 18 43 REFB 19 42 D – A VREF 41 D + A 20 SENSE FCO– 21 40 RBIAS 22 39 AVDD FCO+ 23 38 DCO– VIN + B DCO+ 24 37 VIN – B 05965-003 AD9259 Data Sheet Pin No. Mnemonic Description 30 CSB Chip Select Bar 31 PDWN Power-Down 33 VIN + A ADC A Analog Input True 34 VIN − A ADC A Analog Input Complement 37 VIN − B ADC B Analog Input Complement 38 VIN + B ADC B Analog Input True 40 RBIAS External resistor sets the internal ADC core bias current 41 SENSE Reference Mode Selection 42 VREF Voltage Reference Input/Output 43 REFB Differential Reference (Negative) 44 REFT Differential Reference (Positive) 47 VIN + C ADC C Analog Input True 48 VIN − C ADC C Analog Input Complement Rev. E | Page 12 of 52 Data Sheet AD9259 EQUIVALENT CIRCUITS DRVDD V V D– D+ VIN ± x V V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ 1kΩ SCLK/DTP 10Ω AND PDWN CLK– 30kΩ Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. E | Page 13 of 52 05965-030 05965-032 05965-035 05965-005 05965-031 05965-033 AD9259 Data Sheet AVDD 70kΩ 1kΩ CSB VREF 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit Rev. E | Page 14 of 52 05965-036 05965-034 05965-037 Data Sheet AD9259 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 67.31dB SNR = 73.8dB ENOB = 10.89 BITS ENOB = 11.97 BITS –20 –20 SFDR = 83.4dBc SFDR = 77.38dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.4 MHz, f = 50 MSPS Figure 18. Single-Tone 32k FFT with f = 170 MHz, f = 50 MSPS IN SAMPLE IN SAMPLE 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 66.87dB SNR = 72.94dB ENOB = 11.82 BITS ENOB = 10.82 BITS –20 –20 SFDR = 78.60dBc SFDR = 74.97dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS Figure 19. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 50 MSPS 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 71.96dB SNR = 65.62dB ENOB = 11.66 BITS ENOB = 10.61 BITS –20 –20 SFDR = 76.68dBc SFDR = 68.11dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Single-Tone 32k FFT with f = 120 MHz, f = 50 MSPS IN SAMPLE Figure 20. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 50 MSPS Rev. E | Page 15 of 52 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05965-053 05965-085 05965-052 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05965-050 05965-051 05965-054 AD9259 Data Sheet 100 90 f = 35MHz IN 90 f = 50MSPS SAMPLE 2V p-p, SFDR 85 80 70 2V p-p, SFDR 80 60 75 50 2V p-p, SNR 2V p-p, SNR 40 70 30 80dB 20 REFERENCE 65 10 60 0 –60 –50 –40 –30 –20 –10 0 10 15 20 25 30 35 40 45 50 ANALOG INPUT LEVEL (dBFS) ENCODE (MSPS) Figure 24. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 50 MSPS Figure 21. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 0 90 AIN1 AND AIN2 = –7dBFS SFDR = 87.76dBc IMD2 = 90.18dBc –20 85 IMD3 = 87.27dBc 2V p-p, SFDR –40 80 –60 75 2V p-p, SNR –80 70 –100 65 –120 60 0 5 10 15 20 25 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) ENCODE (MSPS) Figure 25. Two-Tone 32k FFT with f = 15 MHz and f = 16 MHz, Figure 22. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 50 MSPS IN1 IN2 f = 50 MSPS SAMPLE 100 0 AIN1 AND AIN2 = –7dBFS f = 10.3MHz IN 90 SFDR = 80.37dBc f = 50MSPS SAMPLE IMD2 = 79.75dBc –20 80 IMD3 = 84.50dBc 70 2V p-p, SFDR –40 60 –60 50 2V p-p, SNR 40 –80 30 80dB 20 REFERENCE –100 10 0 –120 –60 –50 –40 –30 –20 –10 0 0 5 10 15 20 25 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 23. SNR/SFDR vs. Analog Input Level, f = 10.3 MHz, f = 50 MSPS Figure 26. Two-Tone 32k FFT with f = 70 MHz and f = 71 MHz, IN SAMPLE IN1 IN2 f = 50 MSPS SAMPLE Rev. E | Page 16 of 52 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 05965-066 05965-060 05965-059 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dB) 05965-055 05965-065 05965-056 Data Sheet AD9259 90 0.5 0.4 85 2V p-p, SFDR (dBc) 0.3 80 0.2 75 0.1 70 2V p-p, SNR (dB) 0 –0.1 65 –0.2 60 –0.3 55 –0.4 50 –0.5 1 10 100 1000 0 2000 4000 6000 8000 10000 12000 14000 16000 ANALOG INPUT FREQUENCY (MHz) CODE Figure 27. SNR/SFDR vs. Analog Input Frequency, fSAMPLE = 50 MSPS Figure 30. DNL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS 90 –45.0 –45.5 85 2V p-p, SFDR 80 –46.0 75 –46.5 70 –47.0 2V p-p, SINAD 65 –47.5 60 –48.0 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 45 50 TEMPERATURE (°C) FREQUENCY (MHz) Figure 28. SINAD/SFDR vs. Temperature, f = 10.3 MHz, f = 50 MSPS Figure 31. CMRR vs. Frequency, f = 50 MSPS IN SAMPLE SAMPLE 2.0 1.2 1.006 LSB rms 1.5 1.0 1.0 0.8 0.5 0 0.6 –0.5 0.4 –1.0 0.2 –1.5 0 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 CODE CODE Figure 29. INL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS Figure 32. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS Rev. E | Page 17 of 52 INL (LSB) SNR/SFDR (dB) SINAD/SFDR (dB) 05965-072 05965-071 05965-073 CMRR (dB) DNL (LSB) NUMBER OF HITS (Millions) 05965-086 05965-075 05965-074 AD9259 Data Sheet 0 0 NPR = 63.89dB –1 NOTCH = 18.0MHz –20 NOTCH WIDTH = 3.0MHz –2 –3dB CUTOFF = 315MHz –3 –40 –4 –60 –5 –6 –80 –7 –8 –100 –9 –120 –10 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS Figure 34. Full-Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS Rev. E | Page 18 of 52 AMPLITUDE (dBFS) 05965-076 FUNDAMENTAL LEVEL (dB) 05965-077 Data Sheet AD9259 THEORY OF OPERATION low-Q inductors or ferrite beads is required when driving the The AD9259 architecture consists of a pipelined ADC divided into converter front end at high IF frequencies. Either a shunt three sections: a 4-bit first stage followed by eight 1.5-bit stages and capacitor or two single-ended capacitors can be placed on the a final 3-bit flash. Each stage provides sufficient overlap to correct inputs to provide a matching passive network. This ultimately for flash errors in the preceding stage. The quantized outputs from creates a low-pass filter at the input to limit unwanted each stage are combined into a final 14-bit result in the digital broadband noise. See the AN-742 Application Note, the AN-827 correction logic. The pipelined architecture permits the first stage Application Note, and the Analog Dialogue article “Transformer- to operate with a new input sample while the remaining stages Coupled Front-End for Wideband A/D Converters” (Volume operate with preceding samples. Sampling occurs on the rising 39, April 2005) for more information at www.analog.com. In edge of the clock. general, the precise values depend on the application. Each stage of the pipeline, excluding the last, consists of a low The analog inputs of the AD9259 are not internally dc-biased. resolution flash ADC connected to a switched-capacitor DAC Therefore, in ac-coupled applications, the user must provide and an interstage residue amplifier (for example, a multiplying this bias externally. Setting the device so that V = AVDD/2 is CM digital-to-analog converter (MDAC)). The residue amplifier recommended for optimum performance, but the device can magnifies the difference between the reconstructed DAC output function over a wider range with reasonable performance, as and the flash input for the next stage in the pipeline. One bit of shown in Figure 36 and Figure 37. redundancy is used in each stage to facilitate digital correction of 90 flash errors. The last stage simply consists of a flash ADC. f = 2.3MHz IN f = 50MSPS SFDR (dBc) SAMPLE 85 The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized 80 and aligned to the frame and data clocks. 75 ANALOG INPUT CONSIDERATIONS 70 SNR (dB) The analog input to the AD9259 is a differential switched- 65 capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range 60 while maintaining excellent performance. By using an input 55 common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 36. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, fSAMPLE = 50 MSPS H C 90 PAR H VIN + x f = 30MHz IN C 85 SAMPLE SFDR (dBc) f = 50MSPS SAMPLE S S 80 S S C SAMPLE VIN – x 75 H C PAR 70 SNR (dB) H 65 Figure 35. Switched-Capacitor Input Circuit 60 The clock signal alternately switches the input circuit between 55 sample mode and hold mode (see Figure 35). When the input 50 circuit is switched to sample mode, the signal source must be 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each Figure 37. SNR/SFDR vs. Common-Mode Voltage, input can help reduce the peak transient current injected from fIN = 30 MHz, fSAMPLE = 50 MSPS the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of Rev. E | Page 19 of 52 05965-006 SNR/SFDR (dB) SNR/SFDR (dB) 05965-079 05965-078 AD9259 Data Sheet ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving C R VIN + x VIN + x and VIN − x should be matched such that common- ADC mode settling errors are symmetrical. These errors are reduced 1 2V p-p 49.9Ω C DIFF AD9259 by the common-mode rejection of the ADC. An internal R AVDD VIN – x AGND reference buffer creates the positive and negative reference C 1kΩ voltages, REFT and REFB, respectively, that define the span of 1kΩ the ADC core. The output common-mode of the reference buffer 0.1μF is set to midsupply, and the REFT and REFB voltages and span are defined as 1 C IS OPTIONAL. DIFF Figure 38. Differential Transformer-Coupled Configuration REFT = 1/2 (AVDD + VREF) for Baseband Applications REFB = 1/2 (AVDD − VREF) ADT1-1WT 2V p-p Span = 2 × (REFT − REFB) = 2 × VREF 16nH 0.1μF 16nH 1:1 Z RATIO 33Ω VIN + x 65Ω ADC It can be seen from these equations that the REFT and REFB 499Ω 2.2pF 1kΩ AD9259 16nH 33Ω voltages are symmetrical about the midsupply voltage and, by VIN – x definition, the input span is twice the value of the VREF voltage. AVDD 1kΩ Maximum SNR performance is achieved by setting the ADC to 0.1μF 1kΩ the largest span in a differential configuration. In the case of the AD9259, the largest input span available is 2 V p-p. Figure 39. Differential Transformer-Coupled Configuration for IF Applications Differential Input Configurations There are several ways to drive the AD9259 either actively or Single-Ended Input Configuration passively; however, optimum performance is achieved by driving A single-ended input may provide adequate performance in cost- the analog input differentially. For example, using the AD8332 sensitive applications. In this configuration, SFDR and distortion differential driver to drive the AD9259 provides excellent perfor- performance degrade due to the large input common-mode swing. mance and a flexible interface to the ADC (see Figure 41) for If the application requires a single-ended input configuration, baseband applications. This configuration is commonly used ensure that the source impedances on each input are well matched for medical ultrasound systems. in order to achieve the best possible performance. A full-scale input of 2 V p-p can be applied to the ADC’s VIN + x pin while For applications where SNR is a key parameter, differential the VIN − x pin is terminated. Figure 40 details a typical single- transformer coupling is the recommended input configuration ended input configuration. (see Figure 38 and Figure 39), because the noise performance of AVDD most amplifiers is not adequate to achieve the true performance C of the AD9259. R VIN + x 0.1µF 2V p-p 1kΩ Regardless of the configuration, the value of the shunt capacitor, 49.9Ω 1 ADC C DIFF C, is dependent on the input frequency and may need to be AVDD AD9259 reduced or removed. 1kΩ 25Ω R VIN – x C 0.1µF 1kΩ 1 C IS OPTIONAL. DIFF Figure 40. Single-Ended Input Configuration 0.1μF LOP VIP AVDD 10kΩ 680nH 187Ω 33Ω 0.1μF 120nH VOH INH VIN + x 1V p-p AD8332 10kΩ 1kΩ 22pF + ADC AVDD LNA VGA 68pF AD9259 10kΩ 33Ω LMD VIN – x 0.1μF VOL 187Ω 680nH 10kΩ LPF LON VIN 274Ω 18nF 0.1μF Figure 41. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter Rev. E | Page 20 of 52 05965-007 05965-008 05965-009 05965-047 Data Sheet AD9259 CLK+ input circuit supply is AVDD (1.8 V), this input is CLOCK INPUT CONSIDERATIONS designed to withstand input voltages of up to 3.3 V and For optimum performance, the AD9259 sample clock inputs therefore offers several selections for the drive logic voltage. (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins AD9510/AD9511/ AD9512/AD9513/ via a transformer or capacitors. These pins are biased internally AD9514/AD9515 0.1µF and require no additional biasing. CLK+ CLK OPTIONAL 0.1µF 1 50Ω 100Ω CLK+ CMOS DRIVER Figure 42 shows a preferred method for clocking the AD9259. The ADC low jitter clock source is converted from a single-ended signal CLK AD9259 0.1µF to a differential signal using an RF transformer. The back-to- CLK– back Schottky diodes across the secondary transformer limit 0.1µF 39kΩ clock excursions into the AD9259 to approximately 0.8 V p-p 1 50Ω RESISTOR IS OPTIONAL. differential. This helps prevent the large voltage swings of the Figure 45. Single-Ended 1.8 V CMOS Sample Clock clock from feeding through to other portions of the AD9259, and it preserves the fast rise and fall times of the signal, which AD9510/AD9511/ AD9512/AD9513/ are critical to low jitter performance. AD9514/AD9515 0.1µF CLK+ CLK OPTIONAL 0.1µF 1 100Ω ® 50Ω Mini-Circuits CLK+ CMOS DRIVER ADT1-1WT, 1:1Z 0.1µF 0.1µF ADC XFMR CLK AD9259 CLK+ CLK+ 0.1µF 0.1µF 100Ω ADC 50Ω CLK– 0.1µF AD9259 CLK– 1 50Ω RESISTOR IS OPTIONAL. SCHOTTKY 0.1µF DIODES: Figure 46. Single-Ended 3.3 V CMOS Sample Clock HSM2812 Figure 42. Transformer-Coupled Differential Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a Another option is to ac-couple a differential PECL signal to the variety of internal timing signals. As a result, these ADCs may sample clock input pins as shown in Figure 43. The AD9510/ be sensitive to the clock duty cycle. Commonly, a 5% tolerance is AD9511/AD9512/AD9513/AD9514/AD9515 of clock drivers required on the clock duty cycle to maintain dynamic performance offers excellent jitter performance. characteristics. The AD9259 contains a duty cycle stabilizer (DCS) AD9510/AD9511/ that retimes the nonsampling edge, providing an internal clock AD9512/AD9513/ AD9514/AD9515 signal with a nominal 50% duty cycle. This allows a wide range 0.1µF 0.1µF CLK+ CLK CLK+ of clock input duty cycles without affecting the performance of ADC the AD9259. When the DCS is on, noise and distortion perfor- 100Ω PECL DRIVER AD9259 0.1µF 0.1µF mance are nearly flat for a wide range of duty cycles. However, CLK– CLK– CLK 1 1 240Ω 240Ω some applications may require the DCS function to be off. If so, 50Ω 50Ω keep in mind that the dynamic range performance can be 1 50Ω RESISTORS ARE OPTIONAL. affected when operated in this mode. See the Memory Map Figure 43. Differential PECL Sample Clock section for more details on using this feature. AD9510/AD9511/ Jitter in the rising edge of the input is an important concern, and it AD9512/AD9513/ AD9514/AD9515 is not reduced by the internal stabilization circuit. The duty 0.1µF 0.1µF CLK+ CLK CLK+ cycle control loop does not function for clock rates of less than ADC 20 MHz nominal. The loop has a time constant associated with 100Ω LVDS DRIVER AD9259 0.1µF 0.1µF it that must be considered in applications where the clock rate CLK– CLK– CLK can change dynamically. This requires a wait time of 1.5 µs to 1 50Ω* 50Ω 5 µs after a dynamic clock frequency increase (or decrease) 1 50Ω RESISTORS ARE OPTIONAL before the DCS loop is relocked to the input signal. During the Figure 44. Differential LVDS Sample Clock period that the loop is not locked, the DCS loop is bypassed and the internal device timing is dependent on the duty cycle of the In some applications, it is acceptable to drive the sample clock input clock signal. In such applications, it may be appropriate to inputs with a single-ended CMOS signal. In such applications, disable the duty cycle stabilizer. In all other applications, enabling CLK+ should be driven directly from a CMOS gate, and the the DCS circuit is recommended to maximize ac performance. CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 45). Although the Rev. E | Page 21 of 52 05965-024 05965-026 05965-025 05965-028 05965-027 AD9259 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 48, the power dissipated by the AD9259 is clock input. The degradation in SNR at a given input frequency (fA) proportional to its sample rate. The digital power dissipation due only to aperture jitter (tJ) can be calculated by does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) 200 500 In this equation, the rms aperture jitter represents the root mean 180 square of all jitter sources, including the clock input, analog input AVDD CURRENT 160 450 signal, and ADC aperture jitter. IF undersampling applications 140 are particularly sensitive to jitter (see Figure 47). 120 400 The clock input should be treated as an analog signal in cases TOTAL POWER 100 where aperture jitter may affect the dynamic range of the AD9259. 80 350 Power supplies for clock drivers should be separated from the 60 ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators are 40 300 DRVDD CURRENT the best clock sources. If the clock is generated from another 20 type of source (by gating, dividing, or another method), it 0 250 10 15 20 25 30 35 40 45 50 should be retimed by the original clock during the last step. ENCODE (MSPS) Refer to the AN-501 Application Note and to the AN-756 Figure 48. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS Application Note for more in-depth information about jitter performance as it relates to ADCs at www.analog.com. 130 RMS CLOCK JITTER REQUIREMENT 120 110 100 16 BITS 90 14 BITS 80 12 BITS 70 10 BITS 60 0.125ps 50 0.25ps 0.5ps 1.0ps 40 2.0ps 30 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) Figure 47. Ideal SNR vs. Input Frequency and Jitter Rev. E | Page 22 of 52 SNR (dB) 05965-038 CURRENT (mA) POWER (mW) 05965-089 Data Sheet AD9259 By asserting the PDWN pin high, the AD9259 is placed into placed as close to the receiver as possible. If there is no far-end power-down mode. In this state, the ADC typically dissipates receiver termination or there is poor differential trace routing, 3 mW. During power-down, the LVDS output drivers are placed timing errors may result. To avoid such timing errors, it is into a high impedance state. If any of the SPI features are changed recommended that the trace length be less than 24 inches and before the power-down feature is enabled, the chip continues to that the differential output traces be close together and at equal function after PDWN is pulled low without requiring a reset. The lengths. An example of the FCO and data stream with proper AD9259 returns to normal operating mode when the PDWN pin trace length and position is shown in Figure 49. is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 2.2 μF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 μs is required to restore full operation. CH1 500mV/DIV = DCO 2.5ns/DIV CH2 500mV/DIV = DATA There are several other power-down options available when CH3 500mV/DIV = FCO using the SPI. The user can individually power down each Figure 49. LVDS Output Timing Example in ANSI-644 Mode (Default) channel or put the entire device into standby mode. The latter An example of the LVDS output using the ANSI-644 standard option allows the user to keep the internal PLL powered when (default) data eye and a time interval error (TIE) jitter histogram fast wake-up times (~600 ns) are required. See the Memory with trace lengths less than 24 inches on standard FR-4 material is Map section for more details on using these features. shown in Figure 50. Figure 51 shows an example of trace lengths Digital Outputs and Timing exceeding 24 inches on standard FR-4 material. Notice that the The AD9259 differential outputs conform to the ANSI-644 LVDS TIE jitter histogram reflects the decrease of the data eye opening standard on default power-up. This can be changed to a low power, as the edge deviates from the ideal position. It is the user’s respon- reduced signal option (similar to the IEEE 1596.3 standard) via the sibility to determine if the waveforms meet the timing budget of SDIO/ODM pin or SPI. The LVDS standard can further reduce the the design when the trace lengths exceed 24 inches. Additional SPI overall power dissipation of the device by approximately 17 mW. options allow the user to further increase the internal termination See the SDIO/ODM Pin section or Table 16 in the Memory Map (increasing the current) of all four outputs to drive longer trace section for more information. The LVDS driver current is derived lengths (see Figure 52). Even though this produces sharper rise on-chip and sets the output current at each output equal to a and fall times on the data edges and is less prone to bit errors, the nominal 3.5 mA. A 100 Ω differential termination resistor power dissipation of the DRVDD supply increases when this placed at the LVDS receiver inputs results in a nominal option is used. In addition, notice in Figure 52 that the histogram 350 mV swing at the receiver. is improved compared with that shown in Figure 51. See the Memory Map section for more details. The AD9259 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor Rev. E | Page 23 of 52 05965-045 AD9259 Data Sheet EYE: ALL BITS EYE: ALL BITS ULS: 9599/15599 500 ULS: 10000/15600 400 200 0 0 0 –200 –500 –400 –1.0ns –0.5ns 0ns 0.5ns 1.0ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 100 100 50 50 0 0 –100ps 0ps 100ps –150ps –100ps –50ps 0ps 50ps 100ps 150ps Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only EYE: ALL BITS ULS: 9600/15600 200 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section. 0 Table 8. Digital Output Coding (VIN + x) − (VIN − x), Digital Output Offset Binary Code Input Span = 2 V p-p (V) (D13 ... D0) 16383 +1.00 11 1111 1111 1111 –200 8192 0.00 10 0000 0000 0000 8191 −0.000122 01 1111 1111 1111 –1.0ns –0.5ns 0ns 0.5ns 1.0ns 0 −1.00 00 0000 0000 0000 100 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for 50 a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature. 0 –150ps –100ps –50ps 0ps 50ps 100ps 150ps Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only Rev. E | Page 24 of 52 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 05965-044 05965-043 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (V) 05965-042 Data Sheet AD9259 (DDR) capturing. The FCO is used to signal the start of a new Two output clocks are provided to assist in capturing data from output byte and is equal to the sample clock rate. See the timing the AD9259. The DCO is used to clock the output data and is diagram shown in Figure 2 for more information. equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9259 and must be captured on the rising and falling edges of the DCO that supports double data rate Table 9. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8-bit) Same Yes 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 0010 +Full-scale short 1111 1111 (8-bit) Same Yes 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0011 −Full-scale short 0000 0000 (8-bit) Same Yes 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 0100 Checkerboard 1010 1010 (8-bit) 0101 0101 (8-bit) No 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) 10 1010 1010 1010 (14-bit) 01 0101 0101 0101 (14-bit) 1 0101 PN sequence long N/A N/A Yes 1 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 (8-bit) 0000 0000 (8-bit) No 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) 11 1111 1111 1111 (14-bit) 00 0000 0000 0000 (14-bit) 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8-bit) N/A No 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 1010 1× sync 0000 1111 (8-bit) N/A No 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1011 One bit high 1000 0000 (8-bit) N/A No 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1100 Mixed frequency 1010 0011 (8-bit) N/A No 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) 1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. E | Page 25 of 52 AD9259 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° Table 10. PN Sequence increments relative to the data edge. This enables the user to Initial First Three Output Samples refine system timing margins if required. The default DCO+ Sequence Value (MSB First) and DCO− timing, as shown in Figure 2, is 90° relative to the PN Sequence Short 0x0df 0x37e4, 0x3533, 0x0063 PN Sequence Long 0x26e028 0x191f, 0x35c2, 0x2359 output data edge. An 8-, 10-, or 12-bit serial stream can also be initiated from the Consult the Memory Map section for information on how SPI. This allows the user to implement and test compatibility with to change these additional digital output timing features lower resolution systems. When changing the resolution to an through the SPI. 8-, 10-, or 12-bit serial stream, the data stream is shortened. See Figure 3 for a 12-bit example. SDIO/ODM Pin The SDIO/ODM pin is for use in applications that do not require When the SPI is used, all of the data outputs can also be SPI mode operation. This pin can enable a low power, reduced inverted from their nominal state. This is not to be confused signal option (similar to the IEEE 1596.3 reduced range link with inverting the serial stream to an LSB-first mode. In default output standard) if it and the CSB pin are tied to AVDD during mode, as shown in Figure 2, the MSB is first in the data output device power-up. This option should only be used when the serial stream. However, this can be inverted so that the LSB is digital output trace lengths are less than 2 inches from the LVDS first in the data output serial stream (see Figure 4). receiver. When this option is used, the FCO, DCO, and outputs There are 12 digital output test pattern options available that function normally, but the LVDS signal swing of all channels is can be initiated through the SPI. This is a useful feature when reduced from 350 mV p-p to 200 mV p-p, allowing the user to validating receiver capture and timing. Refer to Table 9 for the further reduce the power on the DRVDD supply. output bit sequencing options available. Some test patterns have For applications where this pin is not used, it should be tied low. two serial sequential words and can be alternated in various In this case, the device pin can be left open, and the 30 kΩ internal ways, depending on the test pattern chosen. Note that some pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. patterns do not adhere to the data format select option. In If applications require this pin to be driven from a 3.3 V logic level, addition, custom user-defined test patterns can be assigned in insert a 1 kΩ resistor in series with this pin to limit the current. the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can Table 11. Output Driver Mode Pin Settings support 8- to 14-bit word lengths to verify data capture to the Resulting Resulting receiver. Selected ODM ODM Voltage Output Standard FCO and DCO Normal 10 kΩ to AGND ANSI-644 ANSI-644 The PN sequence short pattern produces a pseudorandom bit Operation (default) (default) 9 sequence that repeats itself every 2 − 1 or 511 bits. A description ODM AVDD Low power, Low power, of the PN sequence and how it is generated can be found in reduced reduced Section 5.1 of the ITU-T 0.150 (05/96) standard. The only signal option signal option difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values). The PN sequence long pattern produces a pseudorandom bit 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9259 inverts the bit stream with relation to the ITU standard. Rev. E | Page 26 of 52 Data Sheet AD9259 SCLK/DTP Pin RBIAS Pin The SCLK/DTP pin is for use in applications that do not require To set the internal core bias current of the ADC, place a resistor SPI mode operation. This pin can enable a single digital test (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The pattern if it and the CSB pin are held high during device power- resistor current is derived on-chip and sets the AVDD current of up. When SCLK/DTP is tied to AVDD, the ADC channel the ADC to a nominal 185 mA at 50 MSPS. Therefore, it is outputs shift out the following pattern: 10 0000 0000 0000. The imperative that at least a 1% tolerance on this resistor be used to FCO and DCO function normally while all channels shift out the achieve consistent performance. repeatable test pattern. This pattern allows the user to perform Voltage Reference timing alignment adjustments among the FCO, DCO, and output A stable, accurate 0.5 V voltage reference is built into the data. For normal operation, this pin should be tied to AGND AD9259. This is gained up internally by a factor of 2, setting through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant. VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The V is set internally by default; however, the REF Table 12. Digital Test Pattern Pin Settings VREF pin can be driven externally with a 1.0 V reference to Resulting Resulting Selected DTP DTP Voltage D + x and D − x FCO and DCO improve accuracy. Normal 10 kΩ to AGND Normal Normal operation Operation operation When applying the decoupling capacitors to the VREF, REFT, DTP AVDD 10 0000 0000 Normal operation and REFB pins, use ceramic low ESR capacitors. These capacitors 0000 should be close to the ADC pins and on the same layer of the PCB as the AD9259. The recommended capacitor values and Additional and custom test patterns can also be observed when configurations for the AD9259 reference pin are shown in commanded from the SPI port. Consult the Memory Map Figure 53. section for information about the options available. Table 13. Reference Settings CSB Pin Resulting Differential The CSB pin should be tied to AVDD for applications that do Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p) not require SPI mode operation. By tying CSB high, all SCLK External AVDD N/A 2 × external and SDIO information is ignored. This pin is both 1.8 V and Reference reference 3.3 V tolerant. Internal, AGND to 0.2 V 1.0 2.0 2 V p-p FSR Rev. E | Page 27 of 52 AD9259 Data Sheet External Reference Operation Internal Reference Operation The use of an external reference may be necessary to enhance A comparator within the AD9259 detects the potential at the the gain accuracy of the ADC or to improve thermal drift SENSE pin and configures the reference. If SENSE is grounded, characteristics. Figure 56 shows the typical drift characteristics the reference amplifier switch is connected to the internal of the internal reference in 1 V mode. resistor divider (see Figure 53), setting VREF to 1 V. When the SENSE pin is tied to AVDD, the internal reference is The REFT and REFB pins establish the input span of the ADC disabled, allowing the use of an external reference. The external core from the reference configuration. The analog input full- reference is loaded with an equivalent 6 kΩ load. An internal scale range of the ADC equals twice the voltage of the reference reference buffer generates the positive and negative full-scale pin for either an internal or an external reference configuration. references, REFT and REFB, for the ADC core. Therefore, the If the reference of the AD9259 is used to drive multiple external reference must be limited to a nominal 1.0 V. converters to improve gain matching, the loading of the refer- 5 ence by the other converters must be considered. Figure 55 depicts how the internal reference voltage is affected by loading. 0 –5 VIN + x VIN – x REFT –10 0.1µF + ADC –15 0.1µF 2.2µF CORE REFB –20 0.1µF VREF –25 1µF 0.1µF 0.5V SELECT –30 LOGIC 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SENSE CURRENT LOAD (mA) Figure 55. VREF Accuracy vs. Load 0.02 0 –0.02 Figure 53. Internal Reference Configuration –0.04 –0.06 VIN + x –0.08 VIN – x REFT –0.10 0.1µF + ADC –0.12 0.1µF 2.2µF CORE REFB –0.14 EXTERNAL REFERENCE 0.1µF –0.16 VREF –0.18 1 1 1µF 0.1µF 0.5V –40 –20 0 20 40 60 80 SELECT AVDD TEMPERATURE (°C) LOGIC Figure 56. Typical VREF Drift SENSE 1 OPTIONAL. Figure 54. External Reference Operation Rev. E | Page 28 of 52 05965-010 05965-046 V ERROR (%) V ERROR (%) REF REF 05965-083 05965-084 Data Sheet AD9259 SERIAL PORT INTERFACE (SPI) In addition to the operation modes, the SPI port configuration The AD9259 serial port interface allows the user to configure the converter for specific functions or operations through a influences how the AD9259 operates. For applications that do structured register space provided in the ADC. This may not require a control port, the CSB line can be tied and held high. provide the user with additional flexibility and customization, This places the remainder of the SPI pins into their secondary depending on the application. Addresses are accessed via the modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin serial port and can be written to or read from via the port. Memory sections. CSB can also be tied low to enable 2-wire mode. When is organized into bytes that can be further divided into fields, as CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, power-up, the user should ensure that the serial port remains Interfacing to High Speed ADCs via SPI at www.analog.com. synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use a 1-, 2-, There are three pins that define the SPI: SCLK, SDIO, and CSB or 3-byte transfer exclusively. Without an active CSB line, (see Table 14). The SCLK pin is used to synchronize the read streaming mode can be entered but not exited. and write data presented to the ADC. The SDIO pin is a dual- purpose pin that allows data to be sent to and read from the In addition to word length, the instruction phase determines if internal ADC memory map registers. The CSB pin is an active the serial frame is a read or write operation, allowing the serial low control that enables or disables the read and write cycles. port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, Table 14. Serial Port Pins performing a readback causes the SDIO pin to change from an Pin Function input to an output at the appropriate point in the serial frame. SCLK Serial Clock. The serial shift clock input. SCLK is used to Data can be sent in MSB- or LSB-first mode. MSB-first mode synchronize serial interface reads and writes. is the default at power-up and can be changed by adjusting the SDIO Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on configuration register. For more information about this and the instruction sent and the relative position in the other features, see the AN-877 Application Note, Interfacing to timing frame. High Speed ADCs via SPI at www.analog.com. CSB Chip Select Bar (Active Low). This control gates the read and write cycles. HARDWARE INTERFACE The pins described in Table 14 compose the physical interface The falling edge of the CSB in conjunction with the rising edge of between the user’s programming device and the serial port of the SCLK determines the start of the framing sequence. During an the AD9259. The SCLK and CSB pins function as inputs when instruction phase, a 16-bit instruction is transmitted, followed by using the SPI. The SDIO pin is bidirectional, functioning as an one or more data bytes, which is determined by Bit Field W0 and input during write phases and as an output during readback. Bit Field W1. An example of the serial timing and its definitions can be found in Figure 58 and Table 15. During normal operation, If multiple SDIO pins share a common connection, care should CSB is used to signal to the device that SPI commands are to be be taken to ensure that proper V levels are met. Assuming the OH received and processed. When CSB is brought low, the device same load for each AD9259, Figure 57 shows the number of processes SCLK and SDIO to obtain instructions. Normally, SDIO pins that can be connected together and the resulting V OH CSB remains low until the communication cycle is complete. level. This interface is flexible enough to be controlled by either However, if connected to a slow device, CSB can be brought serial PROMS or PIC microcontrollers, providing the user with high between bytes, allowing older microcontrollers enough an alternative method, other than a full SPI controller, to time to transfer data into shift registers. CSB can be stalled program the ADC (see the AN-812 Application Note). when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instruc- tions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. Rev. E | Page 29 of 52 AD9259 Data Sheet 1.800 If the user chooses not to use the SPI, these dual-function pins 1.795 serve their secondary functions when the CSB is strapped to 1.790 1.785 AVDD during device power-up. See the Theory of Operation 1.780 section for details on which pin-strappable functions are 1.775 1.770 supported on the SPI pins. 1.765 1.760 For users who wish to operate the ADC without using the 1.755 1.750 SPI, remove any connections from the CSB, SCLK/DTP, and 1.745 SDIO/ODM pins. By disconnecting these pins from the control 1.740 bus, the ADC can function in its most basic operation. Each 1.735 1.730 of these pins has an internal termination that floats to its 1.725 respective level. 1.720 1.715 03 10 200 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 57. SDIO Pin Loading t t DS HI t t CLK H t t S t DH LO CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Timing Details Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns) Description t 5 Setup time between the data and the rising edge of SCLK DS t 2 Hold time between the data and the rising edge of SCLK DH tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK t 16 Minimum period that SCLK should be in a logic high state HI t 16 Minimum period that SCLK should be in a logic low state LO t 10 EN_SDIO Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58) tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) Rev. E | Page 30 of 52 V (V) OH 05965-093 05965-012 Data Sheet AD9259 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight Undefined memory locations should not be written to except address locations. The memory map is divided into three sections: when writing the default values suggested in this data sheet. the chip configuration register map (Address 0x00 to Address 0x02), Addresses that have values marked as 0 should be considered the device index and transfer register map (Address 0x05 and reserved and have a 0 written into their registers during power-up. Address 0xFF), and the ADC functions register map (Address 0x08 DEFAULT VALUES to Address 0x22). When the AD9259 comes out of a reset, critical registers are The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in address number, and the default value is shown in the second Table 16, where an X refers to an undefined feature. rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the LOGIC LEVELS clock register, has a default value of 0x01, meaning that Bit 7 = 0, An explanation of various registers follows: “Bit is set” is Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and synonymous with “bit is set to Logic 1” or “writing Logic 1 for Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 Logic 0” or “writing Logic 0 for the bit.” of this address followed by a 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com. Rev. E | Page 31 of 52 AD9259 Data Sheet Table 16. Memory Map Register Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Bit 7 Bit 0 (Hex) Comments Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Chip Configuration Registers 00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so that (default) 0 = off 0 = off (default) LSB- or MSB-first (default) (default) mode is set cor- rectly regardless of shift mode. 8-bit Chip ID Bits [7:0] Default is unique 01 chip_id 0x04 (AD9259 = 0x04), (default) chip ID. This is a read-only register. 02 chip_grade X Child ID [6:4] X X X X Child ID used to (identify device variants of Chip ID) differentiate 100 = 50 MSPS graded devices. This is a read- only register. Device Index and Transfer Registers 05 device_index_A X X Clock Clock Data Data Data Data 0x0F Bits are set to channel channel Channel Channel Channel Channel determine which A on-chip device DCO FCO D C B 1 = on receives the next 1 = on 1 = on 1 = on 1 = on 1 = on (default) write command. 0 = off 0 = off (default) (default) (default) (default) (default) 0 = off 0 = off 0 = off 0 = off FF device_update X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the master 0 = off shift register to (default) the slave. ADC Functions Internal power-down mode Determines 08 modes X X X X X 0x00 000 = chip run (default) various generic 001 = full power-down modes of chip 010 = standby operation. 011 = reset 09 clock X X X X X X X Duty 0x01 Turns the cycle internal duty stabilizer cycle stabilizer 1 = on on and off. (default) 0 = off 0D test_io User test mode Reset PN Reset Output test mode—see Table 9 in the 0x00 When this reg- 00 = off (default) long gen PN short Digital Outputs and Timing section ister is set, the 01 = on, single alternate 1 = on gen 0000 = off (default) test data is placed 10 = on, single once 0 = off 1 = on 0001 = midscale short on the output 11 = on, alternate once (default) 0 = off 0010 = +FS short pins in place of (default) 0011 = −FS short normal data. 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1-/0-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) Rev. E | Page 32 of 52 Data Sheet AD9259 Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos format of the 1 = LVDS 0 = off complement data. low power (default) (IEEE 1596.3 similar) 15 output_adjust X X Output driver X X X X 0x00 Determines termination LVDS or other 00 = none (default) output properties. 01 = 200 Ω Primarily func- 10 = 100 Ω tions to set the 11 = 100 Ω LVDS span and common-mode levels in place of an external resistor. 16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) utilize global 0000 = 0° relative to data edge clock divide, 0001 = 60° relative to data edge determines 0010 = 120° relative to data edge which phase of 0011 = 180° relative to data edge (default) the divider 0101 = 300° relative to data edge output is used to 0110 = 360° relative to data edge supply the 1000 = 480° relative to data edge output clock. 1001 = 540° relative to data edge Internal latching 1010 = 600° relative to data edge is unaffected. 1011 to 1111 = 660° relative to data edge 19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 21 serial_control LSB first X X X <10 000 = 14 bits (default, normal bit 0x00 Serial stream 1 = on MSPS, stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native rate 011 = 12 bits bit stream 100 = 14 bits (global). mode 1 = on 0 = off (default) 22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) Rev. E | Page 33 of 52 AD9259 Data Sheet Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9259, it is recommended It is required that the exposed paddle on the underside of the that two separate 1.8 V supplies be used: one for analog (AVDD) ADC be connected to analog ground (AGND) to achieve the and one for digital (DRVDD). If only one supply is available, it best electrical and thermal performance of the AD9259. An should be routed to the AVDD first and then tapped off and exposed continuous copper plane on the PCB should mate to isolated with a ferrite bead or a filter choke preceded by the AD9259 exposed paddle, Pin 0. The copper plane should decoupling capacitors for the DRVDD. The user can employ have several vias to achieve the lowest possible resistive thermal several different decoupling capacitors to cover both high and path for heat dissipation to flow through the bottom of the PCB. low frequencies. These should be located close to the point of These vias should be solder-filled or plugged. entry at the PC board level and close to the parts, with minimal To maximize the coverage and adhesion between the ADC and trace lengths. PCB, partition the continuous copper plane by overlaying a A single PC board ground plane should be sufficient when silkscreen on the PCB into several uniform sections. This provides using the AD9259. With proper decoupling and smart parti- several tie points between the ADC and PCB during the reflow tioning of the PC board’s analog, digital, and clock sections, process, whereas using one continuous plane with no partitions optimum performance can be easily achieved. only guarantees one tie point. See Figure 59 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR Figure 59. Typical PCB Layout Rev. E | Page 34 of 52 05965-013 Data Sheet AD9259 EVALUATION BOARD board individually. Use P501 to connect a different supply for The AD9259 evaluation board provides all of the support cir- each section. At least one 1.8 V supply is needed for AVDD_DUT cuitry required to operate the ADC in its various modes and and DRVDD_DUT; however, it is recommended that separate configurations. The converter can be driven differentially using a supplies be used for analog and digital signals and that each transformer (default) or a AD8332 driver. The ADC can also be supply have a current capability of 1 A. To operate the evaluation driven in a single-ended fashion. Separate power pins are provided board using the VGA option, a separate 5.0 V analog supply to isolate the DUT from the drive circuitry of the AD8332. Each (AVDD_5 V) is needed. To operate the evaluation board using input configuration can be selected by changing the connection the SPI and alternate clock options, a separate 3.3 V analog of various jumpers (see Figure 62 to Figure 66). Figure 60 shows supply (AVDD_3.3 V) is needed in addition to the other the typical bench characterization setup used to evaluate the ac supplies. performance of the AD9259. It is critical that the signal sources used for the analog input and clock have very low phase noise INPUT SIGNALS (<1 ps rms jitter) to realize the optimum performance of the When connecting the clock and analog source to the evaluation converter. Proper filtering of the analog input signal to remove board, use clean signal generators with low phase noise, such as harmonics and lower the integrated or broadband noise at the Rohde & Schwarz SMA or HP8644 signal generators or the input is also necessary to achieve the specified noise performance. equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable. See Figure 62 to Figure 70 for the complete schematics and Enter the desired frequency and amplitude from the ADC speci- fications tables. Typically, most Analog Devices, Inc., evaluation layout diagrams demonstrating the routing and grounding boards can accept approximately 2.8 V p-p or 13 dBm sine wave techniques that should be applied at the system level. input for the clock. When connecting the analog input source, it POWER SUPPLIES is recommended to use a multipole, narrow-band, band-pass This evaluation board has a wall-mountable switching power filter with 50 Ω terminations. Good choices of such band-pass supply that provides a 6 V, 2 A maximum output. Connect the filters are available from TTE, Allen Avionics, and K&L supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to Microwave, Inc. The filter should be connected directly to the 63 Hz. The other end of the supply is a 2.1 mm inner diameter evaluation board if possible. jack that connects to the PCB at P503. Once on the PC board, OUTPUT SIGNALS the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias The default setup uses the Analog Devices HSC-ADC-FIFO5- to each of the various sections on the board. INTZ to interface with the Analog Devices standard dual- channel FIFO data capture board (HCS-ADC-EVALCZ). Two When operating the evaluation board in a nondefault condition, of the eight channels can be evaluated at the same time. For L504 to L507 can be removed to disconnect the switching more information on the channel settings and optional settings power supply. This enables the user to bias each section of the of these boards, visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX 3.3V 5.0V 1.8V 1.8V 3.3V – + – + – + – + – + SWITCHING POWER SUPPLY PC RUNNING ADC ROHDE & SCHWARZ, ANALYZER INTERPOSER HSC-ADC-EVALCZ SMA, AND SPI BAND-PASS FIFO DATA XFMR BOARD 2V p-p SIGNAL USER CAPTURE FILTER INPUT AD9259 SOFTWARE SYNTHESIZER BOARD EVALUATION BOARD CH A TO CH D 14-BIT ROHDE & SCHWARZ, USB SERIAL CLK CONNECTION SMA, LVDS 2V p-p SIGNAL SYNTHESIZER SPI SPI SPI SPI Figure 60. Evaluation Board Connection Rev. E | Page 35 of 52 GND AVDD_5V GND AVDD_DUT GND DRVDD_DUT GND AVDD_3.3V GND VCC 05965-014 AD9259 Data Sheet DEFAULT OPERATION AND JUMPER SELECTION A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and SETTINGS R227 with 0 Ω resistors and remove R217 and R218 to The following is a list of the default and optional settings or disconnect the default clock path inputs. In addition, populate modes allowed on the AD9259 Rev. A evaluation board. C207 and C208 with a 0.1 μF capacitor and remove C210 and  POWER: Connect the switching power supply that is C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a provided in the evaluation kit between a rated 100 V ac to default mode of operation. Consult the AD9515 data sheet 240 V ac wall outlet at 47 Hz to 63 Hz and P503. for more information about these and other options.  AIN: The evaluation board is set up for a transformer- In addition, an on-board oscillator is available on the OSC201 coupled analog input with an optimum 50 Ω impedance and can act as the primary clock source. The setup is quick match of 200 MHz of bandwidth (see Figure 61). For more and involves installing R212 with a 0 Ω resistor and setting bandwidth response, the differential capacitor across the the enable jumper (J205) to the on position. If the user wishes analog inputs can be changed or removed. The common to employ a different oscillator, two oscillator footprint options mode of the analog inputs is developed from the center are available (OSC201) to check the ADC performance. tap of the transformer or AVDD_DUT/2. 0  PDWN: To enable the power-down feature, short J201 to AVDD on the PDWN pin. –2 –3dB CUTOFF = 200MHz –4  SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during –6 device power-up, Test Pattern 10 0000 0000 0000 is enabled. –8 See the SCLK/DTP Pin section for details. –10  SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output –12 standard), use J203. If J203 is tied to AVDD during device –14 power-up, it enables the LVDS outputs in a low power, –16 reduced signal option from the default ANSI-644 standard. 0 50 100 150 200 250 300 350 400 450 500 This option changes the signal swing from 350 mV p-p to FREQUENCY (MHz) 200 mV p-p, reducing the power of the DRVDD supply. See Figure 61. Evaluation Board Full-Power Bandwidth the SDIO/ODM Pin section for more details.  VREF: VREF is set to 1.0 V by tying the SENSE pin to  CSB: To enable processing of the SPI information on the ground, R237. This causes the ADC to operate in 2.0 V p-p SDIO and SCLK pins, tie J202 low in the always enable full-scale range. A separate external reference option using mode. To ignore the SDIO and SCLK information, tie J202 the ADR510 is also included on the evaluation board. to AVDD. Populate R231 and R235 and remove C214. Proper use of the VREF options is noted in the Voltage Reference section.  Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove Jumpers J202, J203, and J204.  RBIAS: RBIAS has a default setting of 10 kΩ (R201) to This disconnects the CSB, SCLK/DTP, and SDIO/ODM ground and is used to set the ADC core bias current. pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination  CLOCK: The default clock input circuitry is derived from a and will float to its respective level. simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very  D + x, D − x: If an alternative data capture method to the setup low amount of jitter to the clock path. The clock input is shown in Figure 60 is used, optional receiver terminations, 50 Ω terminated and ac-coupled to handle single-ended R206 to R211, can be installed next to the high speed back- sine wave types of inputs. The transformer converts the plane connector. single-ended input to a differential signal that is clipped before entering the ADC clock inputs. Rev. E | Page 36 of 52 AMPLITUDE (dBFS) 05965-088 Data Sheet AD9259 ALTERNATIVE ANALOG INPUT DRIVE • Populate R101, R114, R127, and R140 with 0 Ω resistors in CONFIGURATION the analog input path. The following is a brief description of the alternative analog input • Populate R105, R113, R118, R124, R131, R137, R151, and drive configuration using the AD8332 dual VGA. If this drive R160 with 0 Ω resistors in the analog input path to connect option is in use, some components may need to be populated, in the AD8332. which case all the necessary components are listed in Table 17. For more details on the AD8332 dual VGA, including how it works • Populate R152, R153, R154, R155, R156, R157, R158, R159, and its optional pin settings, consult the AD8332 data sheet. C103, C105, C110, C112, C117, C119, C124, and C126 with 10 kΩ resistors to provide an input common-mode To configure the analog input to drive the VGA instead of the level to the ADC analog inputs. default transformer option, the following components need to be removed and/or changed. • Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. • Remove R102, R115, R128, R141, R161, R162, R163, R164, T101, T102, T103, and T104 in the default analog input path. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev. E | Page 37 of 52 AD9259 Data Sheet AVDD_DUT R105 DNP R152 CH_A DNP C101 FB102 R108 R104 P102 T101 0.1µF 10Ω 33Ω VGA INPUT CONNECTION 0Ω DNP 1 6 VIN_A INH1 AIN R106 CHANNEL A DNP R101 R161 2 5 P101 R109 CM1 C103 C104 DNP CM1 499Ω 1kΩ 3 4 DNP 2.2pF AIN R107 FB101 R113 R103 C102 DNP 10Ω DNP R102 0Ω 0.1µF VIN_A CH_A 64.9Ω FB103 R110 C105 CM1 R156 10Ω 33Ω DNP DNP E101 AVDD_DUT C106 R111 DNP C107 R112 AVDD_DUT 1kΩ 0.1µF 1kΩ AVDD_DUT R118 VGA INPUT CONNECTION DNP R153 INH2 CH_B DNP CHANNEL B R114 FB105 R121 P103 T102 DNP 10Ω 33Ω 1 6 AIN VIN_B FB104 R119 R115 C108 10Ω DNP 64.9Ω 0.1µF R162 2 5 R123 P104 C110 C111 CM2 CM2 499Ω 1kΩ DNP 3 4 DNP 2.2pF R120 R116 R124 AIN C109 DNP 0Ω DNP 0.1µF VIN_B R117 CH_B 0Ω FB106 R122 C112 CM2 R157 10Ω 33Ω DNP DNP E102 AVDD_DUT C113 R125 DNP C114 R126 AVDD_DUT 1kΩ 0.1µF 1kΩ AVDD_DUT R131 DNP R154 CH_C DNP C115 FB108 R134 P106 R130 T103 0.1µF 10Ω 33Ω DNP 0Ω VGA INPUT CONNECTION 1 6 VIN_C INH3 AIN R132 CHANNEL C DNP R127 R163 P105 2 5 R135 C117 C118 CM3 DNP CM3 499Ω 1kΩ 3 4 DNP 2.2pF AIN R133 R137 FB107 R129 C116 DNP DNP R128 10Ω 0Ω 0.1µF CH_C VIN_C 64.9Ω FB109 R136 C119 CM3 R158 10Ω 33Ω DNP DNP E103 AVDD_DUT C120 R138 DNP C121 R139 AVDD_DUT 1kΩ 0.1µF 1kΩ AVDD_DUT R151 VGA INPUT CONNECTION DNP R155 INH4 CH_D DNP CHANNEL D R140 FB111 R146 P107 T104 DNP 10Ω 33Ω 1 6 AIN VIN_D FB110 R141 R144 C122 10Ω 64.9Ω DNP 0.1µF R164 2 5 R148 C124 C125 P108 CM4 CM4 499Ω 1kΩ 3 4 DNP 2.2pF DNP R145 R143 R160 AIN C123 DNP 0Ω DNP R142 0.1µF VIN_D CH_D 0Ω FB112 R147 C126 CM4 R159 10Ω 33Ω DNP DNP E104 AVDD_DUT C127 R149 DNP C128 R150 AVDD_DUT 1kΩ 0.1µF 1kΩ DNP: DO NOT POPULATE Figure 62. Evaluation Board Schematic, DUT Analog Inputs Rev. E | Page 38 of 52 05965-015 2 Data Sheet AD9259 AVDD_DUT CW 2 2 2 1 Figure 63. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface Rev. E | Page 39 of 52 REFERENCE CIRCUIT OPTIONAL REF EXT AVDD_DUT U203 VREF SELECT VSENSE_DUT ADR510 R229 R231 VREF_DUT R234 1V 4.99kΩ DNP DNP DNP VREF = 0.5V TRIM/NC V+ R232 R235 DNP DNP DNP DNP VREF = EXTERNAL R230 R201 C212 R228 10kΩ R236 10kΩ 0.1µF C214 DNP VREF = 0.5V(1+R232/R233) 470kΩ DNP 1µF C213 R233 0.1µF R237 DNP VREF = 1V 0Ω AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF DD_DUT AVDD_DUT AV AVDD_DUT AVDD_DUT VIN_A VIN_D VIN_A N ENABLE VIN_D PWD AVDD_DUT AVDD_DUT ALWAYS ENABLE SPI AVDD_DUT J203 1 3 CLK AVDD_DUT J204 1 AVDD_DUT 3 AVDD_DUT DTP ENABLE SCLK_DTP ND GND G DRVDD_DUT DRVDD_DUT R222 4.12kΩ R225 2 R226 0Ω 49.9Ω 3 DNP DNP 5 NC = NO CONNECT R227 0Ω R239 R238 DNP 10kΩ DNP R217 R223 0Ω 0Ω CLIP SINE OUT (DEFAULT) R218 R224 C206 0Ω 0Ω 0.1µF DNP: DO NOT POPULATE DIGITAL OUTPUTS C204 REFERENCE 0.1µF DECOUPLING P202 GNDCD10 60 C202 C203 DCO C10 D10 R206 DCO 2.2µF 0.1µF 40 GNDCD9 50 DNP 59 R207 FCO C9 D9 FCO DNP 39 GNDCD8 C201 49 0.1µF 58 D8 CHA C8 CHA R208 38 GNDCD7 48 DNP 57 CHB D7 CHB R209 C7 37 GNDCD6 47 DNP U201 56 CHC C6 D6 CHC R210 1 36 36 GNDCD5 46 DNP AVDD AVDD 55 2 35 R202 AVDD AVDD 100kΩ CHD C5 D5 CHD R211 3 34 VIN – D VIN – A 35 GNDCD4 45 DNP J201 1 3 4 33 54 VIN + D VIN + A D4 C4 5 32 AVDD AVDD 44 34 GNDCD3 J202 1 R244 R245 6 31 3 AVDD AD9259 LFCSP PDWN 53 DNP 0Ω CSB_DUT 730 C3 D3 AVDD_3.3V CLK CLK– CSB 43 33 GNDCD2 S0 8 29 CLK+ SDIO/ODM ODM ENABLE R246 R247 R256 R257 52 9 28 SDIO_ODM AVDD SCLK/DTP C2 D2 DNP 0Ω DNP 0Ω 32 42 GNDCD1 AVDD_3.3V AVDD_3.3V 10 27 AVDD AVDD S1 S6 51 11 26 DRGND DRGND R248 R249 R258 R259 C1 D1 41 31 GNDAB10 12 25 DNP 0Ω DNP 0Ω DRVDD DRVDD AVDD_3.3V AVDD_3.3V 30 S7 C10 S2 B10 20 10 GNDAB9 R250 R251 R260 R261 DNP 0Ω DNP 0Ω 29 AVDD_3.3V AVDD_3.3V B9 A9 19 S3 S8 9 GNDAB8 R252 R253 R262 R263 28 DNP 0Ω DNP 0Ω A8 B8 AVDD_3.3V AVDD_3.3V 8 GNDAB7 18 S4 S9 AVDD_3.3V 27 R254 R255 R264 R265 A7 B7 DNP 0Ω DNP 0Ω 7 GNDAB6 17 AVDD_3.3V AVDD_3.3V C224 26 S5 S10 0.1µF B6 A6 R214 6 16 GNDAB5 10kΩ OPTIONAL CLOCK DRIVE CIRCUIT OPTIONAL CLOCK 25 OSCILLATOR B5 A5 SCLK_CHB SCLK_CHA ENABLE 5 GNDAB4 15 AVDD_3.3V AVDD_3.3V 2 AVDD_3.3V J205 24 OSC201 C207 B4 SDI_CHB A4 SDI_CHA 14 1 DISABLE 4 GNDAB3 VCC OE 0.1µF 14 R219 R220 R221 DNP 12 3 23 VCC' OE' R215 U202 DNP DNP 10kΩ A3 B3 CLK CSB3__CHB CSB1_CHA 10 5 10kΩ GNDAB2 OUT'GND' 3 13 GND_PAD OPT_CLK ENCODE C208 8 7 R242 OUT GND 22 LVPECL OUTPUT 0.1µF 23 100Ω INPUT B2 CSB4_CHB A2 CSB2_CHA OUT0 VFAC3H-L CLK DNP GNDAB1 12 2 22 R212 AD9515 CLK CLKB OUT0B 21 0Ω SIGNAL = AVDD_3.3V; 4, SDO_CHB OPT_CLK R240 R241 A1 B1 SDO_CHA DNP 17,20, 21, 24, 26, 29, 30 1 243Ω 243Ω 11 19 SYNCB OUT1 SIGNAL = DNC;27,28 HEADER 6469169-1 18 1 OUT1B P201 OPT_CLK E202 C209 R205 TO R211 ENC R243 0.1µF OPTIONAL OUTPUT LVDS OUTPUT AVDD_3.3V C205 DNP 100Ω R213 TERMINATIONS 0.1µF 1 1 49.9kΩ E203 E201 CLOCK CIRCUIT S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C215 T201 CLK 0.1µF OPT_CLK P203 CR201 3 4 C210 DNP C217 C218 C219 C220 C221 C222 C223 HSMS2812 ENC 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DNP 2 5 R216 C216 0.1µF 0Ω 1 6 CLK C211 0.1µF 05965-016 13 D – D CHD 48 VIN – C VIN_C 14 CHD D + D 47 VIN_C VIN + C 15 D – C CHC 46 AVDD AVDD_DUT 16 D + C CHC 45 AVDD AVDD_DUT 17 D – B CHB 44 REFT 18 D + B CHB 43 REFB 19 D – A CHA 42 VREF VREF_DUT 20 D + A CHA 41 SENSE VSENSE_DUT 21 FCO– FCO 40 RBIAS 22 FCO FCO+ 39 AVDD AVDD_DUT 23 DCO– DCO 38 VIN + B VIN_B 24 DCO+ DCO 37 VIN_B VIN – B 6 VREF 7 32 S10 RSET R203 R266 8 S9 100kΩ 100kΩ - DNP 9 1 S8 VS R267 10 R204 S7 100kΩ 100kΩ - DNP 11 31 S6 GND 2 V– 12 S5 3 13 33 R205 S4 10kΩ 1 14 S3 15 S2 16 S1 25 S0 JP301 1 2 AD9259 Data Sheet POPULATE L301 TO L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. R301 R302 EXTERNAL VARIABLE GAIN DRIVE DNP DNP VG C301 C302 VARIABLE GAIN CIRCUIT L301 DNP L302 L303 DNP L304 (0V TO 1.0V DC) 0Ω 0Ω 0Ω 0Ω VG GND CW AVDD_5V C303 C304 L307 L305 DNP L306 DNP L308 R320 R319 0Ω 0Ω 0Ω 0Ω 39kΩ 10kΩ R303 R304 DNP DNP C305 C306 C307 C308 0.1µF 0.1µF 0.1µF 0.1µF R306 R305 R311 C309 374Ω 374Ω 10kΩ 1000pF C310 DNP R307 R308 R309 R310 0.1µF 187Ω 187Ω 187Ω 187Ω R312 U301 10kΩ 25 R313 R314 ENBV RCLMP 16 26 10kΩ 10kΩ VG ENBL GAIN DNP 27 15 DNP MODE HILO 14 28 VCM1 VCM2 29 13 AD8332 VIN1 VIN2 30 12 VIP2 VIP1 11 31 C311 C313 COM1 COM2 0.1µF 32 10 0.1µF LOP2 LOP1 9 C312 C314 0.1µF 0.1µF R316 C320 R317 274Ω 0.1µF C321 R315 C315 C316 274Ω C325 C326 R318 0.1µF 10kΩ 10µF 0.1µF 0.1µF 10µF 10kΩ C317 0.018µF C322 0.018µF C318 C323 22pF 22pF L309 L310 120nH 120nH C319 C324 0.1µF 0.1µF DNP: DO NOT POPULATE INH4 INH3 Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit Rev. E | Page 40 of 52 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL C AND CHANNEL D HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V AVDD_5V POWER DOWN ENABLE (0V TO 1V = DISABLE POWER) CH_D 1 LON1 24 2 COMM AVDD_5V VPS1 23 3 VOH1 INH1 22 VOL1 CH_D 21 4 VPSV AVDD_5V LMD1 5 LMD2 20 NC 19 6 CH_C VOL2 INH2 18 7 VOH2 VPS2 AVDD_5V 17 8 LON2 COMM CH_C AVDD_5V RCLAMP PIN HILO PIN = LO = ±50mV HILO PIN = H = ±75mV MODE PIN POSITIVE GAIN SLOPE = 0V TO 1.0V NEGATIVE GAIN SLOPE = 2.25V TO 5.0V 05965-017 Data Sheet AD9259 J401 PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 9 10 OPTIONAL PIC PROGRAMMING HEADER Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued) Rev. E | Page 41 of 52 R401 R402 DNP DNP C401 C402 DNP L401 DNP L402 L403 L404 0Ω 0Ω 0Ω 0Ω C403 C404 SPI CIRCUITRY FROM FIFO L406 L407 L405 DNP DNP L408 0Ω 0Ω 0Ω 0Ω R403 R404 DNP DNP +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V REMOVE WHEN USING C405 C406 C407 C408 OR PROGRAMMING PIC (U402) AVDD_3.3V AVDD_5V 0.1µF 0.1µF 0.1µF 0.1µF R406 R405 J402 C411 R413 374Ω 374Ω 1000pF 10kΩ AVDD_3.3V C412 C427 DNP R407 R408 R409 R410 0.1µF 0.1µF U402 187Ω 187Ω 187Ω 187Ω R433 8 R421 1 VDD VSS 1kΩ 0Ω, DNP 2 7 R411 U401 GP5 GP0 3 6 10kΩ GP4 GP1 S401 R422 25 1 3 MCLR/ R412 RCLMP R424 0Ω, DNP ENBV 4 5 GP2 26 16 10kΩ 2 4 GP3 10kΩ ENBL GAIN VG SDIO_ODM DNP 15 R423 27 DNP PIC12F629 HILO MODE RESET/REPROGRAM 0Ω, DNP 28 14 AVDD_DUT VCM1 VCM2 R419 29 13 261Ω AD8332 VIN1 VIN2 30 12 VIP2 R432 VIP1 CR401 31 11 R431 NC7WZ07 C409 C423 1kΩ COM1 COM2 1kΩ 10 0.1µF 32 0.1µF 1 A1 Y1 6 LOP2 LOP1 9 2 5 GND VCC AVDD_DUT R425 3 A2 Y2 4 C410 C424 10kΩ 0.1µF 0.1µF C429 E401 U403 0.1µF R415 C416 274Ω 0.1µF C417 NC7WZ16 R414 C413 C414 C425 C426 R417 0.1µF 0.1µF 10kΩ 10µF 0.1µF 10µF 10kΩ 1 A1 Y1 6 C415 SCLK_DTP 0.018µF 2 5 GND VCC AVDD_DUT 3 A2 Y2 4 CSB_DUT R430 R429 C428 C421 U404 C418 10kΩ 10kΩ 0.1µF 22pF 22pF L409 L410 120nH 120nH C419 C422 0.1µF 0.1µF INH2 INH1 DNP: DO NOT POPULATE 05965-018 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0V TO 1.0V AVDD_5V POWER DOWN ENABLE (0V TO 1V = DISABLE POWER) CH_B 1 LON1 24 2 COMM AVDD_5V VPS1 23 3 VOH1 INH1 22 VOL1 CH_B 21 4 LMD1 VPSV AVDD_5V 5 LMD2 20 NC 19 6 CH_A VOL2 INH2 18 7 VOH2 AVDD_5V VPS2 17 8 COMM LON2 R416 C420 274Ω 0.018µF CH_A POPULATE L401 TO L408 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. AVDD_5V MODE PIN RCLAMP PIN POSITIVE GAIN SLOPE = 0V TO 1.0V HILO PIN = LO = ±50mV NEGATIVE GAIN SLOPE = 2.25V-5.0V HILO PIN = H = ±75mV R418 4.75kΩ R426 0Ω CSB1_CHA R428 0Ω SCLK_CHA R420 0Ω SDI_CHA R427 0Ω SDO_CHA AD9259 Data Sheet Figure 66. Evaluation Board Schematic, Power Supply Inputs Rev. E | Page 42 of 52 D502 3A POWER SUPPLY INPUT SHOT_RECT 6V, 2V MAXIMUM F501 DO-214AB FER501 PWR_IN P503 1 2 SMDC110F 1 4 3 CR501 + D501 C501 CHOKE_COIL 2 S2A_RECT 10µF 2A R501 3 DO-214AA 261Ω OPTIONAL POWER INPUT DECOUPLING CAPACITORS L503 P501 10µH 5V_AVDD 1 P1 AVDD_5V +5.0V AVDD_5V 2 P2 C502 C518 C519 C520 C521 C522 C523 DUT_AVDD 10µF C503 3 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF P3 0.1µF 4 P4 3.3V_AVDD L502 5 P5 10µH 6 AVDD_DUT P6 AVDD_DUT +1.8V DUT_DRVDD 7 P7 C504 C526 C527 C528 C529 C530 C531 C505 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 8 P8 0.1µF L508 10µH AVDD_3.3V AVDD_3.3V +3.3V C508 C524 C525 C509 10µF 0.1µF 0.1µF 0.1µF L501 H1 H3 10µH DRVDD_DUT +1.8V DRVDD_DUT C506 C516 C517 H2 H4 C507 10µF 0.1µF 0.1µF 0.1µF MOUNTING HOLES CONNECTED TO GROUND U501 U502 L505 L506 ADP3339AKC-1.8 ADP3339AKC-3.3 10µH 10µH 3 2 3 2 PWR_IN INPUT OUTPUT1 DUT_AVDD PWR_IN INPUT OUTPUT1 3.3V_AVDD 4 4 OUTPUT4 OUTPUT4 C514 C532 C515 C533 1µF 1µF 1µF 1µF U503 U504 L504 L507 ADP3339AKC-1.8 ADP3339AKC-5 10µH 10µH 2 3 2 3 PWR_IN OUTPUT1 DUT_DRVDD PWR_IN OUTPUT1 5V_AVDD INPUT INPUT 4 4 OUTPUT4 OUTPUT4 C534 C512 C513 C535 1µF 1µF 1µF 1µF DNP: DO NOT POPULATE 05965-019 1 1 GND GND 1 1 GND GND Data Sheet AD9259 Figure 67. Evaluation Board Layout, Primary Side Rev. E | Page 43 of 52 05965-020 AD9259 Data Sheet Figure 68. Evaluation Board Layout, Ground Plane Rev. E | Page 44 of 52 05965-021 Data Sheet AD9259 Figure 69. Evaluation Board Layout, Power Plane Rev. E | Page 45 of 52 05965-022 AD9259 Data Sheet Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. E | Page 46 of 52 05965-023 Data Sheet AD9259 1 Table 17. Evaluation Board Bill of Materials (BOM) Manufacturer’s Item Qty. Reference Designator Device Package Value Manufacturer Part Number 1 1 AD9259LFCSP_REVA PCB PCB PCB 2 75 C101, C102, C107, Capacitor 402 0.1 μF, ceramic, Murata GRM155R71C104KA88D C108, C109, C114, X5R, 10 V, 10% tol C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 3 4 C104, C111, C118, Capacitor 402 2.2 pF, ceramic, Murata GRM1555C1H2R2GZ01B C125 COG, 0.25 pF tol, 50 V 4 4 C315, C326, C413, Capacitor 805 10 μF, 6.3 V ±10% Murata GRM219R60J106KE19D C426 ceramic, X5R 5 1 C202 Capacitor 603 2.2 μF, ceramic, Murata GRM188C70J225KE20D X5R, 6.3 V, 10% tol 6 2 C309, C411 Capacitor 402 1000 pF, ceramic, Murata GRM155R71H102KA01D X7R, 25 V, 10% tol 7 4 C317, C322, C415, Capacitor 402 0.018 μF, ceramic, AVX 0402YC183KAT2A C420 X7R, 16 V, 10% tol 8 4 C318, C323, C418, Capacitor 402 22 pF, ceramic, Murata GRM1555C1H220JZ01D C421 NPO, 5% tol, 50 V 9 1 C501 Capacitor 1206 10 μF, tantalum, Rohm TCA1C106M8R 16 V, 20% tol 10 9 C214, C512, C513, Capacitor 603 1 μF, ceramic, X5R, Murata GRM188R61C105KA93D C514, C515, C532, 6.3 V, 10% tol C533, C534, C535 11 8 C305, C306, C307, Capacitor 805 0.1 μF, ceramic, Murata GRM21BR71H104KA01L C308, C405, C406, X7R, 50 V, 10% tol C407, C408 12 4 C502, C504, C506, Capacitor 603 10 μF, ceramic, Murata GRM188R60J106M C508 X5R, 6.3 V, 20% tol 13 1 CR201 Diode SOT-23 30 V, 20 mA, dual Agilent HSMS2812-TRIG Schottky Technologies 14 2 CR401, CR501 LED 603 Green, 4 V, 5 m Panasonic LNJ314G8TRA candela 15 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro SK33-TP Commercial Co. 16 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro S2A-TP Commercial Co. Rev. E | Page 47 of 52 AD9259 Data Sheet Manufacturer’s Item Qty. Reference Designator Device Package Value Manufacturer Part Number 17 1 F501 Fuse 1210 6.0 V, 2.2 A trip- Tyco/Raychem NANOSMDC110F-2 current resettable fuse 18 1 FER501 Choke coil 2020 10 μH, 5 A, 50 V, Murata DLW5BSN191SQ2L 190 Ω @ 100 MHz 19 12 FB101, FB102, FB103, Ferrite bead 603 10 Ω, test freq Murata BLM18BA100SN1B FB104, FB105, FB106, 100 MHz, 25% tol, FB107, FB108, FB109, 500 mA FB110, FB111, FB112 20 1 JP301 Connector 2-pin 100 mil header Samtec TSW-102-07-G-S jumper, 2-pin 21 2 J205, J402 Connector 3-pin 100 mil header Samtec TSW-103-07-G-S jumper, 3-pin 22 4 J201 to J204 Connector 12-pin 100 mil header Samtec TSW-104-08-G-T male, 4 × 3 triple row straight 23 1 J401 Connector 10-pin 100 mil header, Samtec TSW-105-08-G-D male, 2 × 5 double row straight 24 8 L501, L502, L503, L504, Ferrite bead 1210 10 μH, bead core Murata BLM31PG500SN1L 3.2 × 2.5 × 1.6 L505, L506, L507, L508 SMD, 2 A 25 4 L309, L310, L409, L410 Inductor 402 120 nH, test freq Murata LQG15HNR12J02B 100 MHz, 5% tol, 150 mA 26 16 L301, L302, L303, L304, Resistor 805 0 Ω, 1/8 W, 5% tol NIC NRC10ZOTRF L305, L306, L307, L308, Components L401, L402, L403, L404, L405, L406, L407, L408 27 1 OSC201 Oscillator SMT Clock oscillator, Valpey Fisher VFAC3H-L-50MHz 50.00 MHz, 3.3 V 28 5 P101, P103, P105, Connector SMA Side-mount SMA Johnson 142-0710-851 P107, P201 for 0.063" board Components thickness 29 1 P202 Connector Header 1469169-1, right Tyco 6469169-1 angle 2-pair, 25 mm, header assembly 30 1 P503 Connector 0.1", PCMT SC1153, power Switchcraft RAPC722X supply connector 31 15 R201, R205, R214, Resistor 402 10 kΩ, 1/16 W, NIC NRC04J103TRF R215, R221, R239, 5% tol Components R312, R315, R318, R411, R414, R417, R425, R429, R430 32 14 R103, R117, R129, Resistor 402 0 Ω, 1/16 W, NIC NRC04Z0TRF R142, R216, R217, 5% tol Components R218, R223, R224, R237, R420, R426, R427, R428 33 4 R102, R115, R128, Resistor 402 64.9 Ω, 1/16 W, NIC NRC04F64R9TRF R141 1% tol Components 34 4 R104, R116, R130, Resistor 603 0 Ω, 1/10 W, NIC NRC06Z0TRF R143 5% tol Components Rev. E | Page 48 of 52 Data Sheet AD9259 Manufacturer’s Item Qty. Reference Designator Device Package Value Manufacturer Part Number 35 15 R109, R111, R112, Resistor 402 1 kΩ, 1/16 W, NIC NRC04F1001TRF R123, R125, R126, 1% tol Components R135, R138, R139, R148, R149, R150, R431, R432, R433 36 8 R108, R110, R121, Resistor 402 33 Ω, 1/16 W, NIC NRC04J330TRF R122, R134, R136, 5% tol Components R146, R147 37 4 R161, R162, R163, Resistor 402 499 Ω, 1/16 W, NIC NRC04F4990TRF R164 1% tol Components 38 3 R202, R203, R204 Resistor 402 100 kΩ, 1/16 W, NIC NRC04F1003TRF 1% tol Components 39 1 R222 Resistor 402 4.12 kΩ, 1/16 W, NIC NRC04F4121TRF 1% tol Components 40 1 R213 Resistor 402 49.9 Ω, 1/16 W, Susumu RR0510R-49R9-D 0.5% tol 41 1 R229 Resistor 402 4.99 kΩ, 1/16 W, NIC NRC04F4991TRF 5% tol Components 42 2 R230, R319 Potentiometer 3-lead 10 kΩ, cermet BC CT94EW103 trimmer Components potentiometer, 18-turn top adjust, 10%, 1/2 W 43 1 R228 Resistor 402 470 kΩ, 1/16 W, NIC NRC04J474TRF 5% tol Components 44 1 R320 Resistor 402 39 kΩ, 1/16 W, NIC NRC04J393TRF 5% tol Components 45 8 R307, R308, R309, Resistor 402 187 Ω, 1/16 W, NIC NRC04F1870TRF R310, R407, R408, 1% tol Components R409, R410 46 4 R305, R306, R405, Resistor 402 374 Ω, 1/16 W, NIC NRC04F3740TRF R406 1% tol Components 47 4 R316, R317, R415, Resistor 402 274 Ω, 1/16 W, NIC NRC04F2740TRF R416 1% tol Components 48 11 R245, R247, R249, Resistor 201 0 Ω, 1/20 W, 5% tol Panasonic ERJ-1GE0R00C R251, R253, R255, R257, R259, R261, R263, R265 49 1 R418 Resistor 402 4.75 kΩ, 1/16 W, NIC NRC04J472TRF 1% tol Components 50 1 R419 Resistor 402 261 Ω, 1/16 W, NIC NRC04F2610TRF 1% tol Components 51 1 R501 Resistor 603 261 Ω, 1/16 W, NIC NRC06F2610TRF 1% tol Components 52 2 R240, R241 Resistor 402 243 Ω, 1/16 W, NIC NRC04F2430TRF 1% tol Components 53 2 R242, R243 Resistor 402 100 Ω, 1/16 W, NIC NRC04F1000TRF 1% tol Components 54 1 S401 Switch SMD Light touch, Panasonic EVQ-PLDA15 100GE, 5 mm 55 5 T101, T102, T103, Transformer CD542 ADT1-1WT, 1:1 Mini-Circuits ADT1-1WT+ T104, T201 impedance ratio transformer 56 2 U501, U503 IC SOT-223 ADP3339AKC-1.8, Analog Devices ADP3339AKCZ-1.8 1.5 A, 1.8 V LDO regulator Rev. E | Page 49 of 52 AD9259 Data Sheet Manufacturer’s Item Qty. Reference Designator Device Package Value Manufacturer Part Number 57 2 U301, U401 IC LFCSP, AD8332ACP, Analog Devices AD8332ACPZ CP-32 ultralow noise precision dual VGA 58 1 U504 IC SOT-223 ADP3339AKC-5 Analog Devices ADP3339AKCZ-5 59 1 U502 IC SOT-223 ADP3339AKC-3.3 Analog Devices ADP3339AKCZ-3.3 60 1 U201 IC LFCSP, AD9259BCPZ-50, Analog Devices AD9259BCPZ-50 CP-48-1 quad, 14-bit, 50 MSPS serial LVDS 1.8 V ADC 61 1 U203 IC SOT-23 ADR510ARTZ, 1.0 V, Analog Devices ADR510ARTZ precision low noise shunt voltage reference 62 1 U202 IC LFCSP AD9515BCPZ Analog Devices AD9515BCPZ CP-32-2 63 1 U403 IC SC70, NC7WZ07 Fairchild NC7WZ07P6X_NL MAA06A 64 1 U404 IC SC70, NC7WZ16 Fairchild NC7WZ16P6X_NL MAA06A 65 1 U402 IC 8-SOIC Flash prog Microchip PIC12F629-I/SN mem 1k × 14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series 1 This BOM is RoHS compliant. Rev. E | Page 50 of 52 Data Sheet AD9259 OUTLINE DIMENSIONS 7.10 0.30 0.60 MAX 7.00 SQ 0.23 6.90 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 1 36 PIN 1 INDICATOR 0.50 6.85 REF * 5.55 6.75 SQ EXPOSED 5.50 SQ 6.65 PAD (BOTTOM VIEW) 5.45 25 12 24 13 0.50 0.22 MIN TOP VIEW 0.40 5.50 REF 0.30 0.80 MAX 12° MAX 1.00 0.65 TYP FORPROPERCONNECTIONOF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 71. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters ORDERING GUIDE Temperature Package 1 Model Notes Range Package Description Option AD9259ABCPZ-50 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9259ABCPZRL7-50 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel CP-48-8 2 AD9259-50EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. Rev. E | Page 51 of 52 02-23-2010-C AD9259 Data Sheet NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05965-0-1/11(E) Rev. E | Page 52 of 52