ANALOG DEVICES AD9251

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9251 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V to 3.3 V output supply SPI SNR ORA 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input PROGRAMMING DATA D13A VIN+A ADC SFDR VIN–A D0A 93 dBc at 9.7 MHz input DCOA 80 dBc at 200 MHz input VREF Low power SENSE DRVDD 33 mW per channel at 20 MSPS AD9251 REF VCM 73 mW per channel at 80 MSPS SELECT ORB RBIAS Differential input with 700 MHz bandwidth D13B On-chip voltage reference and sample-and-hold circuit VIN–B ADC 2 V p-p differential analog input VIN+B D0B DNL = ±0.45 LSB DCOB Serial port control options Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE 1TO 8 STABILIZER CONTROLS Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider CLK+ CLK– SYNC DCS PDWN DFS OEB Data output multiplex option Figure 1. Built-in selectable digital test pattern generation Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data 1. The AD9251 operates from a single 1.8 V analog power alignment supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent APPLICATIONS performance for input frequencies up to 200 MHz and is Communications designed for low cost, low power, and ease of use. Diversity radio systems 3. A standard serial port interface supports various product Multimode digital receivers features and functions, such as data output formatting, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA internal clock divider, power-down, DCO/DATA timing I/Q demodulation systems and offset adjustments, and voltage reference modes. Smart antenna systems 4. The AD9251 is packaged in a 64-lead RoHS compliant Battery-powered instruments LFCSP that is pin compatible with the AD9268 16-bit Hand held scope meters ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, Portable medical imaging and the AD9204 10-bit ADC, enabling a simple migration Ultrasound path between 10-bit and 16-bit converters sampling from Radar/LIDAR 20 MSPS to 125 MSPS. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 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MUX OPTION CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 07938-001 AD9251 TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference ....................................................................... 23  Applications ....................................................................................... 1  Clock Input Considerations ...................................................... 24  Functional Block Diagram .............................................................. 1  Channel/Chip Synchronization ................................................ 26  Product Highlights ........................................................................... 1  Power Dissipation and Standby Mode .................................... 26  Revision History ............................................................................... 2  Digital Outputs ........................................................................... 27  General Description ......................................................................... 3  Timing ......................................................................................... 27  Specif ica t ions ..................................................................................... 4  Built-In Self-Test (BIST) and Output Test .................................. 28  DC Specifications ......................................................................... 4  Built-In Self-Test (BIST) ............................................................ 28  AC Specifications .......................................................................... 5  Output Test Modes ..................................................................... 28  Digital Specifications ................................................................... 6  Serial Port Interface (SPI) .............................................................. 29  Switching Specifications .............................................................. 7  Configuration Using the SPI ..................................................... 29  Timing Specifications .................................................................. 8  Hardware Interface ..................................................................... 30  Absolute Maximum Ratings .......................................................... 10  Configuration Without the SPI ................................................ 30  Thermal Characteristics ............................................................ 10  SPI Accessible Features .............................................................. 30  ESD Caution ................................................................................ 10  Memory Map .................................................................................. 31  Pin Configuration and Function Descriptions ........................... 11  Reading the Memory Map Register Table ............................... 31  Typical Performance Characteristics ........................................... 13  Open Locations .......................................................................... 31  AD9251-80 .................................................................................. 13  Default Values ............................................................................. 31  AD9251-65 .................................................................................. 15  Memory Map Register Table ..................................................... 32  AD9251-40 .................................................................................. 16  Memory Map Register Descriptions ........................................ 34  AD9251-20 .................................................................................. 17  Applications Information .............................................................. 35  Equivalent Circuits ......................................................................... 18  Design Guidelines ...................................................................... 35  Theory of Operation ...................................................................... 20  Outline Dimensions ....................................................................... 36  ADC Architecture ...................................................................... 20  Ordering Guide .......................................................................... 36  Analog Input Considerations .................................................... 20  REVISION HISTORY 10/09—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Change to Table 1 ............................................................................. 4 Moved Timing Diagrams................................................................. 8 Deleted Table 11; Renumbered Sequentially .............................. 22 Changes to Internal Reference Connection Section .................. 23 Moved Channel/Chip Synchronization Section ......................... 26 Change to Table 15 ......................................................................... 30 Changes to Reading the Memory Map Register Table Section ................................................................................... 31 Changes to Table 16 ........................................................................ 32 7/09—Revision 0: Initial Version Rev. A | Page 2 of 36 AD9251 GENERAL DESCRIPTION A differential clock input controls all internal conversion cycles. The AD9251 is a monolithic, dual-channel, 1.8 V supply, An optional duty cycle stabilizer (DCS) compensates for wide 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital variations in the clock duty cycle while maintaining excellent converter (ADC). It features a high performance sample-and- overall ADC performance. hold circuit and on-chip voltage reference. The digital output data is presented in offset binary, gray code, The product uses multistage differential pipeline architecture or twos complement format. A data output clock (DCO) is with output error correction logic to provide 14-bit accuracy at provided for each ADC channel to ensure proper latch timing 80 MSPS data rates and to guarantee no missing codes over the with receiving logic. Both 1.8 V and 3.3 V CMOS levels are full operating temperature range. supported and output data can be multiplexed onto a single The ADC contains several features designed to maximize output bus. flexibility and minimize system cost, such as programmable The AD9251 is available in a 64-lead RoHS Compliant LFCSP clock and data alignment and programmable digital test pattern and is specified over the industrial temperature range (−40°C generation. The available digital test patterns include built-in to +85°C). deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. A | Page 3 of 36 AD9251 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. AD9251-20/AD9251-40 AD9251-65 AD9251-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.1 ±0.70 ±0.1 ±0.50 ±0.1 ±0.70 % FSR 1 Gain Error Full −1.5 −1.5 −1.5 % FSR 2 Differential Nonlinearity (DNL) Full ±0.60 ±0.75 ±0.70 LSB 25°C ±0.3 ±0.45 ±0.45 LSB 2 Integral Nonlinearity (INL) Full ±1.75 ±1.75 ±2.50 LSB 25°C ±0.6 ±0.6 ±1.0 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.65 ±0.0 ±0.65 ±0.0 ±0.65 % FSR 1 Gain Error 25°C ±0.2 ±0.2 ±0.2 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.98 0.98 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p 3 Input Capacitance Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 IAVDD Full 36.5/49.5 39.4/52.8 69.0 72.9 80.5 85.5 mA 2 IDRVDD (1.8 V) Full 3.4/5.6 8.4 10.3 mA 2 IDRVDD (3.3 V) Full 6.3/10.6 16.0 19.5 mA POWER CONSUMPTION DC Input Full 66/89 125 145 mW 2 Sine Wave Input (DRVDD = 1.8 V) Full 71.8/99 77.0/105.5 139.0 146.5 163.4 173 mW 2 Sine Wave Input (DRVDD = 3.3 V) Full 86.5/124 176.7 209 mW 4 Standby Power Full 37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. A | Page 4 of 36 AD9251 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. AD9251-20/AD9251-40 AD9251-65 AD9251-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 74.7 74.5 74.3 dBFS IN f = 30.5 MHz 25°C 74.4 74.3 74.1 dBFS IN Full 73.6 73.6 dBFS fIN = 70 MHz 25°C 73.7 73.7 73.6 dBFS Full 72.5 dBFS fIN = 200 MHz 25°C 71.5 71.5 71.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 74.6 74.4 74.1 dBFS fIN = 30.5 MHz 25°C 74.3 74.2 74.0 dBFS Full 73.4 73.4 dBFS f = 70 MHz 25°C 73.6 73.6 73.5 dBFS IN Full 72.4 dBFS fIN = 200 MHz 25°C 70.0 70.0 70.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.0 12.0 12.0 Bits fIN = 30.5 MHz 25°C 12.0 12.0 12.0 Bits fIN = 70 MHz 25°C 11.9 11.9 11.9 Bits f = 200 MHz 25°C 11.3 11.3 11.3 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −95 −93 dBc f = 30.5 MHz 25°C −95 −95 −93 dBc IN Full −81 −81 dBc fIN = 70 MHz 25°C −94 −94 −92 dBc Full −81 dBc fIN = 200 MHz 25°C −80 −80 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 94 94 93 dBc Full 81 81 dBc f = 70 MHz 25°C 93 93 92 dBc IN Full 81 dBc fIN = 200 MHz 25°C 80 80 80 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −98 −98 −97 dBc IN fIN = 30.5 MHz 25°C −98 −98 −97 dBc Full −90 −90 dBc f = 70 MHz 25°C −98 −98 −96 dBc IN Full −89 dBc f = 200 MHz 25°C −95 −95 −95 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc IN 2 CROSSTALK Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. A | Page 5 of 36 AD9251 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. AD9251-20/AD9251-40/AD9251-65/AD9251-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (SDIO/DCS) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 μA Full 3.29 V OH High Level Output Voltage, I = 0.5 mA Full 3.25 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, I = 50 μA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. A | Page 6 of 36 AD9251 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. AD9251-20/AD9251-40 AD9251-65 AD9251-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (tDCO) Full 3 3 3 ns DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 9 9 9 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. Rev. A | Page 7 of 36 AD9251 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns t SYNC to rising edge of CLK hold time 0.40 ns HSYNC SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge Timing Diagrams N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 9 N – 8N – 7N – 6N – 5 t PD Figure 2. CMOS Output Data Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 t PD Figure 3. CMOS Interleaved Output Timing Rev. A | Page 8 of 36 07938-003 07938-002 AD9251 CLK+ t t SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev. A | Page 9 of 36 07938-004 AD9251 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. SYNC to AGND −0.3 V to DRVDD + 0.3 V Typical θJA is specified for a 4-layer PCB with a solid ground VREF to AGND −0.3 V to AVDD + 0.2 V plane. As shown in Table 7, airflow improves heat dissipation, SENSE to AGND −0.3 V to AVDD + 0.2 V which reduces θ . In addition, metal in direct contact with the JA VCM to AGND −0.3 V to AVDD + 0.2 V package leads from metal traces, through holes, ground, and RBIAS to AGND −0.3 V to AVDD + 0.2 V power planes, reduces the θ . JA CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V Table 7. Thermal Resistance SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V Airflow OEB to AGND −0.3 V to DRVDD + 0.3 V Velocity PDWN to AGND −0.3 V to DRVDD + 0.3 V 1, 2 1, 3 1, 4 Package Type (m/sec) θ θ θ Unit JA JC JB D0A/D0B through D13A/D13B to AGND −0.3 V to DRVDD + 0.3 V 64-Lead LFCSP 0 23 2.0 °C/W DCOA/DCOB to AGND −0.3 V to DRVDD + 0.3 V (CP-64-4) 1.0 20 12 °C/W Operating Temperature Range (Ambient) −40°C to +85°C 2.5 18 °C/W Maximum Junction Temperature 150°C 1 Under Bias Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Storage Temperature Range (Ambient) −65°C to +150°C 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ESD CAUTION rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 10 of 36 AD9251 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS (LSB) D0B 6 43 ORA D1B 7 42 D13A (MSB) D2B 8 41 D12A AD9251 D3B 9 40 D11A TOP VIEW DRVDD 10 39 D10A (Not to Scale) 38 D4B 11 D9A D5B 12 37 DRVDD D6B 13 36 D8A D7B 14 35 D7A D8B 15 34 D6A D9B 16 33 D5A NOTES 1. NC = NO CONNECT 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 5. Pin Configuration Table 8. Pin Function Description Pin No. Mnemonic Description 0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4, 5, 25, 26 NC Do Not Connect. 6 to 9, 11 to 18, 20, 21 D0B to D13B Channel B Digital Outputs. D13B = MSB. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 27, 29 to 36, 38 to 42 D0A to D13A Channel A Digital Outputs. D13A = MSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull- down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. 49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins. 51, 52 VIN+A, VIN−A Channel A Analog Inputs. Rev. A | Page 11 of 36 D10B 64 AVDD 17 AVDD D11B 18 63 DRVDD 19 62 VIN+B D12B 20 61 VIN–B (MSB) D13B 21 60 AVDD ORB 22 59 AVDD DCOB 23 58 RBIAS DCOA 24 57 VCM NC 25 56 SENSE NC 26 55 VREF (LSB) D0A 27 54 AVDD DRVDD 28 53 AVDD 52 VIN–A D1A 29 D2A 30 51 VIN+A D3A 31 50 AVDD D4A 32 49 AVDD 07938-005 AD9251 Pin No. Mnemonic Description 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog output voltage at midsupply to set common mode of the analog inputs. 58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs. Rev. A | Page 12 of 36 AD9251 TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 30.5MHz @ –1dBFS –15 9.7MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) –15 SNR = 73.4dB (74.4dBFS) SFDR = 93.6dBc SFDR = 94.4dBc –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 3 3 2 5 6 4 2 5 –105 6 4 –105 –120 –120 4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Single-Tone FFT with f = 30.5 MHz IN Figure 6. Single-Tone FFT with f = 9.7 MHz IN 0 0 80MSPS 80MSPS 70.3MHz @ –1dBFS 200MHz @ –1dBFS –15 –15 SNR = 72.1dB (73.1dBFS) SNR = 70.5dB (71.5dBFS) SFDR = 93.5dBc SFDR = 80.2dBc –30 –30 –45 –45 –60 –60 –75 –75 23 –90 2 –90 3 4 6 5 –105 4 6 5 –105 –120 –120 4 8 12 162024283236 4 8 12 162024283236 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Single-Tone FFT with fIN = 70.3 MHz Figure 10. Single-Tone FFT with fIN = 200 MHz 0 80MSPS 0 30.5MHz @ –7dBFS –15 32.5MHz @ –7dBFS SFDR = 89.5dBc (96.5dBFS) –30 –20 SFDR (dBc) –45 –40 –60 IMD3 (dBc) –60 –75 –90 2F1 + F2 –80 2F2 + F1 F2–F1 2F1 – F2 2F2 – F1 F1 + F2 –105 SFDR (dBFS) –100 –120 IMD3 (dBFS) 4 8 12 16 20 24 28 32 36 –120 FREQUENCY (MHz) –90 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 8. Two-Tone FFT with f = 30.5 MHz and f = 32.5 MHz IN1 IN2 Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = IN1 30.5 MHz and f = 32.5 MHz IN2 Rev. A | Page 13 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07938-200 07938-062 07938-033 SFDR/IMD3 (dBc/dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07938-036 07938-034 07938-054 AD9251 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 120 SFDR (dBc) 90 SFDRFS 100 80 70 80 SNR (dBFS) 60 SNRFS 60 50 SFDR 40 40 30 SNR 20 20 10 0 0 –90 –80 –60 –40 –20 0 0 50 100 150 200 INPUT FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 12. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 15. SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN 120 450,000 400,000 SFDR (dBc) 100 350,000 SNR (dBFS) 80 300,000 250,000 60 200,000 40 150,000 100,000 20 50,000 0 0 10 20 30 40 50 60 70 80 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 SAMPLE RATE (MSPS) OUTPUT CODE Figure 13. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 16. Grounded Input Histogram 0.5 2.0 0.4 1.5 0.3 1.0 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 –1.5 –0.4 –0.5 –2.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE OUTPUT CODE Figure 17. INL with f = 9.7 MHz IN Figure 14. DNL Error with fIN = 9.7 MHz Rev. A | Page 14 of 36 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 07938-055 07938-057 07938-038 INL ERROR (LSB) NUMBER OF HITS SNR/SFDR (dBFS) 07938-061 07938-037 07938-048 AD9251 AD9251-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 65MSPS 9.7MHz @ –1dBFS –15 SFDRFS SNR = 73.5dB (74.5dBFS) 100 SFDR = 97.7dBc –30 80 –45 SNRFS –60 60 SFDR –75 40 –90 SNR 3 2 5 4 6 –105 20 –120 0 3 6 9 12 1518 21 2427 30 –90 –80 –60 –40 –20 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 18. Single-Tone FFT with fIN = 9.7 MHz Figure 21. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 100 65MSPS 70.3MHz @ –1dBFS 90 –15 SFDR (dBc) SNR = 72.6dB (73.6dBFS) SFDR = 94.1dBc 80 –30 70 SNR (dBFS) –45 60 –60 50 –75 40 –90 30 2 4 356 20 –105 10 –120 0 3 6 9 12 1518 21 2427 30 0 50 100 150 200 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 19. Single-Tone FFT with fIN = 70.3 MHz Figure 22. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 0 65MSPS 30.5MHz @ –1dBFS –15 SNR = 73.3dB (74.3dBFS) SFDR = 99.3dBc –30 –45 –60 –75 –90 3 2 5 –105 4 6 –120 3 6 9 12 1518 21 2427 30 FREQUENCY (MHz) Figure 20. Single-Tone FFT with f = 30.5 MHz IN Rev. A | Page 15 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07938-031 07938-032 07938-030 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS) 07938-060 07938-056 AD9251 AD9251-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 0 40MSPS 9.7MHz @ –1dBFS –15 SFDRFS SNR = 73.5dB (74.5dBFS) 100 SFDR = 95.4dBc –30 80 –45 SNRFS –60 60 SFDR –75 40 –90 SNR 2 4 5 3 6 –105 20 –120 0 2 4 6 8 10 12 14 16 18 –90 –80 –60 –40 –20 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 23. Single-Tone FFT with fIN = 9.7 MHz Figure 25. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 40MSPS 30.5MHz @ –1dBFS –15 SNR = 73.2dB (74.2dBFS) SFDR = 95.7dBc –30 –45 –60 –75 –90 3 4 5 2 –105 6 –120 2 4 6 8 10 12 14 16 18 FREQUENCY (MHz) Figure 24. Single-Tone FFT with fIN = 30.5 MHz Rev. A | Page 16 of 36 AMPLITUDE (dBFS) AMPLITUDE (dB) 07938-029 07938-028 SNR/SFDR (dBFS) 07938-059 AD9251 AD9251-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 20MSPS 9.7MHz @ –1dBFS –15 SFDR (dBFS) SNR = 73.5dBFS (74.5dBFS) 100 SFDR = 97.2dBc –30 80 SNR (dBFS) –45 –60 60 SFDR (dBc) –75 40 –90 SNR (dBc) 4 3 2 6 5 –105 20 –120 0 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 26. Single-Tone FFT with fIN = 9.7 MHz Figure 28. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 20MSPS 30.5MHz @ –1dBFS –15 SNR = 73.2dB (74.2dBFS) SFDR = 98.1dBc –30 –45 –60 –75 –90 3 2 4 6 5 –105 –120 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) Figure 27. Single-Tone FFT with f = 30.5 MHz IN Rev. A | Page 17 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 07938-026 07938-024 SNR/SFDR (dBc/dBFS) 07938-058 AD9251 EQUIVALENT CIRCUITS DRVDD AVDD VIN±x Figure 29. Equivalent Analog Input Circuit Figure 32. Equivalent Digital Output Circuit 5Ω CLK+ 15kΩ 0.9V 15kΩ DRVDD 5Ω CLK– 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ Figure 30. Equivalent Clock Input Circuit Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS 375Ω 30kΩ RBIAS AND VCM Figure 31. Equivalent SDIO/DCS Input Circuit Figure 34. Equivalent RBIAS, VCM Circuit Rev. A | Page 18 of 36 07938-039 07938-040 07938-041 07938-042 07938-044 07938-043 AD9251 DRVDD AVDD AVDD 30kΩ 350Ω CSB 375Ω VREF 7.5kΩ Figure 35. Equivalent CSB Input Circuit Figure 37. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit Rev. A | Page 19 of 36 07938-046 07938-045 07938-047 AD9251 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9251 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically The analog input to the AD9251 is a differential switched- on the same carrier but from two separate antennae. The ADCs capacitor circuit designed for processing differential input can also be operated with independent analog inputs. The user signals. This circuit can support a wide common-mode range can sample any f /2 frequency segment from dc to 200 MHz, S while maintaining excellent performance. By using an input using appropriate low-pass or band-pass filtering at the ADC common-mode voltage of midsupply, users can minimize inputs with little loss in ADC performance. Operation to signal-dependent errors and achieve optimum performance. 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. H In nondiversity applications, the AD9251 can be used as a base- C band or direct downconversion receiver, where one ADC is PAR H VIN+x used for I input data and the other is used for Q input data. C SAMPLE SS Synchronization capability is provided to allow synchronized SS timing between multiple channels or multiple devices. C SAMPLE VIN–x Programming and control of the AD9251 is accomplished using H C PAR a 3-bit SPI-compatible serial interface. H ADC ARCHITECTURE The AD9251 architecture consists of a multistage, pipelined ADC. Figure 38. Switched-Capacitor Input Circuit Each stage provides sufficient overlap to correct for flash errors in The clock signal alternately switches the input circuit between the preceding stage. The quantized outputs from each stage are sample-and-hold mode (see Figure 38). When the input circuit combined into a final 14-bit result in the digital correction logic. is switched to sample mode, the signal source must be capable The pipelined architecture permits the first stage to operate with a of charging the sample capacitors and settling within one-half new input sample while the remaining stages operate with of a clock cycle. A small resistor in series with each input can preceding samples. Sampling occurs on the rising edge of help reduce the peak transient current injected from the output the clock. stage of the driving source. In addition, low Q inductors or ferrite Each stage of the pipeline, excluding the last, consists of a low beads can be placed on each leg of the input to reduce high resolution flash ADC connected to a switched-capacitor DAC differential capacitance at the analog inputs and, therefore, and an interstage residue amplifier (for example, a multiplying achieve the maximum bandwidth of the ADC. Such use of low digital-to-analog converter (MDAC)). The residue amplifier Q inductors or ferrite beads is required when driving the converter magnifies the difference between the reconstructed DAC output front end at high IF frequencies. Either a shunt capacitor or two and the flash input for the next stage in the pipeline. One bit of single-ended capacitors can be placed on the inputs to provide a redundancy is used in each stage to facilitate digital correction matching passive network. This ultimately creates a low-pass of flash errors. The last stage simply consists of a flash ADC. filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the The output staging block aligns the data, corrects errors, and Analog Dialogue article “Transformer-Coupled Front-End for passes the data to the CMOS output buffers. The output buffers Wideband A/D Converters” (Volume 39, April 2005) for more are powered from a separate (DRVDD) supply, allowing information. In general, the precise values depend on the adjustment of the output voltage swing. During power-down, application. the output buffers go into a high impedance state. Rev. A | Page 20 of 36 07938-006 AD9251 200Ω Input Common Mode 33Ω VIN VIN–x 76.8Ω AVDD 90Ω The analog inputs of the AD9251 are not internally dc-biased. 10pF ADC ADA4938 Therefore, in ac-coupled applications, the user must provide a 0.1µF dc bias externally. Setting the device so that VCM = AVDD/2 is 120Ω 33Ω VCM VIN+x recommended for optimum performance, but the device can 200Ω function over a wider range with reasonable performance, as Figure 41. Differential Input Configuration Using the ADA4938-2 shown in Figure 39 and Figure 40. For baseband applications below ~10 MHz where SNR is a key An on-board, common-mode voltage reference is included in parameter, differential transformer-coupling is the recommended the design and is available from the VCM pin. The VCM pin input configuration. An example is shown in Figure 42. To bias must be decoupled to ground by a 0.1 μF capacitor, as described the analog input, the VCM voltage can be connected to the in the Applications Information section. center tap of the secondary winding of the transformer. 100 VIN+x SFDR (dBc) R 2V p-p 49.9Ω C ADC 90 R VCM VIN–x 80 0.1µF SNR (dBFS) Figure 42. Differential Transformer-Coupled Configuration 70 The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies 60 below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. 50 At input frequencies in the second Nyquist zone and above, the 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 INPUT COMMON-MODE VOLTAGE (V) noise performance of most amplifiers is not adequate to achieve Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, the true SNR performance of the AD9251. For applications above fIN = 32.1 MHz, fS = 80 MSPS ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 44). 100 An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. SFDR (dBc) 90 An example is shown in Figure 45. See the AD8352 data sheet for more information. 80 In any configuration, the value of Shunt Capacitor C is dependent SNR (dBFS) on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set 70 the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. 60 Table 9. Example RC Network R Series 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Frequency Range (MHz) (Ω Each) C Differential (pF) INPUT COMMON-MODE VOLTAGE (V) 0 to 70 33 22 Figure 40. SNR/SFDR vs. Input Common-Mode Voltage, 70 to 200 125 Open f = 10.3 MHz, f = 20 MSPS IN S Differential Input Configurations Optimum performance is achieved while driving the AD9251 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9251 (see Figure 41), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Rev. A | Page 21 of 36 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 07938-050 07938-049 07938-007 07938-008 AD9251 10µF AVDD Single-Ended Input Configuration 1kΩ R A single-ended input can provide adequate performance in VIN+x 1V p-p 0.1µF 49.9Ω 1kΩ cost-sensitive applications. In this configuration, SFDR and AVDD ADC C distortion performance degrade due to the large input common- 1kΩ R mode swing. If the source impedances on each input are matched, VIN–x 10µF there should be little effect on SNR performance. Figure 43 0.1µF 1kΩ shows a typical single-ended input configuration. Figure 43. Single-Ended Input Configuration 0.1µF 0.1µF R VIN+x 2V p-p 25Ω P S S P C ADC A 0.1µF 25Ω 0.1µF R VCM VIN–x Figure 44. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+x 2 200Ω C ADC AD8352 R R C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN–x 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 45. Differential Input Configuration Using the AD8352 Rev. A | Page 22 of 36 07938-010 07938-011 07938-009 AD9251 If the internal reference of the AD9251 is used to drive multiple VOLTAGE REFERENCE converters to improve gain matching, the loading of the reference A stable and accurate 1.0 V voltage reference is built into the by the other converters must be considered. Figure 47 shows AD9251. The VREF can be configured using either the internal how the internal reference voltage is affected by loading. 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that 0 follow. The Reference Decoupling section describes the best practices PCB layout of the reference. –0.5 Internal Reference Connection –1.0 A comparator within the AD9251 detects the potential at the INTERNAL V = 0.993V REF SENSE pin and configures the reference into two possible –1.5 modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor –2.0 divider (see Figure 46), setting VREF to 1.0 V. –2.5 VIN+A/VIN+B –3.0 VIN–A/VIN–B 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 LOAD CURRENT (mA) Figure 47. VREF Accuracy vs. Load Current ADC CORE VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0.5V ADC Figure 46. Internal Reference Configuration Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. A | Page 23 of 36 07938-012 REFERENCE VOLTAGE ERROR (%) 07938-014 AD9251 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance The AD9251 has a very flexible clock input structure. The clock the gain accuracy of the ADC or improve thermal drift charac- input can be a CMOS, LVDS, LVPECL, or sine wave signal. teristics. Figure 48 shows the typical drift characteristics of the Regardless of the type of signal being used, clock source jitter is internal reference in 1.0 V mode. of the most concern, as described in the Jitter Considerations section. 4 3 Figure 50 and Figure 51 show two preferred methods for clock- ing the AD9251 (at clock rates up to 625 MHz). A low jitter clock 2 V ERROR (mV) REF source is converted from a single-ended signal to a differential 1 signal using either an RF transformer or an RF balun. 0 The RF balun configuration is recommended for clock frequencies –1 between 125 MHz and 625 MHz, and the RF transformer is recom- –2 mended for clock frequencies from 10 MHz to 200 MHz. The –3 back-to-back Schottky diodes across the transformer/balun –4 secondary limit clock excursions into the AD9251 to approximately 0.8 V p-p differential. –5 –6 This limit helps prevent the large voltage swings of the clock –40 –20 0 20 40 60 80 from feeding through to other portions of the AD9251 while TEMPERATURE (°C) preserving the fast rise and fall times of the signal that are critical Figure 48. Typical VREF Drift to a low jitter performance. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal ® Mini-Circuits ADT1-1WT, 1:1 Z reference buffer loads the external reference with an equivalent 0.1µF 0.1µF XFMR 7.5 kΩ load (see Figure 37). The internal buffer generates the CLOCK CLK+ INPUT 100Ω positive and negative full-scale references for the ADC core. 50Ω ADC 0.1µF Therefore, the external reference must be limited to a maximum CLK– SCHOTTKY of 1.0 V. 0.1µF DIODES: HSMS2822 CLOCK INPUT CONSIDERATIONS Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) For optimum performance, clock the AD9251 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a 1nF 0.1µF transformer or capacitors. These pins are biased internally CLOCK CLK+ INPUT (see Figure 49) and require no external bias. 50Ω ADC 0.1µF AVDD 1nF CLK– SCHOTTKY DIODES: 0.9V HSMS2822 Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ CLK– 2pF 2pF Figure 49. Equivalent Clock Input Circuit Rev. A | Page 24 of 36 V ERROR (mV) REF 07938-016 07938-052 07938-018 07938-017 AD9251 If a low jitter clock source is not available, another option is to Input Clock Divider ac couple a differential PECL signal to the sample clock input The AD9251 contains an input clock divider with the ability pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ to divide the input clock by integer values between 1 and 8. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer Optimum performance is obtained by enabling the internal excellent jitter performance. duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. 0.1µF 0.1µF The AD9251 clock divider can be synchronized using the CLOCK CLK+ INPUT external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the AD951x 100Ω ADC clock divider to be resynchronized on every SYNC signal or PECL DRIVER 0.1µF 0.1µF CLOCK only on the first SYNC signal after the register is written. A CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their Figure 52. Differential PECL Sample Clock (Up to 625 MHz) clock dividers aligned to guarantee simultaneous input sampling. A third option is to ac couple a differential LVDS signal to the Clock Duty Cycle sample clock input pins, as shown in Figure 53. The AD9510/ Typical high speed ADCs use both clock edges to generate AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 a variety of internal timing signals and, as a result, may be clock drivers offer excellent jitter performance. sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic 0.1µF performance characteristics. 0.1µF CLOCK CLK+ INPUT The AD9251 contains a duty cycle stabilizer (DCS) that retimes AD951x 100Ω ADC LVDS DRIVER the nonsampling (falling) edge, providing an internal clock 0.1µF 0.1µF CLOCK CLK– signal with a nominal 50% duty cycle. This allows the user to INPUT 50kΩ 50kΩ provide a wide range of clock input duty cycles without affecting the performance of the AD9251. Noise and distortion perform- Figure 53. Differential LVDS Sample Clock (Up to 625 MHz) ance are nearly flat for a wide range of duty cycles with the DCS In some applications, it may be acceptable to drive the sample on, as shown in Figure 55. clock inputs with a single-ended 1.8 V CMOS signal. In such Jitter in the rising edge of the input is still of concern and is not applications, drive the CLK+ pin directly from a CMOS gate, and easily reduced by the internal stabilization circuit. The duty bypass the CLK− pin to ground with a 0.1 μF capacitor (see cycle control loop does not function for clock rates less than Figure 54). 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the V CC clock rate can change dynamically. A wait time of 1.5 μs to 5 μs OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ is required after a dynamic clock frequency increase or decrease CMOS DRIVER INPUT 1 1kΩ 50Ω before the DCS loop is relocked to the input signal. ADC 80 CLK– DCS ON 0.1µF 75 1 50Ω RESISTOR IS OPTIONAL. 70 Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 65 DCS OFF 60 55 50 45 40 10 20 30 40 50 60 70 80 POSITIVE DUTY CYCLE (%) Figure 55. SNR vs. DCS On/Off Rev. A | Page 25 of 36 07938-020 07938-019 07938-021 SNR (dBFS) 07938-053 AD9251 Jitter Considerations The maximum DRVDD current (IDRVDD) can be calculated as High speed, high resolution ADCs are sensitive to the quality IDRVDD = V × C × f × N DRVDD LOAD CLK of the clock input. The degradation in SNR from the low fre- where N is the number of output bits (30, in the case of the quency SNR (SNRLF) at a given input frequency (fINPUT) due to AD9251). jitter (tJRMS) can be calculated by This maximum current occurs when every output bit switches (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is estab- In the previous equation, the rms aperture jitter represents the lished by the average number of output bits switching, which clock input jitter specification. IF undersampling applications is determined by the sample rate and the characteristics of the are particularly sensitive to jitter, as illustrated in Figure 56. analog input signal. 80 Reducing the capacitive load presented to the output drivers can 75 0.05ps minimize digital power consumption. The data in Figure 57 was taken using the same operating conditions as those used for the 70 Typical Performance Characteristics, with a 5 pF load on each 0.2ps 65 output driver. 150 60 0.5ps 55 130 1.0ps 1.5ps AD9251-80 50 2.0ps 110 3.0ps 2.5ps 45 1 10 100 1k AD9251-65 FREQUENCY (MHz) 90 Figure 56. SNR vs. Input Frequency and Jitter AD9251-40 The clock input should be treated as an analog signal in cases 70 where aperture jitter may affect the dynamic range of the AD9251. AD9251-20 To avoid modulating the clock signal with digital noise, keep 50 power supplies for clock drivers separate from the ADC output 0 10 20 30 40 50 60 70 80 CLOCK RATE (MSPS) driver supplies. Low jitter, crystal-controlled oscillators make the Figure 57. Analog Core Power vs. Clock Rate best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be The AD9251 is placed in power-down mode either by the SPI retimed by the original clock at the last step. port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2.2 mW. During power-down, the output See the AN-501 Application Note and the AN-756 Application drivers are placed in a high impedance state. Asserting the Note available on www.analog.com for more information. PDWN pin low returns the AD9251 to its normal operating CHANNEL/CHIP SYNCHRONIZATION mode. Note that PDWN is referenced to the digital output The AD9251 has a SYNC input that offers the user flexible driver supply (DRVDD) and should not exceed that supply synchronization options for synchronizing sample clocks voltage. across multiple ADCs. The input clock divider can be enabled Low power dissipation in power-down mode is achieved by to synchronize on a single occurrence of the SYNC signal or on shutting down the reference, reference buffer, biasing networks, every occurrence. The SYNC input is internally synchronized and clock. Internal capacitors are discharged when entering power- to the sample clock; however, to ensure there is no timing down mode and then must be recharged when returning to normal uncertainty between multiple parts, the SYNC input signal should operation. As a result, wake-up time is related to the time spent be externally synchronized to the input clock signal, meeting the in power-down mode, and shorter power-down cycles result in setup and hold times shown in Table 5. Drive the SYNC input proportionally shorter wake-up times. using a single-ended CMOS-type signal. When using the SPI port interface, the user can place the ADC POWER DISSIPATION AND STANDBY MODE in power-down mode or standby mode. Standby mode allows As shown in Figure 57, the analog core power dissipated by the user to keep the internal reference circuitry powered when the AD9251 is proportional to its sample rate. The digital faster wake-up times are required. See the Memory Map section power dissipation of the CMOS outputs are determined for more details. primarily by the strength of the digital drivers and the load on each output bit. Rev. A | Page 26 of 36 SNR (dBFS) 07938-022 ANALOG CORE POWER (mW) 07938-051 AD9251 data drivers and DCOs are enabled. If the OEB pin is high, the DIGITAL OUTPUTS output data drivers and DCOs are placed in a high impedance The AD9251 output drivers can be configured to interface with state. This OEB function is not intended for rapid access to the 1.8 V to 3.3 V CMOS logic families. Output data can also be data bus. Note that OEB is referenced to the digital output multiplexed onto a single output bus to reduce the total number of driver supply (DRVDD) and should not exceed that supply traces required. voltage. The CMOS output drivers are sized to provide sufficient output When using the SPI interface, the data outputs and DCO of current to drive a wide variety of logic families. However, large each channel can be independently three-stated by using the drive currents tend to cause current glitches on the supplies and output disable (OEB) bit (Bit 4) in Register 0x14. may affect converter performance. TIMING Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The AD9251 provides latched data with a pipeline delay of 9 clock cycles. Data outputs are available one propagation delay The output data format can be selected to be either offset binary (t ) after the rising edge of the clock signal. PD or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 11). Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9251. These As detailed in the AN-877 Application Note, Interfacing to High transients can degrade converter dynamic performance. Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. The lowest typical conversion rate of the AD9251 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Table 11. SCLK/DFS Mode Selection (External Pin Mode) Data Clock Output (DCO) Voltage at Pin SCLK/DFS SDIO/DCS The AD9251 provides two data clock output (DCO) signals AGND Offset binary (default) DCS disabled intended for capturing the data in an external register. The CMOS DRVDD Twos complement DCS enabled (default) data outputs are valid on the rising edge of the DCO, unless the Digital Output Enable Function (OEB) DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. The AD9251 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1 Rev. A | Page 27 of 36 AD9251 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of The AD9251 includes a built-in test feature designed to enable the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN verification of the integrity of each channel, as well as to sequence can be continued from its last value by writing a 0 in facilitate board level debugging. A built-in self-test (BIST) feature Bit 2 of Register 0x0E. However, if the PN sequence is not reset, that verifies the integrity of the digital datapath of the AD9251 the signature calculation does not equal the predetermined is included. Various output test options are also provided to place value at the end of the test. At that point, the user needs to rely predictable values on the outputs of the AD9251. on verifying the output data. BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES The BIST is a thorough test of the digital portion of the selected The output test options are described in Table 16 at Address AD9251 signal path. Perform the BIST test after a reset to ensure 0x0D. When an output test mode is enabled, the analog section the part is in a known state. During BIST, data from an internal of the ADC is disconnected from the digital back-end blocks pseudorandom noise (PN) source is driven through the digital and the test pattern is run through the output formatting block. datapath of both channels, starting at the ADC block output. At Some of the test patterns are subject to output formatting, and the datapath output, CRC logic calculates a signature from the some are not. The PN generators from the PN sequence tests data. The BIST sequence runs for 512 cycles and then stops. can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These Once completed, the BIST compares the signature results with a tests can be performed with or without an analog signal (if pre-determined value. If the signatures match, the BIST sets Bit 0 present, the analog signal is ignored), but they do require an of Register 0x24, signifying the test passed. If the BIST test fails, encode clock. For more information, see the AN-877 Bit 0 of Register 0x24 is cleared. The outputs are connected Application Note, Interfacing to High Speed ADCs via SPI. during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence Rev. A | Page 28 of 36 AD9251 SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of The AD9251 serial port interface (SPI) allows the user to configure SCLK, determines the start of the framing. An example of the the converter for specific functions or operations through a serial timing and its definitions can be found in Figure 58 and structured register space provided inside the ADC. The SPI Table 5. gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port Other modes involving the CSB are available. The CSB can be and can be written to or read from via the port. Memory is held low indefinitely, which permanently enables the device; organized into bytes that can be further divided into fields, this is called streaming. The CSB can stall high between bytes to which are documented in the Memory Map section. For allow for additional external timing. When CSB is tied high, SPI detailed operational information, see AN-877 Application functions are placed in high impedance mode. This mode turns Note, Interfacing to High Speed ADCs via SPI. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. CONFIGURATION USING THE SPI Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: the SCLK, the SDIO, and by the W0 and W1 bits as shown in Figure 58. the CSB (see Table 13). The SCLK (a serial clock) is used to All data is composed of 8-bit words. The first bit of the first byte in synchronize the read and write data presented from and to the a multibyte serial data transfer frame indicates whether a read ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC command or a write command is issued. This allows the serial memory map registers. The CSB (chip select bar) is an active- data input/output (SDIO) pin to change direction from an input low control that enables or disables the read and write cycles. to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines Table 13. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial Clock. The serial shift clock input, which is used to the contents of the on-chip memory. If the instruction is a readback synchronize serial interface reads and writes. operation, performing a readback causes the serial data input/ SDIO Serial Data Input/Output. A dual-purpose pin that output (SDIO) pin to change direction from an input to an output typically serves as an input or an output, depending on the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip Select Bar. An active-low control that gates the read first is the default on power-up and can be changed via the SPI and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. A | Page 29 of 36 07938-023 AD9251 feature control. In this mode, connect the CSB chip select to HARDWARE INTERFACE AVDD, which disables the serial port interface. The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port Table 14. Mode Selection of the AD9251. The SCLK pin and the CSB pin function as External inputs when using the SPI interface. The SDIO pin is Pin Voltage Configuration bidirectional, functioning as an input during write phases and SDIO/DCS AVDD (default) Duty cycle stabilizer enabled as an output during readback. AGND Duty cycle stabilizer disabled SCLK/DFS AVDD Twos complement enabled The SPI interface is flexible enough to be controlled by AGND (default) Offset binary enabled either FPGAs or microcontrollers. One method for SPI OEB AVDD Outputs in high impedance configuration is described in detail in the AN-812 Appli- AGND (default) Outputs enabled cation Note, Microcontroller-Based Serial Port Interface PDWN AVDD Chip in power-down or standby (SPI) Boot Circuit. AGND (default) Normal operation The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SPI ACCESSIBLE FEATURES SCLK signal, the CSB signal, and the SDIO signal are typically Table 15 provides a brief description of the general features that asynchronous to the ADC clock, noise from these signals can are accessible via the SPI. These features are described in detail degrade converter performance. If the on-board SPI bus is used for in the AN-877 Application Note, Interfacing to High Speed ADCs other devices, it may be necessary to provide buffers between via SPI. The AD9251 part-specific features are described in this bus and the AD9251 to prevent these signals from transi- detail in Table 16. tioning at the converter inputs during critical sampling periods. Table 15. Features Accessible Using the SPI SDIO/DCS and SCLK/DFS serve a dual function when the Feature Description SPI interface is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated Mode Allows the user to set either power-down mode or standby mode with a specific function. The Digital Outputs section describes Clock Allows the user to access the DCS via the SPI the strappable functions supported on the AD9251. Offset Allows the user to digitally adjust the CONFIGURATION WITHOUT THE SPI converter offset Test I/O Allows the user to set test modes to have known In applications that do not interface to the SPI control registers, data on output bits the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the Output Mode Allows the user to set up outputs PDWN pin serve as standalone CMOS-compatible control pins. Output Phase Allows the user to set the output clock polarity When the device is powered up, it is assumed that the user Output Delay Allows the user to vary the DCO delay intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down Rev. A | Page 30 of 36 AD9251 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) has After the AD9251 is reset, critical registers are loaded with eight bit locations. The memory map is roughly divided into default values. The default values for the registers are given in four sections: the chip configuration registers (Address 0x00 to the memory map register table (see Table 16). Address 0x02); the device index and transfer registers (Address Logic Levels 0x05 and Address 0xFF); the program registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address • “Bit is set” is synonymous with “bit is set to Logic 1” or 0x101). “writing Logic 1 for the bit.” • “Clear a bit” is synonymous with “bit is set to Logic 0” or Table 16 documents the default hexadecimal value for each “writing Logic 0 for the bit.” hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For Transfer Register Map example, Address 0x05, the Channel Index register, has a Address 0x08 to Address 0x18 are shadowed. Writes to these hexadecimal default value of 0x03. This means that in Address addresses do not affect part operation until a transfer command 0x05 Bit[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is issued by writing 0x01 to Address 0xFF, setting the transfer bit. is the default channel index setting. The default value results in This allows these registers to be updated internally and simulta- both ADC channels receiving the next write command. For neously when the transfer bit is set. The internal update takes more information on this function and others, see the AN-877 place when the transfer bit is set, and then the bit autoclears. Application Note, Interfacing to High Speed ADCs via SPI. This Channel-Specific Registers document details the functions controlled by Register 0x00 to register 0xFF. The remaining registers, Register 0x100 and Some channel setup functions can be programmed differently Register 0x101, are documented in the Memory Map Register for each channel. In these cases, channel address locations are Descriptions section following Table 16. internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These OPEN LOCATIONS local registers and bits can be accessed by setting the appropriate All address and bit locations that are not included in the SPI Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. map are not currently supported for this device. Unused bits of If both bits are set, the subsequent write affects the registers of a valid address location should be written with 0s. Writing to these both channels. In a read cycle, set only Channel A or Channel B locations is required only when part of an address location is to read one of the two registers. If both bits are set during an open (for example, Address 0x05). If the entire address location SPI read cycle, the part returns the value for Channel A. is open, it is omitted from the SPI map (for example, Address 0x13) Registers and bits designated as global in the memory map and should not be written. register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. A | Page 31 of 36 AD9251 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Default Address Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft reset 1 1 Soft LSB first 0 0x18 The nibbles are configuration first reset mirrored so (global) that LSB- or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID (global) 8-bit chip ID bits [7:0] Unique chip ID AD9251 = 0x23 used to diffe- rentiate devices; read only 0x02 Chip grade Open Speed grade ID 6:4 Open Unique speed (global) 20 MSPS = 000 grade ID used 40 MSPS = 001 to differentiate 65 MSPS = 010 devices; read 80 MSPS = 011 only Device Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set to default default determine which device on chip receives the next write command; the default is all devices on chip 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program Registers (May or May Not Be Indexed by Device Index) 0x08 Modes External External pin function Open Open 00 = chip run 0x80 Determines power- 0x00 full power- 01 = full power- various generic down down down modes of chip enable 0x01 standby 10 = standby operation (local) (local) 11 = chip wide digital reset (local) 0x09 Clock (global) Open Open Open Open Open Duty 0x00 cycle stabilize 0x0B Clock divide Open Clock divider [2:0] 0x00 The divide ratio (global) is the value Clock divide ratio plus 1 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Rev. A | Page 32 of 36 AD9251 Default Address Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0D Test mode (local) User test mode Reset PN Reset PN Output test mode [3:0] (local) 0x00 When set, the (local) long gen short 0000 = off (default) test data is 00 = single gen 0001 = midscale short placed on the 01 = alternate 0010 = positive FS output pins in 10 = single once 0011 = negative FS place of normal 11 = alternate 0100 = alternating checkerboard data once 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency 0x0E BIST enable Open Open BIST Open BIST 0x00 When Bit 0 is INIT enable set, the BIST function is initiated 0x10 Offset adjust 8-bit device offset adjustment [7:0] (local) 0x00 Device offset (local) Offset adjust in LSBs from +127 to −128 (twos complement format) trim 0x14 Output mode 00 = 3.3 V CMOS Output mux Output Open Output 00 = offset binary 0x00 Configures the outputs and 10 = 1.8 V CMOS enable disable invert 01 = twos (interleaved) (local) (local) complement the format of 10 = gray code the data 11 = offset binary (local) 0x15 OUTPUT_ADJUST 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data 0x22 Determines drive strength drive strength drive strength drive strength CMOS output 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe drive strength (default) 01 = 2 stripes (default) 01 = 2 stripes properties 01 = 2 stripes 10 = 3 stripes (default) 01 = 2 stripes 10 = 3 stripes 10 = 3 stripes 11 = 4 stripes 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 OUTPUT_PHASE DCO Input clock phase adjust [2:0] 0x00 On devices that output (Value is number of input clock utilize global polarity cycles of phase delay) clock divide, 0 = 000 = no delay determines normal 001 = 1 input clock cycle which phase of 1 = 010 = 2 input clock cycles the divider inverted 011 = 3 input clock cycles output is used (local) 100 = 4 input clock cycles to supply the 101 = 5 input clock cycles output clock; 110 = 6 input clock cycles internal 111 = 7 input clock cycles latching is unaffected 0x17 OUTPUT_DELAY Enable Enable 0x00 This sets the DCO/Data delay [2:0] DCO data fine output 000 = 0.56 ns delay delay delay of the 001 = 1.12 ns output clock 010 = 1.68 ns but does not 011 = 2.24 ns change internal 100 = 2.80 ns timing 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB 0x24 MISR_LSB Open Open Open Open Open Open Open B0 0x00 Least significant byte of MISR; read only Rev. A | Page 33 of 36 AD9251 Default Address Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x2A Features Open Open Open Open Open Open Open OR OE 0x01 Disable the OR (local) pin for the indexed channel 0x2E Output assign Open Open Open Open Open Open Open 0 = ADC A Ch A = Assign an ADC 1 = ADC B 0x00 to an output (local) Ch B = channel 0x01 Digital Feature Control 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x01 (global) divider divider sync next sync enable sync enable only 0x101 USR2 Enable Enable Run Open Disable 0x88 Enables Open Open Open OEB GCLK GCLK SDIO pull- internal Pin 47 detect down oscillator for (local) clock rates < 5 MHz USR2 (Register 0x101) MEMORY MAP REGISTER DESCRIPTIONS Bit 7—Enable OEB Pin 47 For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Normally set high, this bit allows Pin 47 to function as the Note, Interfacing to High Speed ADCs via SPI. output enable. If it is set low, it disables Pin 47. Sync Control (Register 0x100) Bit 3—Enable GCLK Detect Bits[7:3]—Reserved Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS. When a low encode rate is detected, Bit 2—Clock Divider Next Sync Only an internal oscillator, GCLK, is enabled ensuring the proper If the master sync enable bit (Address 0x100, Bit 0) and the operation of several circuits. If set low, the detector is disabled. clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2—Run GCLK Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable This bit enables the GCLK oscillator. For some applications bit (Address 0x100, Bit 1) resets after it syncs. with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Bit 1—Clock Divider Sync Enable Bit 0—Disable SDIO Pull-Down Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high and the device is This bit can be set high to disable the internal 30 kΩ pull-down operating in continuous sync mode as long as Bit 2 of the on the SDIO pin, which can be used to limit the loading when sync control is low. many devices are connected to the SPI bus. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. Rev. A | Page 34 of 36 AD9251 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the DESIGN GUIDELINES lowest possible resistive thermal path for heat dissipation to Before starting design and layout of the AD9251 as a system, flow through the bottom of the PCB. Fill or plug these vias it is recommended that the designer become familiar with these with nonconductive epoxy. guidelines, which discuss the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements needed for certain pins. the PCB, a silkscreen should be overlaid to partition the continuous Power and Ground Recommendations plane on the PCB into several uniform sections. This provides When connecting power to the AD9251, it is strongly several tie points between the ADC and the PCB during the reflow recommended that two separate supplies be used. Use one 1.8 V process. Using one continuous plane with no partitions guarantees supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for only one tie point between the ADC and the PCB. For detailed the digital output supply (DRVDD). If a common 1.8 V AVDD information about packaging and PCB layout of chip scale and DRVDD supply must be used, the AVDD and DRVDD packages, see the AN-772 Application Note, A Design and domains must be isolated with a ferrite bead or filter choke and Manufacturing Guide for the Lead Frame Chip Scale Package separate decoupling capacitors. Several different decoupling (LFCSP), at www.analog.com. capacitors can be used to cover both high and low frequencies. VCM Locate these capacitors close to the point of entry at the PCB The VCM pin should be decoupled to ground with a 0.1 μF level and close to the pins of the part, with minimal trace length. capacitor, as shown in Figure 42. A single PCB ground plane should be sufficient when using the RBIAS AD9251. With proper decoupling and smart partitioning of the The AD9251 requires that a 10 kΩ resistor be placed between PCB analog, digital, and clock sections, optimum performance is easily achieved. the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations Reference Decoupling The exposed paddle (Pin 0) is the only ground connection for the AD9251; therefore, it must be connected to analog ground The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF (AGND) on the PCB of the customer. To achieve the best ceramic capacitor. electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9251 SPI Port exposed paddle, Pin 0. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9251 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. A | Page 35 of 36 AD9251 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1, 2 AD9251BCPZ-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZRL7-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZ-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZRL7-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZ-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZRL7-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZ-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9251BCPZRL7-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1 AD9251-80EBZ Evaluation Board 1 AD9251-65EBZ Evaluation Board 1 AD9251-40EBZ Evaluation Board 1 AD9251-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07938-0-10/09(A) Rev. A | Page 36 of 36 091707-C