ANALOG DEVICES AD9245

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter AD9245 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD Single 3 V supply operation (2.7 V to 3.6 V) SNR = 72.7 dBc to Nyquist AD9245 SFDR = 83.0 dBc to Nyquist VIN+ 8-STAGE SHA MDAC1 A/D Low power 1 1/2-BIT PIPELINE VIN– 366 mW at 80 MSPS 4 16 3 300 mW at 65 MSPS A/D REFT 165 mW at 40 MSPS REFB CORRECTION LOGIC OTR 90 mW at 20 MSPS 14 Differential input with 500 MHz bandwidth OUTPUT BUFFERS On-chip reference and sample-and-hold D13 (MSB) DNL = ±0.5 LSB VREF D0 (LSB) Flexible analog input: 1 V p-p to 2 V p-p range SENSE Offset binary or twos complement data format CLOCK 0.5V MODE DUTY CYCLE SELECT Clock duty-cycle stabilizer REF STABILIZER SELECT APPLICATIONS AGND CLK PDWN MODE DGND Medical imaging equipment Figure 1. IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA A single-ended clock input is used to control all internal con- Battery-powered instruments version cycles. A duty cycle stabilizer (DCS) compensates for Hand-held scopemeters wide variations in the clock duty cycle while maintaining Spectrum analyzers excellent overall ADC performance. The digital output data is Power-sensitive military applications presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or GENERAL DESCRIPTION high overflow. Fabricated on an advanced CMOS process, the The AD9245 is a monolithic, single 3 V supply, 14-bit, AD9245 is available in a 32-lead LFCSP and is specified over 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital the industrial temperature range (–40°C to +85°C). converter (ADC) featuring a high performance sample-and- PRODUCT HIGHLIGHTS hold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error 1. The AD9245 operates from a single 3 V power supply and correction logic to provide 14-bit accuracy and guarantee no features a separate digital output driver supply to missing codes over the full operating temperature range. accommodate 2.5 V and 3.3 V logic families. 2. The patented SHA input maintains excellent performance for The wide bandwidth, truly differential SHA allows a variety of input frequencies up to 100 MHz and can be configured for user-selectable input ranges and common modes, including single-ended or differential operation. single-ended applications. It is suitable for multiplexed systems 3. The AD9245 is pin-compatible with the AD9215, AD9235, that switch full-scale voltage levels in successive channels and and AD9236. This allows a simplified migration from 10 bits for sampling single-channel inputs at frequencies well beyond to 14 bits and 20 MSPS to 80 MSPS. the Nyquist rate. Combined with power and cost savings over 4. The clock DCS maintains overall ADC performance over a previously available analog-to-digital converters, the AD9245 is wide range of clock pulse widths. suitable for applications in communications, imaging, and medical ultrasound. 5. The OTR output bit indicates when the signal is beyond the selected input range. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03583-001 AD9245 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 13 Applications....................................................................................... 1 Theory of Operation ...................................................................... 18 General Description ......................................................................... 1 Analog Input and Reference Overview ................................... 18 Functional Block Diagram .............................................................. 1 Clock Input Considerations...................................................... 19 Product Highlights ........................................................................... 1 Jitter Considerations .................................................................. 20 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 20 Specifications..................................................................................... 3 Digital Outputs ........................................................................... 20 DC Specifications ......................................................................... 3 Timing ......................................................................................... 21 AC Specifications.......................................................................... 5 Voltage Reference ....................................................................... 21 Digital Specifications ................................................................... 7 Internal Reference Connection ................................................ 21 Switching Specifications .............................................................. 8 External Reference Operation .................................................. 22 Absolute Maximum Ratings............................................................ 9 Operational Mode Selection ..................................................... 22 Thermal Resistance ...................................................................... 9 Evaluation Board........................................................................ 22 ESD Caution.................................................................................. 9 Outline Dimensions....................................................................... 29 Terminology .................................................................................... 10 Ordering Guide .......................................................................... 29 Pin Configuration and Function Descriptions........................... 11 Equivalent Circuits ......................................................................... 12 REVISION HISTORY 1/06—Rev. C to Rev. D Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17 Changes to Differential Input Configurations Section and Changes to Figure 39...................................................................... 18 Figure 40 .......................................................................................... 19 Changes to Clock Input Consideration Section......................... 19 Changes to Internal Reference Connection Section.................. 21 Changes to Figure 44...................................................................... 20 Changes to Figure 49...................................................................... 23 Changes to Table 10 ....................................................................... 21 Changes to Figure 50...................................................................... 24 Changes to Figure 51...................................................................... 25 Changes to Table 12........................................................................ 28 Changes to Table 12 ....................................................................... 28 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 29 Changes to Ordering Guide .......................................................... 29 Updated Outline Dimensions....................................................... 29 8/05—Rev. B to Rev. C 10/03—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Figure 33...................................................................... 17 Changes to Features, Applications, General Description, and Product Highlights ........................................................................... 1 Added Table 1; Renumbered Sequentially .................................... 3 5/03—Rev. 0 to Rev. A Changes to Table 2............................................................................ 4 Changes to Figure 30...................................................................... 15 Added Table 3; Renumbered Sequentially .................................... 5 Changes to Figure 37...................................................................... 19 Changes to Table 4............................................................................ 6 Changes to Figure 38...................................................................... 20 Changes to Table 5............................................................................ 7 Changes to Figure 39...................................................................... 21 Changes to Table 6............................................................................ 8 Changes to Table 10 ....................................................................... 24 Changes to the Ordering Guide ................................................... 25 Deleted Explanation of Test Levels Table ...................................... 8 Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16 Rev. D | Page 2 of 32 AD9245 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 14 14 Bits ACCURACY No Missing Codes Guaranteed 14 14 14 Bits Offset Error ±0.30 ±1.60 ±0.50 ±1.75 ±0.50 ±1.75 % FSR 1 Gain Error ±0.30 ±3.25 ±0.50 ±3.25 ±0.50 ±6.90 % FSR 2 Differential Nonlinearity (DNL) ±0.50 ±1.00 ±0.50 ±1.00 ±0.50 ±1.00 LSB 2 Integral Nonlinearity (INL) ±1.20 ±3.10 ±1.40 ±3.40 ±1.60 ±5.55 LSB 1 TEMPERATURE DRIFT Offset Error ±2 ±2 ±3 ppm/°C Gain Error ±12 ±12 ±12 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV INPUT REFERRED NOISE VREF = 0.5 V 2.28 2.28 2.28 LSB rms VREF = 1.0 V 1.08 1.08 1.08 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V 1 1 1 V p-p Input Span, VREF = 1.0 V 2 2 2 V p-p 3 Input Capacitance 7 7 7 pF REFERENCE INPUT RESISTANCE 7 7 7 kΩ POWER SUPPLIES Supply Voltages AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V Supply Current 2 IAVDD 30 55 100 mA 2 IDRVDD 2 5 7 mA PSRR ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION 4 DC Input 90 165 300 mW 2 Sine Wave Input 95 120 180 220 320 375 mW 5 Standby Power 1.0 1.0 1.0 mW 1 Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND). Rev. D | Page 3 of 32 AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted. Table 2. AD9245BCP-80 Parameter Min Typ Max Unit RESOLUTION 14 Bits ACCURACY No Missing Codes Guaranteed 1 Offset Error ±0.30 ±1.2 % FSR Gain Error ±0.28 % FSR 1 Gain Error ±0.70 ±4.16 % FSR 2 Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB 2 Integral Nonlinearity (INL) ±1.4 ±5.15 LSB TEMPERATURE DRIFT 1 Offset Error ±10 ppm/°C Gain Error ±12 ppm/°C 1 Gain Error ±17 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±3 ±34 mV Load Regulation @ 1.0 mA ±2 mV Output Voltage Error (0.5 V Mode) ±6 mV Load Regulation @ 0.5 mA ±1 mV INPUT REFERRED NOISE VREF = 0.5 V 1.86 LSB rms VREF = 1.0 V 1.17 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V 1 V p-p Input Span, VREF = 1.0 V 2 V p-p 3 Input Capacitance 7 pF REFERENCE INPUT RESISTANCE 7 kΩ POWER SUPPLIES Supply Voltage AVDD 2.7 3.0 3.6 V DRVDD 2.25 2.5 3.6 V Supply Current 2 IAVDD 122 138 mA 2 IDRVDD 9 mA PSRR ±0.01 % FSR POWER CONSUMPTION 4 Low Frequency Input 366 mW 5 Standby Power 1.0 mW 1 With a 1.0 V internal reference. 2 Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure. 4 Measured at ac specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). Rev. D | Page 4 of 32 AD9245 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 3. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz 73.5 73.5 73.1 dBc INPUT f = 9.7 MHz 70.6 73.3 dBc INPUT f = 19.6 MHz 70.5 73.4 dBc INPUT fINPUT = 32.5 MHz 70.3 72.7 dBc fINPUT = 100 MHz 70.8 71.3 70.2 dBc SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD) fINPUT = 2.4 MHz 73.4 73.4 73.0 dBc fINPUT = 9.7 MHz 69.4 73.2 dBc f = 19.6 MHz 70.0 73.2 dBc INPUT f = 32.5 MHz 68.4 72.6 dBc INPUT f = 100 MHz 69.5 69.1 67.9 dBc INPUT EFFECTIVE NUMBER OF BITS (ENOB) f = 9.7 MHz 11.9 Bits INPUT f = 19.6 MHz 11.8 Bits INPUT fINPUT = 32.5 MHz 11.7 Bits WORST HARMONIC (SECOND OR THIRD) f = 9.7 MHz –89 –80 dBc INPUT fINPUT = 19.6 MHz –89 –80 dBc fINPUT = 32.5 MHz –83 –74 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz 92.0 92.0 92.0 dBc fINPUT = 9.7 MHz 80.0 89.0 dBc fINPUT = 19.6 MHz 80.0 89.0 dBc f = 32.5 MHz 74.0 83.0 dBc INPUT f = 100 MHz 84.0 85.0 80.5 dBc INPUT Rev. D | Page 5 of 32 AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 4. AD9245BCP-80 Parameter Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz 71.1 73.3 dB IN fIN = 40 MHz 72.7 dB fIN = 70 MHz 70.5 71.7 dB fIN = 100 MHz 70.2 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz 70.7 73.2 dB f = 40 MHz 72.5 dB IN f = 70 MHz 69.9 71.2 dB IN f = 100 MHz 69.6 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz 11.5 11.9 Bits IN f = 40 MHz 11.8 Bits IN fIN = 70 MHz 11.3 11.5 Bits fIN = 100 MHz 11.3 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 2.4 MHz −92.8 –76.5 dBc fIN = 40 MHz –87.6 dBc f = 70 MHz −81.6 –75.7 dBc IN f = 100 MHz –79.0 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz 76.5 92.8 dBc IN f = 40 MHz 87.6 dBc IN f = 70 MHz 75.7 81.6 dBc IN fIN = 100 MHz 79.0 dBc Rev. D | Page 6 of 32 AD9245 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted. Table 5. 1 AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80 Parameter Min Typ Max Unit LOGIC INPUTS (CLK, PDWN) High Level Input Voltage 2.0 V Low Level Input Voltage 0.8 V High Level Input Current –10 +10 μA Low Level Input Current –10 +10 μA Input Capacitance 2 pF 2 DIGITAL OUTPUT BITS (D0 to D13, OTR) DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) 3.29 V High Level Output Voltage (IOH = 0.5 mA) 3.25 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 μA) 0.05 V DRVDD = 2.5 V High Level Output Voltage (IOH = 50 μA) 2.49 V High Level Output Voltage (IOH = 0.5 mA) 2.45 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 μA) 0.05 V 1 AD9245BCP-80 performance measured with 1.0 V external reference. 2 Output voltage levels measured with 5 pF load on each output. Rev. D | Page 7 of 32 AD9245 SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 6. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 AD9245BCP-80 Unit Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate 20 40 65 80 MSPS Minimum Conversion Rate 1 1 1 1 MSPS CLK Period 50.0 25.0 15.4 12.5 ns 1 CLK Pulse Width High 15.0 8.8 6.2 4.6 ns 1 CLK Pulse Width Low 15.0 8.8 6.2 4.6 ns DATA OUTPUT PARAMETERS 2 Output Delay (t) 3.5 3.5 3.5 4.2 ns PD Pipeline Delay (Latency) 7 7 7 7 Cycles Aperture Delay (t) 1.0 1.0 1.0 1.0 ns A Aperture Uncertainty Jitter (tJ) 0.5 0.5 0.5 0.3 ps rms 3 Wake-Up Time 3.0 3.0 3.0 7.0 ms OUT-OF-RANGE RECOVERY TIME 1 1 2 2 Cycles 1 For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. N+1 N N+2 N+8 N–1 N+3 t ANALOG A N+7 INPUT N+4 N+6 N+5 CLK DATA N–9 N–8N–7N–6 N–5N–4 N–3N–2 N–1 N OUT t = 6.0ns MAX PD 2.0ns MIN Figure 2. Timing Diagram Rev. D | Page 8 of 32 03583-002 AD9245 ABSOLUTE MAXIMUM RATINGS Table 7. THERMAL RESISTANCE Parameter With Respect to Min Max Unit θ is specified for the worst-case conditions on a 4-layer board JA ELECTRICAL in still air, in accordance with EIA/JESD51-1. AVDD AGND –0.3 +3.9 V Table 8. Thermal Resistance DRVDD DGND –0.3 +3.9 V Package Type Unit θ θ AGND DGND –0.3 +0.3 V JA JC 32-Lead LFCSP 32.5 32.71 °C/W AVDD DRVDD –3.9 +3.9 V D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD + 0.3 V Airflow increases heat dissipation, effectively reducing θJA. VIN+, VIN– AGND –0.3 AVDD + 0.3 V In addition, more metal directly in contact with the package VREF AGND –0.3 AVDD + 0.3 V leads from metal traces, through holes, ground, and power SENSE AGND –0.3 AVDD + 0.3 V planes reduces the θ . It is recommended that the exposed JA REFT, REFB AGND –0.3 AVDD + 0.3 V paddle be soldered to the ground plane for the LFCSP package. PDWN AGND –0.3 AVDD + 0.3 V There is an increased reliability of the solder joints, and ENVIRONMENTAL maximum thermal capability of the package is achieved with Storage Temperature Range –65 +125 °C the exposed paddle soldered to the customer board. Operating Temperature Range –40 +85 °C Lead Temperature 300 °C (Soldering 10 sec) Junction Temperature 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 9 of 32 AD9245 TERMINOLOGY 1 Analog Bandwidth (Full Power Bandwidth) Signal-to-Noise and Distortion (SINAD) The analog input frequency at which the spectral power of the The ratio of the rms input signal amplitude to the rms value of fundamental frequency (as determined by the FFT analysis) is the sum of all other spectral components below the Nyquist reduced by 3 dB. frequency, including harmonics but excluding dc. Aperture Delay (t ) Effective Number of Bits (ENOB) A The delay between the 50% point of the rising edge of the clock The effective number of bits for a sine wave input at a given and the instant at which the analog input is sampled. input frequency can be calculated directly from its measured SINAD using the following formula: Aperture Uncertainty (Jitter, t ) J (SINAD−1.76) The sample-to-sample variation in aperture delay. ENOB= 6.02 Integral Nonlinearity (INL) 1 The deviation of each individual code from a line drawn from Signal-to-Noise Ratio (SNR) negative full scale through positive full scale. The point used as The ratio of the rms input signal amplitude to the rms value of negative full scale occurs ½ LSB before the first code transition. the sum of all other spectral components below the Nyquist Positive full scale is defined as a level 1½ LSB beyond the last frequency, excluding the first six harmonics and dc. code transition. The deviation is measured from the middle of 1 Spurious-Free Dynamic Range (SFDR) each particular code to the true straight line. The difference in dB between the rms input signal amplitude and the peak spurious signal. The peak spurious component Differential Nonlinearity (DNL, No Missing Codes) may or may not be a harmonic. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed 1 Two-Tone SFDR no missing codes to 14-bit resolution indicates that all 16,384 The ratio of the rms value of either input tone to the rms value codes must be present over all operating ranges. of the peak spurious component. The peak spurious component Offset Error may or may not be an IMD product. The major carry transition should occur for an analog value Clock Pulse Width and Duty Cycle ½ LSB below VIN+ = VIN–. Offset error is defined as the Pulse width high is the minimum amount of time that the clock deviation of the actual transition from that point. pulse should be left in the Logic 1 state to achieve rated Gain Error performance. Pulse width low is the minimum time the clock The first code transition should occur at an analog value ½ LSB pulse should be left in the Logic 0 state. At a given clock rate, above negative full scale. The last transition should occur at an these specifications define an acceptable clock duty cycle. analog value 1½ LSB below the positive full scale. Gain error is Minimum Conversion Rate the deviation of the actual difference between first and last code The clock rate at which the SNR of the lowest analog signal transitions and the ideal difference between first and last code frequency drops by no more than 3 dB below the guaranteed limit. transitions. Maximum Conversion Rate Temperature Drift The clock rate at which parametric testing is performed. The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value Output Propagation Delay (tPD) at T or T . MIN MAX The delay between the clock rising edge and the time when all bits are within valid logic levels. Power Supply Rejection Ratio The change in full scale from the value with the supply at the Out-of-Range Recovery Time minimum limit to the value with the supply at its maximum limit. The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% 1 Total Harmonic Distortion (THD) above negative full scale, or from 10% below negative full scale The ratio of the rms input signal amplitude to the rms value of to 10% below positive full scale. the sum of the first six harmonic components. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. D | Page 10 of 32 AD9245 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC 1 24 VREF CLK 2 23 SENSE DNC 3 22 MODE AD9245 PDWN 4 21 OTR CSP (LSB) D0 5 20 D13 (MSB) TOP VIEW (Not to Scale) D1 6 19 D12 D2 7 18 D11 D3 8 17 D10 Figure 3. LFCSP Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1, 3 DNC Do Not Connect 2 CLK Clock Input Pin 4 PDWN Power-Down Function Select 5 to 14, 17 to 20 D0 (LSB) to D13 (MSB) Data Output Bits 15 DGND Digital Output Ground 16 DRVDD Digital Output Driver Supply 21 OTR Out-of-Range Indicator 22 MODE Data Format Select and DCS Mode Selection (See Table 11) 23 SENSE Reference Mode Selection (See Table 10) 24 VREF Voltage Reference Input/Output 25 REFB Differential Reference (–) 26 REFT Differential Reference (+) 27, 32 AVDD Analog Power Supply 28, 31 AGND Analog Ground 29 VIN+ Analog Input Pin (+) 30 VIN– Analog Input Pin (–) Rev. D | Page 11 of 32 D4 9 32 AVDD D5 10 31 AGND D6 11 30 VIN– D7 12 29 VIN+ D8 13 28 AGND D9 14 27 AVDD DGND 15 26 REFT DRVDD 16 25 REFB 03583-022 AD9245 EQUIVALENT CIRCUITS AVDD DRVDD D13-D0, VIN+, VIN– OTR Figure 4. Equivalent Analog Input Circuit Figure 6. Equivalent Digital Output Circuit AVDD AVDD CLK, MODE PDWN 20kΩ Figure 5. Equivalent MODE Input Circuit Figure 7. Equivalent Digital Input Circuit Rev. D | Page 12 of 32 03583-003 03583-004 03583-006 03583-005 AD9245 TYPICAL PERFORMANCE CHARACTERISTICS DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 100 SFDR (dBFS) AIN = –0.5dBFS SNR = 73.2dBc –10 ENOB = 11.8 BITS SFDR = 92.8dBc –20 90 SFDR (dBc) –30 –40 80 SNR (dBFS) –50 –60 70 SFDR = 90dBc –70 REFERENCE LINE –80 60 –90 SNR (dBc) –100 50 –110 –120 40 0 5 10 15 20 25 30 35 40 –30 –25 –20 –15 –10 –5 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz Figure 8. Single Tone 8K FFT @ 2.5 MHz 0 100 AIN = –0.5dBFS SFDR (dBFS) SNR = 72.7dBc –10 ENOB = 11.8 BITS SFDR = 87.6dBc –20 90 SFDR (dBc) –30 –40 80 SNR (dBFS) –50 –60 70 SFDR = 90dBc –70 REFERENCE LINE –80 60 –90 SNR (dBc) –100 50 –110 –120 40 0 5 10 15 20 25 30 35 40 –30 –25 –20 –15 –10 –5 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 9. Single Tone 8K FFT @ 39 MHz Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz 0 100 AIN = –0.5dBFS SNR = 71.7dBc –10 SFDR (DIFF) ENOB = 11.5 BITS SFDR = 81.6dBc –20 90 –30 SNR (DIFF) –40 SFDR (SE) 80 –50 –60 –70 70 –80 SNR (SE) –90 60 –100 –110 –120 50 0 5 10 15 20 25 30 35 40 0 2040 6080 100 FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 10. Single Tone 8K FFT @ 70 MHz Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz Rev. D | Page 13 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03583-024 03583-023 03583-032 SNR/SFDR (dBc) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 03583-025 03583-034 03583-033 AD9245 0 100 SFDR (dBFS) AIN = –6.5dBFS –10 SNR = 73.4dBFS SFDR = 86.0dBFS –20 90 SFDR (dBc) –30 –40 80 –50 70 –60 SNR (dBFS) –70 SFDR = 90dBc –80 60 REFERENCE LINE –90 SNR (dBc) 50 –100 –110 40 –120 –30 –27 –24 –21 –18 –15 –12 –9 –6 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz 100 0 SFDR (dBFS) AIN = –6.5dBFS –10 SNR = 72.7dBFS SFDR = 78.8dBFS 90 –20 SFDR (dBc) –30 80 –40 –50 70 –60 SNR (dBFS) –70 SFDR = 90dBc 60 –80 REFERENCE LINE –90 SNR (dBc) –100 50 –110 40 –120 –30 –27 –24 –21 –18 –15 –12 –9 –6 0 5 10 15 20 25 30 35 40 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz 1.5 1.0 0.8 1.0 0.6 0.4 0.5 0.2 0 0 –0.2 –0.5 –0.4 –0.6 –1.0 –0.8 –1.5 –1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 16. Typical INL Figure 19. Typical DNL Rev. D | Page 14 of 32 INL (LSB) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03583-026 03583-030 03583-029 DNL (LSB) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 03583-028 03583-027 03583-031 AD9245 75 100 74 –40°C 95 73 +25°C 72 90 71 +85°C 70 85 –40°C 69 80 68 +25°C +85°C 67 75 66 65 70 0 25 50 75 100 125 0 25 50 75 100 125 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 20. SNR vs. Input Frequency Figure 23. SFDR vs. Input Frequency 90 0 SFDR (DCS ON) –10 88 –20 86 –30 84 –40 SFDR (DCS OFF) 82 –50 –60 80 –70 78 –80 76 –90 74 –100 SNR (DCS OFF) 72 –110 SNR (DCS ON) –120 70 0 9.6 19.2 28.8 38.4 30 35 40 45 50 55 60 65 70 FREQUENCY (MHz) DUTY CYCLE (%) Figure 21. SNR/SFDR vs. Clock Duty Cycle Figure 24. Two 32K FFT CDMA-2000 Carriers @ FIN = 46.08 MHz; Sample Rate = 61.44 MSPS 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 9.6 19.2 28.8 38.4 0 9.6 19.2 28.8 38.4 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. 32K FFT WCDMA Carrier @ F = 96 MHz; Sample Rate = 76.8 MSPS Figure 25. Two 32K FFT WCDMA Carriers @ IN F = 76.8 MHz; Sample Rate = 61.44 MSPS IN Rev. D | Page 15 of 32 AMPLITUDE (dBFS) SNR/SFDR (dBc) SNR (dBc) 03583-059 03583-037 03583-036 AMPLITUDE (dBFS) SFDR (dBc) AMPLITUDE (dBFS) 03583-061 03583-060 03583-038 AD9245 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 73.4dBc SNR = 72.7dBc –20 –20 ENOB = 11.9 BITS ENOB = 11.7 BITS SFDR = 88.3dBc SFDR = 81.3dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 0 246 8 10 12 14 16 18 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz 1.0 2.0 0.8 1.5 0.6 1.0 0.4 0.5 0.2 0 0 –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –2.0 –1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 27. AD9245-65 Typical INL Figure 30. AD9245-65 Typical DNL 2.0 1.0 0.8 1.5 0.6 1.0 0.4 0.5 0.2 0 0 –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –2.0 –1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 28. AD9245-40 Typical INL Figure 31. AD9245-40 Typical DNL Rev. D | Page 16 of 32 INL (LSB) AMPLITUDE (dBFS) INL (LSB) 03583-064 03583-063 03583-062 DNL (LSB) DNL (LSB) AMPLITUDE (dBFS) 03583-067 03583-066 03583-065 AD9245 2.0 1.0 0.8 1.5 0.6 1.0 0.4 0.5 0.2 0 0 –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –2.0 –1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 32. AD9245-20 Typical INL Figure 35. AD9245-20 Typical DNL 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 73.4dBc SNR = 73.3dBc –20 ENOB = 11.9 BITS –20 ENOB = 11.9 BITS SFDR = 95.0dBc SFDR = 92.6dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 123 45 6 7 8 9 10 0 12345 6 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz 75 10004707 –0.5dBFS 70 7996189 –6dBFS 7281624 65 60 3167101 1755666 55 547498 –20dBFS 253625 N–3 N–2 N–1 N N+1 N+2 N+3 50 1 10 100 CODE INPUT FREQUENCY (MHz) Figure 37. AD9245-20 Grounded-Input Histogram Figure 34. AD9245-20 SINAD vs. Input Frequency Rev. D | Page 17 of 32 SINAD (dBc) AMPLITUDE (dBFS) INL (LSB) 03583-070 03583-069 AMPLITUDE (dBFS) DNL (LSB) HITS 03583-073 03583-072 03583-071 AD9245 THEORY OF OPERATION The AD9245 architecture consists of a front-end sample-and- Referring to Figure 39, the clock signal alternately switches the hold amplifier (SHA) followed by a pipelined switched capacitor SHA between sample mode and hold mode. When the SHA is ADC. The pipelined ADC is divided into three sections switched into sample mode, the signal source must be capable consisting of a 4-bit first stage followed by eight 1.5-bit stages, of charging the sample capacitors and settling within one-half and a final 3-bit flash. Each stage provides sufficient overlap to of a clock cycle. A small resistor in series with each input can correct for flash errors in the preceding stages. The quantized help reduce the peak transient current required from the output outputs from each stage are combined into a final 14-bit result stage of the driving source. In addition, a small shunt capacitor in the digital correction logic. The pipelined architecture can be placed across the inputs to provide dynamic charging permits the first stage to operate on a new input sample, while currents. This passive network creates a low-pass filter at the the remaining stages operate on preceding samples. Sampling ADC’s input; therefore, the precise values are dependent upon occurs on the rising edge of the clock. the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with Each stage of the pipeline, excluding the last, consists of a low the driving source impedance, they would limit the input resolution flash ADC connected to a switched capacitor DAC bandwidth. and interstage residue amplifier (MDAC). The residue amplifier H magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of T T redundancy is used in each stage to facilitate digital correction 5pF VIN+ of flash errors. The last stage simply consists of a flash ADC. C PAR The input stage contains a differential SHA that can be ac-coupled or dc-coupled in differential or single-ended modes. T 5pF The output staging block aligns the data, carries out the error VIN– correction, and passes the data to the output buffers. The output C PAR T buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output H buffers go into a high impedance state. Figure 39. Switched-Capacitor SHA Input ANALOG INPUT AND REFERENCE OVERVIEW For best dynamic performance, the source impedances driving The analog input to the AD9245 is a differential switched- VIN+ and VIN– should be matched such that common-mode capacitor SHA that has been designed for optimum performance settling errors are symmetrical. These errors are reduced by the while processing a differential input signal. The SHA input can common-mode rejection of the ADC. support a wide common-mode range (VCM) and maintain excellent performance, as shown in Figure 38. An input An internal differential reference buffer creates positive and common-mode voltage of midsupply minimizes signal- negative reference voltages, REFT and REFB, that define the dependent errors and provides optimum performance. span of the ADC core. The output common mode of the 100 reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: 95 SFDR (2.5MHz) REFT = ½ (AVDD + VREF) 90 REFB = ½ (AVDD − VREF) 85 SFDR (39MHz) Span = 2 × (REFT − REFB) = 2 × VREF 80 75 SNR (2.5MHz) The previous equations show that the REFT and REFB voltages 70 SNR (39MHz) are symmetrical about the midsupply voltage, and, by definition, the input span is twice the value of the VREF voltage. 65 60 The internal voltage reference can be pin strapped to fixed 55 values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. 50 0.5 1.0 1.5 2.0 2.5 3.0 Maximum SNR performance is achieved with the AD9245 set COMMON-MODE LEVEL (V) to the largest input span of 2 V p-p. The relative SNR degradation Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. Rev. D | Page 18 of 32 SNR/SFDR (dBc) 03583-039 03583-012 AD9245 The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference AVDD 33Ω voltage. The minimum and maximum common-mode input VIN+ levels are defined as 2V p-p 49.9Ω 20pF AD9245 VREF VCM = 33Ω MIN VIN– 2 AGND () AVDD+VREF VCM = 1kΩ MAX 2 0.1μF 1kΩ The minimum common-mode input level allows the AD9245 to accommodate ground referenced inputs. Figure 41. Differential Transformer-Coupled Configuration Although optimum performance is achieved with a differential The signal characteristics must be considered when selecting input, a single-ended source can be applied to VIN+ or VIN–. a transformer. Most RF transformers saturate at frequencies In this configuration, one input accepts the signal, while the below a few MHz, and excessive signal power can also cause opposite input is set to midscale by connecting it to an core saturation, which leads to distortion. appropriate reference. For example, a 2 V p-p signal can be applied to VIN+ while a 1 V reference is applied to VIN–. The Single-Ended Input Configuration AD9245 then accepts an input signal varying between 2 V and A single-ended input can provide adequate performance in 0 V. In the single-ended configuration, distortion performance cost-sensitive applications. In this configuration, there is a can degrade significantly as compared to the differential case. degradation in SFDR and distortion performance due to the However, the effect is less noticeable at lower input frequencies. large input common-mode swing (see Figure 13). However, if Differential Input Configurations the source impedances on each input are matched, there should be little effect on SNR performance. Figure 42 details a typical As previously detailed, optimum performance is achieved while single-ended input configuration. driving the AD9245 in a differential input configuration. For baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The 1kΩ AVDD output common-mode voltage of the AD8351 is easily set to 33Ω VIN+ AVDD/2, and the driver can be configured in a Sallen-Key filter 0.33μF 2V p-p 49.9Ω 1kΩ 20pF topology to provide band limiting of the input signal. AD9245 1kΩ 33Ω + VIN– 1kΩ 1.2kΩ 10μF 0.1μF AGND AVDD 0.1μF 1kΩ 0.1μF 33Ω VIN+ 2V p-p 50Ω 20pF 25Ω AD8351 AD9245 Figure 42. Single-Ended Input Configuration 0.1μF 33Ω VIN– 0.1μF 25Ω CLOCK INPUT CONSIDERATIONS AGND 1kΩ Typical high speed ADCs use both clock edges to generate a Figure 40. Differential Input Configuration Using the AD8351 variety of internal timing signals, and as a result can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the At input frequencies in the second Nyquist zone and above, the clock duty cycle to maintain dynamic performance characteristics. performance of most amplifiers is not adequate to achieve the The AD9245-80 and AD9245-65 contain a clock duty cycle true performance of the AD9245. This is especially true in IF stabilizer (DCS) that retimes the nonsampling edge, providing an undersampling applications where frequencies in the 70 MHz to internal clock signal with a nominal 50% duty cycle. This allows a 100 MHz range are being sampled. For these applications, wide range of clock input duty cycles without affecting the differential transformer coupling is the recommended input performance of the AD9245. As shown in Figure 21, noise and configuration. The value of the shunt capacitor is dependent on distortion performance is nearly flat for a 30% to 70% duty cycle the input frequency and source impedance and should be with the DCS on. reduced or removed. An example is shown in Figure 41. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Rev. D | Page 19 of 32 03583-013 03583-015 03583-014 AD9245 which is determined by the sample rate and the characteristics JITTER CONSIDERATIONS of the analog input signal. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input 450 frequency (fINPUT) due only to aperture jitter (tJ) can be 400 calculated with the following equation: AD9245-80 SNR = −20log [2π f × t ] 350 10 INPUT j In the equation, the rms aperture jitter represents the root- 300 AD9245-65 mean square of all jitter sources, which include the clock input, 250 analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter 200 (see Figure 43). AD9245-40 150 The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9245-20 100 AD9245. Power supplies for clock drivers should be separated 50 from the ADC output driver supplies to avoid modulating the 0 10 2030 4050 60 70 80 clock signal with digital noise. Low jitter, crystal-controlled SAMPLE RATE (MSPS) oscillators make the best clock sources. If the clock is generated Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz from another type of source (by gating, dividing, or other Reducing the capacitive load presented to the output drivers can methods), it should be retimed by the original clock at the last step. Figure 44 was minimize digital power consumption. The data in 75 taken with the same operating conditions as those reported in 0.2ps the Typical Performance Characteristics section, and with a 70 5 pF load on each output driver. MEASURED SNR 65 By asserting the PDWN pin high, the AD9245 is placed in 0.5ps standby mode. In this state, the ADC typically dissipates 60 1 mW if the CLK and analog inputs are static. During standby, 1.0ps the output drivers are placed in a high impedance state. 1.5ps 55 Reasserting the PDWN pin low returns the AD9245 to its 2.0ps normal operational mode. 2.5ps 50 3.0ps Low power dissipation in standby mode is achieved by shutting 45 down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when 40 entering standby mode and then must be recharged when 1 10 100 1000 returning to normal operation. As a result, the wake-up time is INPUT FREQUENCY (MHz) related to the time spent in standby mode, and shorter standby Figure 43. SNR vs. Input Frequency and Jitter cycles result in proportionally shorter wake-up times. With the POWER DISSIPATION AND STANDBY MODE recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 second to fully discharge the As shown in Figure 44, the power dissipated by the AD9245 is reference buffer decoupling capacitors and 7 ms to restore full proportional to its sample rate. The digital power dissipation is operation. determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current DIGITAL OUTPUTS (I ) can be calculated as DRVDD The AD9245 output drivers can be configured to interface with I =V ×C × f ×N DRVDD DRVDD LOAD CLK 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to where N is the number of output bits, 14 in the case of the provide sufficient output current to drive a wide variety of logic AD9245. This maximum current occurs when every output bit families. However, large drive currents tend to cause current switches on every clock cycle, that is, a full-scale square wave at glitches on the supplies, which can affect converter performance. the Nyquist frequency, fCLK/2. In practice, the DRVDD current Applications requiring the ADC to drive large capacitive loads or is established by the average number of output bits switching, large fanouts can require external buffers or latches. Rev. D | Page 20 of 32 SNR (dBc) 03583-041 TOTAL POWER (mW) 03583-074 AD9245 As detailed in Table 11, the data format can be selected for either In all reference configurations, REFT and REFB drive the A/D offset binary or twos complement. conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for TIMING either an internal or an external reference. The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation VIN+ delay (t ) after the rising edge of the clock signal. Refer to PD VIN– Figure 2 for a detailed timing diagram. REFT 0.1μF The length of the output data lines and the loads placed on + ADC 0.1μF 10μF CORE them should be minimized to reduce transients within the REFB AD9245. These transients can degrade the converter’s dynamic 0.1μF performance. VREF + The lowest typical conversion rate of the AD9245 is 1 MSPS. At 10μF 0.1μF SELECT clock rates below 1 MSPS, dynamic performance can degrade. LOGIC SENSE VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the 0.5V AD9245. The input range can be adjusted by varying the reference voltage applied to the AD9245 using either the AD9245 internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes Figure 45. Internal Reference Configuration linearly. The various reference modes are summarized in Table 10 If the internal reference of the AD9245 is used to drive multiple and described in the following sections. converters to improve gain matching, the loading of the reference If the ADC is being driven differentially through a transformer, by the other converters must be considered. Figure 46 depicts the reference voltage can be used to bias the center tap how the internal reference voltage is affected by loading. A (common-mode voltage). 2 mA load is the maximum recommended load. 0.05 INTERNAL REFERENCE CONNECTION A comparator within the AD9245 detects the potential at the 0 SENSE pin and configures the reference into one of four possible states, which are summarized in Table 10. If SENSE is –0.05 grounded, the reference amplifier switch is connected to the 0.5V ERROR (%) internal resistor divider (see Figure 45), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference –0.10 amplifier output to the SENSE pin, completing the loop and 1.0V ERROR (%) providing a 0.5 V reference output. If a resistor divider is –0.15 connected as shown in Figure 47, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting –0.20 mode with the VREF output defined as R2 –0.25 ⎛ ⎞ VREF=0 .5× 1+ ⎜ ⎟ 0 0.5 1.0 1.5 2.0 2.5 3.0 ⎝ R1⎠ LOAD (mA) Figure 46. VREF Accuracy vs. Load Table 10. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF R2 2 × VREF ⎛ ⎞ (See Figure 47) 0.5× 1+ ⎜ ⎟ ⎝ R1⎠ Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. D | Page 21 of 32 ERROR (%) 03583-017 03583-019 AD9245 OPERATIONAL MODE SELECTION VIN+ As discussed earlier, the AD9245 can output data in either VIN– REFT offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The 0.1μF ADC + 0.1μF 10μF CORE MODE pin is a multilevel input that controls the data format REFB and DCS state. The input threshold values and corresponding 0.1μF mode selections are outlined in Table 11. VREF + Table 11. Mode Selection 10μF 0.1μF SELECT R2 LOGIC MODE Voltage Data Format Duty Cycle Stabilizer SENSE AVDD Twos Complement Disabled 2/3 AVDD Twos Complement Enabled R1 0.5V 1/3 AVDD Offset Binary Enabled AGND (Default) Offset Binary Disabled AD9245 EVALUATION BOARD Figure 47. Programmable Reference Configuration The AD9245 evaluation board provides the support circuitry required to operate the ADC in its various modes and EXTERNAL REFERENCE OPERATION configurations. Complete schematics and layout plots follow The use of an external reference can be necessary to enhance and demonstrate the proper routing and grounding techniques the gain accuracy of the ADC or improve thermal drift char- that should be applied at the system level. acteristics. When multiple ADCs track one another, a single reference (internal or external) can be necessary to reduce It is critical that signal sources with very low phase noise gain matching errors to an acceptable level. Figure 48 shows (<1 ps rms jitter) be used to realize the ultimate performance of the typical drift characteristics of the internal reference in both the converter. Proper filtering of the input signal, to remove 1.0 V and 0.5 V modes. harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal The AD9245 can be driven single-ended or differentially reference buffer loads the external reference with an equivalent through a transformer. Separate power pins are provided to 7 kΩ load. The internal buffer still generates the positive and isolate the DUT from the support circuitry. Each input negative full-scale references, REFT and REFB, for the ADC configuration can be selected by proper connection of core. The input span is always twice the value of the reference various jumpers (refer to the schematics). voltage; therefore, the external reference must be limited to a maximum of 1.0 V. An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated 1.0 in production. Designers interested in evaluating the op amp 0.9 with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 0.8 outputs and the AD9245 allows the user to optimize the 0.7 frequency response of the op amp for the application. 0.6 0.5 0.4 0.3 VREF = 1.0V 0.2 0.1 VREF = 0.5V 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 48. Typical VREF Drift Rev. D | Page 22 of 32 VREF ERROR (%) 03583-018 03583-040 AD9245 Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT Rev. D | Page 23 of 32 GND H1 MTHOLE6 H2 MTHOLE6 R5 H3 1k MTHOLE6 H4 MTHOLE6 R7 1k R6 1k OVERRANGE BIT RP2 220 (MSB) 1 16 DRX 2 15 D13X 3 14 D12X FOR SINGLE ENDED INPUT 4 13 PLACE R18, R19, R42, C6, AND C18. D11X REMOVE R3, R12, C15, C17, AND C27 5 12 D10X 6 11 D9X 7 10 R42 C6 D8X R12, R42, C17 0 8 9 0.1 F ONLY ONE SHOULD BE D7X DRVDD AVDD GND DVDD 16 ON BOARD AT A TIME REFT R36 R26 GND DGND 15 MPIN 1k A 1k AVDD AVDD D9 14 AGND R12 GND D8 3 1 0 VIN+ 1 16 VIN+ D6X D7 12 VIN– X R4 VIN– 2 15 D5X D6 11 33 3 14 AGND 4X C21 GND D D5 10 4 13 AVDD 10pF AVDD D3X L1 R10 D4 9 5 12 J1 10nH D2X 36 C26 GND 6 11 E 45 D1X 10pF C15 7 10 GND D0X 0.1 F AMP 8 9 GND C16 R2 C19 GND 20pF (LSB) 0.1 F C5 DNP PRI SEC OR L1 GND 0.1 F FOR FILTER RP1 220 R11 GND GND 36 SENSE PIN SOLDERABLE JUMPER: E TO A: EXTERNAL VOLTAGE DIVIDER X B C23 E TO B: INTERNAL 1V REFERENCE (DEFAULT) 10pF R3 E TO C: EXTERNAL REFERENCE CLK X X FRIN R8 0 E TO D: INTERNAL 0.5V REFERENCE 1k CT AMPINB R15 RABLE JUMPER: MODE PIN SOLDE GND X B 33 5 TO 1: TWOS COMPLEMENT/DCS OFF PRI SEC GND 5 TO 2: TWOS COMPLEMENT/DCS ON C18 AVDD 5 TO 3: OFFSET BINARY/DCS ON 0.10 F / CS OFF 5 TO 4: OFFSET BINARY D AVDD GND R13 R25 1k 1k GND EXTREF AVDD 1 1V MAX E1 P6 AVDD 12 3 45 6 GND Ω P11 R1 P9 P8 C22 C13 10kΩ MODE 10μF 0.10μF 2 2 P7 A B C D P5 P1 E GND GND Ω P10 3 0.1μF P3 R9 C8 10kΩ C12 0.1μF Ω GND C9 GND GND 4 0.10μF GND Ω P4 C29 0.1μF 10μF C11 GND C7 0.1μF GND Ω μ 25 REFB 26 Ω Ω 27 AD9245 28 U4 Ω 29 30 OUT Ω 31 T 1 32 ADT1–1WT Ω XFRIN1 1 6 5 2 CT NC μ 34 μ μ Ω Ω OPTIONAL XFR T2 OUT FT C1–1–13 1 5 OUT 2 Ω Ω 3 4 OUT Ω P14 P13 μ R18 R SINGLE ENDED 25Ω R3, R16, C18 ONLY ONE SHOULD BE Ω Ω ON BOARD AT A TIME 03583-050 1 24 DNC VREF 2 SENSE 23 CLK 3 22 MODE DNC 4 21 PDWN OTR 5 20 D0 D13 6 19 D1 D12 7 D2 18 D11 8 17 D3 D10 3.0V AVDD GND 2.5V DRVDD GND 2.5V VDL VAMP 5.0V P2 AD9245 Figure 50. LFCSP Evaluation Board Schematic—Digital Path Rev. D | Page 24 of 32 374 74LVTH162 U1 P12 GND CLKAT/DAC 25 24 MSB DRY 2 1 23 26 1 GND 2 4 3 27 22 DR 3 4 GND 6 5 28 21 5 6 MSB GND 8 7 29 20 7 8 10 9 30 19 9 10 V DRVDD 12 11 31 18 11 12 14 13 32 17 13 14 16 15 33 16 15 16 GND 18 17 15 34 17 18 20 19 35 14 19 20 22 21 36 13 21 22 24 23 37 12 23 24 26 25 38 11 25 26 GND GND 28 27 39 10 27 28 30 29 40 9 29 30 32 31 41 8 31 32 V DRVDD 34 33 7 42 33 1Q4 34 36 35 43 6 DRY 1Q3 35 36 38 37 44 5 37 GND GND 38 40 39 45 4 39 40 LSB 46 3 47 2 GND GND KLAT/DAC 1 CL GND 48 1 IN OUT R38 R39 1k k 1 GND VAMP VAMP C24 10 F D GN ER DOWN POW 0 OR R41 USE R4 ND GND G TO USE AMPLIFIER C44 C45 PLACE ALL COMPONENTS 0.1 F VAMP GND 0.1 F SHOWN HERE (RIGHT) EXCEPT R40 OR R41. REMOVE R12, R3, R18, R42, R41 R40 C6, C15, AND C18. 10k 10k R14 PWDN 1 VOCM 10 25 RGP1 2 9 VPOS C28 AMP IN 1 F 0. INHI 3 8 OPHI PINB AM AMP R16 C27 7 OPLO 0 0.1 F INLO 4 R19 C35 50 0.10 F COMM AMPIN RPG2 5 6 R33 C17 GND R17 R35 25 0.1 F R34 0 25 1.2k GND G GN ND D 2CLK 2OE DRX 2DB 2QB D13X 2D7 2Q7 GND GND GND 2D6 2Q6 D12X 2D5 2Q5 D11X DRVDD V CC CC 2D4 2Q4 D10X 2D3 2Q3 D9X GND GND GND D8X 2D2 2Q2 D7X 2D1 2Q1 D6X 1Q8 1D8 D5X 1D7 1Q7 GND GND 1D6 1Q6 D4X 1D5 1Q5 D3X V DRVDD CC CC 1D4 D2X D1X 1D3 GND GND D0X 1D2 1Q2 1D1 1Q1 1CLK 1OE Ω Ω μ μ μ Ω Ω U3 AD8351 Ω μ Ω μ Ω μ Ω Ω μ Ω Ω 03583-051 AD9245 Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev. D | Page 25 of 32 VDL DRVDD AVDD AVDD DRVDD VDL C32 C41 C48 C25 C33 C14 C31 C34 C36 C38 C39 C1 C47 C30 0.001μF 0.1μF 0.001μF 0.1μF C2 0.001μF 10μF C4 0.1μF 0.1μF 0.1μF 0.001μF 0.001μF 0.1μF 0.1μF 0.001μF C37 C10 C3 10μF C49 C40 10μF 0.1μF C20 10μF 10μF 0.001μF 0.001μF 10μF GND GND GND GND ANALOG BYPASSING DIGITAL BYPASSING L LA AT TCH BYP CH BYPASSING ASSING DUT BYPASSING VAMP C46 10μF CLOCK TIMING ADJUSTMENTS GND FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 CLK R28 0Ω ENCX ENC 74VCX86 ENCX SCHEMATIC SHOWS TWO GATE DELAY SETUP. ENC E50 E51 FOR ONE DELAY, REMOVE R22 AND R37 AND R27 1 3 1Y ATTACH Rx (Rx = 0Ω). 0Ω 2 6 R32 4 7 R23 2Y 1kΩ GND Rx 0Ω R37 5 GND 8 CLKLAT/DAC DNP 0Ω 9 11 3Y DR VDL GND 10 14 VDL PWR 12 4Y 13 VDL E52 E53 R22 U5 0Ω R31 VDL R20 C43 1kΩ 1kΩ 0.1μF ENCODE GND J2 R29 R30 E31 E35 50Ω 1kΩ R21 1kΩ GND GND VDL GND GND E43 E44 R24 1kΩ VDL GND 03583-052 1A 1B 2A 2B 3A 3B 4A 4 B AD9245 Figure 52. LFCSP Evaluation Board Layout, Primary Side Figure 54. LFCSP Evaluation Board Layout, Ground Plane Figure 53. LFCSP Evaluation Board Layout, Secondary Side Figure 55. LFCSP Evaluation Board Layout, Power Plane Rev. D | Page 26 of 32 03583-054 03583-053 03583-056 03583-055 AD9245 Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. D | Page 27 of 32 03583-057 03583-058 AD9245 Table 12. LFCSP Evaluation Board Bill of Materials Recommended Supplied 1 Item Qty. Omit Reference Designator Device Package Value Vendor/Part No. by ADI 1 18 C1, C5, C7, C8, C9, C11, C12, Chip Capacitors 0603 0.1 μF C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C17, C18, C27, C28, C35, C45, C44 2 8 C2, C3, C4, C10, C20, Tantalum Capacitors TAJC 10 μF C22, C25, C29 2 C24, C46 3 8 C14, C30, C32, C38, Chip Capacitors 0603 0.001 μF C39, C40, C48, C49 4 1 C19 Chip Capacitors 0603 20 pF 5 1 C26 Chip Capacitors 0603 10 pF 2 C21, C23 6 9 E31, E35, E43, E44, Headers EHOLE Jumper Blocks E50, E51, E52, E53 2 E1, E45 7 2 J1, J2 SMA Connectors/50 Ω SMA 8 1 L1 Inductor 0603 10 nH Coilcraft/ 0603CS-10NXGBU 9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0, z5-530-0625-0 10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND 11 5 R3, R12, R23, R28, Rx Chip Resistors 0603 0 Ω 6 R16, R17, R22, R27, R42, R37 12 2 R4, R15 Chip Resistors 0603 33 Ω 13 14 R5, R6, R7, R8, R13, R20, R21, Chip Resistors 0603 1 kΩ R24, R25, R26, R30, R31, R32, R36 14 2 R10, R11 Chip Resistors 0603 36 Ω 15 1 R29 Chip Resistors 0603 50 Ω 1 R19 16 2 RP1, RP2 Resistor Packs R_742 220 Ω Digi-Key CTS/742C163221JTR 17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits 18 1 U1 74LVTH162374 CMOS Register TSSOP-48 19 1 U4 AD9245BCP ADC (DUT) LFCSP-32 Analog Devices, Inc. X 20 1 U5 74VCX86M SOIC-14 Fairchild 21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X 22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X 23 1 T2 M/A-COM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13 24 5 R1, R2, R9, R38, R39 Chip Resistors 0603 SELECT 25 3 R14, R18, R35 Chip Resistors 0603 25 Ω 26 2 R40, R41 Chip Resistors 0603 10 kΩ 27 1 R34 Chip Resistor 1.2 kΩ 28 1 R33 Chip Resistor 25 Ω Total 81 35 1 These items are included in the PCB design, but are omitted at assembly. Rev. D | Page 28 of 32 AD9245 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP 3.25 4.75 EXPOSED VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.20 REF 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9245BCP-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9245BCPRL7–80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 2 AD9245BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9245BCP-80EB Evaluation Board AD9245BCP-65EB Evaluation Board AD9245BCP-40EB Evaluation Board AD9245BCP-20EB Evaluation Board 1 It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. 2 Z = Pb-free part. Rev. D | Page 29 of 32 AD9245 NOTES Rev. D | Page 30 of 32 AD9245 NOTES Rev. D | Page 31 of 32 AD9245 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03583–0–1/06(D) Rev. D | Page 32 of 32