ANALOG DEVICES AD9243

Complete 14-Bit, 3.0 MSPS a Monolithic A/D Converter AD9243 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 14-Bit, 3 MSPS A/D Converter CLK AVDD DVDD DRVDD Low Power Dissipation: 110 mW Single +5 V Supply SHA VINA Integral Nonlinearity Error: 2.5 LSB MDAC1 MDAC2 MDAC3 GAIN = 16 GAIN = 8 GAIN = 8 VINB Differential Nonlinearity Error: 0.6 LSB 5 4 4 CML Input Referred Noise: 0.36 LSB A/D A/D A/D A/D CAPT 5 4 4 4 Complete: On-Chip Sample-and-Hold Amplifier and CAPB DIGITAL CORRECTION LOGIC Voltage Reference 14 Signal-to-Noise and Distortion Ratio: 79.0 dB VREF OUTPUT BUFFERS OTR Spurious-Free Dynamic Range: 91.0 dB SENSE BIT 1 (MSB) 1V Out-of-Range Indicator MODE BIT 14 SELECT AD9243 Straight Binary Output Data (LSB) 44-Lead MQFP REFCOM AVSS DVSS DRVSS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9243 is a 3 MSPS, single supply, 14-bit analog-to- The AD9243 offers a complete single-chip sampling 14-bit, digital converter (ADC). It combines a low cost, high speed analog-to-digital conversion function in a 44-lead Metric Quad CMOS process and a novel architecture to achieve the resolution Flatpack. and speed of existing hybrid implementations at a fraction of the Low Power and Single Supply power consumption and cost. It is a complete, monolithic ADC The AD9243 consumes only 110 mW on a single +5 V power with an on-chip, high performance, low noise sample-and-hold supply. amplifier and programmable voltage reference. An external refer- Excellent DC Performance Over Temperature ence can also be chosen to suit the dc accuracy and temperature The AD9243 provides no missing codes, and excellent tempera- drift requirements of the application. The device uses a multistage ture drift performance over the full operating temperature range. differential pipelined architecture with digital output error correc- tion logic to guarantee no missing codes over the full operating Excellent AC Performance and Low Noise temperature range. The AD9243 provides nearly 13 ENOB performance and has an input referred noise of 0.36 LSB rms. The input of the AD9243 is highly flexible, allowing for easy Flexible Analog Input Range interfacing to imaging, communications, medical, and data- The versatile onboard sample-and-hold (SHA) can be configured acquisition systems. A truly differential input structure allows for either single ended or differential inputs of varying input spans. for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) is equally Flexible Digital Outputs suited for both multiplexed systems that switch full-scale voltage The digital outputs can be configured to interface with +3 V and levels in successive channels as well as sampling single-channel +5 V CMOS logic families. inputs at frequencies up to and beyond the Nyquist rate. Also, the AD9243 performs well in communication systems employ- ing Direct-IF Down Conversion since the SHA in the differen- tial input mode can achieve excellent dynamic performance well beyond its specified Nyquist frequency of 1.5 MHz. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 781/326-8703 © Analog Devices, Inc., 1998 otherwise under any patent or patent rights of Analog Devices. AD9243–SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = 3 MSPS, VREF = 2.5 V, VINB = 2.5 V, T to T unless SAMPLE MIN MAX DC SPECIFICATIONS otherwise noted) Parameter AD9243 Units RESOLUTION 14 Bits min MAX CONVERSION RATE 3 MHz min INPUT REFERRED NOISE V = 1 V 0.9 LSB rms typ REF V = 2.5 V 0.36 LSB rms typ REF ACCURACY Integral Nonlinearity (INL) ±2.5 LSB typ Differential Nonlinearity (DNL) ±0.6 LSB typ ±1.0 LSB max 1 INL ±2.5 LSB typ 1 DNL ±0.7 LSB typ No Missing Codes 14 Bits Guaranteed Zero Error (@ +25°C) 0.3 % FSR max 2 Gain Error (@ +25°C) 1.5 % FSR max 3 Gain Error (@ +25°C) 0.75 % FSR max TEMPERATURE DRIFT Zero Error 3.0 ppm/°C typ 2 20.0 ppm/°C typ Gain Error 3 Gain Error 5.0 ppm/°C typ POWER SUPPLY REJECTION 0.1 % FSR max ANALOG INPUT Input Span (with V = 1.0 V) 2 V p-p min REF Input Span (with V = 2.5 V) 5 V p-p max REF Input (VINA or VINB) Range 0 V min AVDD V max Input Capacitance 16 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1 Volts typ Output Voltage Tolerance (1 V Mode) ±14 mV max Output Voltage (2.5 V Mode) 2.5 Volts typ Output Voltage Tolerance (2.5 V Mode) ±35 mV max 4 Load Regulation 2.0 mV max REFERENCE INPUT RESISTANCE 5 kΩ typ POWER SUPPLIES Supply Voltages AVDD +5 V (±5% AVDD Operating) DVDD +5 V (±5% DVDD Operating) DRVDD +5 V (±5% DRVDD Operating) Supply Current IAVDD 23.0 mA max (20 mA typ) IDRVDD 1.0 mA max (0.5 mA typ) IDVDD 5.0 mA max (3.5 mA typ) POWER CONSUMPTION 110 mW typ 145 mW max NOTES 1 V =1 V. REF 2 Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9243). Specification subject to change without notice. –2– REV. A AD9243 (AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, f = 3 MSPS, VREF = 2.5 V, A = –0.5 dBFS, AC Coupled/ SAMPLE IN AC SPECIFICATIONS Differential Input, T to T unless otherwise noted) MIN MAX Parameter AD9243 Units SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) f = 500 kHz 75.0 dB min INPUT 79.0 dB typ f = 1.5 MHz 77.0 dB typ INPUT EFFECTIVE NUMBER OF BITS (ENOB) f = 500 kHz 12.3 Bits min INPUT 12.8 Bits typ f = 1.5 MHz 12.5 Bits typ INPUT SIGNAL-TO-NOISE RATIO (SNR) f = 500 kHz 76.0 dB min INPUT 80.0 dB typ f = 1.5 MHz 79.0 dB typ INPUT TOTAL HARMONIC DISTORTION (THD) f = 500 kHz –78.0 dB max INPUT –87.0 dB typ f = 1.5 MHz –82.0 dB typ INPUT SPURIOUS FREE DYNAMIC RANGE f = 500 kHz 91.0 dB typ INPUT f = 1.5 MHz 84.0 dB typ INPUT DYNAMIC PERFORMANCE Full Power Bandwidth 40 MHz typ Small Signal Bandwidth 40 MHz typ Aperture Delay 1 ns typ Aperture Jitter 4 ps rms typ Acquisition to Full-Scale Step (0.0025%) 80 ns typ Overvoltage Recovery Time 167 ns typ Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, T to T unless otherwise noted) MIN MAX Parameters Symbol AD9243 Units LOGIC INPUTS High Level Input Voltage V +3.5 V min IH Low Level Input Voltage V +1.0 V max IL High Level Input Current (V = DVDD) I ±10 μA max IN IH Low Level Input Current (V = 0 V) I ±10 μA max IN IL Input Capacitance C 5 pF typ IN LOGIC OUTPUTS (with DRVDD = 5 V) = 50 μA) V +4.5 V min High Level Output Voltage (I OH OH = 0.5 mA) V +2.4 V min High Level Output Voltage (I OH OH = 1.6 mA) V +0.4 V max Low Level Output Voltage (I OL OL = 50 μA) V +0.1 V max Low Level Output Voltage (I OL OL Output Capacitance C 5 pF typ OUT LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (I = 50 μA) V +2.4 V min OH OH Low Level Output Voltage (I = 50 μA) V +0.7 V max OL OL Specifications subject to change without notice. –3– REV. A AD9243 (T to T with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, C = 20 pF) MIN MAX L SWITCHING SPECIFICATIONS Parameters Symbol AD9243 Units 1 t 333 ns min Clock Period C 150 ns min CLOCK Pulsewidth High t CH 150 ns min CLOCK Pulsewidth Low t CL 8 ns min Output Delay t OD 13 ns typ 19 ns max Pipeline Delay (Latency) 3 Clock Cycles NOTES 1 The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C. Specifications subject to change without notice. THERMAL CHARACTERISTICS S1 S2 Thermal Resistance ANALOG S4 t C 44-Lead MQFP INPUT S3 t t CH CL θ = 53.2°C/W JA = 19°C/W θ INPUT JC CLOCK t OD ORDERING GUIDE DATA DATA 1 OUTPUT Temperature Package Package Model Range Description Option* Figure 1. Timing Diagram AD9243AS –40°C to +85°C 44-Lead MQFP S-44 AD9243EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* *S = Metric Quad Flatpack. With Respect Parameter to Min Max Units PIN CONNECTIONS AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V 44 43 42 41 40 39 38 37 36 35 34 DRVDD DRVSS –0.3 +6.5 V DRVSS AVSS –0.3 +0.3 V DVSS 1 33 REFCOM PIN 1 REFCOM AVSS –0.3 +0.3 V 2 IDENTIFIER 32 AVSS VREF CLK DVSS –0.3 DVDD + 0.3 V 3 31 DVDD SENSE Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AVDD 4 30 NC VINA, VINB AVSS –0.3 AVDD + 0.3 V 5 29 DRVSS AVSS AD9243 VREF AVSS –0.3 AVDD + 0.3 V DRVDD 6 28 AVDD TOP VIEW SENSE AVSS –0.3 AVDD + 0.3 V (Not to Scale) 7 CLK 27 NC CAPB, CAPT AVSS –0.3 AVDD + 0.3 V NC 8 NC 26 Junction Temperature +150 °C 9 NC 25 OTR Storage Temperature –65 +150 °C NC 10 BIT 1 (MSB) 24 Lead Temperature 11 (LSB) BIT 14 23 BIT 2 (10 sec) +300 °C 12 13 14 15 16 17 18 19 20 21 22 *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings NC = NO CONNECT for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9243 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. A BIT 13 NC BIT 12 NC BIT 11 VINB BIT 10 VINA BIT 9 NC BIT 8 CML BIT 7 NC BIT 6 CAPT BIT 5 CAPB BIT 4 NC BIT 3 NC AD9243 PIN DESCRIPTION overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range. Pin Number Name Description TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the 1 DVSS Digital Ground maximum change from the initial (+25°C) value to the value at 2, 29 AVSS Analog Ground T or T . MIN MAX 3 DVDD +5 V Digital Supply 4, 28 AVDD +5 V Analog Supply POWER SUPPLY REJECTION 5 DRVSS Digital Output Driver Ground The specification shows the maximum change in full scale from 6 DRVDD Digital Output Driver Supply the value with the supply at the minimum limit to the value 7 CLK Clock Input Pin with the supply at its maximum limit. 8–10 NC No Connect APERTURE JITTER 11 BIT 14 Least Significant Data Bit (LSB) Aperture jitter is the variation in aperture delay for successive 12–23 BIT 13–BIT 2 Data Output Bits samples and is manifested as noise on the input to the A/D. 24 BIT 1 Most Significant Data Bit (MSB) 25 OTR Out of Range APERTURE DELAY 26, 27, 30 NC No Connect Aperture delay is a measure of the sample-and-hold amplifier 31 SENSE Reference Select (SHA) performance and is measured from the rising edge of the 32 VREF Reference I/O clock input to when the input signal is held for conversion. 33 REFCOM Reference Common 34, 35, 38 NC No Connect SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) 40, 43, 44 RATIO 36 CAPB Noise Reduction Pin S/N+D is the ratio of the rms value of the measured input sig- 37 CAPT Noise Reduction Pin nal to the rms sum of all other spectral components below the 39 CML Common-Mode Level (Midsupply) Nyquist frequency, including harmonics but excluding dc. 41 VINA Analog Input Pin (+) The value for S/N+D is expressed in decibels. 42 VINB Analog Input Pin (–) EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the num- DEFINITIONS OF SPECIFICATION ber of bits. Using the following formula, INTEGRAL NONLINEARITY (INL) N = (SINAD – 1.76)/6.02 INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” it is possible to get a measure of performance expressed as N, The point used as “negative full scale” occurs 1/2 LSB before the effective number of bits. the first code transition. “Positive full scale” is defined as a Thus, effective number of bits for a device for sine wave inputs level 1 1/2 LSB beyond the last code transition. The deviation at a given input frequency can be calculated directly from its is measured from the middle of each particular code to the true measured SINAD. straight line. TOTAL HARMONIC DISTORTION (THD) DIFFERENTIAL NONLINEARITY (DNL, NO MISSING THD is the ratio of the rms sum of the first six harmonic CODES) components to the rms value of the measured input signal and An ideal ADC exhibits code transitions that are exactly 1 LSB is expressed as a percentage or in decibels. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 SIGNAL-TO-NOISE RATIO (SNR) codes, respectively, must be present over all operating ranges. SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the ZERO ERROR Nyquist frequency, excluding the first six harmonics and dc. The major carry transition should occur for an analog value The value for SNR is expressed in decibels. 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the GAIN ERROR input signal and the peak spurious signal. The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should TWO-TONE SFDR occur at an analog value 1 1/2 LSB below the nominal full The ratio of the rms value of either input tone to the rms value scale. Gain error is the deviation of the actual difference of the peak spurious component. The peak spurious component between first and last code transitions and the ideal differ- may or may not be an IMD product. May be reported in dBc ence between first and last code transitions. (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). OVERVOLTAGE RECOVERY TIME Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an REV. A –5– AD9243 (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f SAMPLE Typical Differential AC Characterization Curves/Plots = 3.00 MSPS, T = +258C, Differential Input) A 1 0 90 14.7 –40 –15 13.8 85 –50 –30 80 13.0 –0.5dBFS –45 –60 –20.0dBFS 75 12.2 –60 –6.0dBFS 70 11.3 –75 –70 4 9 3 7 6 2 –90 8 65 10.5 –6.0dBFS –80 5 –105 –20.0dBFS 60 9.7 –120 –0.5dBFS –90 55 8.8 –135 50 8.0 –100 –150 0 1.5 100k 1M 10M 20M 20M 100k 1M 10M FREQUENCY – MHz INPUT FREQUENCY – Hz INPUT FREQUENCY – Hz Figure 2. SINAD vs. Input Frequency Figure 3. THD vs. Input Frequency Figure 4. Typical FFT, f = 500 kHz IN (Input Span = 5 V, V = 2.5 V) (Input Span = 5 V, V = 2.5 V) (Input Span = 5 V, V = 2.5 V) CM CM CM 1 90 0 14.7 –40 –15 85 13.8 –50 –30 13.0 80 –45 –60 –0.5dBFS 12.2 75 –60 –20.0dBFS –6.0dBFS –75 70 11.3 –70 9 4 –90 8 7 5 6 2 65 10.5 –6.0dBFS 3 –80 –105 60 9.7 –120 –0.5dBFS –20.0dBFS –90 55 8.8 –135 50 8.0 –100 –150 100k 1M 10M 20M 0 1.5 100k 1M 10M 20M FREQUENCY – MHz INPUT FREQUENCY – Hz INPUT FREQUENCY – Hz Figure 5. SINAD vs. Input Frequency Figure 6. THD vs. Input Frequency Figure 7. Typical FFT, f = 1.50 MHz IN (Input Span = 2 V, V = 2.5 V) (Input Span = 2 V, V = 2.5 V) (Input Span = 2 V, V = 2.5 V) CM CM CM 110 –60 110 dBFS – 5V 105 –65 5V SPAN - dBFS 100 100 dBFS – 2V –70 90 95 2V SPAN - dBFS –75 90 80 5V SPAN –80 85 70 dBc – 5V 80 –85 5V SPAN - dBc 2V SPAN 60 75 –90 70 2V SPAN - dBc 50 dBc – 2V –95 65 –100 40 60 –60 –50 –40 –30 –20 –10 0 –40 –35 –30 –25 –20 –15 –10 –5 0 0.1 1 5 SAMPLE RATE – MSPS AIN – dBFS INPUT POWER LEVEL (F = F ) – dBFS 1 2 Figure 10. Dual Tone SFDR Figure 8. THD vs. Sample Rate Figure 9. Single Tone SFDR (f = 0.95 MHz, f = 1.04 MHz, (f = 1.5 MHz, A = –0.5 dBFS, (f = 1.5 MHz, V = 2.5 V) 1 2 IN IN IN CM V = 2.5 V) V = 2.5 V) CM CM –6– REV. A THD – dB SINAD – dB SINAD – dB ENOB – Bits ENOB – Bits THD – dB SFDR – dBc AND dBFS THD – dB AMPLITUDE – dB AMPLITUDE – dB WORST CASE SPURIOUS – dBc AND dBFS AD9243 (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = 3.00 MSPS, T = +258C, SAMPLE A Single-Ended Input) Other Characterization Curves/Plots 2.5 1.0 4,343,995 0.8 2.0 0.6 1.5 0.4 1.0 0.2 0.5 0.0 –0.2 0.0 –0.4 –0.5 439,383 356,972 –0.6 –1.0 –0.8 –1.5 –1.0 0 16383 0 16383 N–1 N N+1 CODE CODE CODE Figure 12. Typical DNL Figure 13. “Grounded-Input” Figure 11. Typical INL (Input Span = 5 V) Histogram (Input Span = 5 V) (Input Span = 5 V) –40 90 14.7 20 85 13.8 30 –50 80 13.0 40 –60 –20dBFS 75 12.2 –0.5dBFS 50 –70 70 11.3 –6.0dBFS 60 –6.0dBFS 65 10.5 –80 70 60 9.7 –0.5dBFS –90 80 55 8.8 –20.0dBFS –100 90 50 8.0 0.1 1 10 100 100k 1M 10M 100k 1M 10M INPUT FREQUENCY – Hz FREQUENCY – MHz INPUT FREQUENCY – Hz Figure 14. SINAD vs. Input Frequency Figure 15. THD vs. Input Frequency Figure 16. CMR vs. Input Frequency (Input Span = 2 V, V = 2.5 V) (Input Span = 2 V, V = 2.5 V) (Input Span = 2 V, V = 2.5 V) CM CM CM –40 0.01 90 14.7 0.008 85 13.8 –50 0.006 80 13.0 0.004 –0.5dBFS –60 –20dBFS 75 12.2 0.002 –6.0dBFS 0 70 11.3 –70 –0.5dBFS –0.002 65 10.5 –80 –0.004 –6.0dBFS 60 9.7 –20.0dBFS –0.006 –90 55 8.8 –0.008 50 8.0 –100 –0.01 –60 –40 –20 0 20 40 60 80 100 120 140 100k 1M 10M 100k 1M 10M TEMPERATURE – 8C INPUT FREQUENCY – Hz INPUT FREQUENCY – Hz Figure 19. Typical Voltage Reference Figure 17. SINAD vs. Input Frequency Figure 18. THD vs. Input Frequency Error vs. Temperature (Input Span = 5 V, V = 2.5 V) (Input Span = 5 V, V = 2.5 V) CM CM REV. A –7– INL – LSB SINAD – dB SINAD – dB ENOB – Bits ENOB – Bits DNL – LSB THD – dB THD – dB V ERROR – V REF CMR – dB HITS AD9243 INTRODUCTION Therefore, the equation, The AD9243 utilizes a four-stage pipeline architecture with a V = VINA – VINB (1) CORE wideband input sample-and-hold amplifier (SHA) implemented defines the output of the differential input stage and provides the on a cost-effective CMOS process. Each stage of the pipeline, input to the A/D core. excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue The voltage, V , must satisfy the condition, CORE amplifier (MDAC). The residue amplifier amplifies the differ- –VREF ≤ V ≤ VREF (2) CORE ence between the reconstructed DAC output and the flash input where VREF is the voltage at the VREF pin. for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash er- While an infinite combination of VINA and VINB inputs exist rors. The last stage simply consists of a flash A/D. that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9243. The The pipeline architecture allows a greater throughput rate at the power supplies bound the valid operating range for VINA and expense of pipeline delay or latency. This means that while the VINB. The condition, converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) fully processed and appear at the output. This latency is not a AVSS – 0.3 V < VINB < AVDD + 0.3 V concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output where AVSS is nominally 0 V and AVDD is nominally +5 V, buffer to drive the output pins. The output drivers can be con- defines this requirement. Thus, the range of valid inputs for figured to interface with +5 V or +3.3 V logic families. VINA and VINB is any combination that satisfies both Equa- tions 2 and 3. The AD9243 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing For additional information showing the relationship between requirements). The A/D samples the analog input on the rising VINA, VINB, VREF and the digital output of the AD9243, see edge of the clock input. During the clock low time (between the Table IV. falling edge and rising edge of the clock), the input SHA is in Refer to Table I and Table II for a summary of the various the sample mode; during the clock high time it is in the hold analog input and reference configurations. mode. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to ANALOG INPUT OPERATION acquire the wrong value, and should be minimized. Figure 21 shows the equivalent analog input of the AD9243 which consists of a differential sample-and-hold amplifier (SHA). ANALOG INPUT AND REFERENCE OVERVIEW The differential input structure of the SHA is highly flexible, Figure 20, a simplified model of the AD9243, highlights the rela- allowing the devices to be easily configured for either a differen- tionship between the analog inputs, VINA, VINB, and the tial or single-ended input. The dc offset, or common-mode reference voltage, VREF. Like the voltage applied to the top voltage, of the input(s) can be set to accommodate either single- of the resistor ladder in a flash A/D converter, the value VREF supply or dual supply systems. Also, note that the analog inputs, defines the maximum input voltage to the A/D core. The minimum VINA and VINB, are interchangeable with the exception that input voltage to the A/D core is automatically defined to be –VREF. reversing the inputs to the VINA and VINB pins results in a polarity inversion. AD9243 +V C VINA REF H 14 V Q CORE S2 A/D + CORE C PIN Q C S S1 C PAR VINA VINB –V REF Q C Q H1 S S1 VINB – C PIN Figure 20. AD9243 Equivalent Functional Input Circuit Q S2 C PAR The addition of a differential input structure gives the user an C H additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- Figure 21. AD9243 Simplified Input Circuit ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. –8– REV. A AD9243 The input SHA of the AD9243 is optimized to meet the perfor- tion in THD performance as the input frequency increases. mance requirements for some of the most demanding commu- Similarly, note how the THD performance at lower frequencies nication, imaging, and data acquisition applications while becomes less sensitive to the common-mode voltage. As the maintaining low power dissipation. Figure 22 is a graph of the input frequency approaches dc, the distortion will be domi- full-power bandwidth of the AD9243, typically 40 MHz. Note nated by static nonlinearities such as INL and DNL. It is that the small signal bandwidth is the same as the full-power important to note that these dc static nonlinearities are inde- bandwidth. The settling time response to a full-scale stepped pendent of any R modulation. ON input is shown in Figure 23 and is typically 80 ns to 0.0025%. –50 The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13. 0 –60 V = 1.0V CM –3 –70 –6 –80 V = 2.5V CM –9 –90 0.1 1 10 FREQUENCY – MHz Figure 24. AD9243 THD vs. Frequency for V = 2.5 V and CM –12 1 10 100 1.0 V (A = –0.5 dB, Input Span = 2.0 V p-p) IN FREQUENCY – MHz Due to the high degree of symmetry within the SHA topology, a Figure 22. Full-Power Bandwidth significant improvement in distortion performance for differen- tial input signals with frequencies up to and beyond Nyquist can 16000 be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half which 12000 further reduces the degree of R modulation and its effects on ON distortion. The optimum noise and dc linearity performance for either 8000 differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched input impedance for VINA and VINB. Note that only a slight 4000 degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9243 “DC SPECIFICATIONS.” 0 06 10 20 30 40 500 70 80 Referring to Figure 21, the differential SHA is implemented SETTLING TIME – ns using a switched-capacitor topology. Hence, its input imped- Figure 23. Settling Time ance and its subsequent effects on the input drive source should be understood to maximize the converter’s performance. The The SHA’s optimum distortion performance for a differential or combination of the pin capacitance, C , parasitic capacitance PIN single-ended input is achieved under the following two condi- C and the sampling capacitance, C , is typically less than PAR, S tions: (1) the common-mode voltage is centered around mid 16 pF. When the SHA goes into track mode, the input source supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input must charge or discharge the voltage stored on C to the new S signal voltage span of the SHA is set at its lowest (i.e., 2 V input input voltage. This action of charging and discharging C which S span). This is due to the sampling switches, Q , being CMOS S1 is approximately 4 pF, averaged over a period of time and for a switches whose R resistance is very low but has some signal ON given sampling frequency, F , makes the input impedance ap- S dependency which causes frequency dependent ac distortion pear to have a benign resistive component (i.e., 83 kΩ at F = S while the SHA is in the track mode. The R resistance of a ON 3.0 MSPS). However, if this action is analyzed within a sam- CMOS switch is typically lowest at its midsupply but increases pling period (i.e., T = <1/F ), the input impedance is dynamic S symmetrically as the input signal approaches either AVDD or due to the instantaneous requirement of charging and discharg- AVSS. A lower input signal voltage span centered at midsupply ing C . A series resistor inserted between the input drive source S reduces the degree of R modulation. ON and the SHA input as shown in Figure 25 provides the effective Figure 24 compares the AD9243’s THD vs. frequency perfor- isolation. mance for a 2 V input span with a common-mode voltage of 1 V and 2.5 V. Note the difference in the amount of degrada- REV. A –9– CODE AMPLITUDE – dB THD – dB AD9243 V The noise or small-signal bandwidth of the AD9243 is the same CC AD9243 as its full-power bandwidth. For noise sensitive applications, the R * S excessive bandwidth may be detrimental and the addition of a VINA R * S series resistor and/or shunt capacitor can help limit the wide- VINB band noise at the A/D’s input by forming a low-pass filter. V EE VREF Note, however, that the combination of this series resistance 10mF 0.1mF SENSE with the equivalent input capacitance of the AD9243 should be REFCOM evaluated for those time-domain applications that are sensitive to the input signal’s absolute settling time. In applications where *OPTIONAL SERIES RESISTOR harmonic distortion is not a primary concern, the series resis- Figure 25. Series Resistor Isolates Switched-Capacitor tance may be selected in combination with the SHA’s nominal SHA Input from Op Amp. Matching Resistors Improve 16 pF of input capacitance to set the filter’s 3 dB cutoff frequency. SNR Performance A better method of reducing the noise bandwidth, while possi- The optimum size of this resistor is dependent on several factors bly establishing a real pole for an antialiasing filter, is to add which include the AD9243 sampling rate, the selected op amp, some additional shunt capacitance between the input (i.e., and the particular application. In most applications, a 30 Ω to VINA and/or VINB) and analog ground. Since this additional 50 Ω resistor is sufficient. However, some applications may re- shunt capacitance combines with the equivalent input capaci- quire a larger resistor value to reduce the noise bandwidth or tance of the AD9243, a lower series resistance can be selected to possibly limit the fault current in an overvoltage condition. establish the filter’s cutoff frequency while not degrading the Other applications may require a larger resistor value as part of distortion performance of the device. The shunt capacitance an anti-aliasing filter. In any case, since the THD performance also acts like a charge reservoir, sinking or sourcing the addi- is dependent on the series resistance and the above mentioned tional charge required by the hold capacitor, C , further reduc- H factors, optimizing this resistor value for a given application is ing current transients seen at the op amp’s output. encouraged. The effect of this increased capacitive load on the op amp driv- A slight improvement in SNR performance and dc offset perfor- ing the AD9243 should be evaluated. To optimize performance mance is achieved by matching the input resistance connected when noise is the primary consideration, increase the shunt to VINA and VINB. The degree of improvement is dependent on capacitance as much as the transient response of the input signal the resistor value and the sampling rate. For series resistor will allow. Increasing the capacitance too much may adversely values greater than 100 Ω, the use of a matching resistor is affect the op amp’s settling time, frequency response, and dis- encouraged. tortion performance. Table I. Analog Input Configuration Summary Input Input Input Range (V) Figure 1 1 Connection Coupling Span (V) VINA VINB # Comments Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum THD and noise performance, requires ±5 V op amp. 2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to 2 × VREF increase in dynamic range. Headroom/settling time require- ments of ±5 op amp should be evaluated. 5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires op amp with VCC > +5 V due to insufficient headroom @ 5 V. 2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance to improves while THD performance degrades as VREF increases 2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps. Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode 2 × VREF 0 to 2 × VREF level not biased at optimum midsupply level (i.e., 2.5 V). 5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance. 2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with to VREF = 1. Noise performance improves while THD perfor- 2.5 + VREF mance degrades as VREF increases to 2.5 V. Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well be- DC yond the A/Ds Nyquist frequency. 2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale to to THD and SFDR performance can be traded off for better noise 2.5 + VREF/2 2.5 – VREF/2 performance. 5 1.75 to 3.25 3.25 to 1.75 29–31 Widest dynamic range (i.e., ENOBs) due to Optimum Noise performance. NOTE 1 VINA and VINB can be interchanged if signal inversion is required. –10– REV. A AD9243 REFERENCE OPERATION 2.5 V. If the SENSE pin is tied to the VREF pin via a short or The AD9243 contains an onboard bandgap reference that pro- resistor, the switch is connected to the SENSE pin. A short will vides a pin-strappable option to generate either a 1 V or 2.5 V provide a VREF of 1.0 V while an external resistor network will output. With the addition of two external resistors, the user can provide an alternative VREF between 1.0 V and 2.5 V. The generate reference voltages other than 1 V and 2.5 V. Another other comparator controls internal circuitry which will disable alternative is to use an external reference for designs requiring the reference amplifier if the SENSE pin is tied AVDD. Dis- enhanced accuracy and/or drift performance. See Table II for a abling the reference amplifier allows the VREF pin to be driven summary of the pin-strapping options for the AD9243 reference by an external voltage reference. configurations. The actual reference voltages used by the internal circuitry of Figure 26 shows a simplified model of the internal voltage the AD9243 appear on the CAPT and CAPB pins. For proper reference of the AD9243. A pin-strappable reference amplifier operation when using the internal or an external reference, it is buffers a 1 V fixed reference. The output from the reference necessary to add a capacitor network to decouple these pins. amplifier, A1, appears on the VREF pin. The voltage on the Figure 27 shows the recommended decoupling network. This VREF pin determines the full-scale input span of the A/D. This capacitive network performs the following three functions: (1) input span equals, along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D inter- Full-Scale Input Span = 2 × VREF nal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the reference. AD9243 The turn-on time of the reference voltage appearing between TO A/D CAPT and CAPB is approximately 15 ms and should be evalu- 5kV CAPT ated in any power-down mode of operation. 5kV A2 0.1mF 5kV CAPB CAPT 5kV DISABLE AD9243 0.1mF 10mF LOGIC A2 CAPB 0.1mF VREF A1 1V 7.5kV Figure 27. Recommended CAPT/CAPB Decoupling Network The A/D’s input span may be varied dynamically by changing SENSE DISABLE 5kV the differential reference voltage appearing across CAPT and LOGIC A1 REFCOM CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low Figure 26. Equivalent Reference Circuit noise amplifiers. In this case, both internal amplifiers (i.e., A1 The voltage appearing at the VREF pin as well as the state of and A2) must be disabled by connecting SENSE to AVDD and the internal reference amplifier, A1, are determined by the volt- VREF to REFCOM and the capacitive decoupling network age appearing at the SENSE pin. The logic circuitry contains removed. The external voltages applied to CAPT and CAPB two comparators which monitor the voltage at the SENSE pin. must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec- The comparator with the lowest set point (approximately 0.3 V) tively in which the input span can be varied between 2 V and 5 V. controls the position of the switch within the feedback path of Note that those samples within the pipeline A/D during any A1. If the SENSE pin is tied to REFCOM, the switch is con- reference transition will be corrupted and should be discarded. nected to the internal resistor network thus providing a VREF of Table II. Reference Configuration Summary Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To INTERNAL 2 1 SENSE VREF INTERNAL 5 2.5 SENSE REFCOM INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD (NONDYNAMIC) VREF EXT. REF. EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD (DYNAMIC) Externally Driven VREF REFCOM EXT. REF. CAPT EXT. REF. CAPB REV. A –11– AD9243 DRIVING THE ANALOG INPUTS AVDD V INTRODUCTION CC D2 R R S1 S2 The AD9243 has a highly flexible input structure allowing it to 1N4148 30V 20V interface with single-ended or differential input interface cir- AD9243 D1 cuitry. The applications shown in sections “Driving the Analog 1N4148 Inputs” and “Reference Configurations” along with the infor- V EE mation presented in “Input and Reference Overview” of this data sheet, give examples of both single-ended and differential Figure 28. Simple Clamping Circuit operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated DIFFERENTIAL MODE OF OPERATION figures in the data sheet. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single- The optimum mode of operation, analog input range, and asso- ended-to-differential conversion. A single-ended-to-differential ciated interface circuitry will be determined by the particular conversion can be realized with an RF transformer or a dual op applications performance requirements as well as power supply amp differential driver. The optimum method depends on options. For example, a dc coupled single-ended input may be whether the application requires the input signal to be ac or dc appropriate for many data acquisition and imaging applications. coupled to AD9243. Also, many communication applications which require a dc coupled input for proper demodulation can take advantage of AC Coupling via an RF Transformer the excellent single-ended distortion performance of the AD9243. In applications that do not need to be dc coupled, an RF trans- The input span should be configured such that the system’s former with a center tap is the best method to generate differen- performance objectives and the headroom requirements of the tial inputs for the AD9243. It provides all the benefits of driving op amp are simultaneously met. operating the A/D in the differential mode without contributing additional noise or distortion. An RF transformer has the added Alternatively, the differential mode of operation provides the benefit of providing electrical isolation between the signal source best THD and SFDR performance over a wide frequency range. and the A/D. A transformer coupled differential input should be considered for the most demanding spectral-based applications which allow Figure 29 shows the schematic of the suggested transformer ac coupling (e.g., Direct IF to Digital Conversion). The dc- circuit. The circuit uses a Mini-Circuits RF transformer, model coupled differential mode of operation also provides an enhance- #T4-6T, which has an impedance ratio of four (turns ratio of ment in distortion and noise performance at higher input spans. 2). The schematic assumes that the signal source has a 50 Ω Furthermore, it allows the AD9243 to be configured for a 5 V source impedance. The 1:4 impedance ratio requires the 200 Ω span using op amps specified for +5 V or ±5 V operation. secondary termination for optimum power transfer and VSWR. The centertap of the transformer provides a convenient means Single-ended operation requires that VINA be ac or dc coupled of level shifting the input signal to a desired common-mode to the input signal source while VINB of the AD9243 be biased voltage. Optimum performance can be realized when the centertap to the appropriate voltage corresponding to a midscale code is tied to CML of the AD9243 which is the common-mode bias transition. Note that signal inversion may be easily accom- level of the internal SHA. plished by transposing VINA and VINB. Differential operation requires that VINA and VINB be simulta- neously driven with two equal signals that are in and out of VINA 50V phase versions of the input signal. Differential operation of the CML AD9243 offers the following benefits: (1) Signal swings are 0.1mF smaller and therefore linearity requirements placed on the input 200V AD9243 signal source may be easier to achieve, (2) Signal swings are VINB smaller and therefore may allow the use of op amps which may MINI-CIRCUITS T4-6T otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic products, Figure 29. Transformer Coupled Input and (4) Differential operation offers noise immunity based on Transformers with other turns ratios may also be selected to the device’s common-mode rejection as shown in Figure 16. optimize the performance of a given application. For example, a As is typical of most CMOS devices, exceeding the supply limits given input signal source or amplifier may realize an improve- will turn on internal parasitic diodes resulting in transient cur- ment in distortion performance at reduced output power levels rents within the device. Figure 28 shows a simple means of and signal swings. Hence, selecting a transformer with a higher clamping a dc coupled input with the addition of two series impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 imped- resistors and two diodes. Note that a larger series resistor could ance ratio) effectively “steps up” the signal level, further reduc- be used to limit the fault current through D1 and D2 but should be ing the driving requirements of the signal source. evaluated since it can cause a degradation in overall performance. –12– REV. A AD9243 390V DC Coupling with Op Amps AV Applications that require dc coupling can also benefit by driving DD the AD9243 differentially. Since the signal swing requirements V –VIN AD8047 CML 390V 390V 33V of each input is reduced by a factor of two in the differential VINA mode, the AD9243 can be configured for a 5 V input span in a 390V 390V V +5 V or ±5 V system. This allows various high performance op IN AV DD amps specified for +5 V and ±5 V operation to be configured in various differential driver topologies. The optimum op amp 390V AD9243 390V 390V driver topology depends on whether the common-mode voltage V +VIN CML AD8047 of the single-ended-input signal requires level-shifting. 33V VINB Figure 30 shows a cross-coupled differential driver circuit best 390V 390V 2.5kV suited for systems in which the common-mode signal of the 0.1mF input is already biased to approximately midsupply (i.e., 2.5 V). The common-mode voltage of the differential output is set by 100V the voltage applied to the “+” input of A2. The closed loop CML gain of this symmetrical driver can be easily set by R and R . 0.1mF 1mF IN F OP113 For more insight into the operation of this cross-coupled driver, please refer to the AD8042 data sheet. Figure 31. Differential Driver with Level-Shifting R F SINGLE-ENDED MODE OF OPERATION 1kV The AD9243 can be configured for single-ended operation R IN V +VIN CML 1kV using dc or ac coupling. In either case, the input of the A/D AD8042 V IN 33V VINA must be driven from an operational amplifier that will not de- grade the A/D’s performance. Because the A/D operates from a 1kV single supply, it will be necessary to level shift ground-based 1kV 1kV bipolar signals to comply with its input requirements. Both dc C * F AD9243 and ac coupling provide this necessary function, but each 1kV method results in different interface issues which may influence V –VIN CML the system design and performance. 33V VINB AV /2 AD8042 DD DC COUPLING AND INTERFACE ISSUES Many applications require the analog input signal to be dc CML coupled to the AD9243. An operational amplifier can be con- 0.1mF figured to rescale and level shift the input signal so that it is *OPTIONAL NOISE/BAND LIMITING CAPACITOR compatible with the selected input range of the A/D. The input Figure 30. Cross-Coupled Differential Driver range to the A/D should be selected on the basis of system performance objectives as well as the analog power supply The driver circuit shown in Figure 31 is best suited for systems availability since this will place certain constraints on the op in which the bipolar input signal is referenced to AGND and amp selection. requires proper level shifting. This driver circuit provides the ability to level-shift the input signal to within the common- Many of the new high performance op amps are specified for mode range of the AD9243. The two op amps are configured as only ±5 V operation and have limited input/output swing capa- matched difference amplifiers with the input signal applied to bilities. Hence, the selected input range of the AD9243 should opposing inputs to provide the differential output. The common- be sensitive to the headroom requirements of the particular op mode offset voltage is applied to the noninverting resistor net- amp to prevent clipping of the signal. Also, since the output of work which provides the proper level shifting. The circuit also a dual supply amplifier can swing below –0.3 V, clamping its employs optional diodes and pull-up resistors which may help output should be considered in some applications. improve the op amps’ distortion performance by reducing their In some applications, it may be advantageous to use an op amp headroom requirements. Rail-to-rail output amplifiers like the specified for single supply +5 V operation since it will inher- AD8042 have sufficient headroom and thus do not require ently limit its output swing to within the power supply rails. these optional components. Rail-to-rail output amplifiers such as the AD8041 allow the AD9243 to be configured with larger input spans which im- proves the noise performance. REV. A –13– AD9243 If the application requires the largest single-ended input range 500V* (i.e., 0 V to 5 V) of the AD9243, the op amp will require larger +V CC supplies to drive it. Various high speed amplifiers in the “Op 0.1mF Amp Selection Guide” of this data sheet can be selected to +VREF NC accommodate a wide range of supply options. Once again, 500V* 7 0V DC 2 clamping the output of the amplifier should be considered for –VREF 1 R S 6 A1 VINA these applications. Alternatively, a single-ended to differential R ** P 500V* 5 3 AVDD op amp driver circuit using the AD8042 could be used to 4 NC 500V* AD9243 0.1mF achieve the 5 V input span while operating from a single +5 V supply. R S VREF VINB Two dc coupled op amp circuits using a noninverting and inverting *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D topology are discussed below. Although not shown, the nonin- **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE NC = NO CONNECT verting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or Multiple-Feed- Figure 33. Single-Ended Input With DC-Coupled Level Shift back topology, respectively. An additional R-C network can be inserted between the op amp’s output and the AD9243 input to AC COUPLING AND INTERFACE ISSUES provide a real pole. For applications where ac coupling is appropriate, the op amp’s Simple Op Amp Buffer output can be easily level shifted to the common-mode voltage, In the simplest case, the input signal to the AD9243 will already V , of the AD9243 via a coupling capacitor. This has the CM be biased at levels in accordance with the selected input range. advantage of allowing the op amps common-mode level to be It is simply necessary to provide an adequately low source im- symmetrically biased to its midsupply level (i.e., (V + V )/2). CC EE pedance for the VINA and VINB analog input pins of the A/D. Op amps which operate symmetrically with respect to their Figure 32 shows the recommended configuration for a single- power supplies typically provide the best ac performance as well ended drive using an op amp. In this case, the op amp is shown as greatest input/output span. Hence, various high speed/perfor- in a noninverting unity gain configuration driving the VINA pin. mance amplifiers which are restricted to +5 V/–5 V operation The internal reference drives the VINB pin. Note that the and/or specified for +5 V single-supply operation can be easily addition of a small series resistor of 30 Ω to 50 Ω connected to configured for the 5 V or 2 V input span of the AD9243, respec- VINA and VINB will be beneficial in nearly all cases. Refer to tively. The best ac distortion performance is achieved when the section “Analog Input Operation” for a discussion on resistor A/D is configured for a 2 V input span and common-mode selection. Figure 32 shows the proper connection for a 0 V to 5 V voltage of 2.5 V. Note that differential transformer coupling, input range. Alternative single ended input ranges of 0 V to 2 × which is another form of ac coupling, should be considered for VREF can also be realized with the proper configuration of VREF optimum ac performance. (refer to the section “Using the Internal Reference”). Simple AC Interface Figure 34 shows a typical example of an ac-coupled, single- +V ended configuration. The bias voltage shifts the bipolar, ground- 5V AD9243 R S referenced input signal to approximately VREF. The value for 0V U1 VINA R C1 and C2 will depend on the size of the resistor, R. The ca- S VINB pacitors, C1 and C2, are typically a 0.1 μF ceramic and 10 μF –V 2.5V VREF tantalum capacitor in parallel to achieve a low cutoff frequency 10mF 0.1mF while maintaining a low impedance over a wide frequency range. SENSE The combination of the capacitor and the resistor form a high- pass filter with a high-pass –3 dB frequency determined by the equation, Figure 32. Single-Ended AD9243 Op Amp Drive Circuit f = 1/(2 × π × R × (C1 + C2)) –3 dB Op Amp with DC Level Shifting Figure 33 shows a dc-coupled level shifting circuit employing an The low impedance VREF voltage source biases both the VINB op amp, A1, to sum the input signal with the desired dc offset. input and provides the bias voltage for the VINA input. Figure Configuring the op amp in the inverting mode with the given 34 shows the VREF configured for 2.5 V. Thus the input range resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB con- C1 +5V nections to reestablish the original signal polarity. The dc volt- AD9243 +VREF C2 age at VREF sets the common-mode voltage of the AD9243. For R S V 0V IN VINA –VREF example, when VREF = 2.5 V, the output level from the op amp R will also be centered around 2.5 V. The use of ratio matched, R S –5V thin-film resistor networks will minimize gain and offset errors. VINB VREF Also, an optional pull-up resistor, R , may be used to reduce the P C2 C1 SENSE output load on VREF to ±1 mA. Figure 34. AC-Coupled Input –14– REV. A AD9243 of the A/D is 0 V to 5 V. Other input ranges could be selected AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur- by changing VREF but the A/D’s distortion performance will rent Feedback, +5 V to ±15 V Supplies degrade slightly as the input common-mode voltage deviates Best Applications: Differential and/or Low Imped- from its optimum level of 2.5 V. ance Input Drivers Limits: THD above 1 MHz Alternative AC Interface Figure 35 shows a flexible ac coupled circuit which can be con- AD8011: f = 300 MHz, +5 V or ±5 V Supplies, Current –3 dB figured for different input spans. Since the common-mode Feedback voltage of VINA and VINB are biased to midsupply indepen- Best Applications: Single-Supply, AC/DC-Coupled, dent of VREF, VREF can be pin-strapped or reconfigured to Good AC Specs, Low Noise, Low Power (5 mW) achieve input spans between 2 V and 5 V p-p. The AD9243’s Limits: THD above 5 MHz, Usable Input/Output CMRR along with the symmetrical coupling R-C networks will Range reject both power supply variations and noise. The resistors, R, AD8013: Triple, f = 230 MHz, +5 V or ±5 V supplies, –3 dB establish the common-mode voltage. They may have a high value Current Feedback, Disable Function (e.g., 5 kΩ) to minimize power consumption and establish a low Best Applications: 3:1 Multiplexer, Good AC Specs cutoff frequency. The capacitors, C1 and C2, are typically a Limits: THD above 5 MHz, Input Range 0.1 μF ceramic and 10 μF tantalum capacitor in parallel to achieve AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%, a low cutoff frequency while maintaining a low impedance over ± 5 V Supplies a wide frequency range. R isolates the buffer amplifier from the S Best Applications: Best AC Specs, Low Noise, A/D input. The optimum performance is achieved when VINA AC-Coupled and VINB are driven via symmetrical networks. The high pass Limits: Usable Input/Output Range, Power f point can be approximated by the equation, –3 dB Consumption f = 1/(2 × π × R/2 × (C1 + C2)) –3 dB AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%, ±5 V Supplies +5V +5V Best Applications: Good AC Specs, Low Noise, AD9243 R C1 AC-Coupled R V S IN VINA Limits: THD > 5 MHz, Usable Input Range R C2 AD8041: Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling –5V R to 0.01%, +5 V Supply, 26 mW R S +5V VINB Best Applications: Low Power, Single-Supply Sys- C1 C2 R tems, DC-Coupled, Large Input Range Limits: Noise with 2 V Input Range AD8042: Dual AD8041 Figure 35. AC-Coupled Input-Flexible Input Span, Best Applications: Differential and/or Low Imped- V = 2.5 V CM ance Input Drivers Limits: Noise with 2 V Input Range OP AMP SELECTION GUIDE Op amp selection for the AD9243 is highly dependent on a REFERENCE CONFIGURATIONS particular application. In general, the performance requirements The figures associated with this section on internal and external of any given application can be characterized by either time reference operation do not show recommended matching series resistors domain or frequency domain parameters. In either case, one for VINA and VINB for the purpose of simplicity. Please refer to should carefully select an op amp which preserves the perfor- section “Driving the Analog Inputs, Introduction” for a discussion of mance of the A/D. This task becomes challenging when one this topic. Also, the figures do not show the decoupling network asso- considers the AD9243’s high performance capabilities coupled ciated with the CAPT and CAPB pins. Please refer to the section “Ref- with other external system level requirements such as power erence Operation” for a discussion of the internal reference circuitry consumption and cost. and the recommended decoupling network shown in Figure 27. The ability to select the optimal op amp may be further compli- USING THE INTERNAL REFERENCE cated by either limited power supply availability and/or limited Single-Ended Input with 0 to 2 3 VREF Range acceptable supplies for a desired op amp. Newer, high performance Figure 36 shows how to connect the AD9243 for a 0 V to 2 V or op amps typically have input and output range limitations in 0 V to 5 V input range via pin strapping the SENSE pin. An accordance with their lower supply voltages. As a result, some intermediate input range of 0 to 2 × VREF can be established op amps will be more appropriate in systems where ac-coupling using the resistor programmable configuration in Figure 38 and is allowable. When dc-coupling is required, op amps without connecting VREF to VINB. headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. The following In either case, both the common-mode voltage and input span section describes some op amps currently available from Analog are directly dependent on the value of VREF. More specifically, Devices. The system designer is always encouraged to contact the common-mode voltage is equal to VREF while the input the factory or local sales office to be updated on Analog Devices’ span is equal to 2 × VREF. Thus, the valid input range extends latest amplifier product offerings. Highlights of the areas where from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output the op amps excel and where they may limit the performance of will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output the AD9243 are also included. will be 3FFF Hex. REV. A –15– AD9243 Shorting the VREF pin directly to the SENSE pin places the Resistor Programmable Reference Figure 38 shows an example of how to generate a reference internal reference amplifier in unity-gain mode and the resultant VREF output is 1 V. Therefore, the valid input range is 0 V to voltage other than 1 V or 2.5 V with the addition of two exter- 2 V. However, shorting the SENSE pin directly to the REFCOM nal resistors and a bypass capacitor. Use the equation, pin configures the internal reference amplifier for a gain of 2.5 VREF = 1 V × (1 + R1/R2), and the resultant VREF output is 2.5 V. Thus, the valid input to determine appropriate values for R1 and R2. These resistors range becomes 0 V to 5 V. The VREF pin should be bypassed should be in the 2 kΩ to 100 kΩ range. For the example shown, to the REFCOM pin with a 10 μF tantalum capacitor in parallel R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation with a low-inductance 0.1 μF ceramic capacitor. above, the resultant reference voltage on the VREF pin is 1.5 V. This sets the input span to be 3 V p-p. To assure stabil- 2xVREF ity, place a 0.1 μF ceramic capacitor in parallel with R1. VINA 0V VINB The common-mode voltage can be set to VREF by connecting 10mF 0.1mF VREF VINB to VREF to provide an input span of 0 to 2 × VREF. AD9243 SHORT FOR 0V TO 2V Alternatively, the common-mode voltage can be set to 2.5 V INPUT SPAN by connecting VINB to a low impedance 2.5 V source. For SENSE the example shown, the valid input single range for VINA is SHORT FOR 0V TO 5V INPUT SPAN 1 V to 4 V since VINB is set to an external, low impedance 2.5 REFCOM V source. The VREF pin should be bypassed to the REFCOM pin with a 10 μF tantalum capacitor in parallel with a low induc- tance 0.1 μF ceramic capacitor. Figure 36. Internal Reference (2 V p-p Input Span, V = 1 V, or 5 V p-p Input Span, V = 2.5 V) CM CM 4V VINA Single-Ended or Differential Input, V = 2.5 V CM 1V Figure 37 shows the single-ended configuration that gives the 2.5V VINB best SINAD performance. To optimize dynamic specifications, 1.5V VREF center the common-mode voltage of the analog input at R1 C1 0.1mF 10mF AD9243 2.5kV 0.1mF approximately by 2.5 V by connecting VINB to VREF, a low- SENSE impedance 2.5 V source. As described above, shorting the R2 5kV SENSE pin directly to the REFCOM pin results in a 2.5 V REFCOM reference voltage and a 5 V p-p input span. The valid range for input signals is 0 V to 5 V. The VREF pin should be by- passed to the REFCOM pin with a 10 μF tantalum capacitor in Figure 38. Resistor Programmable Reference (3 V p-p parallel with a low inductance 0.1 μF ceramic capacitor. Input Span, V = 2.5 V) CM This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as USING AN EXTERNAL REFERENCE shown in Figure 29. In this case, the common-mode voltage, Using an external reference may enhance the dc performance of , is set at midsupply by connecting the transformers center V CM the AD9243 by improving drift and accuracy. Figures 39 tap to CML of the AD9243. VREF can be configured for 1 V through 41 show examples of how to use an external reference or 2.5 V by connecting SENSE to either VREF or REFCOM with the A/D. Table III is a list of suitable voltage references respectively. Note that the valid input range for each of the from Analog Devices. To use an external reference, the user differential inputs is one half of the single-ended input and thus must disable the internal reference amplifier and drive the VREF – VREF/2 to V + VREF/2. becomes V CM CM pin. Connecting the SENSE pin to AVDD disables the inter- nal reference amplifier. 5V VINA 0V Table III. Suitable Voltage References VINB AD9243 2.5V VREF Initial Operating 10mF 0.1mF SENSE Output Drift Accuracy Current Voltage (ppm/8C) % (max) (mA) REFCOM Internal 1.00 26 1.4 N/A AD589 1.235 10–100 1.2–2.8 50 Figure 37. Internal Reference—5 V p-p Input Span, AD1580 1.225 50–100 0.08–0.8 50 V = 2.5 V CM REF191 2.048 5–25 0.1–0.5 45 Internal 2.50 26 1.4 N/A REF192 2.50 5–25 0.08–0.4 45 REF43 2.50 10–25 0.06–0.1 600 AD780 2.50 3–7 0.04–0.2 1000 –16– REV. A AD9243 The AD9243 contains an internal reference buffer, A2 (see Low Cost/Power Reference Figure 26), that simplifies the drive requirements of an external The external reference circuit shown in Figure 41 uses a low reference. The external reference must be able to drive a ≈5 kΩ cost 1.225 V external reference (e.g., AD580 or AD1580) along (±20%) load. Note that the bandwidth of the reference buffer is with an op amp and transistor. The 2N2222 transistor acts in deliberately left small to minimize the reference noise contribu- conjunction with 1/2 of an OP282 to provide a very low imped- tion. As a result, it is not possible to change the reference volt- ance drive for VINB. The selected op amp need not be a high age rapidly in this mode without the removal of the CAPT/ speed op amp and may be selected based on cost, power, and CAPB Decoupling Network, and driving these pins directly. accuracy. Variable Input Span with V = 2.5 V CM 3.75V Figure 39 shows an example of the AD9243 configured for an VINA +5V input span of 2 × VREF centered at 2.5 V. An external 2.5 V 1.25V reference drives the VINB pin thus setting the common-mode 820V 1kV voltage at 2.5 V. The input span can be independently set by a 0.1mF VINB voltage divider consisting of R1 and R2 which generates the 1kV 10mF VREF signal. A1 buffers this resistor network and drives VREF. 2N2222 0.1mF AD9243 1kV Choose this op amp based on accuracy requirements. It is 316V 1/2 essential that a minimum of a 10 μF capacitor in parallel with a OP282 7.5kV 1.225V 0.1 μF low inductance ceramic capacitor decouple the reference +5V VREF output to ground. 10mF 0.1mF AD1580 +5V SENSE 2.5V+VREF 2.5V VINA Figure 41. External Reference Using the AD1580 and Low 2.5V–VREF Impedance Buffer 2.5V +5V VINB REF 0.1mF 0.1mF 22mF R1 DIGITAL INPUTS AND OUTPUTS AD9243 Digital Outputs A1 VREF The AD9243 output data is presented in positive true straight R2 0.1mF binary for all input ranges. Table IV indicates the output data SENSE +5V formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB. Figure 39. External Reference, V = 2.5 V (2.5 V on VINB, CM Resistor Divider to Make VREF) Table IV. Output Data Format Single-Ended Input with 0 to 2 3 VREF Range Input (V) Condition (V) Digital Output OTR Figure 40 shows an example of an external reference driving both VINB and VREF. In this case, both the common mode VINA –VINB < – VREF 00 0000 0000 0000 1 voltage and input span are directly dependent on the value of VINA –VINB = – VREF 00 0000 0000 0000 0 VREF. More specifically, the common-mode voltage is equal to VINA –VINB = 0 10 0000 0000 0000 0 VREF while the input span is equal to 2 × VREF. Thus, the VINA –VINB = + VREF – 1 LSB 11 1111 1111 1111 0 valid input range extends from 0 to 2 × VREF. For example, if VINA –VINB ≥ + VREF 11 1111 1111 1111 1 the REF191, a 2.048 external reference was selected, the valid input range extends from 0 V to 4.096 V. In this case, 1 LSB of +FS –1 1/2 LSB the AD9243 corresponds to 0.250 mV. It is essential that a OTR DATA OUTPUTS OTR 1 minimum of a 10 μF capacitor in parallel with a 0.1 μF low induc- 111111 1111 1111 0 111111 1111 1111 tance ceramic capacitor decouple the reference output to ground. 0 111111 1111 1110 –FS +1/2 LSB 2xREF VINA 0 000000 0000 0001 0V 0 000000 0000 0000 1 000000 0000 0000 +5V VREF VINB –FS +FS 10mF 0.1mF 0.1mF AD9243 –FS –1/2 LSB +FS –1/2 LSB VREF Figure 42. Output Data Format 0.1mF Out Of Range (OTR) +5V SENSE An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital Figure 40. Input Range = 0 V to 2 × VREF output that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 42. OTR will remain HIGH REV. A –17– AD9243 until the analog input returns within the input range and an- For clock rates below 3 MSPS, the duty cycle may deviate from other conversion is completed. By logical ANDing OTR with this range to the extent that both t and t are satisfied. CH CL the MSB and its complement, overrange high or underrange low All high speed high resolution A/Ds are sensitive to the quality conditions can be detected. Table V is a truth table for the over/ of the clock input. The degradation in SNR at a given full-scale underrange circuit in Figure 43 which uses NAND gates. Sys- input frequency (f ) due to only aperture jitter (t ) can be IN A tems requiring programmable gain conditioning of the AD9243 calculated with the following equation: input signal can immediately detect an out-of-range condition, SNR = 20 log [1/(2 π f t )] 10 IN A thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration. In the equation, the rms aperture jitter, t , represents the root- A sum square of all the jitter sources which include the clock in- Table V. Out-of-Range Truth Table put, analog input signal, and A/D aperture jitter specification. For example, if a 1.5 MHz full-scale sine wave is sampled by an OTR MSB Analog Input Is A/D with a total rms jitter of 15 ps, the SNR performance of the 0 0 In Range A/D will be limited to 77 dB. Undersampling applications are 0 1 In Range particularly sensitive to jitter. 1 0 Underrange The clock input should be treated as an analog signal in cases 1 1 Overrange where aperture jitter may affect the dynamic range of the AD9243. As such, supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the MSB OVER = “1” clock signal with digital noise. Low jitter crystal controlled OTR oscillators make the best clock sources. If the clock is generated UNDER = “1” from another type of source (by gating, dividing, or other method), MSB it should be retimed by the original clock at the last step. Figure 43. Overrange or Underrange Logic Most of the power dissipated by the AD9243 is from the analog power supply. However, lower clock speeds will reduce digital Digital Output Driver Considerations (DRVDD) current slightly. Figure 44 shows the relationship between power The AD9243 output drivers can be configured to interface with and clock rate. +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V respectively. The AD9243 output drivers are sized to provide 125 sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the 120 supplies and may affect SINAD performance. Applications requir- ing the AD9243 to drive large capacitive loads or large fanout 115 may require additional decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required. 110 5V p-p Clock Input and Considerations 105 The AD9243 internal timing uses the two edges of the clock 2V p-p input to generate a variety of internal timing signals. The clock 100 input must meet or exceed the minimum specified pulsewidth high and low (t and t ) specifications for the given A/D as 95 CH CL defined in the Switching Specifications at the beginning of the 90 data sheet to meet the rated performance specifications. For 0 1 2 3 4 5 6 example, the clock input to the AD9243 operating at 3 MSPS CLOCK FREQUENCY – MHz may have a duty cycle between 45% to 55% to meet this timing Figure 44. AD9243 Power Consumption vs. Clock requirement since the minimum specified t and t is 150 ns. CH CL Frequency –18– REV. A POWER – mW AD9243 GROUNDING AND DECOUPLING adequately low impedance over a wide frequency range. Note Analog and Digital Grounding that the AVDD and AVSS pins are co-located on the AD9243 Proper grounding is essential in any high speed, high resolution to simplify the layout of the decoupling capacitors and provide system. Multilayer printed circuit boards (PCBs) are recom- the shortest possible PCB trace lengths. The AD9243/EB power mended to provide optimal grounding and power schemes. The plane layout, shown in Figure 55 depicts a typical arrangement use of ground and power planes offers distinct advantages: using a multilayer PCB. 1. The minimization of the loop area encompassed by a signal and its return path. AVDD 2. The minimization of the impedance associated with ground 0.1mF and power paths. AVSS AD9243 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. AVDD 0.1mF These characteristics result in both a reduction of electro- AVSS magnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling Figure 46. Analog Supply Decoupling onto the input signal. Digital signals should not be run in paral- The CML is an internal analog bias point used internally by the lel with input signal traces and should be routed away from the AD9243. This pin must be decoupled with at least a 0.1 μF input circuitry. While the AD9243 features separate analog and capacitor as shown in Figure 47. The dc level of CML is ap- digital ground pins, it should be treated as an analog compo- proximately AVDD/2. This voltage should be buffered if it is to nent. The AVSS, DVSS and DRVSS pins must be joined together be used for any external biasing. directly under the AD9243. A solid ground plane under the A/D is acceptable if the power and ground return currents are managed carefully. Alternatively, the ground plane under the A/D may CML contain serrations to steer currents in predictable directions 0.1mF AD9243 where cross-coupling between analog and digital would other- wise be unavoidable. The AD9243/EB ground layout, shown in Figure 54, depicts the serrated type of arrangement. The analog Figure 47. CML Decoupling and digital grounds are connected by a jumper below the A/D. The digital activity on the AD9243 chip falls into two general Analog and Digital Supply Decoupling categories: correction logic, and output drivers. The internal The AD9243 features separate analog and digital supply and correction logic draws relatively small surges of current, mainly ground pins, helping to minimize digital corruption of sensitive during the clock transitions. The output drivers draw large analog signals. current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the 120 output bits: large capacitive loads are to be avoided. Note that the internal correction logic of the AD9243 is referenced DVDD while the output drivers are referenced to DRVDD. DVDD 100 The decoupling shown in Figure 48, a 0.1 μF ceramic chip capacitor, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications 80 involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/ latches. 60 AVDD DVDD DRVDD 0.1mF 0.1mF 40 AD9243 1 10 100 1000 DVSS DRVSS FREQUENCY – kHz Figure 45. AD9243 PSSR vs. Frequency Figure 48. Digital Supply Decoupling Figure 45 shows the power supply rejection ratio vs. frequency A complete decoupling scheme will also include large tantalum for a 200 mV p-p ripple applied to both AVDD and DVDD. or electrolytic capacitors on the PCB to reduce low-frequency In general, AVDD, the analog supply, should be decoupled to ripple to negligible levels. Refer to the AD9243/EB schematic AVSS, the analog common, as close to the chip as physically and layouts in Figures 51–55 for more information regarding the possible. Figure 46 shows the recommended decoupling for the placement of decoupling capacitors. analog supplies; 0.1 μF ceramic chip capacitors should provide REV. A –19– PSRR – dBFS AD9243 APPLICATIONS 0 1 DIRECT IF DOWN CONVERSION USING THE AD9243 –15 As previously noted, the AD9243’s performance in the differen- –30 tial mode of operation extends well beyond its baseband region –45 and into several Nyquist zone regions. Hence, the AD9243 may be well suited as a mix down converter in both narrow and –60 wideband applications. Various IF frequencies exist over the –75 frequency range in which the AD9243 maintains excellent dy- 2 –90 9 7 4 namic performance (e.g., refer to Figure 5 and 6). The IF sig- –105 nal will be aliased to the ADC’s baseband region due to the sampling process in a similar manner that a mixer will down –120 convert an IF signal. For signals in various Nyquist zones, the –135 following equation may be used to determine the final frequency –150 after aliasing. 0 1.25 FREQUENCY – MHz f = f 1 NYQUIST SIGNAL f = f – f 2 NYQUIST SAMPLE SIGNAL Figure 49. IF Sampling a 10.7 MHz Input Using the f = abs (f – f ) 3 NYQUIST SAMPLE SIGNAL AD9243 (V = 2.5 V, Input Span = 2 V p-p) CM f = 2 × f – f 4 NYQUIST SAMPLE SIGNAL f = abs (2 × f – f ) 5 NYQUIST SAMPLE SIGNAL 110 There are several potential benefits in using the ADC to alias 100 (i.e., mix) down a narrowband or wideband IF signal. First and SFDR – dBFS foremost is the elimination of a complete mixer stage with its 90 associated amplifiers and filters, reducing cost and power dissi- pation. Second is the ability to apply various DSP techniques to 80 perform such functions as filtering, channel selection, quadra- 70 ture demodulation, data reduction, and detection. SFDR – dBc One common example is the digitization of a 10.7 MHz IF using a 60 low jitter 2.5 MHz sample clock. Using the equation above for the fifth Nyquist zone, the resultant frequency after sampling is 50 700 kHz. Figure 49 shows the typical performance of the 40 AD9243 operating under these conditions. Figure 50 demon- –60 –50 –40 –30 –20 –10 0 strates how the AD9243 is still able to maintain a high degree of AIN – dBFS linearity and SFDR over a wide amplitude. Figure 50. AD9243 Differential Input SNR/SFDR vs. Input Amplitude (AIN) @ 10.7 MHz –20– REV. A AMPLITUDE – dB SFDR – dBc AND dBFS AD9243 Figure 51. Evaluation Board Schematic REV. A –21– JP7 +5VA R20 TP10 22.1V C9 TP1 A D13 13 J8 0.1mF C8 A U5 TPC 0.1mF 13 12 R21 TP11 + C1 C2 22.1V JP2 +5VA U6 10mF JP6 0.1mF 28 29 11 J8 TPD 42 1 A 16V G1 R22 JP3 TP12 C41 U5 11 U5 19 R1 11 10 98 JP15 G2 Y7 22.1V 0.1mF TP24 10kV 12 D7 9 9 JP4 Y6 J8 A A7 13 CLKB D8 8 32 25 Y5 R23 TP13 A6 VREF OTR 14 JP5 D9 7 R2 Y4 22.1V A5 JP16 U1 10kV 24 D13 D10 6 15 7J8 U8 ADC CLK Y3 A4 BIT1 65 AD9243MQFP 23 D12 16 A D11 5 R24 TP14 CLK Y2 BIT2 A3 A 31 17 22.1V 22 D11 D12 4 Y1 SENSE BIT3 A2 5 C23 J8 21 D10 18 J9 TP2 D13 3 Y0 BIT4 A1 0.1mF R25 TP15 33 20 D9 2 REFCOM BIT5 A0 C3 CLKIN 22.1V + C5 20 +DRVDD 19 D8 10 0.1mF C6 3 BIT6 GND +5VD J8 10mF A R19 18 D7 JP17 0.1mF 16V BIT7 R26 TP16 C24 50V 17 D6 A +5VA 37 74HC541N CAPT 22.1V BIT8 JP18 0.1mF 16 D5 1 J8 A BIT9 U7 C4 15 D4 36 R27 A 1 TP3 CAPB BIT10 R16 0.1mF G1 14 D3 5kV 22.1V 11 BIT11 R40 19 G2 Y7 33 J8 39 13 D2 12 BIT12 CLK 9 CML CML R17 A7 Y6 R28 TP4 12 D1 41 BIT13 13 D0 8 1kV CW Y5 22.1V VINA A6 11 D0 BIT14 14 R41 D1 7 42 27 J8 C7 A5 Y4 A VINB D2 6 15 0.1mF R29 TP5 R18 A4 Y3 7 16 CLK D3 5 22.1V VINA2 5kV A3 Y2 17 25 J8 D4 4 A JP11 B Y1 A2 18 R30 TP17 VINA1 A D5 3 ADC_CLK A1 Y0 321 22.1V 2 5 1 63 A0 23 J8 20 +DRVDD 10 VINB2 GND +5VD R31 TP6 JP8 A JP12 B C25 22.1V +5VD +5VA VINB1 +DRVDD 74HC541N 21 0.1mF J8 321 C10 C11 C43 R32 TP7 0.1mF 0.1mF 0.1mF R6 TP25 22.1V 820V 19 J8 TPD R33 TP8 V C17 CC 22.1V U2 10mF C18 C16 17 J8 TP18 C14 0.1mF 16V 0.1mF L1 R34 TP9 EXTERNAL REFERENCE DRIVE 0.1mF REF43 U3 +5A J2 +5VA 22.1V 2 V V V OUT 6 CC IN 15 J8 + C28 A Q1 C32 R7 C12 A 22mF 7 3 2N2222 GND 0.1mF R3 1kV 0.1mF JP10 25V R4 AD817 6 4 15kV A 50V TP19 A A A 2 L2 4 C15 A C13 R8 R5 +5D J3 +5VD 0.1mF 10mF 316V 10kV + C29 C33 16V 22mF 0.1mF A A A 25V A V EE TP20 A A L3 J1 C38 +V J4 V CC CC T1 VIN + C30 R37 J10 C34 V 22mF CC 33V AC COUPLE OPTION 0.1mF 1 6 25V R11 AIN VINA1 A C19 JP24 500V +5VA TP21 A A C36 0.1mF U4 PRI SEC R9 L4 15pF A DIRECT COUPLE OPTION 50V V D1 –V J5 EE A EE 2 5 R12 7 A + C31 1N5711 3 2 A C35 33V 22mF R35 R36 R10 AD845 6 0.1mF A BUFFER VINA2 R38 25V 50V 200V 2 500V 33V JP23 3 D2 4 4 TP27 A A 3 C21 B 1N5711 L5 VINB1 0.1mF R39 1 C20 R14 C37 A J11 +DRVDD A 0.1mF 10kV 15pF CW + +5 OR +3 C39 C40 AC COUPLE OPTION R13 A 22mF A 0.1mF V JP21 A A 10kV EE +5VA 25V JP14 TPC 2 J8 26 J8 TPD JP22 D3 R15 TPD NC 39 J8 1N5711 4J8 33V JP13 JP1 TPC VINB2 6 28 J8 J8 CML TP22 D4 8 J8 29 J8 C42 U8 1N5711 0.1mF 11 DGND J6 10 10 30 J8 J8 5 SETS OF A A U5 PADS TO 31 12 J8 J8 U8 5 6 U8 U5 CONNECT TP26 TP23 98 DECOUPLING DECOUPLING 14 J8 32 J8 GROUNDS U5 AGND J7 16 J8 U8 J8 34 +5VD 40 J8 +5VA 12 34 JG1-WIRE ETCH A 18 J8 NC 35 J8 CKT SIDE SJ6 C22 C26 U8 U5 20 J8 36 J8 0.1mF 0.1mF 1 2 3 4 22 NC 37 J8 J8 A U8 24 J8 38 J8 74HC04 13 12 SPARE GATES A 74HC14 JG1 SJ1 SJ2 SJ3 SJ4 SJ5 DRVSS AVDD2 DVSS AVDD1 DRVDD AVSS2 DVDD AVSS1 AD9243 Figure 52. Evaluation Board Component Side Layout (Not to Scale) Figure 53. Evaluation Board Solder Side Layout (Not to Scale) –22– REV. A AD9243 Figure 54. Evaluation Board Ground Plane Layout (Not to Scale) Figure 55. Evaluation Board Power Plane Layout (Not to Scale) REV. A –23– AD9243 OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 44-Lead Metric Quad Flatpack (MQFP) (S-44) 13.45 (0.530) 12.95 (0.510) 2.45 (0.096) 10.1 (0.398) MAX 9.90 (0.390) 1.03 (0.041) 08 0.73 (0.029) 44 34 MIN 1 33 SEATING PIN 1 PLANE IDENTIFIER 8.45 (0.333) TOP VIEW (PINS DOWN) 8.3 (0.327) 11 23 0.25 (0.01) 12 22 MIN 0.23 (0.009) 0.13 (0.005) 0.45 (0.018) 0.8 (0.031) BSC 2.1 (0.083) 0.3 (0.012) 1.95 (0.077) –24– REV. A PRINTED IN U.S.A. C2202a–0–5/98