ANALOG DEVICES AD9241

Complete 14-Bit, 1.25 MSPS a Monolithic A/D Converter AD9241 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 14-Bit, 1.25 MSPS A/D Converter Low Power Dissipation: 60 mW CLK AVDD DVDD DRVDD Single +5 V Supply SHA Integral Nonlinearity Error: 2.5 LSB VINA MDAC1 MDAC2 MDAC3 GAIN = 16 GAIN = 8 Differential Nonlinearity Error: 0.6 LSB VINB GAIN = 8 5 4 Input Referred Noise: 0.36 LSB 4 CML A/D A/D A/D A/D Complete: On-Chip Sample-and-Hold Amplifier and CAPT 5 4 4 4 Voltage Reference CAPB DIGITAL CORRECTION LOGIC Signal-to-Noise and Distortion Ratio: 78.0 dB 14 VREF OTR OUTPUT BUFFERS Spurious-Free Dynamic Range: 88.0 dB SENSE BIT 1 Out-of-Range Indicator (MSB) 1V MODE Straight Binary Output Data SELECT AD9241 BIT 14 (LSB) 44-Pin MQFP REFCOM AVSS DVSS DRVSS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-to- The AD9241 offers a complete single-chip sampling 14-bit, digital converter (ADC). It combines a low cost, high speed analog-to-digital conversion function in a 44-pin Metric Quad CMOS process and a novel architecture to achieve the resolution Flatpack. and speed of existing hybrid implementations at a fraction of the Low Power and Single Supply power consumption and cost. It is a complete, monolithic ADC The AD9241 consumes only 60 mW on a single +5 V power with an on-chip, high performance, low noise sample-and-hold supply. amplifier and programmable voltage reference. An external refer- Excellent DC Performance Over Temperature ence can also be chosen to suit the dc accuracy and temperature The AD9241 provides no missing codes, and excellent tempera- drift requirements of the application. The device uses a multistage ture drift performance over the full operating temperature range. differential pipelined architecture with digital output error correc- tion logic to guarantee no missing codes over the full operating Excellent AC Performance and Low Noise temperature range. The AD9241 provides nearly 13 ENOB performance and has an input referred noise of 0.36 LSB rms. The input of the AD9241 is highly flexible, allowing for easy Flexible Analog Input Range interfacing to imaging, communications, medical, and data- The versatile onboard sample-and-hold (SHA) can be configured acquisition systems. A truly differential input structure allows for either single-ended or differential inputs of varying input spans. for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) is equally Flexible Digital Outputs suited for both multiplexed systems that switch full-scale voltage The digital outputs can be configured to interface with +3 V and levels in successive channels as well as sampling single-channel +5 V CMOS logic families. inputs at frequencies up to and beyond the Nyquist rate. Also, the AD9241 performs well in communication systems employ- ing Direct-IF Down Conversion since the SHA in the differen- tial input mode can achieve excellent dynamic performance well beyond its specified Nyquist frequency of 0.625 MHz. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an over- flow condition which can be used with the most significant bit to determine low or high overflow. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 617/326-8703 © Analog Devices, Inc., 1997 otherwise under any patent or patent rights of Analog Devices. AD9241–SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = 1.25 MSPS, VREF = 2.5 V, VINB = 2.5 V, SAMPLE DC SPECIFICATIONS T to T unless otherwise noted) MIN MAX Parameter AD9241 Units RESOLUTION 14 Bits min MAX CONVERSION RATE 1.25 MHz min INPUT REFERRED NOISE VREF = 1 V 0.9 LSB rms typ VREF = 2.5 V 0.36 LSB rms typ ACCURACY Integral Nonlinearity (INL) ±2.5 LSB typ Differential Nonlinearity (DNL) ±0.6 LSB typ ±1.0 LSB max 1 INL ±2.5 LSB typ 1 DNL ±0.7 LSB typ No Missing Codes 14 Bits Guaranteed Zero Error (@ +25°C) 0.3 % FSR max 2 Gain Error (@ +25°C) 1.5 % FSR max 3 Gain Error (@ +25°C) 0.75 % FSR max TEMPERATURE DRIFT Zero Error 3.0 ppm/°C typ 2 Gain Error 20.0 ppm/°C typ 3 Gain Error 5.0 ppm/°C typ POWER SUPPLY REJECTION 0.1 % FSR max ANALOG INPUT Input Span (with VREF = 1.0 V) 2 V p-p min Input Span (with VREF = 2.5 V) 5 V p-p max Input (VINA or VINB) Range 0 V min AVDD V max Input Capacitance 16 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1 Volts typ Output Voltage Tolerance (1 V Mode) ±14 mV max Output Voltage (2.5 V Mode) 2.5 Volts typ Output Voltage Tolerance (2.5 V Mode) ±35 mV max 4 Load Regulation 5.0 mV max REFERENCE INPUT RESISTANCE 5 kΩ typ POWER SUPPLIES Supply Voltages AVDD +5 V (±5% AVDD Operating) DVDD +5 V (±5% DVDD Operating) DRVDD +5 V (±5% DRVDD Operating) Supply Current IAVDD 13.0 mA max (10 mA typ ) IDRVDD 1.0 mA max (1 mA typ ) IDVDD 3.0 mA max (2 mA typ ) POWER CONSUMPTION 65 mW typ 85 mW max NOTES 1 VREF =1 V. 2 Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9241). Specification subject to change without notice. –2– REV. 0 AD9241 (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = 1.25 MSPS, VREF = 2.5 V, A = –0.5 dBFS, AC Coupled/ SAMPLE IN AC SPECIFICATIONS Differential Input, T to T unless otherwise noted) MIN MAX Parameter AD9241 Units SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) f = 100 kHz 78.0 dB typ INPUT f = 500 kHz 74.5 dB min INPUT 77.0 dB typ EFFECTIVE NUMBER OF BITS (ENOB) f = 100 kHz 12.7 Bits typ INPUT f = 500 kHz 12.1 Bits min INPUT 12.5 Bits typ SIGNAL-TO-NOISE RATIO (SNR) f = 100 kHz 79.0 dB typ INPUT f = 500 kHz 75.5 dB min INPUT 79.0 dB typ TOTAL HARMONIC DISTORTION (THD) f = 100 kHz –88.0 dB typ INPUT f = 500 kHz –77.5 dB max INPUT –88.0 dB typ SPURIOUS FREE DYNAMIC RANGE f = 100 kHz 88.0 dB typ INPUT f = 500 kHz 86.0 dB typ INPUT DYNAMIC PERFORMANCE Full Power Bandwidth 25 MHz typ Small Signal Bandwidth 25 MHz typ Aperture Delay 1 ns typ Aperture Jitter 4 ps rms typ Acquisition to Full-Scale Step (0.0025%) 240 ns typ Overvoltage Recovery Time 167 ns typ Specifications subject to change without notice. (AVDD = +5 V, DVDD = +5 V, T to T unless otherwise noted) DIGITAL SPECIFICATIONS MIN MAX Parameters Symbol AD9241 Units LOGIC INPUTS High Level Input Voltage V +3.5 V min IH Low Level Input Voltage V +1.0 V max IL High Level Input Current (V = DVDD) I ±10 μA max IN IH Low Level Input Current (V = 0 V) I ±10 μA max IN IL Input Capacitance C 5 pF typ IN LOGIC OUTPUTS (with DRVDD = 5 V) High Level Output Voltage (I = 50 μA) V +4.5 V min OH OH High Level Output Voltage (I = 0.5 mA) V +2.4 V min OH OH Low Level Output Voltage (I = 1.6 mA) V +0.4 V max OL OL Low Level Output Voltage (I = 50 μA) V +0.1 V max OL OL Output Capacitance C 5 pF typ OUT LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (I = 50 μA) V +2.4 V min OH OH Low Level Output Voltage (I = 50 μA) V +0.7 V max OL OL Specifications subject to change without notice. –3– REV. 0 AD9241 (T to T with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, C = 20 pF) SWITCHING SPECIFICATIONS MIN MAX L Parameters Symbol AD9241 Units 1 Clock Period t 800 ns min C CLOCK Pulse Width High t 360 ns min CH CLOCK Pulse Width Low t 360 ns min CL Output Delay t 8 ns min OD 13 ns typ 19 ns max Pipeline Delay (Latency) 3 Clock Cycles NOTES 1 The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C. Specifications subject to change without notice. THERMAL CHARACTERISTICS S1 S2 Thermal Resistance ANALOG S4 t C INPUT 44-Pin MQFP S3 t t CH CL θ = 53.2°C/W JA INPUT θ = 19°C/W JC CLOCK t OD ORDERING GUIDE DATA DATA 1 OUTPUT Temperature Package Package Model Range Description Option* Figure 1. Timing Diagram o o AD9241AS –40 C to +85 C 44-Pin MQFP S-44 AD9241EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* *S = Metric Quad Flatpack. With Respect Parameter to Min Max Units PIN CONNECTION AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V 44 43 42 41 40 39 38 37 36 35 34 DRVDD DRVSS –0.3 +6.5 V DRVSS AVSS –0.3 +0.3 V DVSS 1 33 REFCOM PIN 1 REFCOM AVSS –0.3 +0.3 V IDENTIFIER AVSS 2 32 VREF CLK DVSS –0.3 DVDD + 0.3 V DVDD 3 31 SENSE Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AVDD 4 30 NC VINA, VINB AVSS –0.3 AVDD + 0.3 V DRVSS 5 29 AVSS AD9241 VREF AVSS –0.3 AVDD + 0.3 V DRVDD 6 28 AVDD TOP VIEW SENSE AVSS –0.3 AVDD + 0.3 V (Not to Scale) CLK 7 27 NC CAPB, CAPT AVSS –0.3 AVDD + 0.3 V NC NC 8 26 Junction Temperature +150 °C NC 9 25 OTR Storage Temperature –65 +150 °C 10 BIT 1 (MSB) NC 24 Lead Temperature (LSB) BIT 14 11 23 BIT 2 (10 sec) +300 °C 13 20 12 14 15 16 17 18 19 21 22 *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings NC = NO CONNECT for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9241 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 NC BIT 13 NC BIT 12 VINB BIT 11 BIT 10 VINA NC BIT 9 BIT 8 CML NC BIT 7 BIT 6 CAPT CAPB BIT 5 NC BIT 4 BIT 3 NC AD9241 PIN FUNCTION DESCRIPTIONS overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range. Pin Number Name Description TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the 1 DVSS Digital Ground maximum change from the initial (+25°C) value to the value at 2, 29 AVSS Analog Ground T or T . MIN MAX 3 DVDD +5 V Digital Supply 4, 28 AVDD +5 V Analog Supply POWER SUPPLY REJECTION 5 DRVSS Digital Output Driver Ground The specification shows the maximum change in full scale, 6 DRVDD Digital Output Driver Supply from the value with the supply at the minimum limit to the 7 CLK Clock Input Pin value with the supply at its maximum limit. 8–10 NC No Connect APERTURE JITTER 11 BIT 14 Least Significant Data Bit (LSB) Aperture jitter is the variation in aperture delay for successive 12–23 BIT 13–BIT 2 Data Output Bits samples and is manifested as noise on the input to the A/D. 24 BIT 1 Most Significant Data Bit (MSB) 25 OTR Out of Range APERTURE DELAY 26, 27, 30 NC No Connect Aperture delay is a measure of the sample-and-hold amplifier 31 SENSE Reference Select (SHA) performance and is measured from the rising edge of the 32 VREF Reference I/O clock input to when the input signal is held for conversion. 33 REFCOM Reference Common 34, 35, 38 NC No Connect SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) 40, 43, 44 RATIO 36 CAPB Noise Reduction Pin S/N+D is the ratio of the rms value of the measured input sig- 37 CAPT Noise Reduction Pin nal to the rms sum of all other spectral components below the 39 CML Common-Mode Level (Midsupply) Nyquist frequency, including harmonics but excluding dc. 41 VINA Analog Input Pin (+) The value for S/N+D is expressed in decibels. 42 VINB Analog Input Pin (–) EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the num- DEFINITIONS OF SPECIFICATION ber of bits. Using the following formula, INTEGRAL NONLINEARITY (INL) N = (SINAD – 1.76)/6.02 INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” it is possible to get a measure of performance expressed as N, The point used as “negative full scale” occurs 1/2 LSB before the effective number of bits. the first code transition. “Positive full scale” is defined as a level Thus, the effective number of bits for a device for sine wave 1 1/2 LSB beyond the last code transition. The deviation is inputs at a given input frequency can be calculated directly measured from the middle of each particular code to the true from its measured SINAD. straight line. TOTAL HARMONIC DISTORTION (THD) DIFFERENTIAL NONLINEARITY (DNL, NO MISSING THD is the ratio of the rms sum of the first six harmonic CODES) components to the rms value of the measured input signal; this An ideal ADC exhibits code transitions that are exactly 1 LSB is expressed as a percentage or in decibels. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 SIGNAL-TO-NOISE RATIO (SNR) codes, respectively, must be present over all operating ranges. SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the ZERO ERROR Nyquist frequency, excluding the first six harmonics and dc. The major carry transition should occur for an analog value The value for SNR is expressed in decibels. 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the GAIN ERROR input signal and the peak spurious signal. The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should TWO-TONE SFDR occur at an analog value 1 1/2 LSB below the nominal full The ratio of the rms value of either input tone to the rms value scale. Gain error is the deviation of the actual difference of the peak spurious component. The peak spurious component between first and last code transitions, and the ideal differ- may or may not be an IMD product. It may be reported in dBc ence between first and last code transitions. (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). OVERVOLTAGE RECOVERY TIME Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an REV. 0 –5– AD9241 (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = SAMPLE Typical Differential AC Characterization Curves/Plots 1.25 MSPS, T = +258C, Differential Input) A 0 80 –40 FUND –0.5dBFS –10 –20 75 –50 –30 –40 70 –6.0dBFS –50 –60 –60 65 –70 –20.0dBFS –80 60 –70 –20dBFS –90 2 4 6 7 –100 3 9 5 8 55 –110 –6.0dBFS –80 –120 50 –130 –140 –90 45 –150 –0.5dBFS –160 40 –100 –170 0 100 200 300 400 500 600 0.01 0.1 1.0 10.0 0.01 0.1 1.0 10.0 FREQUENCY – kHz INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz Figure 2. SINAD vs. Input Frequency Figure 4. Typical FFT, f > 500 kHz Figure 3. THD vs. Input Frequency IN (Input Span = 5 V, V = 2.5 V) (Input Span = 5 V, V = 2.5 V) CM (Input Span = 5 V, V = 2.5 V) CM CM 80 0 –40 FUND –10 75 –20 –50 –30 –0.5dBFS 70 –40 –50 –60 –60 65 –70 –20.0dBFS –6.0dBFS –80 60 –70 2 –90 4 3 7 –100 8 55 5 9 6 –110 –80 –20.0dBFS –6.0dBFS –120 50 –130 –90 –140 45 –150 –0.5dBFS –160 40 –100 –170 0.01 0.1 1.0 10.0 0 100 200 300 400 500 600 0.01 0.1 1.0 10.0 FREQUENCY – kHz INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz Figure 7. Typical FFT, f > 500 kHz Figure 5. SINAD vs. Input Frequency IN Figure 6. THD vs. Input Frequency (Input Span = 2 V, V = 2.5 V) (Input Span = 2 V, V = 2.5 V) CM CM (Input Span = 2 V, V = 2.5 V) CM –40 110 110 105 5V SPAN - dBFS 100 dBFS - 5V –50 100 90 95 –60 2V SPAN - dBFS 90 dBc - 5V 80 –70 85 70 dBFS - 5V 80 –80 5V SPAN - dBc 75 60 5V SPAN 2V SPAN - dBc 70 dBc - 2V –90 50 65 2V SPAN –100 40 60 0.1 1.0 10.0 –39 –33 –27 –21 –15 –9 –3 0 –40 –35 –30 –25 –20 –15 –10 –5 0 –45 SAMPLE RATE – MSPS INPUT POWER LEVEL (f = f ) – dBFS AIN – dBFS 1 2 Figure 10. Dual Tone SFDR Figure 8. THD vs. Sample Rate Figure 9. Single Tone SFDR (f = 0.5 MHz, f = 0.6 MHz, 1 2 (f = 0.3 MHz, A = –0.5 dBFS, (f = 0.6 MHz, V = 2.5 V) IN IN IN CM V = 2.5 V) CM V = 2.5 V) CM –6– REV. 0 THD – dB SINAD – dB SINAD – dB THD – dB THD – dB SFDR – dBc AND dBFS AMPLITUDE – dB AMPLITUDE – dB WORST CASE SPURIOUS – dBc AND dBFS AD9241 (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f = 1.25 MSPS, T = +258C, SAMPLE A Other Characterization Curves/Plots Single-Ended Input) 100% 3.0 1.0 12,901,627 2.5 0.8 2.0 0.6 1.5 0.4 1.0 0.5 0.2 0.0 0.0 –0.5 –0.2 –1.0 –0.4 –1.5 1,137,700 1,146,291 –0.6 –2.0 –2.5 –0.8 –3.0 –1.0 N–1 N N+1 0 16383 16383 0 CODE CODE CODE Figure 13. “Grounded-Input” Figure 11. Typical INL Figure 12. Typical DNL Histogram (Input Span = 5 V) (Input Span = 5 V) (Input Span = 5 V) 40 –40 90 85 –50 50 80 –60 75 –0.5dBFS 60 –6.0dBFS –20dBFS –70 70 –6dBFS 70 65 –80 –20.0dBFS –0.5dBFS 60 80 –90 55 –100 90 50 0.01 0.1 1.0 10.0 100 0.01 0.1 1.0 10.0 0.01 0.1 1.0 10.0 INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz FREQUENCY – MHz Figure 14. SINAD vs. Input Frequency Figure 15. THD vs. Input Frequency Figure 16. CMR vs. Input Frequency (Input Span = 2 V, V = 2.5 V) CM (Input Span = 2 V, V = 2.5 V) CM (Input Span = 2 V, V = 2.5 V) CM 0.01 90 –40 85 0.008 –50 80 0.006 –0.5dBFS 75 0.004 –60 70 0.002 –6dBFS 65 –70 0 –20dBFS –20dBFS 60 –6dBFS –0.002 –80 55 –0.004 –0.5dBFS 50 –0.006 –90 45 –0.008 40 –100 –0.01 0.01 0.1 1.0 10.0 0.01 0.1 1.0 10.0 –60 –40 –20 0 20 40 60 80 100 120 140 INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz TEMPERATURE – 8C Figure 18. THD vs. Input Frequency Figure 17. SINAD vs. Input Frequency Figure 19. Typical Voltage Reference (Input Span = 5 V, V = 2.5 V) (Input Span = 5 V, V = 2.5 V) CM CM Error vs. Temperature REV. 0 –7– INL – LSB SINAD – dB SINAD – dB DNL – LSB THD – dB THD – dB V ERROR – V CMR – dB REF HITS AD9241 INTRODUCTION converter. Specifically, the input to the A/D core is the difference The AD9241 uses a four-stage pipeline architecture with a of the voltages applied at the VINA and VINB input pins. wideband input sample-and-hold amplifier (SHA) implemented Therefore, the equation, on a cost-effective CMOS process. Each stage of the pipeline, V = VINA – VINB (1) CORE excluding the last, consists of a low resolution flash A/D con- defines the output of the differential input stage and provides the nected to a switched capacitor DAC and interstage residue input to the A/D core. amplifier (MDAC). The residue amplifier amplifies the differ- ence between the reconstructed DAC output and the flash input The voltage, V , must satisfy the condition, CORE for the next stage in the pipeline. One bit of redundancy is used –VREF ≤ V ≤ VREF (2) CORE in each of the stages to facilitate digital correction of flash er- where VREF is the voltage at the VREF pin. rors. The last stage simply consists of a flash A/D. While an infinite combination of VINA and VINB inputs exist The pipeline architecture allows a greater throughput rate at the to satisfy Equation 2, an additional limitation is placed on the expense of pipeline delay or latency. This means that while the inputs by the power supply voltages of the AD9241. The power converter is capable of capturing a new input sample every clock supplies bound the valid operating range for VINA and VINB. cycle, it actually takes three clock cycles for the conversion to be The condition, fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) the out-of-range indicator (OTR), is latched into an output AVSS – 0.3 V < VINB < AVDD + 0.3 V buffer to drive the output pins. The output drivers can be con- figured to interface with +5 V or +3.3 V logic families. where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. Thus, the range of valid inputs for The AD9241 uses both edges of the clock in its internal timing VINA and VINB is any combination that satisfies both Equa- circuitry (see Figure 1 and specification page for exact timing tions 2 and 3. requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the For additional information showing the relationship between falling edge and rising edge of the clock), the input SHA is in VINA, VINB, VREF and the digital output of the AD9241, see the sample mode; during the clock high time it is in the hold Table IV. mode. System disturbances just prior to the rising edge of the Refer to Table I and Table II for a summary of the various clock and/or excessive clock jitter may cause the input SHA to analog input and reference configurations. acquire the wrong value and should be minimized. ANALOG INPUT OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Figure 21 shows the equivalent analog input of the AD9241, Figure 20, a simplified model of the AD9241, highlights the rela- which consists of a differential sample-and-hold amplifier tionship between the analog inputs, VINA, VINB, and the (SHA). The differential input structure of the SHA is highly reference voltage, VREF. Like the voltage applied to the top of flexible, allowing the devices to be easily configured for either a the resistor ladder in a flash A/D converter, the value VREF defines differential or single-ended input. The dc offset, or common- the maximum input voltage to the A/D core. The minimum input mode voltage, of the input(s) can be set to accommodate either voltage to the A/D core is automatically defined to be –VREF. single-supply or dual supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable, with the exception AD9241 that reversing the inputs to the VINA and VINB pins results in a +VREF VINA polarity inversion. V 14 CORE A/D C CORE H Q S2 VINB –VREF + C PIN C Q C S1 S PAR VINA Q C Figure 20. Equivalent Functional Input Circuit Q H1 S S1 VINB – C The addition of a differential input structure gives the user an PIN Q S2 C PAR additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- C H ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the Figure 21. Simplified Input Circuit –8– REV. 0 AD9241 The input SHA of the AD9241 is optimized to meet the perfor- 1 V and 2.5 V. Note the difference in the amount of degrada- mance requirements for some of the most demanding commu- tion in THD performance as the input frequency increases. nication, imaging and data acquisition applications, while Similarly, note how the THD performance at lower frequencies maintaining low power dissipation. Figure 22 is a graph of the becomes less sensitive to the common-mode voltage. As the full-power bandwidth of the AD9241, typically 40 MHz. Note input frequency approaches dc, the distortion will be domi- that the small signal bandwidth is the same as the full-power nated by static nonlinearities such as INL and DNL. It is bandwidth. The settling time response to a full-scale stepped important to note that these dc static nonlinearities are inde- input is shown in Figure 23 and is typically less than 80 ns to pendent of any R modulation. ON 0.0025%. The low input referred noise of 0.36 LSB’s rms is –40 displayed via a grounded histogram and is shown in Figure 13. –45 2 –50 0 –55 –2 –60 –65 –4 –70 –6 V = 1V CM –75 –8 –80 V = 2.5V CM –85 –10 0.01 0.1 1.0 10.0 FREQUENCY – MHz –12 0.01 0.1 1.0 10.0 100 Figure 24. THD vs. Frequency for V = 2.5 V and 1.0 V CM FREQUENCY – MHz (A = –0.5 dB, Input Span = 2.0 V p-p) IN Figure 22. Full-Power Bandwidth Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen- 16000 tial input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. In addition, 12000 the required input signal voltage span is reduced by a factor of two, which further reduces the degree of R modulation and ON its effects on distortion. 8000 The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched 4000 input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in AD9241 DC SPECIFICATIONS. 0 0 10 20 30 40 50 60 70 80 Referring to Figure 21, the differential SHA is implemented SETTLING TIME – ns using a switched-capacitor topology. Hence, its input imped- ance and its subsequent effects on the input drive source should Figure 23. Settling Time be understood to maximize the converter’s performance. The combination of the pin capacitance, C , parasitic capacitance The SHA’s optimum distortion performance for a differential or PIN C and the sampling capacitance, C , is typically less than single-ended input is achieved under the following two condi- PAR, S 16 pF. When the SHA goes into track mode, the input source tions: (1) the common-mode voltage is centered around mid- must charge or discharge the voltage stored on C to the new supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input S input voltage. This action of charging and discharging C , which signal voltage span of the SHA is set at its lowest (i.e., 2 V input S is approximately 4 pF, averaged over a period of time and for a span). This is due to the sampling switches, Q , being CMOS S1 given sampling frequency, F , makes the input impedance ap- switches whose R resistance is very low but has some signal S ON pear to have a benign resistive component (i.e., 83 kΩ at F = dependency causing frequency-dependent ac distortion while S 1.25 MSPS). However, if this action is analyzed within a sam- the SHA is in the track mode. The R resistance of a CMOS ON pling period (i.e., T = <1/F ), the input impedance is dynamic switch is typically lowest at its midsupply, but increases sym- S due to the instantaneous requirement of charging and discharg- metrically as the input signal approaches either AVDD or ing C . A series resistor inserted between the input drive source AVSS. A lower input signal voltage span centered at midsupply S and the SHA input, as shown in Figure 25, provides effective reduces the degree of R modulation. ON isolation. Figure 24 compares the AD9241’s THD vs. frequency perfor- mance for a 2 V input span with a common-mode voltage of REV. 0 –9– CODE AMPLITUDE – dB THD – dB AD9241 V CC The noise or small-signal bandwidth of the AD9241 is the same AD9241 as its full-power bandwidth. For noise sensitive applications, the R * S VINA excessive bandwidth may be detrimental and the addition of a R * S series resistor and/or shunt capacitor can help limit the wide- VINB V band noise at the A/D’s input by forming a low-pass filter. Note, EE VREF however, that the combination of this series resistance with the 10µF 0.1µF equivalent input capacitance of the AD9241 should be evalu- SENSE ated for those time-domain applications that are sensitive to the REFCOM input signal’s absolute settling time. In applications where har- monic distortion is not a primary concern, the series resistance *OPTIONAL SERIES RESISTOR may be selected in combination with the SHA’s nominal 16 pF of input capacitance to set the filter’s 3 dB cutoff frequency. Figure 25. Series Resistor Isolates Switched-Capacitor SHA Input from Op Amp. Matching Resistors Improve A better method of reducing the noise bandwidth, while possi- SNR Performance bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., The optimum size of this resistor is dependent on several fac- VINA and/or VINB) and analog ground. Since this additional tors, including the AD9241 sampling rate, the selected op amp shunt capacitance combines with the equivalent input capaci- and the particular application. In most applications, a 30 Ω to tance of the AD9241, a lower series resistance can be selected 50 Ω resistor is sufficient. Some applications may require a to establish the filter’s cutoff frequency while not degrading the larger resistor value to reduce the noise bandwidth or possibly distortion performance of the device. The shunt capacitance limit the fault current in an overvoltage condition. Other appli- also acts as a charge reservoir, sinking or sourcing the additional cations may require a larger resistor value as part of an antialiasing charge required by the hold capacitor, C , further reducing H filter. In any case, since the THD performance is dependent on current transients seen at the op amp’s output. the series resistance and the above mentioned factors, optimiz- ing this resistor value for a given application is encouraged. The effect of this increased capacitive load on the op amp driv- ing the AD9241 should be evaluated. To optimize performance A slight improvement in SNR performance and dc offset when noise is the primary consideration, increase the shunt performance is achieved by matching the input resistance con- capacitance as much as the transient response of the input signal nected to VINA and VINB. The degree of improvement is depen- will allow. Increasing the capacitance too much may adversely dent on the resistor value and the sampling rate. For series affect the op amp’s settling time, frequency response and distor- resistor values greater than 100 Ω, the use of a matching tion performance. resistor is encouraged. Table I. Analog Input Configuration Summary Input Input Input Range (V) Figure 1 1 Connection Coupling Span (V) VINA VINB # Comments Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum THD and noise performance, requires ±5 V op amp. 2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to 2 × VREF increase in dynamic range. Headroom/settling time require- ments of ±5 V op amp should be evaluated. 5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires op amp with VCC > +5 V due to insufficient headroom @ 5 V. 2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance to improves while THD performance degrades as VREF increases 2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps. Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode 2 × VREF 0 to 2 × VREF level not biased at optimum midsupply level (i.e., 2.5 V). 5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance. 2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with to VREF = 1. Noise performance improves while THD performance 2.5 + VREF degrades as VREF increases to 2.5 V. Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well beyond DC the A/Ds Nyquist frequency. 2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale to to THD and SFDR performance can be traded off for better noise 2.5 + VREF/2 2.5 – VREF/2 performance. 5 1.25 to 3.75 3.75 to 1.25 29–31 Widest dynamic range (i.e., ENOBs) due to Optimum Noise performance. 1 VINA and VINB can be interchanged if signal inversion is required. –10– REV. 0 AD9241 REFERENCE OPERATION connected to the internal resistor network thus providing a The AD9241 contains an onboard bandgap reference that pro- VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a vides a pin-strappable option to generate either a 1 V or 2.5 V short or resistor, the switch is connected to the SENSE pin. A output. With the addition of two external resistors, the user can short will provide a VREF of 1.0 V while an external resistor generate reference voltages other than 1 V and 2.5 V. Another network will provide an alternative VREF between 1.0 V and alternative is to use an external reference for designs requiring 2.5 V. The second comparator controls internal circuitry that enhanced accuracy and/or drift performance. See Table II for a will disable the reference amplifier if the SENSE pin is tied to summary of the pin-strapping options for the AD9241 reference AVDD. Disabling the reference amplifier allows the VREF pin configurations. to be driven by an external voltage reference. Figure 26 shows a simplified model of the internal voltage refer- The actual reference voltages used by the internal circuitry of ence of the AD9241. A pin-strappable reference amplifier buff- the AD9241 appear on the CAPT and CAPB pins. For proper ers a 1 V fixed reference. The output from the reference amplifier, operation when using the internal or an external reference, it is A1, appears on the VREF pin. The voltage on the VREF pin necessary to add a capacitor network to decouple these pins. determines the full-scale input span of the A/D. This input span Figure 27 shows the recommended decoupling network. This equals, capacitive network performs the following three functions: (1) in conjunction with the reference amplifier, A2, it provides a low Full-Scale Input Span = 2 × VREF source impedance over a large frequency range to drive the A/D internal circuitry, (2) it provides the necessary compensation for AD9241 TO A2, and (3) it bandlimits the noise contribution from the refer- A/D ence. The turn-on time of the reference voltage appearing be- 5kΩ CAPT tween CAPT and CAPB is approximately 15 ms and should be 5kΩ evaluated in any power-down mode of operation. A2 5kΩ 0.1µF CAPB 5kΩ CAPT DISABLE LOGIC 0.1µF 10µF A2 AD9241 CAPB VREF 0.1µF A1 1V 7.5kΩ Figure 27. Recommended CAPT/CAPB Decoupling Network SENSE The A/D’s input span may be varied dynamically by changing DISABLE LOGIC 5kΩ A1 the differential reference voltage appearing across CAPT and REFCOM CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low Figure 26. Equivalent Reference Circuit noise amplifiers. In this case, both internal amplifiers (i.e., A1 The voltage appearing at the VREF pin, and the state of the and A2) must be disabled by connecting SENSE to AVDD and internal reference amplifier, A1, are determined by the voltage VREF to REFCOM, and the capacitive decoupling network appearing at the SENSE pin. The logic circuitry contains two removed. The external voltages applied to CAPT and CAPB comparators that monitor the voltage at the SENSE pin. The must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec- comparator with the lowest set point (approximately 0.3 V) tively where the input span can be varied between 2 V and 5 V. controls the position of the switch within the feedback path of Note that those samples within the pipeline A/D during any A1. If the SENSE pin is tied to REFCOM, the switch is reference transition will be corrupted and should be discarded. Table II. Reference Configuration Summary Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To INTERNAL 2 1 SENSE VREF INTERNAL 5 2.5 SENSE REFCOM INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD (NONDYNAMIC) VREF EXT. REF. EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD (DYNAMIC) Externally Driven VREF REFCOM EXT. REF. 1 CAPT EXT. REF. 2 CAPB REV. 0 –11– AD9241 AVDD DRIVING THE ANALOG INPUTS V CC INTRODUCTION D2 R R S1 S2 1N4148 30Ω 20Ω The AD9241 has a highly flexible input structure allowing it to AD9243 interface with single-ended or differential input interface cir- D1 1N4148 cuitry. The applications shown in sections Driving the Analog V EE Inputs and Reference Configurations, along with the informa- tion presented in Input and Reference Overview of this data Figure 28. Simple Clamping Circuit sheet, give examples of both single-ended and differential opera- tion. Refer to Tables I and II for a list of the different possible DIFFERENTIAL MODE OF OPERATION input and reference configurations and their associated figures Since not all applications have a signal preconditioned for differ- in the data sheet. ential operation, there is often a need to perform a single-ended- The optimum mode of operation, analog input range and asso- to-differential conversion. A single-ended-to-differential conversion ciated interface circuitry, will be determined by the particular can be realized with an RF transformer or a dual op amp differ- applications performance requirements as well as power supply ential driver. The optimum method depends on whether the options. For example, a dc coupled single-ended input may be application requires the input signal to be ac or dc coupled to appropriate for many data acquisition and imaging applications. AD9241. Also, many communication applications requiring a dc coupled AC Coupling via an RF Transformer input for proper demodulation can take advantage of the excel- In applications that do not need to be dc coupled, an RF trans- lent single-ended distortion performance of the AD9241. The former with a center tap is the best method of generating differ- input span should be configured so the system’s performance ential inputs for the AD9241. It provides all the benefits of objectives and the headroom requirements of the driving op amp operating the A/D in the differential mode without contributing are simultaneously met. additional noise or distortion. An RF transformer has the added Alternatively, the differential mode of operation provides the benefit of providing electrical isolation between the signal source best THD and SFDR performance over a wide frequency range. and the A/D. A transformer coupled differential input should be considered Figure 29 shows the schematic of the suggested transformer for the most demanding spectral-based applications that allow circuit. The circuit uses a Mini-Circuits RF transformer, model ac coupling (e.g., Direct IF to Digital Conversion). The dc #T4-6T, which has an impedance ratio of four (turns ratio of coupled differential mode of operation also provides an enhance- 2). The schematic assumes that the signal source has a 50 Ω ment in distortion and noise performance at higher input spans. source impedance. The 1:4 impedance ratio requires the 200 Ω Furthermore, it allows the AD9241 to be configured for a 5 V secondary termination for optimum power transfer and VSWR. span using op amps specified for +5 V or ±5 V operation. The centertap of the transformer provides a convenient means Single-ended operation requires that VINA be ac or dc coupled of level-shifting the input signal to a desired common-mode to the input signal source, while VINB of the AD9241 be biased voltage. Optimum performance can be realized when the centertap to the appropriate voltage corresponding to a midscale code is tied to CML of the AD9241 which is the common-mode bias transition. Note that signal inversion may be easily accom- level of the internal SHA. plished by transposing VINA and VINB. Differential operation requires that VINA and VINB be simulta- VINA 50Ω neously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the CML 0.1µF AD9241 AD9241 offers the following benefits: (1) Signal swings are 200Ω smaller and therefore linearity requirements placed on the input VINB signal source may be easier to achieve, (2) Signal swings are MINI-CIRCUITS smaller and therefore may allow the use of op amps that may T4-6T otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic prod- Figure 29. Transformer Coupled Input ucts and (4) Differential operation offers noise immunity based Transformers with other turns ratios may also be selected to on the device’s common-mode rejection as shown in Figure 16. optimize the performance of a given application. For example, a As is typical of most CMOS devices, exceeding the supply limits given input signal source or amplifier may realize an improve- will turn on internal parasitic diodes resulting in transient cur- ment in distortion performance at reduced output power levels rents within the device. Figure 28 shows a simple means of clamp- and signal swings. Hence, selecting a transformer with a higher ing a dc coupled input with the addition of two series resistors and impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 imped- two diodes. Note that a larger series resistor could be used to limit ance ratio) effectively “steps up” the signal level, further reduc- the fault current through D1 and D2, but should be evaluated ing the driving requirements of the signal source. since it can cause a degradation in overall performance. –12– REV. 0 AD9241 390Ω DC Coupling with Op Amps AVDD Applications that require dc coupling can also benefit by driv- 0.1µF ing the AD9241 differentially. Since the signal swing require- V –VIN 220.2Ω AD8047 CML 390Ω ments of each input is reduced by a factor of two in the differential 33Ω VINA mode, the AD9241 can be configured for a 5 V input span in a 390Ω 390Ω +5 V or ±5 V system. This allows various high performance op V IN amps specified for +5 V and ±5 V operation to be configured in AVDD various differential driver topologies. The optimum op amp 220.2Ω 390Ω 390Ω AD9241 driver topology depends on whether the common-mode voltage 0.1µF V +VIN CML of the single-ended-input signal requires level-shifting. AD8047 33Ω Figure 30 shows a cross-coupled differential driver circuit best VINB 390Ω 390Ω 2.5kΩ suited for systems in which the common-mode signal of the input is already biased to approximately midsupply (i.e., 2.5 V). 0.1µF The common-mode voltage of the differential output is set by 100Ω the voltage applied to the “+” input of A2. The closed loop CML gain of this symmetrical driver can easily be set by R and R . 0.1µF 1µF IN F OP113 For more insight into the operation of this cross-coupled driver, please refer to the AD8042 data sheet. Figure 31. Differential Driver with Level-Shifting 1kΩ R V +VIN F CML SINGLE-ENDED MODE OF OPERATION 1kΩ AD8042 V IN The AD9241 can be configured for single-ended operation R VINA A1 IN 33Ω using dc or ac coupling. In either case, the input of the A/D 1kΩ must be driven from an operational amplifier that will not de- grade the A/D’s performance. Because the A/D operates from a 1kΩ 1kΩ C * F single supply, it will be necessary to level-shift ground-based AD9241 bipolar signals to comply with its input requirements. Both dc V –VIN CML and ac coupling provide this necessary function, but each 1kΩ 33Ω method results in different interface issues that may influence A2 VINB the system design and performance. AD8042 AVDD/2 CML DC COUPLING AND INTERFACE ISSUES 0.1µF Many applications require the analog input signal to be dc *OPTIONAL NOISE/BAND LIMITING CAPACITOR coupled to the AD9241. An operational amplifier can be con- figured to rescale and level-shift the input signal to make it Figure 30. Cross-Coupled Differential Driver compatible with the selected input range of the A/D. The input range to the A/D should be selected on the basis of system The driver circuit shown in Figure 31 is best suited for systems performance objectives as well as the analog power supply in which the bipolar input signal is referenced to AGND and availability since this will place certain constraints on the op requires proper level shifting. This driver circuit provides the amp selection. ability to level-shift the input signal to within the common- mode range of the AD9241. The two op amps are configured as Many of the new high performance op amps are specified for matched difference amplifiers, with the input signal applied to only ±5 V operation and have limited input/output swing capa- opposing inputs to provide the differential output. The common- bilities. Hence, the selected input range of the AD9241 should mode offset voltage is applied to the noninverting resistor net- be sensitive to the headroom requirements of the particular op work that provides the proper level-shifting. The circuit also amp to prevent clipping of the signal. Also, since the output of employs optional diodes and pull-up resistors that may help a dual supply amplifier can swing below –0.3 V, clamping its improve the op amps’ distortion performance by reducing their output should be considered in some applications. headroom requirements. Rail-to-rail output amplifiers such as In some applications, it may be advantageous to use an op amp the AD8042 have sufficient headroom and do not require these specified for single supply +5 V operation since it will inher- optional components. ently limit its output swing to within the power supply rails. Rail-to-rail output amplifiers such as the AD8041 allow the AD9241 to be configured with larger input spans, which im- proves the noise performance. REV. 0 –13– AD9241 500Ω* If the application requires the largest single-ended input range (i.e., 0 V to 5 V) of the AD9241, the op amp will require larger +V CC 0.1µF supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to +VREF NC 500Ω* 0V 7 accommodate a wide range of supply options. Once again, clamp- DC 2 R –VREF 1 S ing the output of the amplifier should be considered for these A1 6 VINA R ** 500Ω* P applications. Alternatively, a single-ended-to-differential op amp 5 3 AVDD 4 driver circuit using the AD8042 could be used to achieve the NC 0.1µF 500Ω* AD9241 5 V input span while operating from a single +5 V supply, as R discussed in the previous section. S VREF VINB Two dc coupled op amp circuits using a noninverting and inverting *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE topology are discussed below. Although not shown, the nonin- verting and inverting topologies can easily be configured as part Figure 33. Single-Ended Input With DC-Coupled Level Shift of an antialiasing filter by using a Sallen-Key or Multiple-Feed- back topology, respectively. An additional R-C network can be AC COUPLING AND INTERFACE ISSUES inserted between the op amp’s output and the AD9241 input to For applications where ac coupling is appropriate, the op amp’s provide a real pole. output can easily be level-shifted to the common-mode voltage, Simple Op Amp Buffer V , of the AD9241 via a coupling capacitor. This has the CM In the simplest case, the input signal to the AD9241 will already advantage of allowing the op amps common-mode level to be be biased at levels in accordance with the selected input range. symmetrically biased to its midsupply level (i.e., (V + V )/2). CC EE It is merely a matter of providing an adequately low source imped- Op amps that operate symmetrically with respect to their power ance for the VINA and VINB analog input pins of the A/D. Figure supplies typically provide the best ac performance as well as the 32 shows the recommended configuration for a single-ended drive greatest input/output span. Hence, various high speed/performance using an op amp. In this case, the op amp is shown in a nonin- amplifiers that are restricted to +5 V/–5 V operation and/or verting unity gain configuration driving the VINA pin. The specified for +5 V single-supply operation can easily be config- internal reference drives the VINB pin. Note that the addition of ured for the 5 V or 2 V input span of the AD9241, respectively. a small series resistor of 30 Ω to 50 Ω connected to VINA and The best ac distortion performance is achieved when the A/D is VINB will be beneficial in nearly all cases. Refer to section configured for a 2 V input span and common-mode voltage of Analog Input Operation for a discussion on resistor selection. 2.5 V. Note that differential transformer coupling, another form of Figure 32 shows the proper connection for a 0 V to 5 V input ac coupling, should be considered for optimum ac performance. range. Alternative single ended input ranges of 0 V to 2 × VREF Simple AC Interface can also be realized with the proper configuration of VREF Figure 34 shows a typical example of an ac-coupled, single- (refer to the section Using the Internal Reference). ended configuration. The bias voltage shifts the bipolar, ground- +V referenced input signal to approximately VREF. The value for AD9241 5V C1 and C2 will depend on the size of the resistor, R. The ca- R S 0V U1 VINA pacitors, C1 and C2, are typically a 0.1 μF ceramic and 10 μF R S tantalum capacitor in parallel to achieve a low cutoff frequency VINB –V 2.5V while maintaining a low impedance over a wide frequency range. VREF The combination of the capacitor and the resistor form a high- 10µF 0.1µF pass filter with a high-pass –3 dB frequency determined by the SENSE equation, f = 1/(2 × π × R × (C1 + C2)) –3 dB Figure 32. Single-Ended AD9241 Op Amp Drive Circuit The low impedance VREF voltage source both biases the VINB Op Amp with DC Level Shifting input and provides the bias voltage for the VINA input. Figure Figure 33 shows a dc-coupled level shifting circuit employing an 34 shows the VREF configured for 2.5 V. Thus the input range op amp, A1, to sum the input signal with the desired dc offset. Configuring the op amp in the inverting mode with the given C1 +5V resistor values results in an ac signal gain of –1. If the signal AD9241 +VREF inversion is undesirable, interchange the VINA and VINB con- C2 R S V IN 0V VINA nections to reestablish the original signal polarity. The dc volt- –VREF age at VREF sets the common-mode voltage of the AD9241. For R R S –5V example, when VREF = 2.5 V, the output level from the op amp VINB will also be centered around 2.5 V. The use of ratio matched, VREF thin-film resistor networks will minimize gain and offset errors. C2 C1 SENSE Also, an optional pull-up resistor, R , may be used to reduce the P output load on VREF to ±1 mA. Figure 34. AC-Coupled Input –14– REV. 0 AD9241 of the A/D is 0 V to 5 V. Other input ranges could be selected AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur- by changing VREF, but the A/D’s distortion performance will rent Feedback, +5 V to ±15 V Supplies degrade slightly as the input common-mode voltage deviates Best Applications: Differential and/or Low Imped- from its optimum level of 2.5 V. ance Input Drivers Limits: THD above 1 MHz Alternative AC Interface Figure 35 shows a flexible ac coupled circuit that can be config- AD8011: f = 300 MHz, +5 V or ±5 V Supplies, Current –3 dB ured for different input spans. Since the common-mode voltage Feedback of VINA and VINB are biased to midsupply independent of Best Applications: Single-Supply, AC/DC-Coupled, VREF, VREF can be pin-strapped or reconfigured to achieve Good AC Specs, Low Noise, Low Power (5 mW) input spans between 2 V and 5 V p-p. The AD9241’s CMRR, Limits: THD above 5 MHz, Usable Input/Output along with the symmetrical coupling R-C networks, will reject Range both power supply variations and noise. The resistors, R, estab- AD8013: Triple, f = 230 MHz, +5 V or ±5 V supplies, –3 dB lish the common-mode voltage. They may have a high value (e.g., Current Feedback, Disable Function 5 kΩ) to minimize power consumption and establish a low cutoff Best Applications: 3:1 Multiplexer, Good AC Specs frequency. The capacitors, C1 and C2, are typically a 0.1 μF Limits: THD above 5 MHz, Input Range ceramic and 10 μF tantalum capacitor in parallel to achieve a AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%, low cutoff frequency while maintaining a low impedance over a ±5 V Supplies wide frequency range. R isolates the buffer amplifier from the S Best Applications: Best AC Specs, Low Noise, A/D input. The optimum performance is achieved when VINA AC-Coupled and VINB are driven via symmetrical networks. The high-pass Limits: Usable Input/Output Range, Power f point can be approximated by the equation, –3 dB Consumption f = 1/(2 × π × R/2 × (C1 + C2)) –3 dB AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%, +5V ±5 V Supplies +5V Best Applications: Good AC Specs, Low Noise, AD9241 R C1 R S AC-Coupled V IN VINA Limits: THD > 5 MHz, Usable Input Range C2 R AD8041: Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling –5V to 0.01%, +5 V Supply, 26 mW R R S Best Applications: Low Power, Single-Supply Sys- VINB +5V tems, DC-Coupled, Large Input Range C2 C1 R Limits: Noise with 2 V Input Range AD8042: Dual AD8041 Best Applications: Differential and/or Low Imped- Figure 35. AC-Coupled Input-Flexible Input Span, V = 2.5 V CM ance Input Drivers Limits: Noise with 2 V Input Range OP AMP SELECTION GUIDE Op amp selection for the AD9241 is highly dependent on a REFERENCE CONFIGURATIONS particular application. In general, the performance requirements The figures associated with this section on internal and external of any given application can be characterized by either time reference operation do not show recommended matching series domain or frequency domain parameters. In either case, one resistors for VINA and VINB for the purpose of simplicity. should carefully select an op amp that preserves the performance Please refer to section Driving the Analog Inputs, Introduction, for of the A/D. This task becomes challenging when one considers a discussion of this topic. Also, the figures do not show the the high performance capabilities of the AD9241, coupled with decoupling network associated with the CAPT and CAPB pins. other external system level requirements such as power con- Please refer to the Reference Operation section for a discussion of sumption and cost. the internal reference circuitry and the recommended decoupling network shown in Figure 27. The ability to select the optimal op amp may be further compli- cated by limited power supply availability and/or limited accept- USING THE INTERNAL REFERENCE able supplies for a desired op amp. Newer, high performance op Single-Ended Input with 0 to 2 3 VREF Range amps typically have input and output range limitations in accor- Figure 36 shows how to connect the AD9241 for a 0 V to 2 V or dance with their lower supply voltages. As a result, some op 0 V to 5 V input range via pin strapping the SENSE pin. An inter- amps will be more appropriate in systems where ac-coupling is mediate input range of 0 to 2 × VREF can be established using allowable. When dc-coupling is required, op amps without the resistor programmable configuration in Figure 38 and con- headroom constraints, such as rail-to-rail op amps or those necting VREF to VINB. where larger supplies can be used, should be considered. The In either case, both the common-mode voltage and input span following section describes some op amps currently available are directly dependent on the value of VREF. More specifically, from Analog Devices. The system designer is always encouraged the common-mode voltage is equal to VREF while the input to contact the factory or local sales office to be updated on span is equal to 2 × VREF. Thus, the valid input range extends Analog Devices’ latest amplifier product offerings. Highlights of from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output the areas where the op amps excel, and where they may limit the will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output performance of the AD9241, are also included. will be 3FFF Hex. REV. 0 –15– AD9241 Shorting the VREF pin directly to the SENSE pin places the ternal resistors and a bypass capacitor. Use the equation, internal reference amplifier in unity-gain mode and the resultant VREF = 1 V × (1 + R1/R2), VREF output is 1 V. Therefore, the valid input range is 0 V to to determine appropriate values for R1 and R2. These resistors 2 V. However, shorting the SENSE pin directly to the REFCOM should be in the 2 kΩ to 100 kΩ range. For the example shown, pin configures the internal reference amplifier for a gain of 2.5 R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above, and the resultant VREF output is 2.5 V. Thus, the valid input the resultant reference voltage on the VREF pin is 1.5 V. This range becomes 0 V to 5 V. The VREF pin should be bypassed sets the input span to be 3 V p-p. To assure stability, place a to the REFCOM pin with a 10 μF tantalum capacitor in parallel 0.1 μF ceramic capacitor in parallel with R1. with a low-inductance 0.1 μF ceramic capacitor. The common-mode voltage can be set to VREF by connecting 2xVREF VINB to VREF to provide an input span of 0 to 2 × VREF. VINA 0V Alternatively, the common-mode voltage can be set to 2.5 V VINB by connecting VINB to a low impedance 2.5 V source. For 10µF 0.1µF the example shown, the valid input signal range for VINA is VREF AD9241 1 V to 4 V since VINB is set to an external, low impedance SHORT FOR 0 TO 2V INPUT SPAN 2.5 V source. The VREF pin should be bypassed to the REFCOM SENSE pin with a 10 μF tantalum capacitor in parallel with a low induc- SHORT FOR 0 TO 5V tance 0.1 μF ceramic capacitor. INPUT SPAN REFCOM 4V VINA 1V 2.5V VINB Figure 36. Internal Reference (2 V p-p Input Span, 1.5V V = 1 V, or 5 V p-p Input Span, V = 2.5 V) CM CM VREF R1 C1 AD9241 10µF 0.1µF Single-Ended or Differential Input, V = 2.5 V 2.5kΩ 0.1µF CM SENSE Figure 37 shows the single-ended configuration that gives the R2 best SINAD performance. To optimize dynamic specifications, 5kΩ center the common-mode voltage of the analog input at REFCOM approximately 2.5 V by connecting VINB to VREF, a low- impedance 2.5 V source. As described above, shorting the SENSE pin directly to the REFCOM pin results in a 2.5 V Figure 38. Resistor Programmable Reference (3 V p-p reference voltage and a 5 V p-p input span. The valid range Input Span, V = 2.5 V) CM for input signals is 0 V to 5 V. The VREF pin should be by- passed to the REFCOM pin with a 10 μF tantalum capacitor in USING AN EXTERNAL REFERENCE parallel with a low inductance 0.1 μF ceramic capacitor. Using an external reference may enhance the dc performance This reference configuration could also be used for a differential of the AD9241 by improving drift and accuracy. Figures 39 input wherein VINA and VINB are driven via a transformer as through 41 show examples of how to use an external reference shown in Figure 29. In this case, the common-mode voltage, with the A/D. Table III is a list of suitable voltage references V , is set at midsupply by connecting the transformers center CM from Analog Devices. To use an external reference, the user tap to CML of the AD9241. VREF can be configured for 1 V or must disable the internal reference amplifier and drive the VREF 2.5 V by connecting SENSE to either VREF or REFCOM pin. Connecting the SENSE pin to AVDD disables the inter- respectively. Note that the valid input range for each of the nal reference amplifier. differential inputs is one half of the single-ended input and thus becomes V – VREF/2 to V + VREF/2. CM CM Table III. Suitable Voltage References Initial Operating 5V VINA Output Drift Accuracy Current 0V Voltage (ppm/8C) % (max) (mA) VINB AD9241 Internal 1.00 26 1.4 N/A 2.5V AD589 1.235 10–100 1.2–2.8 50 VREF AD1580 1.225 50–100 0.08–0.8 50 10µF 0.1µF SENSE REF191 2.048 5–25 0.1–0.5 45 Internal 2.50 26 1.4 N/A REFCOM REF192 2.50 5–25 0.08–0.4 45 REF43 2.50 10–25 0.06–0.1 600 AD780 2.50 3–7 0.04–0.2 1000 Figure 37. Internal Reference—5 V p-p Input Span, V = 2.5 V CM The AD9241 contains an internal reference buffer, A2 (see Resistor Programmable Reference Figure 26), that simplifies the drive requirements of an external Figure 38 shows an example of how to generate a reference reference. The external reference must be able to drive a ≈5 kΩ voltage other than 1 V or 2.5 V with the addition of two ex- (±20%) load. Note that the bandwidth of the reference buffer is –16– REV. 0 AD9241 deliberately left small to minimize the reference noise contribu- Low Cost/Power Reference tion. As a result, it is not possible to change the reference volt- The external reference circuit shown in Figure 41 uses a low age rapidly in this mode without removing the CAPT/CAPB cost 1.225 V external reference (e.g., AD580 or AD1580) along Decoupling Network and driving these pins directly. with an op amp and transistor. The 2N2222 transistor acts in conjunction with 1/2 of an OP282 to provide a very low imped- Variable Input Span with V = 2.5 V CM ance drive for VINB. The selected op amp need not be a high Figure 39 shows an example of the AD9241 configured for an speed op amp and may be selected based on cost, power and input span of 2 × VREF centered at 2.5 V. An external 2.5 V accuracy. reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a 3.75V voltage divider consisting of R1 and R2, which generates the VINA 1.25V VREF signal. A1 buffers this resistor network and drives VREF. 820Ω Choose this op amp based on accuracy requirements. It is +5V 1kΩ essential that a minimum of a 10 μF capacitor in parallel with a 0.1µF VINB 0.1 μF low inductance ceramic capacitor decouple the reference 1kΩ 10µF 0.1µF AD9241 output to ground. 2N2222 1kΩ 316Ω 1/2 2.5V+VREF OP282 7.5kΩ 2.5V VINA 1.225V 2.5V–VREF +5V VREF AD1580 10µF 0.1µF +5V SENSE 2.5V +5V VINB REF 0.1µF 22µF 0.1µF R1 AD9241 A1 VREF Figure 41. External Reference Using the AD1580 and Low Impedance Buffer 0.1µF R2 +5V SENSE DIGITAL INPUTS AND OUTPUTS Digital Outputs The AD9241 output data is presented in positive true straight Figure 39. External Reference, V = 2.5 V (2.5 V on VINB, CM binary for all input ranges. Table IV indicates the output data Resistor Divider to Make VREF) formats for various input ranges, regardless of the selected input Single-Ended Input with 0 to 2 3 VREF Range range. A twos-complement output data format can be created Figure 40 shows an example of an external reference driving by inverting the MSB. both VINB and VREF. In this case, both the common mode Table IV. Output Data Format voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to Input (V) Condition (V) Digital Output OTR VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. For example, if VINA –VINB < – VREF 00 0000 0000 0000 1 the REF191, a 2.048 external reference, was selected, the valid VINA –VINB = – VREF 00 0000 0000 0000 0 input range extends from 0 V to 4.096 V. In this case, 1 LSB of VINA –VINB = 0 10 0000 0000 0000 0 the AD9241 corresponds to 0.250 mV. It is essential that a VINA –VINB = + VREF – 1 LSB 11 1111 1111 1111 0 minimum of a 10 μF capacitor in parallel with a 0.1 μF low induc- VINA –VINB ≥ + VREF 11 1111 1111 1111 1 tance ceramic capacitor decouple the reference output to ground. +FS –1 1/2 LSB OTR DATA OUTPUTS 2xREF VINA 111111 1111 1111 OTR 1 0V 0 111111 1111 1111 111111 1111 1110 0 –FS+1/2 LSB +5V VREF VINB 0.1µF 10µF 0.1µF AD9241 000000 0000 0001 0 0 000000 0000 0000 VREF 1 000000 0000 0000 0.1µF –FS +FS –FS –1/2 LSB +FS –1/2 LSB +5V SENSE Figure 42. Output Data Format Figure 40. Input Range = 0 V to 2 × VREF Out Of Range (OTR) An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. REV. 0 –17– AD9241 It is HIGH when the analog input voltage exceeds the input with a total rms jitter of 15 ps, the SNR performance of the A/D range as shown in Figure 42. OTR will remain HIGH until the will be limited to 80.5 dB. Undersampling applications are analog input returns within the input range and another conver- particularly sensitive to jitter. sion is completed. By logical ANDing OTR with the MSB and The clock input should be treated as an analog signal in cases its complement, overrange high or underrange low conditions where aperture jitter may affect the dynamic range of the can be detected. Table V is a truth table for the over/underrange AD9241. As such, supplies for clock drivers should be separated circuit in Figure 43, which uses NAND gates. Systems requiring from the A/D output driver supplies to avoid modulating the programmable gain conditioning of the AD9241 input signal clock signal with digital noise. Low jitter crystal controlled oscil- can immediately detect an out-of-range condition, thus elimi- lators make the best clock sources. If the clock is generated from nating gain selection iterations. Also, OTR can be used for another type of source (by gating, dividing or other method), it digital offset and gain calibration. should be retimed by the original clock at the last step. Most of the power dissipated by the AD9241 is from the analog Table V. Out-of-Range Truth Table power supply. However, lower clock speeds will slightly reduce OTR MSB Analog Input Is digital current. Figure 44 shows the relationship between power and clock rate. 0 0 In Range 0 1 In Range 150 1 0 Underrange 140 1 1 Overrange 130 120 MSB OVER = “1” 5V p-p 110 OTR 2V p-p UNDER = “1” 100 MSB 90 80 Figure 43. Overrange or Underrange Logic 70 Digital Output Driver Considerations (DRVDD) The AD9241 output drivers can be configured to interface with 60 0 1 2 3 4 5 6 789 10 +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V CLOCK RATE – MHz respectively. The AD9241 output drivers are sized to provide sufficient output current to drive a wide variety of logic families. Figure 44. AD9241 Power Consumption vs. Clock However, large drive currents tend to cause glitches on the Frequency supplies and may affect SINAD performance. Applications requiring the AD9241 to drive large capacitive loads or large GROUNDING AND DECOUPLING fanout may require additional decoupling capacitors on DRVDD. Analog and Digital Grounding In extreme cases, external buffers or latches may be required. Proper grounding is essential in any high speed, high resolution Clock Input and Considerations system. Multilayer printed circuit boards (PCBs) are recom- The AD9241 internal timing uses the two edges of the clock mended to provide optimal grounding and power schemes. The input to generate a variety of internal timing signals. The clock use of ground and power planes offers distinct advantages: input must meet or exceed the minimum specified pulse width 1. The minimization of the loop area encompassed by a signal high and low (t and t ) specifications for the given A/D, as CH CL and its return path. defined in the Switching Specifications section at the beginning of the data sheet, to meet the rated performance specifications. 2. The minimization of the impedance associated with ground For example, the clock input to the AD9241 operating at 1.25 and power paths. MSPS may have a duty cycle between 45% to 55% to meet this 3. The inherent distributed capacitor formed by the power timing requirement since the minimum specified t and t is CH CL plane, PCB insulation and ground plane. 360 ns. For clock rates below 1.25 MSPS, the duty cycle may These characteristics result in both a reduction of electro- deviate from this range to the extent that both t and t are CH CL magnetic interference (EMI) and an overall improvement in satisfied. performance. All high speed, high resolution A/Ds are sensitive to the quality It is important to design a layout that prevents noise from coupling of the clock input. The degradation in SNR at a given full-scale onto the input signal. Digital signals should not be run in paral- input frequency (f ) due only to aperture jitter (t ) can be IN A lel with input signal traces, and should be routed away from the calculated with the following equation: input circuitry. While the AD9241 features separate analog and SNR = 20 log [1/(2 π f t )] 10 IN A digital ground pins, it should be treated as an analog compo- In the equation, the rms aperture jitter, t , represents the root- nent. The AVSS, DVSS and DRVSS pins must be joined to- A sum square of all the jitter sources including the clock input, gether directly under the AD9241. A solid ground plane under analog input signal and A/D aperture jitter specification. For the A/D is acceptable if the power and ground return currents example, if a 1.0 MHz full-scale sine wave is sampled by an A/D are carefully managed. Alternatively, the ground plane under –18– REV. 0 POWER – mW AD9241 The CML is an internal analog bias point used internally by the the A/D may contain serrations to steer currents in predictable AD9241. This pin must be decoupled with at least a 0.1 μF directions where cross-coupling between analog and digital capacitor as shown in Figure 47. The dc level of CML is ap- would otherwise be unavoidable. The AD9241/EB ground lay- proximately AVDD/2. This voltage should be buffered if it is to out shown in Figure 52 depicts the serrated type of arrange- be used for any external biasing. ment. The analog and digital grounds are connected by a jumper below the A/D. Analog and Digital Supply Decoupling CML The AD9241 features separate analog and digital supply and 0.1µF AD9241 ground pins, helping to minimize digital corruption of sensitive analog signals. Figure 47. CML Decoupling 120 The digital activity on the AD9241 chip falls into two general categories: correction logic and output drivers. The internal DVDD correction logic draws relatively small surges of current, prima- 100 rily during the clock transitions. The output drivers draw large AVDD current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the 80 output bits: large capacitive loads are to be avoided. Note that the internal correction logic of the AD9241 is referenced DVDD while the output drivers are referenced to DRVDD. 60 The decoupling shown in Figure 48 (a 0.1 μF ceramic chip capacitor) is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications in- 40 1 10 100 1000 volving greater digital loads should consider increasing the digi- FREQUENCY – kHz tal decoupling proportionally and/or using external buffers/ latches. Figure 45. PSRR vs. Frequency Figure 45 shows the power supply rejection ratio vs. frequency DVDD DRVDD for a 200 mV p-p ripple applied to both AVDD and DVDD. AD9241 0.1µF 0.1µF In general, AVDD, the analog supply, should be decoupled to DVSS DRVSS AVSS, the analog common, as close to the chip as physically possible. Figure 46 shows the recommended decoupling for the analog supplies; 0.1 μF ceramic chip capacitors should provide Figure 48. Digital Supply Decoupling adequately low impedance over a wide frequency range. Note A complete decoupling scheme will also include large tantalum that the AVDD and AVSS pins are co-located on the AD9241 or electrolytic capacitors on the PCB to reduce low-frequency to simplify the layout of the decoupling capacitors and provide ripple to negligible levels. Refer to the AD9241/EB schematic the shortest possible PCB trace lengths. The AD9241/EB power and layouts in Figures 49–53 for more information regarding the plane layout shown in Figure 53 depicts a typical arrangement placement of decoupling capacitors. using a multilayer PCB. AVDD 0.1µF AVSS AD9241 AVDD 0.1µF AVSS Figure 46. Analog Supply Decoupling REV. 0 –19– PSRR – dBFS AD9241 Figure 49. Evaluation Board Schematic –20– REV. 0 JP7 +5VA R20 TP10 22.1Ω TP1 C9 A D13 0.1µF 13 J8 C8 U5 A 0.1µF R21 TPC 13 12 TP11 + C1 22.1Ω C2 JP2 +5VA U6 10µF TPD JP6 0.1µF 28 29 11 J8 42 1 16V A G1 R22 TP12 JP3 U5 U5 C41 11 19 R1 TP24 11 1098 JP15 Y7 22.1Ω G2 0.1µF 10kΩ D7 9 12 JP4 9 J8 A A7 Y6 CLKB 8 13 D8 R23 TP13 32 25 A6 Y5 JP5 VREF OTR 14 D9 7 22.1Ω R2 U1 Y4 24 JP16 A5 U8 7 J8 10kΩ D13 D10 6 15 AD9241MQFP ADC_CLK 65 Y3 BIT1 A4 A 23 D12 CLK 5 16 R24 TP14 D11 BIT2 A3 Y2 A 31 22.1Ω 22 D11 17 D12 4 SENSE BIT3 A2 Y1 5J8 C23 21 18 D10 TP2 D13 3 J9 Y0 BIT4 0.1µF A1 R25 TP15 33 20 D9 2 REFCOM BIT5 A0 22.1Ω C3 +DRVDD C5 CLKIN 20 + 19 D8 10 C6 3J8 0.1µF BIT6 GND 10µF +5VD A R19 0.1µF 18 D7 JP17 R26 16V TP16 BIT7 50Ω C24 37 A +5VA 17 D6 74HC541N 22.1Ω CAPT JP18 BIT8 0.1µF 16 D5 1 J8 A BIT9 U7 C4 36 D4 R27 15 R16 TP3 A 1 CAPB BIT10 0.1µF 5kΩ R40 22.1Ω 14 D3 G1 11 BIT11 19 J8 ? Y7 33 39 13 D2 G2 12 BIT12 CLK 9 CML CML R17 Y6 R28 TP4 D1 A7 12 41 13 D0 8 BIT13 1kΩ CW 22.1Ω VINA Y5 11 D0 R41 A6 14 42 BIT14 D1 7 27 J8 C7 Y4 A VINB ? A5 15 0.1µF D2 6 R29 TP5 R18 Y3 CLK 7 A4 16 D3 5 22.1Ω VINA2 5kΩ Y2 A3 25 J8 A B 4 17 JP11 D4 Y1 A2 R30 VINA1 18 TP17 A D5 3 ADC_CLK Y0 A1 22.1Ω 321 D6 2 5 1 63 23 J8 A0 +DRVDD 20 10 VINB2 R31 GND +5VD TP6 JP8 A B JP12 22.1Ω +5VD C25 VINB1 +DRVDD +5VA 74HC541N 21 J8 321 0.1µF C10 C11 C43 R32 TP7 0.1µF 0.1µF 0.1µF R6 TP25 22.1Ω 820Ω 19 J8 TPD R33 TP8 C17 V 22.1Ω CC 10µF C18 U2 C16 J8 17 TP18 C14 16V 0.1µF 0.1µF L1 R34 TP9 0.1µF REF43 EXTERNAL REFERENCE DRIVE U3 22.1Ω +5A J2 +5VA 2 V V VCC IN 6 OUT J8 Q1 15 + C28 A C32 R7 C12 7 2N2222 22µF 3 A 0.1µF GND 1kΩ 0.1µF R3 JP10 25V R4 6 4 15kΩ AD817 A 50Ω TP19 A A A L2 2 4 C15 A R8 C13 +5D J3 +5VD R5 0.1µF 316Ω 10µF 10kΩ + C29 C33 16V 22µF 0.1µF A A A 25V A V EE TP20 A A L3 C38 J1 +VCC J4 VCC T1 ? + C30 J10 R37 C34 VIN 22µF 33Ω 1 0.1µF 6 V 25V CC AIN AC COUPLE OPTION VINA1 R11 TP21 A C19 C36 A A JP24 500Ω L4 +5VA PRI SEC 0.1µF 15pF A U4 R9 –VEE J5 VEE 2 5 A 50Ω DIRECT COUPLE OPTION D1 + C31 R12 7 C35 A 1N5711 3 2 22µF R36 33Ω R35 A 0.1µF R38 R10 25V 200Ω A BUFFER AD845 6 VINA2 50Ω 33Ω 2 500Ω TP27 4 A A 3 D2 JP23 3 L5 VINB1 4 C21 1N5711 B R39 C37 0.1µF J11 +DRVDD 1 R14 C20 A 15pF ? A 10kΩ +C39 0.1µF +5_OR _+3 C40 CW 22µF A AC COUPLE OPTION 0.1µF R13 A JP21 25V V +5VA 10kΩ A A EE TPC JP14 26 2J8 J8 JP22 TPD D3 4J8 TPD R15 NC 39 J8 JP13 33Ω 1N5711 JP1 6J8 28 J8 TPC CML VINB2 TP22 8J8 29 J8 C42 D4 U8 0.1µF 1N5711 DGND J6 11 10 10 J8 30 J8 5 SETS OF A U5 A 12 J8 31 J8 PADS TO 5 6 U8 U8 U5 TP26 TP23 98 CONNECT 14 J8 32 J8 DECOUPLING DECOUPLING GROUNDS AGND J7 U5 16 J8 34 J8 U8 J8 +5VA +5VD 40 12 3 4 JG1-WIRE ETCH A 18 J8 NC 35 J8 SJ6 C22 CKT SIDE C26 20 J8 36 J8 U8 U5 0.1µF 0.1µF 1 2 3 4 22 J8 NC 37 J8 A 24 U8 J8 38 J8 74HC04 13 12 SPARE GATES A 74HC14 JG1 SJ1 SJ2 SJ3 SJ4 SJ5 DRVSS AVDD2 DVSS AVDD1 DRVDD AVSS2 DVDD AVSS1 AD9241 Figure 50. Evaluation Board Component Side Layout (Not to Scale) Figure 51. Evaluation Board Solder Side Layout (Not to Scale) REV. 0 –21– AD9241 Figure 52. Evaluation Board Ground Plane Layout (Not to Scale) Figure 53. Evaluation Board Power Plane Layout (Not to Scale) –22– REV. 0 AD9241 OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 44-Pin Metric Quad Flatpack (MQFP) (S-44) 13.45 (0.529) 12.95 (0.510) 2.45 (0.096) 10.1 (0.398) MAX 9.90 (0.390) 1.03 (0.041) 0° 0.73 (0.029) 44 34 MIN 1 33 SEATING PLANE 8.45 (0.333) TOP VIEW (PINS DOWN) 8.3 (0.327) 11 23 0.25 (0.01) 12 22 MIN 0.23 (0.009) 0.13 (0.005) 0.8 (0.031) 0.45 (0.018) BSC 2.1 (0.083) 0.3 (0.012) 1.95 (0.077) REV. 0 –23– –24– PRINTED IN U.S.A. C2961–10–4/97