ANALOG DEVICES AD9239

Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC AD9239 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 4 ADCs in 1 package Coded serial digital outputs with ECC per channel AD9239 On-chip temperature sensor VIN + A DOUT + A PIPELINE −95 dB channel-to-channel crosstalk SHA 12 CHANNEL A BUF ADC VIN – A DOUT – A SNR = 65 dBFS with AIN = 85 MHz at 250 MSPS VCM A SFDR = 77 dBc with AIN = 85 MHz at 250 MSPS VIN + B DOUT + B PIPELINE SHA 12 CHANNEL B BUF Excellent linearity ADC VIN – B DOUT – B DNL = ±0.3 LSB (typical) VCM B INL = ±0.7 LSB (typical) VIN + C DOUT + C PIPELINE BUF SHA 12 CHANNEL C ADC 780 MHz full power analog bandwidth VIN – C DOUT – C VCM C Power dissipation = 380 mW per channel at 250 MSPS VIN + D DOUT + D 1.25 V p-p input voltage range, adjustable up to 1.5 V p-p PIPELINE SHA 12 CHANNEL D BUF ADC VIN – D DOUT – D 1.8 V supply operation VCM D Clock duty cycle stabilizer PGM3 REFERENCE Serial port interface features PGM2 RBIAS DATA RATE Power-down modes MULTIPLIER PGM1 Digital test pattern enable SERIAL TEMPOUT PGM0 PORT Programmable header RESET Programmable pin functions (PGMx, PDWN) SCLK SDI/ SDO CSB CLK+ CLK– SDIO APPLICATIONS Figure 1. Communication receivers Cable head end equipment/M-CMTS Broadband radios Wireless infrastructure transceivers Radar/military-aerospace subsystems Test equipment GENERAL DESCRIPTION The AD9239 is a quad, 12-bit, 250 MSPS analog-to-digital Fabricated on an advanced CMOS process, the AD9239 is avail- converter (ADC) with an on-chip temperature sensor and a able in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is high speed serial interface. It is designed to support digitizing specified over the industrial temperature range of −40°C to +85°C. high frequency, wide dynamic range signals with an input PRODUCT HIGHLIGHTS bandwidth up to 780 MHz. The output data are serialized and 1. Four ADCs are contained in a small, space-saving package. presented in packet format, consisting of channel-specific 2. An on-chip PLL allows users to provide a single ADC information, coded samples, and error correction code. sampling clock, and the PLL distributes and multiplies up The ADC requires a single 1.8 V power supply and the input to produce the corresponding data rate clock. clock may be driven differentially with a sine wave, LVPECL, 3. Coded data rate supports up to 4.0 Gbps per channel. TTL, or LVDS. A clock duty cycle stabilizer allows high Coding includes scrambling to ensure proper dc common performance at full speed with a wide range of clock duty mode, embedded clock, and error correction. cycles. The on-chip reference eliminates the need for external 4. The AD9239 operates from a single 1.8 V power supply. decoupling and can be adjusted by means of SPI control. 5. Flexible synchronization schemes and programmable Various power-down and standby modes are supported. The mode pins. ADC typically consumes 145 mW per channel with the digital 6. On-chip temperature sensor. link still in operation when standby operation is enabled. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DATA SERIALIZER, ENCODER, AND CML DRIVERS 06980-001 AD9239 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ........................................... 11  Applications ....................................................................................... 1  Equivalent Circuits ......................................................................... 17  Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 19  General Description ......................................................................... 1  Analog Input Considerations ................................................... 19  Product Highlights ........................................................................... 1  Clock Input Considerations ...................................................... 21  Revision History ............................................................................... 2  Serial Port Interface (SPI) .............................................................. 31  Specif ica t ions ..................................................................................... 3  Hardware Interface ..................................................................... 31  AC Specifications .......................................................................... 4  Memory Map .................................................................................. 33  Digital Specifications ................................................................... 5  Reading the Memory Map Table .............................................. 33  Switching Specifications .............................................................. 6  Reserved Locations .................................................................... 33  Timing Diagram ........................................................................... 7  Default Values ............................................................................. 33  Absolute Maximum Ratings ............................................................ 8  Logic Levels ................................................................................. 33  Thermal Resistance ...................................................................... 8  Outline Dimensions ....................................................................... 38  ESD Caution .................................................................................. 8  Ordering Guide .......................................................................... 38  Pin Configuration and Function Description .............................. 9  REVISION HISTORY 5/10—Rev. A to Rev. B Changes to Table 15 .................................................................. 35, 36 2/10—Rev. 0 to Rev. A Changes to Analog Inputs, Differential Input Voltage Range Parameter and Endnote 3, Table 1 .................................................. 3 Changes to Table 8 ............................................................................ 9 Changes to Clock Duty Cycle Considerations Section .............. 21 Changes to Digital Outputs and Timing Section ....................... 23 Changes to Table 15 ........................................................................ 34 10/08—Revision 0: Initial Version Rev. B | Page 2 of 40 AD9239 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 1. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C −2 ±12 −2 ±12 −2 ±12 mV Offset Matching 25°C 4 12 4 12 4 12 mV Gain Error 25°C −2.8 +1 +4.7 −2.8 +1 +4.7 −2.8 +1 +4.7 % FS Gain Matching 25°C 0.9 2.7 0.9 2.7 0.9 2.7 % FS Differential Nonlinearity (DNL) Full ±0.28 ±0.6 ±0.28 ±0.6 ±0.3 ±0.6 LSB Integral Nonlinearity (INL) Full ±0.45 ±0.9 ±0.7 ±1.3 ±0.7 ±1.3 LSB ANALOG INPUTS 2 Differential Input Voltage Range Full 1.0 1.25 1.5 1.0 1.25 1.5 1.0 1.25 1.5 V p-p Common-Mode Voltage Full 1.4 1.4 1.4 V Input Capacitance 25°C 2 2 2 pF Input Resistance Full 4.3 4.3 4.3 kΩ Analog Bandwidth, Full Power Full 780 780 780 MHz Voltage Common Mode (VCMx) Voltage Output Full 1.4 1.44 1.5 1.4 1.44 1.5 1.4 1.44 1.5 V Current Drive Full 1 1 1 mA Temperature Sensor Output −1.12 −1.12 −1.12 mV/°C Voltage Output Full 739 737 734 mV Current Drive Full 10 10 10 μA POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 535 570 610 650 725 775 mA I Full 98 105 111 120 123 133 mA DRVDD Total Power Dissipation Full 1.139 1.215 1.298 1.386 1.526 1.634 W (Including Output Drivers) Power-Down Dissipation Full 3 3 3 mW 2 Standby Dissipation Full 152 173 195 mW CROSSTALK Full −95 −95 −95 dB 3 Overrange Condition Full −90 −90 −90 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 AVDD/DRVDD, with link established. 3 Overrange condition is specified as 6 dB above the full-scale input range. Rev. B | Page 3 of 40 AD9239 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 2. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 64.5 dB IN f = 84.3 MHz Full 63.5 64.5 63.2 64.2 63.1 64.1 dB IN f = 170.3 MHz 25°C 63.9 dB IN fIN = 240.3 MHz 25°C 64.1 63.2 63.3 dB SIGNAL-TO-NOISE RATIO (SINAD) f = 9.7 MHz 25°C 64.2 dB IN fIN = 84.3 MHz Full 63.3 64.4 62.8 63.9 62.8 63.8 dB fIN = 170.3 MHz 25°C 63.1 dB fIN = 240.3 MHz 25°C 63.9 63 63.1 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 10.4 Bits f = 84.3 MHz Full 10.2 10.4 10.1 10.3 10.1 10.3 Bits IN 4 f = 170.3 MHz 25°C 10.2 Bits IN fIN = 240.3 MHz 25°C 10.3 10.2 10.2 Bits WORST HARMONIC (SECOND) f = 9.7 MHz 25°C 90 dBc IN fIN = 84.3 MHz Full 87.5 78.6 86 77 86 74.5 dBc fIN = 170.3 MHz 25°C 76 dBc fIN = 240.3 MHz 25°C 82 80 82 dBc WORST HARMONIC (THIRD) fIN = 9.7 MHz 25°C 78 dBc f = 84.3 MHz Full 79 74 76 72.6 76 72.5 dBc IN f = 170.3 MHz 25°C 74 dBc IN f = 240.3 MHz 25°C 84 77 80 dBc IN WORST OTHER (EXCLUDING SECOND OR THIRD) f = 9.7 MHz 25°C 85 dBc IN f = 84.3 MHz Full 96 86 90 83.7 94 83.6 dBc IN fIN = 170.3 MHz 25°C 85 dBc fIN = 240.3 MHz 25°C 88 88 85 dBc TWO-TONE INTERMOD DISTORTION (IMD) fIN1 = 140.2 MHz, fIN2 = 141.3 MHz, 25°C 78 77 76 dBc AIN1 and AIN2 = −7.0 dBFS f = 170.2 MHz, f = 171.3 MHz, 25°C 77 76 dBc IN1 IN2 2 AIN1 and AIN2 = −7.0 dBFS 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Tested at 210 MSPS and 250 MSPS only. Rev. B | Page 4 of 40 AD9239 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK–) Logic Compliance Full LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − AVDD + AVDD − AVDD + AVDD − AVDD + V 0.3 1.6 0.3 1.6 0.3 1.6 Internal Common-Mode Bias Full 1.2 1.2 1.2 V Input Common-Mode Voltage Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (V) Full 1.2 3.6 1.2 3.6 1.2 3.6 V IH Low Level Input Voltage (V) Full 0 0.8 0 0.8 0 0.8 V IL High Level Input Current (I) Full −10 +10 −10 +10 −10 +10 μA IH Low Level Input Current (I) Full −10 +10 −10 +10 −10 +10 μA IL Differential Input Resistance 25°C 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC INPUTS (PDWN, CSB, SDI/ 2 SDIO, SCLK, RESET, PGMx) Logic 1 Voltage Full 0.8 × 0.8 × 0.8 × V AVDD AVDD AVDD Logic 0 Voltage Full 0.2 × 0.2 × 0.2 × V AVDD AVDD AVDD Logic 1 Input Current (CSB) Full 0 0 0 μA Logic 0 Input Current (CSB) Full −60 −60 −60 μA Logic 1 Input Current Full 55 55 55 μA (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Logic 0 Input Current Full 0 0 0 μA (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC OUTPUTS (SDO) Logic 1 Voltage Full 1.2 AVDD + 1.2 AVDD + 1.2 AVDD + V 0.3 0.3 0.3 Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V DIGITAL OUTPUTS (DOUT + x, DOUT − x) Logic Compliance Current Current Current mode mode mode logic logic logic Differential Output Voltage Full 0.8 0.8 0.8 V Common-Mode Level Full DRVDD/2 DRVDD/2 DRVDD/2 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Specified for 13 SDI/SDIO pins sharing the same connection. Rev. B | Page 5 of 40 AD9239 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless otherwise noted. Table 4. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK Clock Rate Full 170 100 210 100 250 100 MSPS Clock Pulse Width High (tEH) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns Clock Pulse Width Low (tEL) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns DATA OUTPUT PARAMETERS Data Output Period or UI Full 1/(16 × fCLK) 1/(16 × fCLK) 1/(16 × fCLK) sec (DOUT + x, DOUT − x) Data Output Duty Cycle 25°C 50 50 50 % Data Valid Time 25°C 0.8 0.8 0.8 UI PLL Lock Time (tLOCK) 25°C 4 4 4 μs Wake-Up Time (Standby) 25°C 250 250 250 ns 2 Wake-Up Time (Power-Down) 25°C 50 50 50 μs Pipeline Latency Full 40 40 40 CLK cycles Data Rate per Channel (NRZ) 25°C 2.72 3.36 4.0 Gbps Deterministic Jitter 25°C 10 10 10 ps max Random Jitter 25°C 6 6 6 ps rms Channel-to-Channel Bit Skew 25°C 0 0 0 sec 3 Channel-to-Channel Packet Skew 25°C +1 +1 +1 CLK cycles Output Rise/Fall Time 25°C 50 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25°C 100 100 100 Ω APERTURE Aperture Delay (t) 25°C 1.2 1.2 1.2 ns A Aperture Uncertainty (Jitter) 25°C 0.2 0.2 0.2 ps rms OUT-OF-RANGE RECOVERY TIME 25°C 1 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Receiver dependent. 3 See the Digital Start-Up Sequence section. Rev. B | Page 6 of 40 AD9239 TIMING DIAGRAM SAMPLE N + 1 N N – 40 ANALOG N – 39 INPUT SIGNAL N – 38 N – 37 SAMPLE RATE CLOCK SAMPLE ... ... RATE CLOCK SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ... SERIAL ... ... ... ... ... ... DATA OUT DATA PACKET 1 (64 BITS) 8-BIT HEADER 48-BIT ADC 8-BIT ERROR CHANNEL ID DATA-WORD CORRECTION Figure 2. Timing Diagram Table 5. Packet Protocol Bits[64:57] Bits[56:45] Bits[44:33] Bits[32:21] Bits[20:9] Bits[8:1] Header Data 1 Data 2 Data 3 Data 4 ECC (8 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (8 bits MSB first) Rev. B | Page 7 of 40 06980-002 AD9239 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the customer Electrical board increases the reliability of the solder joints, maximizing AVDD to AGND −0.3 V to +2.0 V the thermal capability of the package. DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V Table 7. Thermal Resistance AVDD to DRVDD −2.0 V to +2.0 V Package Type θJA θJB θJC Unit DOUT ± x to DRGND −0.3 V to DRVDD + 0.3 V 72-Lead LFCSP (CP-72-3) 16.2 7.9 0.6 °C/W SDO, SDI/SDIO, CLK± , VIN ± x, −0.3 V to AVDD + 0.3 V VCMx, TEMPOUT, RBIAS to AGND SCLK, CSB, PGMx, RESET, −0.3 V to AVDD + 0.3 V Typical θJA, θJB, and θJC values are specified for a 4-layer board in PDWN to AGND still air. Airflow increases heat dissipation, effectively reducing Environmental θ . In addition, metal in direct contact with the package leads JA Storage Temperature Range −65°C to +125°C from metal traces and through holes, ground, and power planes Operating Temperature Range −40°C to +85°C reduces the θ . JA Lead Temperature 300°C ESD CAUTION (Soldering 10 sec) Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 40 AD9239 PIN CONFIGURATION AND FUNCTION DESCRIPTION NC 1 54 NC PIN 1 TEMPOUT 2 INDICATOR 53 PGM0 RBIAS 3 52 PGM1 AVDD 4 51 PGM2 NC 5 50 PGM3 PIN 0 = EPAD = AGND NC 6 49 NC AVDD 7 48 AVDD AD9239 VCM D 8 47 VCM A AVDD 9 46 AVDD TOP VIEW VIN – D 10 45 VIN – A (Not to Scale) VIN + D 11 44 VIN + A AVDD 12 43 AVDD AVDD 13 42 AVDD AVDD 14 41 AVDD AVDD 15 40 CSB CLK– 16 39 SCLK CLK+ 17 38 SDI/SDIO AVDD 18 37 SDO NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE CUSTOMER BOARD INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle). 23, 34 DRGND Digital Output Driver Ground. AVDD 1.8 V Analog Supply. 4, 7, 9, 12, 13, 14, 15, 18, 20, 21, 41, 42, 43, 46, 48, 55, 57, 60, 61, 62, 64, 65, 66, 69, 71 24, 33 DRVDD 1.8 V Digital Output Driver Supply. 2 TEMPOUT Output Voltage to Monitor Temperature. 3 RBIAS External Resistor to Set the Internal ADC Core Bias Current. 8 VCM D Common-Mode Output Voltage Reference. 10 VIN − D ADC D Analog Complement. 11 VIN + D ADC D Analog True. 16 CLK− Input Clock Complement. 17 CLK+ Input Clock True. 22 RESET Digital Output Timing Reset. 25 DOUT + D ADC D True Digital Output. 26 DOUT − D ADC D Complement Digital Output. 27 DOUT + C ADC C True Digital Output. 28 DOUT − C ADC C Complement Digital Output. 29 DOUT + B ADC B True Digital Output. 30 DOUT − B ADC B Complement Digital Output. 31 DOUT + A ADC A True Digital Output. 32 DOUT − A ADC A Complement Digital Output. 35 PDWN Power-Down. Rev. B | Page 9 of 40 NC 19 72 NC AVDD 20 71 AVDD AVDD 21 70 VCM C RESET 22 69 AVDD DRGND 23 VIN – C 68 DRVDD 24 67 VIN + C DOUT + D 25 66 AVDD DOUT – D 26 65 AVDD DOUT + C 27 64 AVDD DOUT – C 28 63 NC DOUT + B 29 62 AVDD DOUT – B 30 61 AVDD DOUT + A 31 60 AVDD DOUT – A 32 59 VIN + B DRVDD 33 58 VIN – B DRGND 34 57 AVDD PDWN 35 56 VCM B NC 36 55 AVDD 06980-004 AD9239 Pin No. Mnemonic Description 37 SDO Serial Data Output. Used for 4-wire SPI interface. 38 SDI/SDIO Serial Data Input/Serial Data IO for 3-Wire SPI Interface. 39 SCLK Serial Clock. 40 CSB Chip Select Bar. 44 VIN + A ADC A Analog Input True. 45 VIN − A ADC A Analog Input Complement. 47 VCM A Common-Mode Output Voltage Reference. 50 PGM3 Optional Pin to be Programmed by Customer. 51 PGM2 Optional Pin to be Programmed by Customer. 52 PGM1 Optional Pin to be Programmed by Customer. 53 PGM0 Optional Pin to be Programmed by Customer. 56 VCM B Common-Mode Output Voltage Reference. 58 VIN − B ADC B Analog Input Complement. 59 VIN + B ADC B Analog Input True. 67 VIN + C ADC C Analog Input True. 68 VIN − C ADC C Analog Input Complement. 70 VCM C Common-Mode Output Voltage Reference. 1, 5, 6, 19, 36, NC No Connection. 49, 54, 63, 72 Rev. B | Page 10 of 40 AD9239 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 63.13dB SNR = 64.88dB ENOB = 10.19 BITS –20 ENOB = 10.49 BITS –20 SFDR = 76.07dBc SFDR = 77.57dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 10 2030 40 5060 70 80 020 40 60 80 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Single-Tone 32k FFT with f = 84.3 MHz, f = 170 MSPS Figure 7. Single-Tone 32k FFT with f = 240.3 MHz, f = 210 MSPS IN SAMPLE IN SAMPLE 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 63.95dB SNR = 64.62dB –20 ENOB = 10.33 BITS ENOB = 10.44 BITS –20 SFDR = 78.90dBc SFDR = 75.48dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 10 2030 40 5060 70 80 0 20 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Single-Tone 32k FFT with f = 240.3 MHz, f = 170 MSPS IN SAMPLE Figure 8. Single-Tone 32k FFT with fIN = 10.3 MHz, fSAMPLE = 250 MSPS 0 0 AIN = –1.0dBFS AIN = –1.0dBFS SNR = 64.65dB SNR = 64.50dB ENOB = 10.44 BITS –20 ENOB = 10.42 BITS –20 SFDR = 77.54dBc SFDR = 77.97dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 0 20 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 210 MSPS Figure 9. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 250 MSPS Rev. B | Page 11 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06980-061 06980-060 06980-059 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06980-064 06980-063 06980-062 AD9239 90 0 AIN = –1.0dBFS 88 SNR = 63.90dB ENOB = 10.32 BITS –20 SFDR = 73.10dBc 86 84 –40 82 170MSPS 250MSPS –60 80 78 –80 76 74 210MSPS –100 72 –120 70 0 20 40 60 80 100 120 50 70 90 110 130 150 170 190 210 230 250 FREQUENCY (MHz) ENCODE (MSPS) Figure 10. Single-Tone 32k FFT with fIN = 171.3 MHz, fSAMPLE = 250 MSPS Figure 13. SFDR vs. Encode, fIN = 84.3 MHz 0 100 AIN = –1.0dBFS 90 SNR = 63.41dB SFDR (dBFS) ENOB = 10.24 BITS –20 80 SFDR = 77.49dBc 70 SNR (dBFS) –40 60 –60 50 SFDR (dB) 40 –80 30 SNR (dB) 20 –100 10 –120 0 0 20 40 60 80 100 120 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 11. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 250 MSPS Figure 14. SNR/SFDR vs. Analog Input Level, f = 84.3 MHz, f = 170 MSPS IN SAMPLE 70 100 69 90 SFDR (dBFS) 68 80 250MSPS 67 70 SNR (dBFS) 66 60 65 50 SFDR (dB) 64 40 170MSPS 210MSPS 63 30 SNR (dB) 62 20 61 10 60 0 50 70 90 110 130 150 170 190 210 230 250 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ENCODE (MSPS) ANALOG INPUT LEVEL (dBFS) Figure 12. SNR vs. Encode, f = 84.3 MHz IN Figure 15. SNR/SFDR vs. Analog Input Level, f = 84.3 MHz, f = 210 MSPS IN SAMPLE Rev. B | Page 12 of 40 SNR (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06980-066 06980-065 06980-067 SFDR (dBFS) SNR/SFDR (dB) SNR/SFDR (dB) 06980-070 06980-069 06980-068 AD9239 100 0 AIN1 AND AIN2 = –7.0dBFS 90 SFDR = 76.88dBc SFDR (dBFS) –20 IMD2 = –78.75dBc 80 IMD3 = –78.68dBc SNR (dBFS) 70 –40 60 –60 50 SFDR (dB) 40 –80 30 SNR (dB) 20 –100 10 –120 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 20 40 60 80 100 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 19. Two-Tone 32k FFT with fIN1 = 170.2 MHz and fIN2 = 171.3 MHz, Figure 16. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 250 MSPS fSAMPLE = 2 10 MSPS 0 0 AIN1 AND AIN2 = –7.0dBFS AIN1 AND AIN2 = –7.0dBFS SFDR = 77.26dBc SFDR = 74.48dBc –20 IMD2 = –86.55dBc IMD2 = –76.10dBc –20 IMD3 = –77.26dBc IMD3 = –74.48dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 10 2030 40 5060 70 80 0 20 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Two-Tone 32k FFT with f = 140.2 MHz and f = 141.3 MHz, IN1 IN2 Figure 20. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz, f = 170 MSPS SAMPLE fSAMPLE = 250 MSPS 0 0 AIN1 AND AIN2 = –7.0dBFS AIN1 AND AIN2 = –7.0dBFS SFDR = 75.44dBc SFDR = 74.29dBc –20 IMD2 = –78.34dBc IMD2 = –76.51dBc –20 IMD3 = –75.44dBc IMD3 = –74.30dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 0 20 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz, Figure 21. Two-Tone 32k FFT with fIN1 = 170.2 MHz and fIN2 = 171.3 MHz, fSAMPLE = 210 MSPS fSAMPLE = 250 MSPS Rev. B | Page 13 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dB) 06980-073 06980-072 06980-071 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06980-076 06980-075 06980-074 AD9239 70 95 90 69 85 68 80 67 SNR, 170MSPS SFDR (dB) SNR, 210MSPS 66 75 65 70 64 65 SNR (dB) SNR, 250MSPS 63 60 62 55 61 50 60 45 0 50 100 150 200 250 300 350 400 450 500 –40 –20 0 20 40 60 80 AIN FREQUENCY (MHz) TEMPERATURE (°C) Figure 22. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 170 MSPS Figure 25. SNR vs. Temperature, fIN = 84.3 MHz 90 95 90 85 85 SFDR, 250MSPS SFDR, 210MSPS 80 80 SFDR (dB) 75 70 75 SFDR, 170MSPS 65 SNR (dB) 70 60 55 65 50 60 45 0 50 100 150 200 250 300 350 400 450 500 –40 –20 0 20 40 60 80 TEMPERATURE (°C) AIN FREQUENCY (MHz) Figure 23. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 210 MSPS Figure 26. SFDR vs. Temperature, fIN = 84.3 MHz 95 1.0 90 0.8 85 0.6 0.4 80 75 0.2 SFDR (dB) 0 70 –0.2 65 SNR (dB) –0.4 60 –0.6 55 50 –0.8 45 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 50 100 150 200 250 300 350 400 450 500 AIN FREQUENCY (MHz) CODE Figure 24. SNR/SFDR Amplitude vs. AIN Frequency, f = 250 MSPS Figure 27. INL, f = 9.7 MHz, f = 250 MSPS SAMPLE IN SAMPLE Rev. B | Page 14 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06980-079 06980-078 06980-077 INL (LSB) SFDR (dB) SNR (dB) 06980-081 06980-080 06980-082 AD9239 0.5 40000 INPUT REFERRED NOISE: 0.71 LSB 0.4 35000 0.3 30000 0.2 25000 0.1 20000 0 –0.1 15000 –0.2 10000 –0.3 5000 –0.4 –0.5 0 0 500 1000 1500 2000 2500 3000 3500 4000 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE CODE BIN Figure 28. DNL, fIN = 9.7 MHz, fSAMPLE = 250 MSPS Figure 31. Input-Referred Noise Histogram, fSAMPLE = 250 MSPS 0 40000 INPUT REFERRED NOISE: 0.72 LSB NPR = 52dB NOTCH = 18.9MHz 35000 –20 NOTCH WIDTH = 1MHz 30000 –40 25000 –60 20000 –80 15000 –100 10000 –120 5000 –140 0 020 40 60 80 100 120 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE FREQUENCY (Hz) BIN Figure 29. Input-Referred Noise Histogram, f = 170 MSPS Figure 32. Noise Power Ratio (NPR), fSAMPLE = 250 MSPS SAMPLE 40000 90 INPUT REFERRED NOISE: 0.70 LSB 85 35000 SFDR (dBc) 80 30000 75 25000 70 20000 65 SNR (dB) 60 15000 55 10000 50 5000 45 0 40 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 BIN ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 30. Input-Referred Noise Histogram, f = 210 MSPS SAMPLE Figure 33. SNR/SFDR vs. Analog Input Common-Mode Voltage, f = 84.3 MHz, f = 250 MSPS IN SAMPLE Rev. B | Page 15 of 40 NUMBER OF HITS NUMBER OF HITS DNL (LSB) 06980-083 06980-107 06980-106 NUMBER OF HITS AMPLITUDE (dBFS) SNR/SFDR (dB) 06980-087 06980-109 06980-108 AD9239 0 –1 –3dB CUTOFF = –2 780MHz –3 –4 –5 –6 –7 –8 –9 –10 1M 10M 100M 1G 10G AIN FREQUENCY (Hz) Figure 34. Full-Power Bandwidth Amplitude vs. AIN Frequency, fSAMPLE = 250 MSPS Rev. B | Page 16 of 40 AMPLITUDE (dBFS) 06980-088 AD9239 EQUIVALENT CIRCUITS AVDD AVDD AVDD 1.2V 10kΩ 10kΩ CLK+ CLK– 250Ω SDI/SDIO 30kΩ Figure 35. CLK± Inputs Figure 39. Equivalent SDI/SDIO Input Circuit AVDD AVDD VIN + x BUF 2kΩ AVDD BUF ~1.4V AVDD 2kΩ TEMPOUT VIN – x BUF Figure 40. Equivalent TEMPOUT Output Circuit Figure 36. Analog Inputs 100Ω 175Ω 175Ω SCLK, RBIAS PDWN, 30kΩ PGMx, RESET Figure 37. Equivalent SCLK, PDWN, PGMx, RESET Input Circuit Figure 41. Equivalent RBIAS Input/Output Circuit AVDD 175Ω VCMx 26kΩ 1kΩ CSB Figure 38. Equivalent CSB Input Circuit Figure 42. Equivalent VCMx Output Circuit Rev. B | Page 17 of 40 06980-008 06980-007 06980-006 06980-005 06980-010 06980-012 06980-009 06980-011 AD9239 AVDD SDO DRVDD AVDD 4mA R 4mA TERM DOUT + x V DOUT – x CM 345Ω 4mA 4mA Figure 43. Equivalent Digital Output Circuit Figure 44. Equivalent SDO Output Circuit Rev. B | Page 18 of 40 06980-089 06980-030 AD9239 THEORY OF OPERATION series with each input can help reduce the peak transient current The AD9239 architecture consists of a differential input buffer, injected from the output stage of the driving source. front-end sample-and-hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from In addition, low-Q inductors or ferrite beads can be placed on each stage are combined into a final 12-bit result in the digital each leg of the input to reduce high differential capacitance at correction logic. The pipelined architecture permits the first the analog inputs and therefore achieve the maximum bandwidth stage to operate on a new input sample, while the remaining of the ADC. Such use of low-Q inductors or ferrite beads is stages operate on preceding samples. Sampling occurs on the required when driving the converter front end at high intermediate rising edge of the clock. frequency (IF). Either a shunt capacitor or two single-ended capac- itors can be placed on the inputs to provide a matching passive Each stage of the pipeline, excluding the last, consists of a low network. This ultimately creates a low-pass filter at the input to resolution flash ADC connected to a switched capacitor DAC limit unwanted broadband noise. See the AN-827 Application Note and interstage residue amplifier (for example, a multiplying and the Analog Dialogue article “Transformer-Coupled Front-End digital-to-analog converter (MDAC)). The residue amplifier for Wideband A/D Converters” (Volume 39, April 2005) for magnifies the difference between the reconstructed DAC output more information on this subject. In general, the precise values and the flash input for the next stage in the pipeline. One bit of depend on the application. redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the The input stage contains a differential SHA that can be ac- or AD9239, the default input span is 1.25 V p-p. To configure the dc-coupled in differential or single-ended mode. The output of ADC for a different input span, see Register 18. For the best the pipeline ADC is put into its final serial format by the data performance, an input span of 1.25 V p-p or greater should be serializer, encoder, and CML drivers block. The data rate multiplier used (see Table 15 for details). creates the clock used to output the high speed serial data at the CML outputs. Differential Input Configurations There are several ways to drive the AD9239 either actively or ANALOG INPUT CONSIDERATIONS passively; in either case, optimum performance is achieved by The analog input to the AD9239 is a differential buffer. This driving the analog input differentially. For example, using the input is optimized to provide superior wideband performance ADA4937 differential amplifier to drive the AD9239 provides and requires that the analog inputs be driven differentially. SNR excellent performance and a flexible interface to the ADC (see and SINAD performance degrades if the analog input is driven Figure 45 and Figure 46) for baseband and second Nyquist with a single-ended signal. (~100 MHz IF) applications. In either application, 1% resistors For best dynamic performance, the source impedances driving should be used for good gain matching. It should also be noted VIN + x and VIN − x should be matched such that common- that the dc-coupled configuration will show some degradation mode settling errors are symmetrical. These errors are reduced in spurious performance. For further reference, consult the by the common-mode rejection of the ADC. A small resistor in ADA4937 data sheet. 3.3V 1.8V 1.8V 205Ω 0.1µF 1.25V p-p 200Ω 24Ω 33Ω VIN + x AVDD DRVDD +V S 1.65V 62Ω SIGNAL 10kΩ V AD9239 OCM ADA4937 GENERATOR OPTIONAL C R C ADC INPUT G = UNITY 0.1µF 10kΩ IMPEDANCE 200Ω –V S VIN – x 24Ω 33Ω 0.1µF 27Ω 205Ω Figure 45. Differential Amplifier Configuration for AC-Coupled Baseband Applications 3.3V 1.8V 1.8V 205Ω 1.25V p-p 24Ω 33Ω 200Ω VIN + x AVDD DRVDD +V S 62Ω AD9239 SIGNAL V OCM ADA4937 GENERATOR OPTIONAL C R C ADC INPUT G = UNITY 0.1µF IMPEDANCE 200Ω –V S VCMx VIN – x 24Ω 33Ω 27Ω 205Ω 1.4V Figure 46. Differential Amplifier Configuration for DC-Coupled Baseband Applications Rev. B | Page 19 of 40 06980-091 06980-090 AD9239 For applications where SNR is a key parameter, differential 1.25V p-p 0.1µF BALUN 33Ω 1:1 Z VIN + x transformer coupling is the recommended input configuration 0.1µF (see Figure 47 to Figure 49), to achieve the true performance of ADC 4.7pF 66Ω AD9239 the AD9239. 0.1µF 33Ω VIN – x Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced BALUN or removed. 1:1 Z ADT1-1WT 1:1 Z RATIO C 33Ω VIN + x Figure 50. Differential Balun-Coupled Configuration ADC 0.1µF for Wideband IF Applications 1.25V p-p 50Ω *C DIFF AD9239 33Ω Single-Ended Input Configuration VIN – x AGND C 0.1μF A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and *C DIFF IS OPTIONAL distortion performance can degrade due to input common-mode Figure 47. Differential Transformer-Coupled Configuration for Baseband Applications swing mismatch. If the application requires a single-ended input configuration, ensure that the source impedances on each input ADT1-1WT 1.25V p-p 0.1μF L L 1:1 Z RATIO 33Ω are well matched in order to achieve the best possible performance. VIN + x 65Ω 2.2pF A full-scale input of 1.25 V p-p can be applied to the ADC’s ADC 250Ω AD9239 L 33Ω VIN + x pin while the VIN − x pin is terminated. Figure 51 VIN – x details a typical single-ended input configuration. 0.1μF C 33Ω Figure 48. Differential Transformer-Coupled Configuration VIN + x for Wideband IF Applications 0.1µF 1.25V p-p 49.9Ω ADC ADT1-1WT *C 1.25V p-p DIFF 0.1μF 1:1 Z RATIO 33Ω AD9239 VIN + x 25Ω 33Ω ADC VIN – x 250Ω L AD9239 C 0.1µF 33Ω VIN – x *C 0.1μF DIFF IS OPTIONAL Figure 51. Single-Ended Input Configuration Figure 49. Differential Transformer-Coupled Configuration for Narrow-Band IF Applications Rev. B | Page 20 of 40 06980-015 06980-013 06980-014 06980-016 06980-017 AD9239 CLK+ input circuit supply is AVDD (1.8 V), this input is CLOCK INPUT CONSIDERATIONS designed to withstand input voltages of up to 3.3 V and For optimum performance, the AD9239 sample clock inputs therefore offers several selections for the drive logic voltage. (CLK+ and CLK−) should be clocked with a differential signal. AD9510/AD9511/ This signal is typically ac-coupled to the CLK+ and CLK− pins AD9512/AD9513/ via a transformer or capacitors. These pins are biased internally AD9514/AD9515/ 0.1µF AD9516/AD9518 to 1.2 V and require no additional biasing. CLK+ CLK OPTIONAL 50Ω* 100Ω Figure 52 shows a preferred method for clocking the AD9239. The CMOS DRIVER CLK+ 0.1µF low jitter clock source is converted from a single-ended signal ADC CLK AD9239 to a differential signal using an RF transformer. The back-to- 0.1µF CLK– back Schottky diodes across the secondary transformer limit 0.1µF 39kΩ clock excursions into the AD9239 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the *50Ω RESISTOR IS OPTIONAL. clock from feeding through to other portions of the AD9239, Figure 55. Single-Ended 1.8 V CMOS Sample Clock and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ ® Mini-Circuits 0.1µF AD9516/AD9518 ADT1-1WT, 1:1Z CLK+ CLK OPTIONAL 0.1µF 0.1µF 50Ω* 100Ω XFMR CMOS DRIVER CLK+ CLK+ CLK+ ADC 0.1µF 50Ω ADC 0.1µF AD9239 CLK AD9239 0.1µF CLK– 0.1µF CLK– SCHOTTKY 0.1µF DIODES: HSM2812 *50Ω RESISTOR IS OPTIONAL. Figure 52. Transformer-Coupled Differential Clock Figure 56. Single-Ended 3.3 V CMOS Sample Clock Another option is to ac-couple a differential PECL signal to the Clock Duty Cycle Considerations sample clock input pins as shown in Figure 53. The AD9510/ Typical high speed ADCs use both clock edges to generate a AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9518 variety of internal timing signals. As a result, these ADCs may family of clock drivers offers excellent jitter performance. be sensitive to the clock duty cycle. Commonly, a 5% tolerance AD9510/AD9511/ is required on the clock duty cycle to maintain dynamic perfor- AD9512/AD9513/ AD9514/AD9515/ mance characteristics. 0.1µF AD9516/AD9518 0.1µF CLK+ CLK CLK+ The AD9239 contains a duty cycle stabilizer (DCS) that retimes ADC the nonsampling edge, providing an internal clock signal with a 100Ω PECL DRIVER AD9239 0.1µF 0.1µF nominal 50% duty cycle. This allows a wide range of clock input CLK– CLK– CLK duty cycles without affecting the performance of the AD9239. 240Ω 240Ω 50Ω* 50Ω* When the DCS is on (default), noise and distortion performance are nearly flat for a wide range of duty cycles. However, some *50Ω RESISTORS ARE OPTIONAL. applications may require the DCS function to be off. If so, keep Figure 53. Differential PECL Sample Clock in mind that the dynamic range performance may be affected AD9510/AD9511/ AD9512/AD9513/ when operated in this mode. See the Memory Map section for AD9514/AD9515/ more details on using this feature. 0.1µF 0.1µF AD9516/AD9518 CLK+ CLK CLK+ Jitter in the rising edge of the input is an important concern, ADC 100Ω LVDS DRIVER AD9239 and it is not reduced by the internal stabilization circuit. The 0.1µF 0.1µF CLK– CLK– duty cycle control loop does not function for clock rates of less CLK 50Ω* 50Ω* than 50 MHz nominal. It is not recommended that this ADC clock be dynamic in nature. Moving the clock around dynamically *50Ω RESISTORS ARE OPTIONAL. requires long wait times for the back end serial capture to retime Figure 54. Differential LVDS Sample Clock and resynchronize to the receiving logic. This long time constant far exceeds the time it takes for the DCS and PLL to lock and In some applications, it is acceptable to drive the sample clock stabilize. Only in rare applications would it be necessary to disable inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the the DCS circuitry of Register 9 (see Table 15). Keeping the DCS CLK− pin should be bypassed to ground with a 0.1 μF capacitor circuit enabled is recommended to maximize ac performance. in parallel with a 39 kΩ resistor (see Figure 55). Although the Rev. B | Page 21 of 40 06980-018 06980-019 06980-020 06980-022 06980-021 AD9239 2.0 0.8 Clock Jitter Considerations 1.8 0.7 High speed, high resolution ADCs are sensitive to the quality of the 1.6 clock input. The degradation in SNR at a given input frequency (fA) 0.6 due only to aperture jitter (tJ) can be calculated by 1.4 I AVDD 0.5 1.2 SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) POWER 1.0 0.4 In this equation, the rms aperture jitter represents the root mean 0.8 square of all jitter sources, including the clock input, analog input 0.3 signal, and ADC aperture jitter. IF undersampling applications 0.6 0.2 are particularly sensitive to jitter (see Figure 57). 0.4 I DRVDD 0.1 The clock input should be treated as an analog signal in cases 0.2 where aperture jitter may affect the dynamic range of the AD9239. 0 0 50 70 90 110 130 150 170 Power supplies for clock drivers should be separated from the ENCODE (MSPS) ADC output driver supplies to avoid modulating the clock signal Figure 58. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 170 MSPS with digital noise. Low jitter, crystal-controlled oscillators are 2.0 0.8 the best clock sources. If the clock is generated from another 1.8 type of source (by gating, dividing, or another method), it 0.7 should be retimed by the original clock during the last step. 1.6 I AVDD 0.6 1.4 Refer to the AN-501 Application Note, the AN-756 Application 0.5 Note, and the Analog Dialogue article “Analog-to-Digital Converter 1.2 POWER Clock Optimization: A Test Engineering Perspective” (Volume 42, 1.0 0.4 Number 2, February 2008) for more in-depth information about 0.8 0.3 jitter performance as it relates to ADCs (visit www.analog.com). 0.6 130 0.2 RMS CLOCK JITTER REQUIREMENT 0.4 120 I DRVDD 0.1 0.2 110 0 0 16 BITS 100 50 70 90 110 130 150 170 190 210 ENCODE (MSPS) 90 14 BITS Figure 59. Supply Current vs. Encode for f = 84.3 MHz, f = 210 MSPS IN SAMPLE 80 12 BITS 2.0 0.8 70 1.8 10 BITS I AVDD 0.7 60 0.125 ps 1.6 50 0.25 ps 0.6 0.5 ps 1.4 1.0 ps 40 POWER 0.5 2.0 ps 1.2 30 1 10 100 1000 1.0 0.4 ANALOG INPUT FREQUENCY (MHz) 0.8 0.3 Figure 57. Ideal SNR vs. Input Frequency and Jitter 0.6 0.2 Power Dissipation 0.4 I DRVDD As shown in Figure 58 to Figure 60, the power dissipated by the 0.1 0.2 AD9239 is proportional to its clock rate. The digital power 0 0 dissipation does not vary significantly because it is determined 50 70 90 110 130 150 170 190 210 230 250 ENCODE (MSPS) primarily by the DRVDD supply and bias current of the digital Figure 60. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 250 MSPS output drivers. Rev. B | Page 22 of 40 SNR (dB) 06980-024 POWER (W) POWER (W) POWER (W) CURRENT (mA) CURRENT (mA) CURRENT (mA) 06980-058 06980-057 06980-056 AD9239 Digital Start-Up Sequence A 100 Ω differential termination resistor should be placed at each receiver input to result in a nominal 400 mV p-p swing at the The output digital data from the AD9239 is coded and packetized, receiver. Alternatively, single-ended 50 Ω termination can be which requires the device to have a certain start-up sequence. used. When single-ended termination is used, the termination The following steps should be initialized by the user to capture voltage should be DRVDD/2; otherwise, ac coupling capacitors coherent data at the receiving logic. can be used to terminate to any single-ended voltage. 1. Initialize a soft reset via Bit 5 of Register 0 (see Table 15). The AD9239 digital outputs can interface with custom application- 2. All PGMx pins are automatically initialized as sync pins by specific integrated circuits (ASICs) and field-programmable gate default. These pins can be used to lock the FPGA timing array (FPGA) receivers, providing superior switching performance and data capture during initial startup. These pins are in noisy environments. Single point-to-point net topologies are respective to each channel (PGM3 = Channel A). recommended with a single differential 100 Ω termination resistor 3. Each sync pin is held low until its respective PGMx pin placed as close to the receiver logic as possible. The common mode receives a high signal input from the receiver, during which of the digital output automatically biases itself to half the supply time the ADC outputs a training pattern. of DRVDD if dc-coupled connecting is used. For receiver logic 4. The training pattern defaults to the values implemented by that is not within the bounds of the DRVDD supply, an ac-coupled the user in Register 19 through Register 20. connection should be used. Simply place a 0.1 μF capacitor on 5. When the receiver finds the frame boundary, the sync each output pin and derive a 100 Ω differential termination identification is deasserted high via the sync pin or via a close to the receiver side. SPI write. The ADC outputs the valid data on the next packet boundary. The time necessary for sync establishment is highly If there is no far-end receiver termination or there is poor dependent on the receiver logic processing. Refer to the differential trace routing, timing errors may result. To avoid Switching Specifications section; the switching timing is such timing errors, it is recommended that the trace length be directly related to the ADC channel. less than 6 inches and that the differential output traces be close 6. Once steady state operation for the device has occurred, together and at equal lengths. these pins can each be assigned to be a standby option by 100Ω DRVDD DIFFERENTIAL using Register 53 (see Table 15). All other pins act as TRACE PAIR DOUT + x universal sync pins. 100Ω RECEIVER To minimize skew and time misalignment between each DOUT – x channel of the digital outputs, the following actions should be taken to ensure that each channel data packet is within ±1 clock V = DRVDD/2 OUTPUT SWING = 400mV p-p CM cycle of its specified switching time. For some receiver logic, this is not required. Figure 61. DC-Coupled Digital Output Termination Example 1. Full power-down through external PDWN pin. V RXCM 2. Chip reset via external RESET pin. 100Ω DRVDD 3. Power back up by releasing external PDWN pin. DIFFERENTIAL TRACE PAIR 0.1µF DOUT + x Digital Outputs and Timing 100Ω OR RECEIVER The AD9239 has differential digital outputs that power up on DOUT – x default. The driver current is derived on chip and sets the output 0.1µF current at each output equal to a nominal 4 mA. Each output V = Rx V presents a 100 Ω dynamic internal termination to reduce unwanted OUTPUT SWING = 400mV p-p CM CM reflections Figure 62. AC-Coupled Digital Output Termination Example Rev. B | Page 23 of 40 06980-092 06980-093 AD9239 HEIGHT1: EYE DIAGRAM TIE1: HISTOGRAM TJ@BERI: BATHTUB 1 (y1) –375.023m 600 1 2 3 (y2) +409.847m 600 (Δy) +784.671m + + + 0.01 500 400 0.0001 400 200 –6 1E 300 0 –8 1E –200 200 –10 1E –400 100 –12 1E EYE: ALL BITS OFFSET: 0.015 –600 ULS: 5000: 40044, TOTAL: 12000: 80091 –14 1E 0 –200 –100 0 100 200 –30 –10 10 30 –0.5 0 0.5 TIME (ps) TIME (ps) ULS Figure 63. Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver HEIGHT1: EYE DIAGRAM TIE1: HISTOGRAM TJ@BERI: BATHTUB 1 300 (y1) –402.016m 1 2 3 600 (y2) +398.373m + + + (Δy) +800.389m 0.01 250 400 0.0001 200 200 –6 1E 150 0 –8 1E –200 100 –10 1E –400 50 –12 1E EYE: ALL BITS OFFSET: 0.015 –600 ULS: 5000: 40044, TOTAL 8000: 40044 –14 1E 0 –200 –100 0 100 200 –50 0 50 –0.5 0 0.5 TIME (ps) TIME (ps) ULS Figure 64. Digital Outputs Data Eye with Trace Lengths Greater than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver An example of the digital output (default) data eye and a time To change the output data format to twos complement or gray interval error (TIE) jitter histogram with trace lengths less than code, see the Memory Map section. 6 inches on standard FR-4 material is shown in Figure 63. Table 9. Digital Output Coding Figure 64 shows an example of trace lengths exceeding 12 inches (VIN + x) − (VIN − x), Digital Output Offset Binary on standard FR-4 material. Notice that the TIE jitter histogram Code Input Span = 1.25 V p-p (V) (D11 ... D0) reflects the decrease of the data eye opening as the edge deviates 4095 +0.625 1111 1111 1111 from the ideal position. It is the user’s responsibility to determine 2048 0.00 1000 0000 0000 if the waveforms meet the timing budget of the design when the 2047 −0.000305 0111 1111 1111 trace lengths exceed 6 inches. 0 −0.625 0000 0000 0000 Additional SPI options allow the user to further increase the output driver voltage swing of all four outputs in order to drive Data from each ADC is serialized and provided on a separate longer trace lengths (see Register 15 in Table 15). Even though channel. The data rate for each serial stream is equal to N bits this produces sharper rise and fall times on the data edges and is times the sample clock rate, in addition to some amount of less prone to bit errors, the power dissipation of the DRVDD overhead to account for the 8-bit header and error correction, for a supply increases when this option is used. See the Memory Map maximum of 3.15 Gbps (that is, 12 bits × 210 MSPS × 25% = section for more details. 3.15 Gbps). The lowest typical clock rate is 100 MSPS. For clock rates slower than 100 MSPS, refer to Register 21 in the SPI The format of the output data is offset binary by default. An Memory Map. This option allows the user to adjust the PLL example of the output coding format can be found in Table 9. loop bandwidth in order to use clock rates as low as 50 MSPS. Rev. B | Page 24 of 40 VOLTAGE (mV) VOLTAGE (mV) HITS HITS BER BER 06980-095 06980-094 AD9239 Table 10. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A Yes 0001 Midscale short 1000 0000 0000 Same Yes 0010 +Full-scale short 1111 1111 1111 Same Yes 0011 −Full-scale short 0000 0000 0000 Same Yes 0100 Checkerboard 1010 1010 1010 0101 0101 0101 No 1 0101 PN sequence longN/A N/A Yes 1 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Register 14 allows the user to invert the digital outputs from Digital Output Scrambler and Error Code Correction their nominal state. This is not to be confused with inverting The data from the AD9239 is sent serially in packets of 64 bits. the serial stream to an LSB-first mode. In default mode, as These numbers are derived from the necessity to have the output shown in Figure 2, the MSB is first in the data output serial data streaming at 16× the encode clock. The data packets consist stream. However, this can be inverted so that the LSB is first in of a header, data, and error correction code (that is, 8 Bits of the data output serial stream. Header + 48 Bits of Data (4 Conv.) + 8 Bits of ECC = 64 Bits). The 12-bit protocol is shown in Figure 2 and Table 5. There are eight digital output test pattern options available that can be initiated through the SPI. This feature is useful when Error Correction Code validating receiver capture and timing. Refer to Table 10 for the The error correction code (ECC) is a Hamming code due to the output bit sequencing options available. Some test patterns have ease of implementation. Seven bits are used for the ECC to two serial sequential words and can be alternated in various correct one error or detect one or two errors during transmission. ways, depending on the test pattern chosen. It should be noted The MSB of the ECC is always 0 and is not used to detect an that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be error. The six LSBs of the ECC are the result of the XORs of the assigned in the 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, and given bits (see Figure 68 to Figure 75). These bits allow for a 0x20 register addresses. parity check for any bit in the header and data field. The PN sequence short pattern produces a pseudorandom bit The seventh parity bit is applied to the entire packet after the 9 sequence that repeats itself every 2 − 1 or 511 bits. A description Hamming parity bits are calculated. This parity check allows of the PN sequence and how it is generated can be found in correction of an error in the data or in the ECC bits. Section 5.1 of the ITU-T 0.150 (05/96) standard. The only In the general implementation, the parity bits are located in the difference is that the starting value must be a specific value power of 2 positions, but are pulled from these locations and instead of all 1s (see Table 11 for the initial values). placed together at the end of the packet. Figure 68 to Figure 75 The PN sequence long pattern produces a pseudorandom bit show which header and data bits are associated with the parity bits. 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A In the receiver, these parity checks are performed and the description of the PN sequence and how it is generated can be receiver parity bits are calculated. The difference between the found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The received parity bits and the calculated parity bits indicate which only differences are that the starting value must be a specific bit was in error. value instead of all 1s (see Table 11 for the initial values) and the AD9239 inverts the bit stream with relation to the ITU standard. Table 11. PN Sequence Initial First Three Output Samples Sequence Value (MSB First) PN Sequence Short 0x0df 0xdf9, 0x353, 0x301 PN Sequence Long 0x29b80a 0x591, 0xfd7, 0x0a3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. B | Page 25 of 40 AD9239 is balanced based on an overranged condition. If each packet is Scramblers balanced, the bit stream should be balanced. Instead of a random There are three scramblers on the AD9239. The scramblers are sequence that changes from packet to packet, certain inverts are 58 39 7 an Ethernet scrambler (x + x + 1), a SONET scrambler (x + set at predetermined bit positions within the packet. This allows 6 x + 1), and a static inverter scrambler (inverts bits at set locations the decoding to be done in the receiver end. Figure 67 shows the in the packet). The scramblers are used to help balance the number inverters in the packet for the 12-bit data case and the inverter of 1s and 0s in the packet. order in the header. The Ethernet and SONET scramblers work on scrambling the Table 12 shows the average value of the packet for various whole packet (64 bits), the header and the data (56 bits), or just conditions. the data (48 bits). The scrambler is self-synchronizing on the descramble end or receive end and does not require an additional Table 12. Average of 1s and 0s in Overrange Conditions sync bit. For a copy of either the Ethernet or SONET scrambler Assuming Header Bits are All 0 12-Bit ECC code, send an email to highspeed.converters@analog.com. No Scramble (Data = 0) 0 00000000 Figure 65 and Figure 66 show the serial implementation of the No Scramble (Data = 1) 0.844 00111111 Ethernet and SONET scramblers. The parallel implementation Average of Negative and Positive 0.422 allows the scrambler and descrambler to run at a slower clock Overrange rate and can be implemented in the fabric of a receiver. Scramble Only Data (Data = 0) 0.375 00000000 Scramble Only Data (Data = 1) 0.469 00111111 The serial implementations of the Ethernet and SONET scramblers Average of Negative and Positive 0.422 more easily show what is being done. The parallel implementation Overrange must be derived from the serial implementation. The end product Scramble Data and Header (Data = 0) 0.437 00000000 depends on how many bits need to be processed in parallel. For Scramble Data and Header (Data = 1) 0.531 00111111 the scrambler, 64 bits are processed even in the 56- and 48-bit Average of Negative and Positive 0.484 cases. To achieve this for 56 bits and 48 bits, a portion of two Overrange samples is used to fill the rest of the input word. Inverter Balance Example If the analog signal is out of range, there should be about the same The inverter implementation uses predetermined bit positions number of out-of-range positive and out-of-range negative values. to balance the packet in an overrange condition (all 1s or all 0s) The average for no scrambling and for scrambling just the data in the converter. The inversions are present in all conditions, is about the same. If the header is used to indicate out of range, not just the overrange condition. the balance improves for the 12-bit case. The descrambler can be based off any number of bits the user chooses to process. In the inverter-based scrambler, the packet Rev. B | Page 26 of 40 AD9239 39 58 POLYNOMIAL = 1 + x + x D 58 S S S S S S 57 56 19 18 1 0 S 58 S 58 S S S S S S 57 56 19 18 1 0 D 58 Figure 65. Serial Implementation of Ethernet Scrambler 6 7 POLYNOMIAL = 1 + x + x D 7 S S S S S S S 6 5 4 3 2 1 0 S 7 S 7 S S S S S S S 6 5 4 3 2 1 0 D 7 Figure 66. Serial Implementation of SONET Scrambler D1 D1 D1 D1 D1 D1 D1 D1 h7 h6 h5 h4 h3 h2 h1 h0 <11> <10> <9> <8> <7> <6> <5> <4> D1 D1 D1 D1 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 <3> <2> <1> <0> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> D3 D3 D3 D3 D4 D4 D4 D4 D3 D3 D3 D3 D3 D3 D3 D3 <3> <2> <1> <0> <11> <10> <9> <8> <11> <10> <9> <8> <7> <6> <5> <4> D4 D4 D4 D4 D4 D4 D4 D4 0 p7 p6p5 p4p3p2 p1 <7> <6> <5> <4> <3> <2> <1> <0> = INVERTED BIT Figure 67. Scrambler Inverters for 64-Bit Packet: 12-Bit Case Rev. B | Page 27 of 40 06980-026 06980-025 06980-105 AD9239 Calculating the Parity Bits for the Hamming Code is just the inversion. A separate document will show the proper way to correct an error in the transmission. The Hamming bits are defined as follows. The definition is shown in the charts for a 12-bit example. The Hamming parity The p8 bit (MSB of the parity bits) will always be 0. The p7 bit is bits are shown interleaved in the data. This makes it easier to a parity bit for the entire packet after the other parity bits are see the numeric relationship. The decoding on the receive side calculated. D1 D1 D1 D1 D1 D1 D1 D1 h7 h6 h5 h4 h3 h2 h1 h0 <11> <10> <9> <8> <7> <6> <5> <4> D2 D2 D2 D2 D2 D2 D2 D2 D1 D1 D1 D1 D2 D2 D2 D2 <7> <6> <5> <4> <3> <2> <1> <0> <3> <2> <1> <0> <11> <10> <9> <8> D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D4 D4 D4 D4 <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> <11> <10> <9> <8> D4 D4 D4 D4 D4 D4 D4 D4 0 p7 p6p5 p4p3p2 p1 <7> <6> <5> <4> <3> <2> <1> <0> Figure 68. 64-Bit Packet: 12-Bit Case D1 D1 D1 D1 D1 D1 D1 p7 h7 h6 h5 h4 h3 h2 h1 h0 <11> <10> <9> <8> <7> <6> <5> D1 D1 D1 D1 D1 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 <4> <3> <2> <1> <0> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> D2 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D4 D4 p6 <0> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> <11> <10> D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 p5 p4 p3 0 p2 p1 <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> Figure 69. 64-Bit Packet Hamming Template for 12-Bit Case D1 D1 D1 D1 h7 h5 h3 h1 <11> <9> <7> <5> D1 D1 D2 D2 D2 D2 D2 D2 <3> <1> <11> <9> <7> <5> <3> <1> D3 D3 D3 D4 D2 D3 D3 D3 <4> <2> <0> <10> <0> <10> <8> <6> D4 D4 D4 D4 D4 D4 0p1 <9> <7> <5> <3> <2> <0> p1 = h7^h5^h3^h1^d1<11>^d1<9>^d1<7>^d1<5>^d1<3>^d1<1>^d2<11>^d2<9>^d2<7>^d2<5>^d2<3>^d2<1>^d2<0> ^d3<10>^d3<8>^d3<6>^d3<4>^d3<2>^d3<0>^d4<10>^d4<9>^d4<7>^d4<5>^d4<3>^d4<2>^d4<0>^0 Figure 70. p1 Bit for 64-Bit Packet: 12-Bit Case D1 D1 D1 D1 h7 h6 h3 h2 <11> <10> <7> <6> D1 D1 D2 D2 D2 D2 D2 D2 <3> <2> <11> <10> <7> <6> <3> <2> D2 D3 D3 D3 D3 D3 D3 D4 <0> <11> <8> <7> <4> <3> <0> <11> D4 D4 D4 D4 D4 D4 0p2 <9> <8> <5> <4> <2> <1> p2 = h7^h6^h3^h2^d1<11>^d1<10>^d1<7>^d1<6>^d1<3>^d1<2>^d2<11>^d2<10>^d2<7>^d2<6>^d2<3>^d2<2>^ d2<0>^d3<11>^d3<8>^d3<7>^d3<4>^d3<3>^d3<0>^d4<11>^d4<9>^d4<8>^d4<5>^d4<4>^d4<2>^d4<1>^0 Figure 71. p2 Bit for 64-Bit Packet: 12-Bit Case Rev. B | Page 28 of 40 06980-099 06980-098 06980-097 06980-096 AD9239 D1 D1 D1 D1 h7 h6 h5 h4 <11> <10> <9> <8> D1 D1 D1 D1 D2 D2 D2 D2 <3> <2> <1> <0> <7> <6> <5> <4> D2 D3 D3 D3 D3 D3 D3 D3 <0> <11> <10> <9> <4> <3> <2> <1> D4 D4 D4 D4 D4 D4 D4 p3 <9> <8> <7> <6> <2> <1> <0> p3 = h7^h6^h5^h4^d1<11>^d1<10>^d1<9>^d1<8>^d1<3>^d1<2>^d1<1>^d1<0>^d2<7>^d2<6>^d2<5>^d2<4>^d2<0>^ d3<11>^d3<10>^d3<9>^d3<4>^d3<3>^d3<2>^d3<1>^d4<9>^d4<8>^d4<7>^d4<6>^d4<2>^d4<1>^d4<0> Figure 72. p3 Bit for 64-Bit Packet: 12-Bit Case h7 h6 h5 h4 h3 h2 h1 h0 D1 D1 D1 D1 D2 D2 D2 D2 <3> <2> <1> <0> <11> <10> <9> <8> D3 D2 D3 D3 D3 D3 D3 D3 <5> <0> <11> <10> <9> <8> <7> <6> D4 D4 D4 D4 D4 D4 D4 p4 <9> <8> <7> <6> <5> <4> <3> p4 = h7^h6^h5^h4^h3^h2^h1^h0^d1<3>^d1<2>^d1<1>^d1<0>^d2<11>^d2<10>^d2<9>^d2<8>^d2<0>^d3<11>^ d3<10>^d3<9>^d3<8>^d3<7>^d3<6>^d3<5>^d4<9>^d4<8>^d4<7>^d4<6>^d4<5>^d4<4>^d4<3> Figure 73. p4 Bit for 64-Bit Packet: 12-Bit Case D1 D1 D1 D1 D1 D1 D1 h7 h6 h5 h4 h3 h2 h1 h0 <11> <10> <9> <8> <7> <6> <5> D1 <4> D3 D3 D3 D3 D3 D3 D4 D4 D2 D3 D3 D3 D3 D3 D3 <5> <4> <3> <2> <1> <0> <11> <10> <0> <11> <10> <9> <8> <7> <6> p5 p5 = h7^h6^h5^h4^h3^h2^h1^h0^d1<11>^d1<10>^d1<9>^d1<8>^d1<7>^d1<6>^d1<5>^d1<4>^d2<0>^d3<11>^ d3<10>^d3<9>^d3<8>^d3<7>^d3<6>^d3<5>^d3<4>^d3<3>^d3<2>^d3<1>^d3<0>^d4<11>^d4<10> Figure 74. p5 Bit for 64-Bit Packet: 12-Bit Case D1 D1 D1 D1 D1 D1 D1 h7 h6 h5 h4 h3 h2 h1 h0 <11> <10> <9> <8> <7> <6> <5> D1 D1 D1 D1 D1 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 <4> <3> <2> <1> <0> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> p6 p6 = h7^h6^h5^h4^h3^h2^h1^h0^d1<11>^d1<10>^d1<9>^d1<8>^d1<7>^d1<6>^d1<5>^d1<4>^d1<3>^d1<2>^d1<1>^ d1<0>^d2<11>^d2<10>^d2<9>^d2<8>^d2<7>^d2<6>^d2<5>^d2<4>^d2<3>^d2<2>^d2<1> Figure 75. p6 Bit for 64-Bit Packet: 12-Bit Case Rev. B | Page 29 of 40 06980-103 06980-102 06980-101 06980-100 AD9239 TEMPOUT Pin the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9239 The TEMPOUT pin can be used as a course temperature sensor returns to normal operating mode when the PDWN pin is pulled to monitor the internal die temperature of the device. This pin low. This pin is only 1.8 V tolerant. typical has a 734 mV output with a clock rate of 250 MSPS and a negative temperature going coefficient of −1.12 mV/C. The SDO Pin voltage response of this pin is characterized in Figure 76. The SDO pin is for use in applications that require a 4-wire SPI 0.85 mode operation. For normal operation, it should be tied low to 0.83 AGND through a 10 kΩ resistor. Alternatively, the device pin can be left open, and the 345 Ω internal pull-down resistor pulls 0.81 this pin low. This pin adheres to only 1.8 V logic. 0.79 SDI/SDIO Pin 0.77 The SDI/SDIO pin is for use in applications that require either a 0.75 4- or 3-wire SPI mode operation. For normal operation, it should 0.73 be tied low to AGND through a 10 kΩ resistor. Alternatively, 0.71 the device pin can be left open, and the 30 kΩ internal pull- 0.69 down resistor pulls this pin low. This pin is only 1.8 V tolerant. 0.67 SCLK Pin 0.65 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 For normal operation, the SCLK pin should be tied to AGND TEMPERATURE (°C) through a 10 kΩ resistor. Alternatively, the device pin can be left Figure 76. TEMPOUT Pin Voltage vs. Temperature open, and the 30 kΩ internal pull-down resistor pulls this pin low. RBIAS Pin This pin is only 1.8 V tolerant. To set the internal core bias current of the ADC, place a resistor CSB Pin (nominally equal to 10.0 kΩ) between ground and the RBIAS pin. For normal operation, the CSB pin should be tied high to The resistor current is derived on chip and sets the AVDD current AVDD through a 10 kΩ resistor. Alternatively, the device pin of the ADC to a nominal 725 mA at 250 MSPS. Therefore, it is can be left open, and the 26 kΩ internal pull-up resistor pulls imperative that a 1% or less tolerance on this resistor be used to this pin high. By tying the CSB pin to AVDD, all SCLK and achieve consistent performance. SDI/SDIO information is ignored. In comparison, by tying the VCMx Pins CSB pin low, all information on the SDO and SDI/SDIO pins are written to the device. This feature allows the user to reduce The common-mode output pins can be enabled through the SPI the number of traces to the device if necessary. This pin is only to provide an external reference bias voltage of 1.4 V for driving the 1.8 V tolerant. VIN + x/VIN − x analog inputs. These pins may be required when connecting external devices, such as an amplifier or transformer, PGMx Pins to interface to the analog inputs. All PGMx pins are automatically initialized as a sync pin by RESET Pin default. These pins are used to lock the FPGA timing and data capture during initial startup. These pins are respective to each The RESET pin sets all SPI registers to their default values and channel (PGM3 = Channel A). The sync pin should be pulled the datapath. Using this pin requires the user to resync the low until this pin receives a high signal input from the receiver, digital outputs. This pin is only 1.8 V tolerant. during which time the ADC outputs a training word. The training PDWN Pin word defaults to the values implemented by the user in Register 19 When asserted high, the PDWN pin turns off all the ADC through Register 20. When the receiver finds the frame boundary, channels, including the output drivers. This function can be the sync identification is deasserted high and the ADC outputs changed to a standby function. See Register 8 in Table 15. Using the valid data on the next packet boundary. this feature allows the user to put all channels into standby mode. Once steady state operation for the device has occurred, these The output drivers transmit pseudorandom data until the outputs pins can be assigned as a standby option using Register 53 in are disabled using Register 14. Table 15. All other pins change to a global sync pin. By asserting the PDWN pin high, the AD9239 is placed into This pin is only 1.8 V tolerant. power-down mode, shutting down the reference, reference buffer, PLL, and biasing networks. In this state, the ADC typically dissipates 3 mW. If any of the SPI features are changed before Rev. B | Page 30 of 40 TEMPOUT PIN VOLTAGE (V) 06980-055 AD9239 SERIAL PORT INTERFACE (SPI) The AD9239 serial port interface allows the user to configure the additional instructions. Regardless of the mode, if CSB is taken converter for specific functions or operations through a structured high in the middle of a byte transfer, the SPI state machine is register space provided in the ADC. This may provide the user reset and the device waits for a new instruction. with additional flexibility and customization, depending on the In addition to the operation modes, the SPI port configuration application. Addresses are accessed via the serial port and can influences how the AD9239 operates. For applications that do be written to or read from via the port. Memory is organized not require a control port, the CSB line can be tied and held into bytes that can be further divided into fields, as documented high. This places the SDI/SDIO pin into its secondary mode, as in the Memory Map section. Detailed operational information defined in the SDI/SDIO Pin section. CSB can also be tied low to can be found in the Analog Devices, Inc., AN-877 Application enable 2-wire mode. When CSB is tied low, SCLK and SDI/SDIO Note, Interfacing to High Speed ADCs via SPI. are the only pins required for communication. Although the Four pins define the SPI: SCLK, SDI/SDIO, SDO, and CSB (see device is synchronized during power-up, the user should ensure Table 13). The SCLK pin is used to synchronize the read and that the serial port remains synchronized with the CSB line write data presented to the ADC. The SDI/SDIO pin is a dual- when using this mode. When operating in 2-wire mode, it is purpose pin that allows data to be sent to and read from the recommended to use a 1-, 2-, or 3-byte transfer exclusively. internal ADC memory map registers. The CSB pin is an active Without an active CSB line, streaming mode can be entered but low control that enables or disables the read and write cycles. not exited. In addition to word length, the instruction phase determines if Table 13. Serial Port Pins the serial frame is a read or write operation, allowing the serial Pin Function port to be used to both program the chip and read the contents SCLK Serial Clock. The serial shift clock input. SCLK is used of the on-chip memory. If the instruction is a readback operation, to synchronize serial interface reads and writes. performing a readback causes the SDI/SDIO pin to change from SDI/SDIO Serial Data Input/Output. A dual-purpose pin that an input to an output at the appropriate point in the serial frame. typically serves as an input or output, depending on the SPI wire mode and instruction sent and the Data can be sent in MSB- or LSB-first mode. MSB-first mode relative position in the timing frame. is the default at power-up and can be changed by adjusting the SDO Serial Data Output is used only in 4-wire SPI mode. configuration register. For more information about this and When set, the SDO pin becomes active. When cleared, other features, see the AN-877 Application Note, Interfacing to the SDO pin remains in tristate, and all read data is routed to the SDI/SDIO pin. High Speed ADCs via SPI. CSB Chip Select Bar (Active Low). This control gates the HARDWARE INTERFACE read and write cycles. The pins described in Table 13 constitute the physical interface between the user’s programming device and the serial port of The falling edge of the CSB in conjunction with the rising edge of the AD9239. The SDO, SCLK and CSB pins function as inputs the SCLK determines the start of the framing sequence. During an when using the SPI. The SDI/SDIO pin is bidirectional, functioning instruction phase, a 16-bit instruction is transmitted, followed by as an input during write phases and as an output during readback. one or more data bytes, which is determined by Bit Field W0 and If multiple SDI/SDIO pins share a common connection, care Bit Field W1. An example of the serial timing and its definitions should be taken to ensure that proper VOH levels are met. Assuming can be found in Figure 78 and Table 14. the same load for each AD9239, Figure 77 shows the number of During normal operation, CSB is used to signal to the device SDI/SDIO pins that can be connected together and the resulting that SPI commands are to be received and processed. When VOH level. This interface is flexible enough to be controlled by CSB is brought low, the device processes SCLK and SDI/SDIO either serial PROMS or PIC mirocontrollers, providing the to execute instructions. Normally, CSB remains low until the user with an alternative method, other than a full SPI controller, communication cycle is complete. However, if connected to a to program the ADC (see the AN-812 Application Note). slow device, CSB can be brought high between bytes, allowing For users who wish to operate the ADC without using the older microcontrollers enough time to transfer data into shift SPI, remove any connections from the CSB, SCLK, SDO, and registers. CSB can be stalled when transferring one, two, or three SDI/SDIO pins. By disconnecting these pins from the control bus, bytes of data. When W0 and W1 are set to 11, the device enters the ADC can function in its most basic operation. Each of these streaming mode and continues to process data, either reading pins has an internal termination that floats to its respective level. or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring Rev. B | Page 31 of 40 AD9239 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 03 10 200 40 50 60 70 80 90 100 NUMBER OF SDI/SDIO PINS CONNECTED TOGETHER Figure 77. SDI/SDIO Pin Loading t t DS HI t t CLK H t t S t DH LO CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9A8 A7 D5D4D3D2D1D0 SDIO DON’T CARE DON’T CARE Figure 78. Serial Timing Details Table 14. Serial Timing Definitions Parameter Timing (Minimum, ns) Description t 5 Setup time between the data and the rising edge of SCLK DS t 2 Hold time between the data and the rising edge of SCLK DH tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK t 16 Minimum period that SCLK should be in a logic high state HI t 16 Minimum period that SCLK should be in a logic low state LO t 10 Minimum time for the SDI/SDIO pin to switch from an input to an output relative to the EN_SDI/SDIO SCLK falling edge (not shown in Figure 78) tDIS_SDI/SDIO 10 Minimum time for the SDI/SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 78) Rev. B | Page 32 of 40 V (V) OH 06980-104 06980-028 AD9239 MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map register table (Table 15) has eight when writing the default values suggested in this data sheet. bit locations. The memory map is divided into three sections: the Addresses that have values marked as 0 should be considered chip configuration registers (Address 0x00 to Address 0x02), the reserved and have a 0 written into their registers during power-up. device index and transfer registers (Address 0x05 and Address 0xFF), and the ADC functions registers (Address 0x08 to DEFAULT VALUES Address 0x53). When the AD9239 comes out of a reset, critical registers are The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in address number, and the default value is shown in the second Table 15, where an X refers to an undefined feature. rightmost column. The Bit 7 column is the start of the default LOGIC LEVELS hexadecimal value given. For example, Address 0x09, the clock An explanation of various registers follows: “bit is set” is register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 synonymous with “bit is set to Logic 1” or “writing Logic 1 for = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Bit 0 = 1, or 0000 0001 in binary. This setting is the default for Logic 0” or “writing Logic 0 for the bit.” the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address, followed by a 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. B | Page 33 of 40 AD9239 Table 15. Memory Map Register Default Default Addr. Register (MSB) (LSB) Value Notes/ (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip Configuration Registers 00 chip_port_ SDO active LSB Soft 16 bit 0x18 config (local, (not first reset address master) required, (default ignored if mode for not used) ADCs) 01 chip_id 8-bit Chip ID Bits[2:0] Read (global) 0x0B – AD9239 – 12-bit quad only 02 chip_grade Speed grade Read (global) 010 = 170 only 100 = 210 101 = 250 Device Index and Transfer Registers 05 device_ ADC A ADC B ADC C ADC D 0x0F Bits are set index_A to determine (global) which device on chip receives the next write command. The default is all devices on chip. FF device_ SW 0x00 Synchro- update (local, transfer nously master) 1 = on transfers 0 = off data from (default) the master shift register to the slave. ADC Functions Registers 08 modes External 00 = chip run 0x00 Determines (local) PDWN (default) various ge- pin 01 = full power-down neric modes function 10 = standby of chip 00 = full 11 = reset operation. PDWN (default) 01 = standby 09 Clock Duty 0x01 Turns the (global) cycle internal stabilize duty cycle 1 = on stabilizer (default) on and off. 0 = off 0D test_io Reset PN Reset PN Flex output test mode 0x00 When set, (local) long gen short gen 0000 = off (normal operation) the test data 1 = on 1 = on 0001 = midscale short is placed on 0 = off 0 = off 0010 = +FS short the output (default) (default) 0011 = −FS short pins in place 0100 = checkerboard output of normal 0101 = PN 23 sequence data. 0110 = PN 9 sequence 0111 = one/zero word toggle 0E test_bist BIST init BIST 0x00 When Bit 0 (local) 1 = on enable is set, the 0 = off 1 = on built-in self- (default) 0 = off test function (default) is initiated. Rev. B | Page 34 of 40 AD9239 Default Default Addr. Register (MSB) (LSB) Value Notes/ (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0F adc_input Analog VCM 0x00 (local) disconnect enable enable 1 = on 1 = on 0 = off 0 = off (default) (default) 10 offset 6-bit Device Offset Adjustment[5:0] 0x00 Device (local) 011111 = +31 LSB offset 011110 = +30 LSB trim. 011101 = +29 LSB … 000010 = +2 LSB 000001 = +1 LSB 000000 = 0 LSB 111111 = −1 LSB 111110 = −2 LSB 111101 = −3 LSB … 100001 = −31 LSB 100000 = −32 LSB 14 output_mode Output Output Data format select 0x00 Configures (local/global) enable bar invert (global) the outputs (local) (global) 00 = offset binary and the 1 = off enable (default) format of 0 = on 1 = on 01 = twos the data. (default) 0 = off complement (default) 10 = gray code 15 output_adjust Output Drive 0x00 VCM output (global) Current[1:0] adjustments. 00 = 400 mV (default) 01 = 500 mV 10 = 440 mV 11 = 320 mV 18 vref Ref_Vfs[4:0] 0x00 Select (global) Reference full-scale adjust adjustments 10000 = 0.98 V p-p for VREF. 10001 = 1.00 V p-p 10010 = 1.02 V p-p 10011 = 1.04 V p-p … 11111 = 1.23 V p-p 00000 = 1.25 V p-p (default) 00001 = 1.27 V p-p … 01110 = 1.48 V p-p 01111 = 1.5 V p-p 19 user_ B7 B6 B5 B4 B3 B2 B1 B0 0xA5 User-defined patt1_lsb pattern, (local) 1 LSB. 1A user_ B15 B14 B13 B12 B11 B10 B9 B8 0x66 User-defined patt1_msb pattern, (local) 1 MSB 1B user_ B7 B6 B5 B4 B3 B2 B1 B0 0x53 User-defined patt2_lsb pattern, (local) 2 LSB 1C user_ B15 B14 B13 B12 B11 B10 B9 B8 0x35 User-defined patt2_msb pattern, (local) 2 MSB 1D user_ B7 B6 B5 B4 B3 B2 B1 B0 0xBB User-defined patt3_lsb pattern, (local) 3 LSB 1E user_ B15 B14 B13 B12 B11 B10 B9 B8 0xDD User-defined patt3_msb pattern, (local) 3 MSB Rev. B | Page 35 of 40 AD9239 Default Default Addr. Register (MSB) (LSB) Value Notes/ (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 1F user_ B7 B6 B5 B4 B3 B2 B1 B0 0xAA User-defined patt4_lsb pattern, (local) 4 LSB. 20 user_ B15 B14 B13 B12 B11 B10 B9 B8 0xCC User defined patt4_msb pattern (local) 4 MSB. 21 serial_control PLL 0x08 Serial stream (global) high control. encode rate mode (global) 0 = low rate 1 = high rate (default) 24 misr_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 Least (local) significant byte of MISR. Read only. 25 misr_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 Most (local) significant byte of MISR. Read only. 32 adi_link_ Hamming Scramble Data flow Over- Scramble options Scramble 0x4B Default is options enable data only order range in 00 = inverted enable 56-bit (global) 1 = on 0 = 0 = header 01 = SONET (default) 1 = on SONET (default) scramble ECC last 1 = on 10 = Ethernet (default) scrambler 0 = off header (default) (default) 0 = off with over and data 1 = 0 = off range in the (default) Scrambler header bits. 1 = last scramble (Override data only 0x032[5]) 34 Channel ID Channel ID 0x00 (local) (Only Bits[3:0] used if overrange is included in header) 50 coarse_ Gain adjust Coarse Gain Adjust[5:0] = Output[63:0] 0x00 gain_adj enable 000000 = 0000…0001 (local) 1 = on 000001 = 0000…0011 0 = off 000010 = 0000…0111 (default) … 111101 = 0011…1111 111110 = 0111…1111 111111 = 1111…1111 51 fine_ Fine Gain Adjust[3:0] = Output[15:0] 0x00 gain_adj 0000 = 0000000000000001 (local) 0001 = 0000000000000010 0010 = 0000000000000100 … 1101 = 0010000000000000 1110 = 0100000000000000 1111 = 1000000000000000 52 gain_cal_ctl Temp. sensor Gain quar- Gain cal Gain cal 0x02 enable ter LSB resetb enable 1 = on 1 = on 1 = on 1 = on 0 = off 0 = off (default) 0 = off (default) (default) 0 = off (default) 53 Dynamic pgm_3 pgm_2 pgm_1 pgm_0 0x00 Standby = pgm pins 00 = sync 00 = sync 00 = sync 00 = sync ADC core (global) 01 = standby A 01 = standby B 01 = standby C 01 = standby D off, PN23 10 = standby A and D 10 = standby B and C 10 = standby C and B 10 = standby D and A enabled, 11 = standby A and B 11 = standby B and A 11 = standby C and D 11 = standby D and C serial channel enabled. Rev. B | Page 36 of 40 AD9239 Exposed Paddle Thermal Heat Slug Recommendations Power and Ground Recommendations It is required that the exposed paddle on the underside of the When connecting power to the AD9239, it is recommended ADC is connected to analog ground (AGND) to achieve the best that two separate 1.8 V supplies be used: one for analog (AVDD) electrical and thermal performance of the AD9239. An exposed and one for digital (DRVDD). If only one supply is available, it continuous copper plane on the PCB should mate to the AD9239 should be routed to the AVDD first and then tapped off and exposed paddle, Pin 0. The copper plane should have several vias isolated with a ferrite bead or a filter choke preceded by to achieve the lowest possible resistive thermal path for heat decoupling capacitors for the DRVDD. The user can employ dissipation to flow through the bottom of the PCB. These vias several different decoupling capacitors to cover both high and should be solder-filled or plugged with nonconductive epoxy. low frequencies. These should be located close to the point of entry at the printed circuit board (PCB) level and close to the To maximize the coverage and adhesion between the ADC and parts, with minimal trace lengths. PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides A single PCB ground plane should be sufficient when using the several tie points between the ADC and PCB during the reflow AD9239. With proper decoupling and smart partitioning of the process, whereas using one continuous plane with no partitions analog, digital, and clock sections of the PCB, optimum guarantees only one tie point. See Figure 79 for a PCB layout performance can easily be achieved. example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR Figure 79. Typical PCB Layout Rev. B | Page 37 of 40 06980-029 AD9239 OUTLINE DIMENSIONS 0.60 10.00 0.42 0.60 BSC SQ 0.24 0.42 0.24 PIN 1 55 72 INDICATOR 1 54 PIN 1 INDICATOR 0.50 9.75 8.35 BSC BSC SQ TOP VIEW 8.20 SQ 8.05 0.50 37 18 0.40 36 19 0.30 12° MAX 0.80 MAX 8.50 REF 1.00 0.65 TYP 0.85 0.05 MAX 0.80 FOR PROPER CONNECTION OF 0.02 NOM THE EXPOSED PAD, REFER TO COPLANARITY THE PIN CONFIGURATION AND SEATING 0.30 0.08 0.20 REF FUNCTION DESCRIPTIONS PLANE 0.23 SECTION OF THIS DATA SHEET. 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 80. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-3) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9239BCPZ-170 –40°C to +85°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-3 AD9239BCPZ-210 –40°C to +85°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-3 AD9239BCPZ-250 –40°C to +85°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-3 AD9239-250KITZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 38 of 40 030408-A AD9239 NOTES Rev. B | Page 39 of 40 AD9239 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06980-0-5/10(B) Rev. B | Page 40 of 40