ANALOG DEVICES AD9237

12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter AD9237 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultralow power AVDD DRVDD 85 mW at 20 MSPS VIN+ 10-STAGE 135 mW at 40 MSPS SHA MDAC1 1 1/2-BIT A/D PIPELINE VIN– 190 mW at 65 MSPS 4 15 3 SNR = 66 dBc to Nyquist at 65 MSPS REFT A/D SFDR = 80 dBc to Nyquist at 65 MSPS REFB DNL = ±0.7 LSB CORRECTION LOGIC Differential input with 500 MHz bandwidth 12 OE MODE2 Flexible analog input: 1 V p-p to 4 V p-p range OUTPUT BUFFERS OTR Offset binary, twos complement, or gray code data formats D11 AD9237 Output enable pin VREF D0 2-step power-down CLOCK DUTY CYCLE MODE SENSE Full power-down and sleep mode STABILIZER SELECT Clock duty cycle stabilizer REF 0.5V SELECT APPLICATIONS AGND CLK PDWN MODE DGND Figure 1. Ultrasound and medical imaging Battery-powered instruments Hand-held scope meters Low cost digital oscilloscopes Low power digital still cameras and copiers Low power communications GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. Operating at 65 MSPS, the AD9237 consumes a low 190 mW The AD9237 is a family of monolithic, single 3 V supply, 12-bit, at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS. 20 MSPS/40 MSPS/65 MSPS analog-to-digital converters 2. Power scaling reduces the operating power further when (ADC). This family features a high performance sample-and- running at lower speeds. hold amplifier (SHA) and voltage reference. The AD9237 uses a 3. The AD9237 operates from a single 3 V power supply and multistage differential pipelined architecture with output error features a separate digital output driver supply to correction logic to provide 12-bit accuracy at 20 MSPS/ accommodate 2.5 V and 3.3 V logic families. 40 MSPS/65 MSPS data rates and guarantees no missing codes 4. The patented SHA input maintains excellent performance over the full operating temperature range. for input frequencies beyond Nyquist and can be configured With significant power savings over previously available ADCs, for single-ended or differential operation. the AD9237 is suitable for applications in imaging and medical 5. The AD9237 is optimized for selectable and flexible input ultrasound. ranges from 1 V p-p to 4 V p-p. 6. An output enable pin allows for multiplexing of the outputs. Fabricated on an advanced CMOS process, the AD9237 is 7. Two-step power-down supports a standby mode in addition available in a 32-lead LFCSP and is specified over the industrial to a power-down mode. temperature range (−40°C to +85°C). 8. The OTR output bit indicates when the signal is beyond the selected input range. 9. The clock duty cycle stabilizer (DCS) maintains converter performance over a wide range of clock pulse widths. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05455-001 AD9237 TABLE OF CONTENTS Features .............................................................................................. 1  Pin Configuration and Function Descriptions ..............................8  Applications ....................................................................................... 1  Terminology .......................................................................................9  Functional Block Diagram .............................................................. 1  Equivalent Circuits ......................................................................... 10  General Description ......................................................................... 1  Typical Performance Characteristics ........................................... 11  Product Highlights ........................................................................... 1  Applying the AD9237 .................................................................... 16  Revision History ............................................................................... 2  Theory of Operation .................................................................. 16  Specif ica t ions ..................................................................................... 3  Analog Input and Reference Overview ................................... 16  DC Specifications ......................................................................... 3  Voltage Reference ....................................................................... 18  Digital Specifications ................................................................... 4  Clock Input Considerations ...................................................... 19  AC Specifications .......................................................................... 4  Power Dissipation, Power Scaling, and Standby Mode ......... 19  Switching Specifications .............................................................. 5  Digital Outputs ........................................................................... 21  Timing Diagram ............................................................................... 6  Outline Dimensions ....................................................................... 22  Absolute Maximum Ratings ............................................................ 7  Ordering Guide .......................................................................... 22  ESD Caution .................................................................................. 7  REVISION HISTORY 5/10—Rev. 0 to Rev. A Changes to Product Highlights Section ......................................... 1 Changes to Pipeline Delay Parameter in Table 4 .......................... 5 Changes to Figure 2 .......................................................................... 6 Changes to Figure 3 and Table 6 ..................................................... 8 10/05—Revision 0: Initial Version Rev. A | Page 2 of 24 AD9237 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, T to T , MIN MAX unless otherwise noted. Table 1. AD9237BCP-20 AD9237BCP-40 AD9237BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Guaranteed 12 12 12 Bits Offset Error ±1.30 ±1.95 ±1.30 ±1.95 ±1.30 ±1.95 % FSR 1 Gain Error ±0.70 ±2.10 ±0.75 ±2.10 ±1.05 ±2.25 % FSR 2 Differential Nonlinearity (DNL) ±0.70 ±0.95 ±0.70 ±0.95 −1.00 ±0.70 +1.25 LSB 2 Integral Nonlinearity (INL) ±0.90 ±1.35 ±0.90 ±1.35 ±0.90 ±2.00 LSB TEMPERATURE DRIFT Offset Error ±2 ±2 ±2 ppm/°C 1 Gain Error ±12 ±12 ±12 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±5 ±25 ±5 ±25 ±5 ±25 mV Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV Reference Input Resistance 7 7 7 kΩ INPUT REFERRED NOISE VREF = 0.5 V 1.35 1.35 1.35 LSB rms VREF = 1.0 V 0.70 0.70 0.70 LSB rms ANALOG INPUT Input Span VREF = 0.5 V; MODE2 = 0 V 1 1 1 V p-p VREF = 1.0 V; MODE2 = 0 V 2 2 2 V p-p VREF = 0.5 V; MODE2 = AVDD 2 2 2 V p-p VREF = 1.0 V; MODE2 = AVDD 4 4 4 V p-p 3 Input Capacitance 7 7 7 pF POWER SUPPLIES Supply Voltages AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V Supply Current 2 IAVDD 30.5 45.5 64.5 mA 2 IDRVDD 3.0 4.5 5.5 mA PSRR ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION 4 DC Input 85 135 190 mW 2 Sine Wave Input 100 120 150 180 210 270 mW Power-Down Mode 1 1 1 mW Standby Power 20 20 20 mW 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate, f = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. IN 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. Rev. A | Page 3 of 24 AD9237 DIGITAL SPECIFICATIONS Table 2. AD9237BCP-20 AD9237BCP-40 AD9237BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage 2.0 2.0 2.0 V Low Level Input Voltage 0.8 0.8 0.8 V High Level Input Current –10 +10 –10 +10 –10 +10 μA Low Level Input Current –10 +10 –10 +10 –10 +10 μA Input Capacitance 2 2 2 pF 1 LOGIC OUTPUTS DRVDD = 3.3 V High-Level Output Voltage (IOH = 50 μA) 3.29 3.29 3.29 V High-Level Output Voltage (IOH = 0.5 mA) 3.25 3.25 3.25 V Low-Level Output Voltage (IOL = 1.6 mA) 0.2 0.2 0.2 V Low-Level Output Voltage (IOL = 50 μA) 0.05 0.05 0.05 V DRVDD = 2.5 V High-Level Output Voltage (IOH = 50 μA) 2.49 2.49 2.49 V High-Level Output Voltage (IOH = 0.5 mA) 2.45 2.45 2.45 V Low-Level Output Voltage (IOL = 1.6 mA) 0.2 0.2 0.2 V Low-Level Output Voltage (IOL = 50 μA) 0.05 0.05 0.05 V 1 Output voltage levels measured with 5 pF load on each output. AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 3. AD9237BCP-20 AD9237BCP-40 AD9237BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz 66.8 66.5 66.5 dBc f = 9.7 MHz 65.6 66.6 dBc INPUT f = 19.6 MHz 65.3 66.6 dBc INPUT f = 34.2 MHz 64.0 66.1 dBc INPUT fINPUT = 70 MHz 66.0 66.3 65.9 dBc SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD) f = 2.4 MHz 66.7 66.4 66.3 dBc INPUT fINPUT = 9.7 MHz 65.1 66.5 dBc fINPUT = 19.6 MHz 64.4 66.4 dBc fINPUT = 34.2 MHz 63.5 65.8 dBc f = 70 MHz 65.6 65.8 65.2 dBc INPUT EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 9.7 MHz 10.8 Bits f = 19.6 MHz 10.7 Bits INPUT f = 34.2 MHz 10.6 Bits INPUT Rev. A | Page 4 of 24 AD9237 AD9237BCP-20 AD9237BCP-40 AD9237BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz 88.0 83.5 85.5 dBc INPUT f = 9.7 MHz 72.4 87.5 dBc INPUT f = 19.6 MHz 72.2 82.4 dBc INPUT fINPUT = 34.2 MHz 69.4 80.1 dBc fINPUT = 70 MHz 80.5 77.9 74.9 dBc WORST HARMONIC (SECOND OR THIRD) fINPUT = 2.4 MHz −88.0 −83.5 −85.5 dBc fINPUT = 9.7 MHz −72.4 −87.5 dBc fINPUT = 19.6 MHz −72.2 −82.4 dBc f = 34.2 MHz −69.4 −80.1 dBc INPUT f = 70 MHz −80.5 −77.9 −74.9 dBc INPUT WORST OTHER SPUR f = 2.4 MHz −90 −90 −90 dBc INPUT f = 9.7 MHz −73.4 −90 dBc INPUT fINPUT = 19.6 MHz −73.1 −90 dBc fINPUT = 34.2 MHz −72.0 −90 dBc fINPUT = 70 MHz −90 −90 −90 dBc SWITCHING SPECIFICATIONS Table 4. AD9237BCP-20 AD9237BCP-40 AD9237BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit CLK INPUT PARAMETERS Maximum Conversion Rate 20 40 65 MSPS Minimum Conversion Rate 1 1 1 MSPS CLK Period 50.0 25.0 15.4 ns 1 CLK Pulse Width High 15.0 8.8 6.2 ns 1 CLK Pulse Width Low 15.0 8.8 6.2 ns DATA OUTPUT PARAMETERS 2 Output Delay (t ) 3.5 3.5 3.5 ns PD Pipeline Delay (Latency) 9 9 9 Cycles Output Enable Time 6 6 6 ns Output Disable Time 3 3 3 ns Aperture Delay (tA) 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) 0.5 0.5 0.5 ps rms 3 Wake-Up Time (Sleep Mode) 3.0 3.0 3.0 ms 3 Wake-Up Time (Standby Mode) 3.0 3.0 3.0 μs OUT-OF-RANGE RECOVERY TIME 1 1 2 Cycles 1 With duty cycle stabilizer enabled. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. Rev. A | Page 5 of 24 AD9237 TIMING DIAGRAM N+1 N N+2 N+8 N–1 N+3 ANALOG t A INPUT N+7 N+4 N+5 N+6 CLK DATA N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 OUT t PD Figure 2. Timing Diagram Rev. A | Page 6 of 24 05455-002 AD9237 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Pin Name Respect to Min Max Unit rating only; functional operation of the device at these or any ELECTRICAL other conditions above those indicated in the operational AVDD AGND –0.3 +3.9 V section of this specification is not implied. Exposure to absolute DRVDD DGND –0.3 +3.9 V maximum rating conditions for extended periods may affect AGND DGND –0.3 +0.3 V device reliability. AVDD DRVDD –3.9 +3.9 V Digital DGND –0.3 DRVDD + 0.3 V Absolute maximum ratings are limiting values to be applied Outputs, OE individually and beyond which the serviceability of the circuit CLK, MODE, AGND −0.3 AVDD + 0.3 V may be impaired. Functional operability is not necessarily MODE2 implied. Exposure to absolute maximum rating conditions for VIN+, VIN– AGND –0.3 AVDD + 0.3 V an extended period may affect device reliability. VREF AGND –0.3 AVDD + 0.3 V ESD CAUTION SENSE AGND –0.3 AVDD + 0.3 V REFB, REFT AGND –0.3 AVDD + 0.3 V PDWN AGND –0.3 AVDD + 0.3 V 1 ENVIRONMENTAL Operating Temperature –40 +85 °C Junction Temperature 150 °C Lead Temperature (10 sec) 300 °C Storage Temperature –65 +150 °C 1 Typical thermal impedances (32-lead LFCSP), θ = 32.5°C/W, θ = 32.71°C/W. JA JC These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1. Rev. A | Page 7 of 24 AD9237 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MODE2 1 24 VREF PIN 1 CLK 2 23 SENSE INDICATOR OE 3 22 MODE PDWN 4 21 OTR AD9237 GC 5 20 D11 (MSB) TOP VIEW DNC 6 19 D10 (Not to Scale) D0 (LSB) 7 18 D9 D1 8 17 D8 NOTES 1. DNC = DO NOT CONNECT. 2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE. Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin Number Mnemonic Description 1 MODE2 SHA Gain Select and Power Scaling Control (see Table 8). 2 CLK Clock Input Pin. 3 OE Output Enable Pin (Active Low). 4 PDWN Power-Down Function Selection (see Table 9). 5 GC Gray Code Control (Active High). 6 DNC Do Not Connect. 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits. 15 DGND Digital Output Ground. 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 21 OTR Out-of-Range Indicator. 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10). 23 SENSE Reference Mode Selection (see Table 7). 24 VREF Voltage Reference Input/Output (see Table 7). 25 REFB Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor. 26 REFT Differential Reference (+). 27, 32 AVDD Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 28, 31 AGND Analog Ground. 29 VIN+ Analog Input Pin (+). 30 VIN− Analog Input Pin (−). EP It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. Rev. A | Page 8 of 24 05455-003 D2 9 32 AVDD 31 AGND D3 10 D4 11 30 VIN– D5 12 29 VIN+ D6 13 28 AGND D7 14 27 AVDD DGND 15 26 REFT DRVDD 16 25 REFB AD9237 TERMINOLOGY 1 Analog Bandwidth (Full Power Bandwidth) Signal-To-Noise and Distortion (SINAD) The analog input frequency at which the spectral power of the The ratio of the rms signal amplitude to the rms value of the fundamental frequency (as determined by the FFT analysis) is sum of all other spectral components below the Nyquist reduced by 3 dB. frequency, including harmonics but excluding dc. Aperture Delay (t ) Effective Number of Bits (ENOB) A The delay between the 50% point of the rising edge of the clock The effective number of bits for a device for sine wave inputs and the instant at which the analog input is sampled. at a given input frequency can be calculated directly from its measured SINAD using the following formula: Aperture Jitter (t ) J ENOB = (SINADdBFS − 1.76)/6.02 The sample-to-sample variation in aperture delay. 1 Signal-to-Noise Ratio (SNR) Integral Nonlinearity (INL) The ratio of the rms signal to the rms value of the sum of all The deviation of each individual code from a line drawn from other spectral components below the Nyquist frequency, negative full scale through positive full scale. The point used excluding the first six harmonics and dc. as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSBs 1 Spurious-Free Dynamic Range (SFDR) beyond the last code transition. The deviation is measured SFDR is the difference in dB between the rms amplitude of the from the middle of each particular code to the true straight line. input signal and the rms value of the peak spurious signal. The peak spurious signal may not be an harmonic. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB 1 Two-Tone SFDR apart. DNL is the deviation from this ideal value. Guaranteed The ratio of the rms value of either input tone to the rms value no missing codes to 12-bit resolution indicates that all 4096 of the peak spurious component. The peak spurious component codes must be present over all operating ranges. may or may not be an IMD product. Offset Error Clock Pulse Width and Duty Cycle The major carry transition should occur for an analog value Pulse width high is the minimum amount of time that the clock ½ LSB below VIN+ = VIN–. Offset error is defined as the pulse should be left in the Logic 1 state to achieve rated deviation of the actual transition from that point. performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these Gain Error specifications define an acceptable clock duty cycle. The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur Minimum Conversion Rate at an analog value 1½ LSB below the positive full scale. Gain The clock rate at which the SNR of the lowest analog signal error is the deviation of the actual difference between first and frequency drops by no more than 3 dB below the guaranteed last code transitions and the ideal difference between first and limit. last code transitions. Maximum Conversion Rate Temperature Drift The clock rate at which parametric testing is performed. The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value Output Propagation Delay (tPD) at T or T . The delay between the clock logic threshold and the time when MIN MAX all bits are within valid logic levels. Power Supply Rejection Ratio The change in full scale from the value with the supply at the Out-of-Range Recovery Time The time it takes the ADC to reacquire the analog input after a minimum limit to the value with the supply at its maximum limit. transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% 1 Total Harmonic Distortion (THD) below positive full scale. The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. A | Page 9 of 24 AD9237 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– D11–D0, OTR Figure 4. Equivalent Analog Input Circuit Figure 6. Equivalent Digital Output Circuit MODE, 375Ω 375Ω CLK, MODE2, PDWN GC, OE 70kΩ Figure 5. Equivalent MODE, MODE2, GC, OE Input Circuit Figure 7. Equivalent CLK, PDWN Input Circuit Rev. A | Page 10 of 24 05455-004 05455-005 05455-006 05455-007 AD9237 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate with DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS, VREF = 1.0 V internal, FFT length 16 K, unless otherwise noted. 0 90 SNR = 66.9dBc SFDR = 87.0dBc SFDR –20 85 –40 80 –60 75 –80 70 SNR –100 65 –120 60 01 2 4 680 10.0 12.5 15.0 17.5 20.0 FREQUENCY (MHz) CLOCK FREQUENCY (MSPS) Figure 8. AD9237-20 10 MHz FFT Figure 11. AD9237-20 SNR/SFDR vs. Clock Frequency with fIN = 10 MHz 0 90 SNR = 66.8dBc SFDR = 83.1dBc –20 85 SFDR –40 80 –60 75 –80 70 –100 SNR –120 65 02 241 6 8 10 12 14 1680 20 25 30 35 40 FREQUENCY (MHz) CLOCK FREQUENCY (MSPS) Figure 9. AD9237-40 20 MHz FFT Figure 12. AD9237-40 SNR/SFDR vs. Clock Frequency with f = 20 MHz IN 0 90 SNR = 66.0dBc SFDR = 78.6dBc –20 85 SFDR –40 80 –60 75 –80 70 SNR –100 65 –120 60 0 5 10 15 20 25 30 32.5 40 45 50 55 60 65 FREQUENCY (MHz) CLOCK FREQUENCY (MSPS) Figure 10. AD9237-65 70 MHz FFT Figure 13. AD9237-65 SNR/SFDR vs. Clock Frequency with f = 35 MHz IN Rev. A | Page 11 of 24 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05455-010 05455-009 05455-008 SNR/SFDR (dBc) SNR/SFDR (dBc) SNR/SFDR (dBc) 05455-012 05455-013 05455-011 AD9237 0 90 SFDR DCS SNR = 65.6dBc ENABLED SFDR = 67.1dBc 85 –20 80 SFDR DCS –40 DISABLED 75 –60 70 SNR DCS ENABLED 65 –80 60 SNR DCS DISABLED –100 55 –120 50 0 5 10 15 20 25 30 32.5 30 35 40 45 50 55 60 65 70 FREQUENCY (MHz) DUTY CYCLE (%) Figure 14. AD9237-65 100 MHz FFT Figure 17. SNR/SFDR vs. Clock Duty Cycle 90 90 SFDR dBFS 4V p-p SFDR dBFS 2V p-p 80 80 SFDR dBFS 1V p-p SFDR dBFS 2V p-p SFDR dBc 2V p-p SNR dBFS 2V p-p SNR dBFS 2V p-p SNR dBFS 4V p-p 70 70 SFDR dBc 1V p-p SNR dBFS 1V p-p 60 60 SFDR dBc 4V p-p SFDR dBc 2V p-p 50 50 SNR dBc 1V p-p 40 40 SNR dBc 2V p-p SNR dBc 4V p-p SNR dBc 2V p-p 30 30 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 15. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz Figure 18. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz 100 100 SFDR dBFS 2V p-p SFDR dBFS 2V p-p 90 90 SFDR dBc 2V p-p SFDR dBc 2V p-p 80 80 SFDR dBFS 1V p-p SFDR dBFS 1V p-p SFDR dBc 1V p-p SFDR dBc 1V p-p 70 70 60 60 SNR dBFS 2V p-p SNR dBFS 2V p-p SNR dBFS 1V p-p SNR dBFS 1V p-p 50 50 40 40 SNR dBc 2V p-p SNR dBc 2V p-p SNR dBc 1V p-p SNR dBc 1V p-p 30 30 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 16. AD9237-40 SNR/SFDR vs. Input Amplitude with fIN = 20 MHz Figure 19. AD9237-20 SNR/SFDR vs. Input Amplitude with fIN = 10 MHz Rev. A | Page 12 of 24 SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) AMPLITUDE (dBc) 05455-019 05455-017 05455-014 SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc) 05455-020 05455-018 05455-030 AD9237 0 100 SNR = 67.0dBFS SFDR = 87.8dBFS 90 –20 SFDR dBFS 80 –40 SNR dBFS 70 –60 60 SFDR dBc –80 50 –100 40 SNR dBc –120 30 0 5 10 15 20 25 30 32.5 –30 –25 –20 –15 –10 –6.5 FREQUENCY (MHz) INPUT AMPLITUDE (AIN) Figure 20. AD9237-65 Two-Tone FFT, f = 45 MHz, f = 46 MHz Figure 23. AD9237-65 Two-Tone SNR/SFDR , vs. Analog Input with IN1 IN2 f = 45 MHz, f = 46 MHz IN1 IN2 0 100 SNR = 67.2dBFS SFDR = 88.3dBFS 90 –20 SFDR dBFS 80 –40 SNR dBFS 70 –60 60 SFDR dBc –80 50 –100 40 SNR dBc –120 30 02 5 10 150 –30 –25 –20 –15 –10 –6.5 FREQUENCY (MHz) INPUT AMPLITUDE (AIN) Figure 21. AD9237-40 Two-Tone FFT Figure 24. AD9237-40 Two-Tone SNR/SFDR , vs. Analog Input with fIN1 = 45 MHz, fIN2 = 46 MHz fIN1 = 45 MHz, fIN2 = 46 MHz 0 100 SNR = 66.9dBFS SFDR = 84.1dBFS 90 –20 SFDR dBFS 80 –40 SNR dBFS 70 –60 60 SFDR dBc –80 50 –100 40 SNR dBc –120 30 03 5 10 15 20 250 –30 –25 –20 –15 –10 –6.5 FREQUENCY (MHz) INPUT AMPLITUDE (AIN) Figure 22. AD9237-65 Two-Tone FFT, fIN1 = 69 MHz, fIN2 = 70 MHz Figure 25. AD9237-65 Two-Tone SNR/SFDR vs. Analog Input with fIN1 = 69 MHz, fIN2 = 70 MHz Rev. A | Page 13 of 24 AMPLITUDE (dBFS) AMPLITUDE (dBc) AMPLITUDE (dBc) 05455-094 05455-021 05455-095 SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) SNR/SFDR (dBc and dBFS) 05455-098 05455-025 05455-024 AD9237 0 100 SNR = 67.1dBFS SFDR = 87.3dBFS 90 –20 SFDR dBFS 80 –40 SNR dBFS 70 –60 60 SFDR dBc –80 50 –100 40 SNR dBc –120 30 02 5 10 150 –30 –25 –20 –15 –10 –6.5 FREQUENCY (MHz) INPUT AMPLITUDE (AIN) Figure 26. AD9237-40 Two-Tone FFT Figure 29. AD9237-40 Two-Tone SNR/SFDR vs. Analog Input with f = 69 MHz, f = 70 MHz f = 69 MHz, f = 70 MHz IN1 IN2 IN1 IN2 90 90 85 85 SFDR SFDR 80 80 75 75 70 70 SNR SNR 65 65 60 60 55 55 0 25 50 75 100 125 0 25 50 75 100 125 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 27. AD9237-65 SNR/SFDR vs. Input Frequency Figure 30. AD9237-40 SNR/SFDR vs. Input Frequency 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 28. Typical INL Figure 31. Typical DNL Rev. A | Page 14 of 24 INL (LSB) SNR/SFDR (dBc) AMPLITUDE (dBc) 05455-032 05455-015 05455-026 DNL (LSB) SNR/SFDR (dBc) SNR/SFDR (dBc and dBFS) 05455-035 05455-016 05455-097 AD9237 67.5 90 85 67.0 10.83 AD9237-20 SNR AD9237-40 80 66.5 10.75 75 AD9237-65 66.0 10.67 70 SFDR 65.5 10.59 65 65.0 10.50 60 –40 –20 0 20 40 60 8085 10 20 30 40 50 60 70 TEMPERATURE (°C) CLOCK FREQUENCY (MSPS) Figure 32. AD9237 SINAD/ENOB vs. Clock Frequency with f = Nyquist IN Figure 33. AD9237-65 SNR/SFDR vs. Temperature with fIN = 32.5MHz Rev. A | Page 15 of 24 SINAD (dBc) ENOB (Bits) 05455-062 SNR/SFDR (dBc) 05455-063 AD9237 APPLYING THE AD9237 90 THEORY OF OPERATION 2.5MHz SFDR The AD9237 uses a calibrated, 11-stage pipeline architecture 80 34.2MHz SFDR with a patented input SHA implemented. Each stage of the pipeline, excluding the last, consists of a low resolution flash 70 2.5MHz SNR ADC connected to a switched capacitor digital-to-analog 34.2MHz SNR converter (DAC) and an interstage residue amplifier (MDAC). 60 The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the 50 pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a 40 flash ADC. 30 The pipelined architecture permits the first stage to operate on a 0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT COMMON-MODE LEVEL (V) new input sample, while the remaining stages operate on preceding Figure 34. AD9237-65 SNR/SFDR vs. Input Common-Mode Level samples. While the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be In addition, a small shunt capacitor placed across the inputs fully processed and to appear at the output, as shown in Figure 2. provides dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the The input stage contains a differential SHA that can be ac- or precise values are dependent on the application. In IF under- dc-coupled in differential or single-ended modes. The output- sampling applications, the shunt capacitor(s) should be reduced staging block aligns the data, carries out the error correction, or removed depending on the input frequency. In combination and passes the data to the output buffers. The output buffers with the driving source impedance, the capacitors limit the are powered from a separate supply, allowing adjustment of input bandwidth. the output voltage swing. During power-down and stand-by operation, the output buffers go into a high impedance state. H The ADC samples the analog input on the rising edge of T T the clock. System disturbances just prior to, or immediately 5pF following, the rising edge of the clock and/or excessive clock VIN+ jitter can cause the SHA to acquire the wrong input value and C PAR should be minimized. ANALOG INPUT AND REFERENCE OVERVIEW T 5pF The analog input to the AD9237 is a differential switched VIN– capacitor SHA that has been designed for optimum C PAR performance while processing a differential input signal. T The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 34. H An input common-mode voltage of midsupply minimizes Figure 35. Switched-Capacitor SHA Input signal-dependant errors and provides optimum performance. For best dynamic performance, the source impedances driving Figure 35 shows the clock signal alternately switching the VIN+ and VIN– should be matched so that common-mode SHA between sample mode and hold mode. When the SHA is settling errors are symmetrical. These errors are reduced by the switched into sample mode, the signal source must be capable common-mode rejection of the ADC. of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can An internal differential reference buffer creates positive and help reduce the peak transient current required from the output negative reference voltages, REFT and REFB, that define the stage of the driving source. span of the ADC core. Rev. A | Page 16 of 24 SNR/SFDR (dBc) 05455-038 05455-039 AD9237 The output common mode of the reference buffer is set to mid- 1kΩ 25Ω AVDD 1.2kΩ 0.1μF supply, and the REFT and REFB voltages and input span are 0.1μF 33Ω VIN+ + defined as: 15pF AD8351 2V p-p 49.9Ω AD9237 0.1μF 33Ω REFT = ½(AVDD + VREF) – VIN– 0.1μF 25Ω REFB = ½(AVDD − VREF) AGND 1kΩ 4×() REFT − REFB 4×VREF Span = = Figure 36. Differential Input Configuration Using the AD8351 Span _ Factor Span _ Factor At input frequencies in the second Nyquist zone and above, the The previous equations show that the REFT and REFB voltages performance of most amplifiers is not adequate to achieve the are symmetrical about the midsupply voltage, and the input true performance of the AD9237. This is especially true in IF span is proportional to the value of the VREF voltage, see Table 7 undersampling applications where frequencies in the 70 MHz for more details. to 100 MHz range are being sampled. For these applications, The internal voltage reference can be pin strapped to fixed differential transformer coupling is the recommended input values of 0.5 V or 1.0 V, or adjusted within this range as configuration, as shown in Figure 37. discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9237 AVDD set to an input span of 2 V p-p or greater. The relative SNR 33Ω VIN+ degradation is 3 dB when changing from 2 V p-p mode to 15pF AD9237 2V p-p 1 V p-p mode. 49.9Ω 33Ω VIN– The SHA must be driven from a source that keeps the signal 1kΩ AGND peaks within the allowable range for the selected reference 0.1μF 1kΩ voltage. The minimum and maximum common-mode input levels are defined as: Figure 37. Differential Transformer-Coupled Configuration VCM = VREF/2 MIN The signal characteristics must be considered when selecting a VCM = (AVDD + VREF)/2 MAX transformer. Most RF transformers saturate at frequencies The minimum common-mode input level allows the AD9237 to below a few MHz, and excessive signal power can cause core accommodate ground-referenced inputs. saturation, which leads to distortion. Single-Ended Input Configuration Although optimum performance is achieved with a differential input, a single-ended source can be driven into VIN+ or VIN–. A single-ended input can provide adequate performance in In this configuration, one input accepts the signal while the cost-sensitive applications. In this configuration, there is opposite input should be set to midscale by connecting it to an degradation in SFDR and distortion performance due to the appropriate reference. For example, a 2 V p-p signal can be large input common-mode swing. However, if the source applied to VIN+ while a 1 V reference is applied to VIN–. The impedances on each input are matched, there should be little AD9237 then accepts an input signal varying between 2 V and effect on SNR performance. Figure 38 details a typical single- 0 V. In the single-ended configuration, distortion performance ended input configuration. may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and AVDD in the lower speed grade models (AD9237-40 and AD9237-20). 0.1μF 1kΩ 33Ω VIN+ 1kΩ 49.9Ω Differential Input Configurations 15pF 2V p-p AD9237 1kΩ 33Ω As previously detailed, optimum performance is achieved while VIN– 0.1μF 1kΩ AGND driving the AD9237 in a differential input configuration. For 25Ω baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8351 is easily set to Figure 38. Single-Ended Input Configuration AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Figure 36 details a typical configuration using the AD8351. Rev. A | Page 17 of 24 05455-042 05455-099 05455-041 AD9237 Table 7. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Span Factor Resulting Differential Span (V p-p) External Reference AVDD N/A 2 4×ExternalReference Span_Factor 1 Internal Fixed Reference VREF 0.5 2 1.0 V 1 4.0 V Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 4×VREF (See Figure 40) Span_Factor 1 Internal Fixed Reference AGND to 0.2 V 1.0 2 2.0 V 1 1.0 V VOLTAGE REFERENCE VIN+ VIN– A stable and accurate 0.5 V voltage reference is built into REFT the AD9237. The input range can be adjusted by varying 0.1μF + ADC the reference voltage applied to the AD9237, using either the 0.1μF 10μF CORE internal reference or an externally applied reference voltage. REFB The input span of the ADC tracks reference voltage changes 0.1μF linearly. VREF + 10μF 0.1μF 0.5V In all reference configurations, REFT and REFB drive the SELECT LOGIC A/D conversion core and, in conjunction with the span factor, SENSE establish its input span. The input range of the ADC always equals four times the voltage at the reference pin divided by the span factor for either an internal or an external reference. AD9237 It is required to decouple REFT to REFB with 0.1 μF and 10 μF decoupling capacitors, as shown in Figure 39. Figure 39. Internal Reference Configuration Internal Reference Connection A comparator within the AD9237 detects the potential at VIN+ VIN– the SENSE pin and configures the reference into one of four REFT possible states, which are summarized in Table 7. If SENSE is 0.1μF + ADC grounded, the reference amplifier switch is connected to the 0.1μF 10μF CORE internal resistor divider, setting VREF to 1 V (see Figure 39). REFB Connecting the SENSE pin to VREF switches the reference 0.1μF VREF amplifier output to the SENSE pin, completing the loop and + providing a 0.5 V reference output. If a resistor divider is 10μF 0.1μF 0.5V SELECT connected, as shown in Figure 40, then the switch is again set to R2 LOGIC the SENSE pin. This puts the reference amplifier in a non- SENSE inverting mode with the VREF output defined as R1 R2 ⎛ ⎞ VREF= 0.5× 1+ ⎜ ⎟ AD9237 ⎝ R1⎠ Figure 40. Programmable Reference Configuration Rev. A | Page 18 of 24 05455-043 05455-044 AD9237 CLOCK INPUT CONSIDERATIONS External Reference Operation Typical high speed ADCs use both clock edges to generate The use of an external reference may be necessary to enhance a variety of internal timing signals and, as a result, can be the gain accuracy of the ADC or to improve thermal drift sensitive to clock duty cycle. Commonly a 5% tolerance is characteristics. Figure 41 shows the typical drift characteristics required on the clock duty cycle to maintain dynamic of the internal reference in both 1 V and 0.5 V modes. When performance characteristics. The AD9237 contains a clock multiple ADCs track one another, a single reference (internal or duty cycle stabilizer (DCS) that retimes the nonsampling, or external) reduces gain matching errors. falling edge, providing an internal clock signal with a nominal When the SENSE pin is connected to AVDD, the internal 50% duty cycle. This allows a wide range of clock input duty reference is disabled, allowing the use of an external reference. cycles without affecting the performance of the AD9237. As An internal reference buffer loads the external reference with shown in Figure 17, noise and distortion performance are an equivalent 7 kΩ load. The internal buffer still generates the nearly flat over a 30% range of duty cycle with the DCS enabled. positive and negative full-scale references, REFT and REFB, for The duty cycle stabilizer uses a delay-locked loop (DLL) to the ADC core. The input span is always four times the value of create the nonsampling edge. As a result, any changes to the the reference voltage divided by the span factor; therefore, the sampling frequency require approximately 100 clock cycles to external reference must be limited to a maximum of 1 V. allow the DLL to acquire and lock to the new rate. 0.7 High speed, high resolution ADCs are sensitive to the quality 0.6 of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to rms aperture jitter (tJ) can 0.5 be calculated by 1V REFERENCE 0.4 ⎡ ⎤ 1 SNRDegradation= 20log ⎢ ⎥ 10 0.3 2πf t ⎢ J⎥ INPUT ⎣ ⎦ 0.2 In this equation, the rms aperture jitter represents the root- 0.5V REFERENCE sum-square of all jitter sources, which include the clock input, 0.1 analog input signal, and ADC aperture jitter specification. 0 Undersampling applications are particularly sensitive to jitter. –40 –20 0 20 40 60 80 85 TEMPERATURE (°C) The clock input should be treated as an analog signal in Figure 41. Typical VREF Drift cases where aperture jitter can affect the dynamic range of the AD9237. Power supplies for clock drivers should be separated If the internal reference of the AD9237 is used to drive multiple from the ADC output driver supplies to avoid modulating the converters to improve gain matching, the loading of the refer- clock signal with digital noise. Low jitter, crystal-controlled ence by the other converters must be considered. Figure 42 oscillators make the best clock sources. If the clock is generated shows how the internal reference voltage is affected by loading. from another type of source (such as gating, dividing, or other A 2 mA load is the maximum recommended load. methods), then it should be retimed by the original clock at the 0.05 last step. 0 The lowest typical conversion rate of the AD9237 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. –0.05 0.5V ERROR (%) POWER DISSIPATION, POWER SCALING, AND STANDBY MODE –0.10 As shown in Figure 43, the power dissipated by the AD9237 is 1V ERROR (%) –0.15 proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades –0.20 because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD –0.25 current can be calculated as 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD (mA) I =V ×C × f ×N DRVDD DRVDD LOAD CLK Figure 42. VREF Accuracy vs. Load where N is 12, the number of output bits. Rev. A | Page 19 of 24 ERROR (%) VREF ERROR (%) 05455-093 05455-046 AD9237 190 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the 170 Nyquist frequency, f /2. In practice, the DRVDD current is CLK AD9237-65 established by the average number of output bits switching, 150 which is determined by the encode rate and the characteristics of the analog input signal. 130 190 110 170 AD9237-40 90 150 AD9237-20 70 10 20 30 40 50 60 65 130 SAMPLE RATE (MSPS) AD9237-65 Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled 110 AD9237-40 The MODE2 pin is a multilevel input that controls the span 90 factor and power scaling modes. The MODE2 pin is internally pulled down to AGND by a 70 kΩ resistor. The input threshold AD9237-20 70 and corresponding mode selections are outlined in Table 8. 10 20 30 40 50 60 65 SAMPLE RATE (MSPS) Table 8. MODE2 Selection Figure 43. Total Power vs. Sample Rate with fIN = 10 MHz MODE2 Voltage Span Factor Power Scaling AVDD 1 Disabled For the AD9237-20 speed grade, the digital power consumption 2/3 AVDD 1 Enabled can represent as much as 10% of the total dissipation. Digital 1/3 AVDD 2 Enabled power consumption can be minimized by reducing the AGND (Default) 2 Disabled capacitive load presented to the output drivers. The data in Figure 43 was taken with a 5 pF load on each output driver. The PDWN pin is a multilevel input that controls the power states. The input threshold values and corresponding power The AD9237 is designed to provide excellent performance with states are outlined in Table 9. minimum power. The analog circuitry is optimally biased so Table 9. PDWN Selection that each speed grade provides excellent performance while PDWN Voltage Power State Power (mW) affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases AVDD Power-Down Mode 1 linearly with the clock frequency, as shown in Figure 43. 1/3 AVDD Standby Mode 20 AGND (Default) Normal Operation Based on speed grade The power scaling feature provides an additional power savings By asserting the PDWN pin high, the AD9237 is placed in when enabled, as shown in Figure 44. The power scaling mode power-down mode. In this state, the ADC typically dissipates cannot be enabled if the clock is varied during operation. This is 1 mW. During power-down, the output drivers are placed in a because the internal circuitry cannot quickly track a changing high impedance state. Low power dissipation in power-down clock, and the part does not have enough power to operate mode is achieved by shutting down the reference, reference properly. buffer, biasing networks, clock, and duty cycle stabilizer circuitry. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation. Rev. A | Page 20 of 24 POWER (mW) 05455-047 POWER (mW) 05455-096 AD9237 By asserting the PDWN pin to AVDD/3, the AD9237 is placed completed. By logically AND-ing OTR with the MSB and its in standby mode. In this state, the ADC typically dissipates complement, overrange high or underrange low conditions can 20 mW. The output drivers are placed in a high impedance be detected. Table 11 is a truth table for the overrange/ under- state. The reference circuitry is enabled, allowing for a quick range circuit in Figure 46, which uses NAND gates. Systems start upon bringing the ADC into normal operating mode. requiring programmable gain condition of the AD9237 can, after eight clock cycles, detect an out-of-range condition; DIGITAL OUTPUTS therefore, eliminating gain selection iterations. In addition, The AD9237 output drivers can be configured to interface with OTR can be used for digital offset and gain calculation. 2.5 V or 3.3 V logic families by matching DRVDD to the digital OTR DATA OUTPUTS supply of the interfaced logic. The output drivers are sized to OTR 1 1111 1111 1111 provide sufficient output current to drive a wide variety of logic 0 1111 1111 1111 families. However, large drive currents tend to cause current +FS – 1 LSB 0 1111 1111 1110 glitches on the supplies that can affect converter performance. Applications requiring the ADC to drive large capacitive loads +FS or large fanouts may require external buffers or latches. –FS + 1/2 LSB The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9237; these transients can detract from the converter’s dynamic 0 0000 0000 0001 performance. 0 0000 0000 0000 0 0000 0000 0000 As detailed in Table 10, the data format can be selected for either offset binary, twos complement, or gray code. –FS –FS – 1/2 LSB –FS – 1/2 LSB Operational Mode Selection Figure 45. OTR Relation to Input Voltage and Output Data The AD9237 can output data in either offset binary, twos complement, or gray code format. There is also a provision Table 11. Output Data Format for enabling or disabling the duty cycle stabilizer (DCS). OTR MSB Analog Input Is The MODE pin is a multilevel input that controls the data 0 0 Within range format (except for gray code) and DCS state. The MODE pin 0 1 Within range is internally pulled down to AGND by a 70 kΩ resistor. The 1 0 Underrange input threshold values and corresponding mode selections are 1 1 Overrange outlined in Table 10. The gray code output format is obtained by connecting GC to MSB OVER = 1 AVDD. When the part is in gray code mode, the MODE pin controls the DCS function only. The GC pin is internally pulled OTR down to AGND by a 70 kΩ resistor. UNDER = 1 MSB Table 10. MODE Selection MODE Voltage Data Format Duty Cycle Stabilizer Figure 46. Overrange/Underrange Logic AVDD Twos Complement Disabled Digital Output Enable Function (OE) 2/3 AVDD Twos Complement Enabled The AD9237 has three-state ability. The OE pin is internally 1/3 AVDD Offset Binary Enabled pulled down to AGND by a 70 kΩ resistor. If the OE pin is low, AGND (Default) Offset Binary Disabled the output data drivers are enabled. If the OE pin is high, the Out of Range (OTR) output data drivers are placed in a high impedance state. It is not intended for rapid access to the data bus. Note that the An out-of-range condition exists when the analog input voltage OE pin is referenced to the digital supplies (DRVDD) and is beyond the input range of the ADC. The OTR pin is a digital should not exceed that voltage. output that is updated along with the data output corresponding to the particular sampled input voltage. Therefore, the OTR pin Timing has the same pipeline latency as the digital data. OTR is low The AD9237 provides latched data outputs with a pipeline delay when the analog input voltage is within the analog input range, of eight clock cycles. Data outputs are available one propagation and high when the analog input voltage exceeds the input range, delay (t ) after the rising edge of the clock signal. Refer to PD as shown in Figure 45. OTR remains high until the analog input Figure 2 for a detailed timing diagram. returns to within the input range and another conversion is Rev. A | Page 21 of 24 05455-050 05455-049 AD9237 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE 1, Model Temperature Range Package Description Package Option AD9237BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9237BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9237BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9237BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9237BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9237BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 1 Z = RoHS-Compliant Part. Rev. A | Page 22 of 24 011708-A AD9237 NOTES Rev. A | Page 23 of 24 AD9237 NOTES © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05455–0–5/10(A) Rev. A | Page 24 of 24