ANALOG DEVICES AD9230

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9230 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD (1.8V) SNR = 64.9 dBFS @ f up to 70 MHz @ 250 MSPS IN ENOB of 10.4 @ f up to 70 MHz @ 250 MSPS (−1.0 dBFS) IN REFERENCE AD9230 SFDR = −79 dBc @ f up to 70 MHz @ 250 MSPS (−1.0 dBFS) IN CML DRVDD Excellent linearity DRGND VIN+ DNL = ±0.3 LSB typical TRACK-AND-HOLD VIN– INL = ±0.5 LSB typical ADC 12 OUTPUT 12 12-BIT STAGING D11 TO D0 LVDS at 250 MSPS (ANSI-644 levels) CORE LVDS CLK+ 700 MHz full power analog bandwidth CLOCK OR+ MANAGEMENT CLK– OR– On-chip reference, no external decoupling required Integrated input buffer and track-and-hold SERIAL PORT DCO+ Low power dissipation DCO– 434 mW @ 250 MSPS—LVDS SDR mode RESET SCLK SDIO CSB 400 mW @ 250 MSPS—LVDS DDR mode Figure 1. Functional Block Diagram Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9230 is a 12-bit monolithic sampling analog-to-digital 1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS converter optimized for high performance, low power, and ease with a 70 MHz input. of use. The product operates at up to a 250 MSPS conversion 2. Low Power—Consumes only 434 mW @ 250 MSPS. rate and is optimized for outstanding dynamic performance in 3. Ease of Use—LVDS output data and output clock signal wideband carrier and broadband systems. All necessary allow interface to current FPGA technology. The on-chip functions, including a track-and-hold (T/H) and voltage reference and sample and hold provide flexibility in system reference, are included on the chip to provide a complete signal design. Use of a single 1.8 V supply simplifies system conversion solution. power supply design. The ADC requires a 1.8 V analog voltage supply and a 4. Serial Port Control—Standard serial port interface supports differential clock for full performance operation. The digital various product functions, such as data formatting, disabling outputs are LVDS (ANSI-644) compatible and support either the clock duty cycle stabilizer, power-down, gain adjust, twos complement, offset binary format, or Gray code. A data and output test pattern generation. clock output is available for proper output data timing. 5. Pin-Compatible Family—10-bit pin-compatible family Fabricated on an advanced CMOS process, the AD9230 is offered as AD9211. available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06002-001 AD9230 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 21 Applications....................................................................................... 1 Analog Input and Voltage Reference ....................................... 21 Functional Block Diagram .............................................................. 1 Clock Input Considerations...................................................... 22 General Description ......................................................................... 1 Power Dissipation and Power-Down Mode ........................... 23 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 23 Revision History ............................................................................... 2 Timing ......................................................................................... 24 Specifications..................................................................................... 3 RBIAS........................................................................................... 24 DC Specifications ......................................................................... 3 AD9230 Configuration Using the SPI..................................... 24 AC Specifications.......................................................................... 4 Hardware Interface..................................................................... 25 Digital Specifications ................................................................... 5 Configuration Without the SPI ................................................ 25 Switching Specifications .............................................................. 6 Memory Map .................................................................................. 27 Timing Diagrams.......................................................................... 7 Reading the Memory Map Table.............................................. 27 Absolute Maximum Ratings............................................................ 8 Reserved Locations .................................................................... 27 Thermal Resistance ...................................................................... 8 Default Values ............................................................................. 27 ESD Caution.................................................................................. 8 Logic Levels................................................................................. 27 Pin Configurations and Function Descriptions ........................... 9 Outline Dimensions....................................................................... 30 Equivalent Circuits ......................................................................... 13 Ordering Guide .......................................................................... 30 Typical Performance Characteristics ........................................... 14 REVISION HISTORY 2/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9230 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, T = −40°C, T = +85°C, f = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. MIN MAX IN Table 1. AD9230-170 AD9230-210 AD9230-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.2 4.3 4.5 mV Full −12 12 −12 12 −12 12 mV Gain Error 25°C 0.89 1.0 1.1 mV Full −1.5 3.5 −1.5 3.5 −1.5 3.5 % FS Differential Nonlinearity 25°C ±0.3 ±0.3 ±0.3 LSB (DNL) Full −0.5 0.5 −0.5 0.5 −0.6 0.6 LSB Integral Nonlinearity (INL) 25°C ±0.5 ±0.4 ±0.5 LSB Full −0.75 0.75 −0.75 0.75 −1.0 +1.0 LSB TEMPERATURE DRIFT Offset Error Full μV/°C ±9 ±8 ±7 Gain Error Full 0.019 0.021 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) 2 Differential Input Voltage Range Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents 3 I Full 136 145 154 164 181 194 mA AVDD 3 4 IDRVDD /SDR Mode Full 58 61 59 62 60 63 mA 3 5 IDRVDD /DDR Mode Full 39 40 41 mA 3 Power Dissipation Full mW 4 SDR Mode Full 349 371 383 407 434 463 mW 5 DDR Mode Full 315 349 400 mW 1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 I and I are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9230. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 32 AD9230 1 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 2. AD9230-170 AD9230-210 AD9230-250 2 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SNR fIN = 10 MHz 25°C 63.8 64.6 63.7 64.5 63.3 64.1 dB Full 63.5 63.4 62.5 dB f = 70 MHz 25°C 63.5 64.3 63.3 64.2 63.0 63.9 dB IN Full 63.3 63.1 62.3 dB 3 fIN = 170 MHz 25°C 63.5 63.4 63.3 dB fIN = 225 MHz 25°C 63.0 61.5 63.3 dB SINAD fIN = 10 MHz 25°C 63.7 64.5 63.6 64.4 63.3 64.0 dB Full 63.4 63.4 62.4 dB f = 70 MHz 25°C 63.3 64.1 63.2 64.0 62.9 63.7 dB IN Full 63.1 63.0 62.2 dB 3 f = 170 MHz 25°C 63.3 63.1 63.0 dB IN fIN = 225 MHz 25°C 61.8 61.1 62.8 dB EFFECTIVE NUMBER OF BITS (ENOB) f = 10 MHz 25°C 10.6 10.6 10.5 Bits IN fIN = 70 MHz 25°C 10.5 10.5 10.4 Bits 3 fIN = 170 MHz 25°C 10.4 10.4 10.3 Bits fIN = 225 MHz 25°C 10.1 10.0 10.3 Bits WORST HARMONIC (Second or Third) fIN = 10 MHz 25°C −82 −78 −86 −80 −84 −79 dBc Full −78 −78 −76 dBc f = 70 MHz 25°C −78 −76 −80 −77 −79 −76 dBc IN Full −75 −75 −75 dBc 3 fIN = 170 MHz 25°C −78 −79 −78 dBc fIN = 225 MHz 25°C −68 −70 −75 dBc WORST OTHER (SFDR Excluding Second and Third) fIN = 10 MHz 25°C −89 −84 −89 −84 −84 −79 dBc Full −83 −83 −76 dBc f = 70 MHz 25°C −89 −83 −86 −81 −83 −79 dBc IN Full −83 −81 −75 dBc 3 f = 170 MHz 25°C −89 −79 −83 dBc IN fIN = 225 MHz 25°C −80 −79 −80 dBc TWO-TONE IMD 140.2 MHz/141.3 MHz @ −7 dBFS 25°C 73 75 78 dBc 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 67 73 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 3 140 MHz for the AD9230-170 speed grade, 170 MHz for the AD9230-210 and AD9230-250 speed grades. Rev. 0 | Page 4 of 32 AD9230 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 3. AD9230-170 AD9230-210 AD9230-250 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − AVDD + AVDD − AVDD + AVDD − AVDD + V 0.3 1.6 0.3 1.6 0.3 1.6 Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (V) Full 0 0.8 0 0.8 0 0.8 V IL High Level Input Current (I) Full −10 +10 −10 +10 −10 +10 μA IH Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 μA Input Resistance Full 16 20 24 16 20 24 16 20 24 kΩ (Differential) Input Capacitance Full 4 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × 0.8 × 0.8 × V VDD VDD VDD Logic 0 Voltage Full 0.2 × 0.2 × 0.2 × V AVDD AVDD AVDD Logic 1 Input Current (SDIO) Full 0 0 0 μA Logic 0 Input Current (SDIO) Full −60 −60 −60 μA Logic 1 Input Current Full 55 55 50 μA (SCLK, PDWN, CSB, RESET) Logic 0 Input Current Full 0 0 0 μA (SCLK, PDWN, CSB, RESET) Input Capacitance 25°C 4 4 4 pF 2 LOGIC OUTPUTS VOD Differential Output Voltage Full 247 454 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 LVDS R = 100 Ω. TERMINATION Rev. 0 | Page 5 of 32 AD9230 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 4. AD9230-170 AD9230-210 AD9230-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 170 210 250 MSPS Minimum Conversion Rate Full 40 40 40 MSPS CLK+ Pulse Width High (t ) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns CH CLK+ Pulse Width Low (t ) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns CL 1 Output (LVDS − SDR Mode) Data Propagation Delay (tPD) Full 3.0 3.0 3.0 ns Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns Fall Time (t ) (20% to 80%) 25°C 0.2 0.2 0.2 ns F DCO Propagation Delay (t ) Full 3.9 3.9 3.9 ns CPD Data to DCO Skew (tSKEW) Full −0.3 0.1 0.5 −0.3 0.1 0.5 −0.3 0.1 0.5 ns Latency Full 7 7 7 Cycles 2 Output (LVDS − DDR Mode) Data Propagation Delay (t ) Full 3.8 3.8 3.8 ns PD Rise Time (t ) (20% to 80%) 25°C 0.2 0.2 0.2 ns R Fall Time (t ) (20% to 80%) 25°C 0.2 0.2 0.2 ns F DCO Propagation Delay (tCPD) Full 3.9 3.9 3.9 ns Data to DCO Skew (tSKEW) Full −0.5 0.1 0.3 −0.5 0.1 0.3 −0.5 0.1 0.3 ns Latency Full 7 7 7 Cycles Aperture Uncertainty (Jitter, t ) 25°C 0.2 0.2 ps rms J 1 See Figure 2. 2 See Figure 3. Rev. 0 | Page 6 of 32 AD9230 TIMING DIAGRAMS N – 1 t N + 4 A N + 5 N N + 3 VIN N + 1 N + 2 t t 1/f CH CL S CLK+ CLK– t CPD DCO+ DCO– t SKEW t PD DX+ N – 7 N – 6 N – 5 N – 4 N – 3 DX– Figure 2. Single Data Rate Mode N – 1 t N + 4 A N + 5 N N + 3 VIN N + 1 N + 2 t t 1/f CH CL S CLK+ CLK– t CPD DCO+ DCO– t SKEW t PD D0/D6+ D6 D0 D6 D0 D6 D0 D6 D0 D6 D0 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 N – 5 N – 4 N – 4 N – 3 D0/D6– D5/D11+ D11 D5 D11 D5 D11 D5 D11 D5 D11 D5 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 N – 5 N – 4 N – 4 N – 3 D5/D11– 6 MSBs 6 LSBs Figure 3. Double Data Rate Mode Rev. 0 | Page 7 of 32 06002-003 06002-002 AD9230 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any ELECTRICAL other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D13+/D13− −0.3 V to DRVDD + 0.3 V THERMAL RESISTANCE to DRGND The exposed paddle must be soldered to the ground plane for DCO to DRGND −0.3 V to DRVDD + 0.3 V the LFCSP package. Soldering the exposed paddle to the OR to DGND −0.3 V to DRVDD + 0.3 V customer board increases the reliability of the solder joints, CLK+ to AGND −0.3 V to +3.9 V maximizing the thermal capability of the package. CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V Table 6. VIN− to AGND −0.3 V to AVDD + 0.2 V Package Type θJA θJC Unit SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V 56-Lead LFCSP (CP-48-3) 30.4 2.9 °C/W PDWN to AGND −0.3 V to +3.9 V Typical θJA and θJC are specified for a 4-layer board in still air. CSB to AGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In SCLK/DFS to AGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from ENVIRONMENTAL metal traces, and through holes, ground, and power planes Storage Temperature Range −65°C to +125°C reduces the θ . JA Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering 10 sec) ESD CAUTION Junction Temperature 150°C Rev. 0 | Page 8 of 32 AD9230 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D3– 1 PIN 1 42 AVDD INDICATOR D3+ 2 41 AVDD D4– 3 40 CML D4+ 4 39 AVDD D5– 5 38 AVDD D5+ 6 37 AVDD AD9230 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) D6– 9 34 AVDD D6+ 10 33 AVDD D7– 11 32 AVDD D7+ 12 31 RBIAS PIN 0 (EXPOSED PADDLE) = AGND D8– 13 30 AVDD D8+ 14 29 PWDN Figure 4. Single Data Rate Mode Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. Mnemonic Description 30, 32 to 34, 37 to 39, AVDD 1.8 V Analog Supply. 41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 1 0 AGND Analog Ground. 1 8, 23, 48 DRGND Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS Serial Port Interface (SPI®) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output Bit (LSB). 52 D0+ D0 True Output Bit (LSB). 53 D1− D1 Complement Output Bit. 54 D1+ D1 True Output Bit. 55 D2− D2 Complement Output Bit. 56 D2+ D2 True Output Bit. 1 D3− D3 Complement Output Bit. 2 D3+ D3 True Output Bit. 3 D4− D4 Complement Output Bit. 4 D4+ D4 True Output Bit. Rev. 0 | Page 9 of 32 06002-004 D9– 15 56 D2+ D9+ 16 55 D2– D10– 17 54 D1+ D10+ 18 53 D1– (MSB) D11– 19 52 D0+ (LSB) (MSB) D11+ 20 51 D0– (LSB) 50 DCO+ OR– 21 OR+ 22 49 DCO– DRGND 23 48 DRGND DRVDD 24 47 DRVDD SDIO/DCS 25 46 AVDD SCLK/DFS 26 45 CLK– CSB 27 44 CLK+ ESET 43 AVDD R 28 AD9230 Pin No. Mnemonic Description 5 D5− D5 Complement Output Bit. 6 D5+ D5 True Output Bit. 9 D6− D6 Complement Output Bit. 10 D6+ D6 True Output Bit. 11 D7− D7 Complement Output Bit. 12 D7+ D7 True Output Bit. 13 D8− D8 Complement Output Bit. 14 D8+ D8 True Output Bit. 15 D9− D9 Complement Output Bit. 16 D9+ D9 True Output Bit. 17 D10− D10 Complement Output Bit. 18 D10+ D10 True Output Bit. 19 D11− D11 Complement Output Bit (MSB). 20 D11+ D11 True Output Bit (MSB). 21 OR− Overrange Complement Output Bit. 22 OR+ Overrange True Output Bit. 1 AGND and DRGND should be tied to a common quiet ground plane. Rev. 0 | Page 10 of 32 AD9230 D3/D9– 1 PIN 1 42 AVDD INDICATOR D3/D9+ 2 41 AVDD D4/D10– 3 40 CML D4/D10+ 4 39 AVDD (MSB) D5/D11– 5 38 AVDD (MSB) D5/D11+ 6 37 AVDD AD9230 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) OR– 9 34 AVDD OR+ 10 33 AVDD DNC 11 32 AVDD DNC 12 31 RBIAS PIN 0 (EXPOSED PADDLE) = AGND DNC 13 30 AVDD DNC 14 29 PWDN DNC = DO NOT CONNECT Figure 5. Double Data Rate Table 8. Double Data Rate Mode Pin Function Descriptions Pin No. Mnemonic Description 30, 32 to 34, 37 to 39, AVDD 1.8 V Analog Supply. 41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 1 0 AGND Analog Ground. 1 8, 23, 48 DRGND Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0/D6− D0/D6 Complement Output Bit (LSB). 52 D0/D6+ D0/D6 True Output Bit (LSB). 53 D1/D7− D1/D7 Complement Output Bit. 54 D1/D7+ D1/D7 True Output Bit. 55 D2/D8− D2/D8 Complement Output Bit. 56 D2/D8+ D2/D8 True Output Bit. 1 D3/D9− D3/D9 Complement Output Bit. 2 D3/D9+ D3/D9 True Output Bit. 3 D4/D10− D4/D10 Complement Output Bit. 4 D4/D10+ D4/D10 True Output Bit. 5 D5/D11− D5/D11 Complement Output Bit (MSB). 6 D5/D11+ D5/D11 True Output Bit (MSB). Rev. 0 | Page 11 of 32 06002-005 DNC 15 56 D2/D8+ DNC 16 55 D2/D8– DNC 17 54 D1/D7+ 18 DNC 53 D1/D7– DNC 19 52 D0/D6+ (LSB) DNC 20 51 D0/D6– (LSB) DNC/(OR–) 21 50 DCO+ DNC/(OR+) 22 49 DCO– DRGND 23 48 DRGND DRVDD 24 47 DRVDD SDIO/DCS 25 46 AVDD SCLK/DFS 26 45 CLK– CSB 27 44 CLK+ RESET 28 43 AVDD AD9230 Pin No. Mnemonic Description 9 OR− D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) 10 OR+ D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) 11 to 20 DNC Do Not Connect. 21 DNC/(OR−) Do Not Connect. (This pin can be reconfigured as the Overrange Complement Output Bit through the serial port register.) 22 DNC/(OR+) Do Not Connect. (This pin can be reconfigured as the Overrange True Output Bit through the serial port register.) 1 AGND and DRGND should be tied to a common quiet ground plane. Rev. 0 | Page 12 of 32 AD9230 EQUIVALENT CIRCUITS AVDD AVDD 26kΩ 1kΩ CSB 1.2V 10kΩ 10kΩ CLK+ CLK– Figure 6. Clock Inputs Figure 9. Equivalent CSB Input Circuit AVDD DRVDD AVDD VIN+ BUF 2kΩ V+ V– V CML BUF DATAOUT– DATAOUT+ ~1.4V AVDD 2kΩ V– V+ VIN– BUF Figure 7. Analog Inputs (VCML = ~1.4 V) Figure 10. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) 1kΩ DRVDD SCLK/DFS RESET 30kΩ PDWN 1kΩ SDIO/DCS Figure 8. Equivalent SCLK/DFS, RESET, PDWN Input Circuit Figure 11. Equivalent SDIO/DCS Input Circuit Rev. 0 | Page 13 of 32 06002-008 06002-007 06002-006 06002-010 06002-009 06002-011 AD9230 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless otherwise noted. 0 40000 170MSPS INPUT REFERRED NOISE: 0.72 LSBs 10.3MHz @ –1.0dBFS 35000 SNR: 64.6dB –20 ENOB: 10.6 BITS SFDR: 82dBc 30000 –40 25000 –60 20000 –80 15000 –100 10000 –120 5000 –140 0 08 10 20 30 40 50 60 700 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE FREQUENCY (MHz) BIN Figure 12. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 10.3 MHz Figure 15. AD9230-170 Grounded Input Histogram; 170 MSPS 0 85 170MSPS 70.3MHz @ –1.0dBFS SNR: 64.3dB –20 80 ENOB: 10.5 BITS SFDR (dBc) +25°C SFDR: 78dBc –40 75 SFDR (dBc) –40°C –60 70 SFDR (dBc) +85°C –80 65 –100 60 SNR (dB) +85°C SNR (dB) +25°C SNR (dB) –40°C –120 55 –140 50 08 10 20 30 40 50 60 700 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 13. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 70.3 MHz Figure 16. AD9230-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 170 MSPS 0 100 170MSPS SFDR (dBFS) 140.3MHz @ –1.0dBFS 90 SNR: 63.5dB –20 ENOB: 10.2 BITS 80 SFDR: 78dBc SNR (dBFS) –40 70 60 –60 50 SFDR (dBc) –80 40 30 –100 20 SNR (dB) –120 10 –140 0 08 10 20 30 40 50 60 700 90 80 70 60 50 40 30 20 10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 14. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz Figure 17. AD9230-170 SNR/SFDR vs. Input Amplitude; 140.3 MHz Rev. 0 | Page 14 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06002-014 06002-134 06002-133 SNR/SFDR (dB) SNR/SFDR (dB) NUMBER OF HITS 06002-108 06002-106 06002-109 AD9230 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 –0.2 –0.1 –0.4 –0.2 –0.6 –0.3 –0.8 –0.4 –1.0 –0.5 –1 1023 2047 3071 4095 –1 1023 2047 3071 4095 OUTPUT CODE OUTPUT CODE Figure 18. AD9230-170 INL; 170 MSPS Figure 21. AD9230-170 DNL; 170 MSPS 0 120 IMD3 (dBFS) –20 100 –40 80 SFDR (dBFS) –60 60 –80 40 –100 SFDR (dBc) 20 –120 –140 0 08 10 20 30 40 50 60 700 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) AMPLITUDE (dBFS) Figure 19. AD9230-170 64k Point, Two-Tone FFT; 170 MSPS, Figure 22. AD9230-170 Two-Tone SFDR vs. Input Amplitude; 170 MSPS, 140.1 MHz, 141.1 MHz 140.1 MHz, 141.1 MHz 140 380 IAVDD 130 370 120 360 110 350 100 340 90 TOTAL POWER 330 80 320 70 310 60 IDVDD 50 300 40 60 80 100 120 140 160 180 SAMPLE RATE (MHz) Figure 20. AD9230-170 Power Supply Current vs. Sample Rate Rev. 0 | Page 15 of 32 CURRENT (mA) INL (LSBs) AMPLITUDE (dB) 06002-104 06002-018 POWER (mW) 06002-107 SFDR (dB) DNL (LSBs) 06002-111 06002-021 AD9230 0 40000 210MSPS INPUT REFERRED NOISE: 0.70 LSBs 10.3MHz @ –1.0dBFS SNR: 64.5dB 35000 –20 ENOB: 10.5 BITS SFDR: 79dBc 30000 –40 25000 –60 20000 –80 15000 –100 10000 –120 5000 –140 0 0 20 40 60 80 100 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE FREQUENCY (MHz) BIN Figure 23. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 10.3 MHz Figure 26. AD9230-210 Grounded Input Histogram; 210 MSPS 0 90 210MSPS 70.3MHz @ –1.0dBFS SNR: 63.9dB 85 –20 ENOB: 10.4 BITS SFDR (dBc) +25°C SFDR: 80dBc 80 –40 SFDR (dBc) –40°C 75 –60 SFDR (dBc) +85°C 70 –80 65 –100 60 SNR (dB) +25°C –120 55 SNR (dB) +85°C SNR (dB) –40°C –140 50 0 20 40 60 80 100 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 24. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 70.3 MHz Figure 27. AD9230-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 210 MSPS 0 100 210MSPS SFDR (dBFS) 170.3MHz @ –1.0dBFS 90 SNR: 631.7dB –20 ENOB: 9.9 BITS 80 SFDR: 67dBc –40 SNR (dBFS) 70 60 –60 SFDR (dBc) 50 –80 40 30 –100 SNR (dB) 20 –120 10 –140 0 0 20 40 60 80 100 90 80 70 60 50 40 30 20 10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 25. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 170.3 MHz Figure 28. AD9230-210 SNR/SFDR vs. Input Amplitude; 210 MSPS, 170.3 MHz Rev. 0 | Page 16 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06002-024 06002-024 06002-023 SNR/SFDR (dB) SNR/SFDR (dB) NUMBER OF HITS 06002-117 06002-115 06002-118 AD9230 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 –0.2 –0.1 –0.4 –0.2 –0.6 –0.3 –0.8 –0.4 –1.0 –0.5 –1 1023 2047 3071 4095 –1 1023 2047 3071 4095 OUTPUT CODE OUTPUT CODE Figure 29. AD9230-210 INL; 210 MSPS Figure 32. AD9230-210 DNL; 210 MSPS 0 120 IMD3 (dBFS) –20 100 –40 80 SFDR (dBFS) –60 60 –80 40 –100 SFDR (dBc) 20 –120 –140 0 0 20 40 60 80 100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) AMPLITUDE (dBFS) Figure 30. AD9230-210 64 Point, Two-Tone FFT; 210 MSPS, Figure 33. AD9230-210 Two-Tone SFDR vs. Input Amplitude; 210 MSPS, 170.1 MHz, 171.1 MHz 170.1 MHz, 171.1 MHz 170 400 390 150 IAVDD 380 130 370 TOTAL POWER 110 360 350 90 340 70 330 IDRVDD 50 320 40 90 140 190 240 SAMPLE RATE (MSPS) Figure 31. AD9230-210 Power Supply Current vs. Sample Rate Rev. 0 | Page 17 of 32 CURRENT (mA) INL (LSBs) AMPLITUDE (dB) 06002-112 06002-029 POWER (mW) 06002-116 SFDR (dB) DNL (LSBs) 06002-111 06002-032 AD9230 0 40000 250MSPS INPUT REFERRED NOISE: 0.71 LSBs 10.3MHz @ –1.0dBFS 35000 SNR: 64.1dB –20 ENOB: 10.5 BITS SFDR: 84dBc 30000 –40 25000 –60 20000 –80 15000 –100 10000 –120 5000 –140 0 0 20 40 60 80 100 120 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 MORE FREQUENCY (MHz) BIN Figure 34. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz Figure 37. AD9230-250 Grounded Input Histogram; 250 MSPS 0 90 250MSPS 70.3MHz @ –1.0dBFS 85 SNR: 63.9dB –20 ENOB: 10.5 BITS SFDR (dBc) +25°C SFDR: 79dBc 80 –40 SFDR (dBc) –40°C 75 –60 SFDR (dBc) +85°C 70 –80 65 –100 60 SNR (dB) +25°C –120 55 SNR (dB) +85°C SNR (dB) –40°C –140 50 0 20 40 60 80 100 120 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 35. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz Figure 38. AD9230-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 250 MSPS 0 100 250MSPS SFDR (dBFS) 170.3MHz @ –1.0dBFS 90 SNR: 63.3dB –20 ENOB: 10.5 BITS 80 SFDR: 78dBc –40 SNR (dBFS) 70 60 –60 50 SFDR (dBc) –80 40 30 –100 SNR (dBc) 20 –120 10 –140 0 0 20 40 60 80 100 120 100 90 80 70 60 50 40 30 20 10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 36. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz Figure 39. AD9230-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz Rev. 0 | Page 18 of 32 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 06002-125 06002-124 06002-123 SNR/SFDR (dB) SNR/SFDR (dB) NUMBER OF HITS 06002-128 06002-126 06002-118 AD9230 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 –0.2 –0.1 –0.4 –0.2 –0.6 –0.3 –0.8 –0.4 –1.0 –0.5 –1 1023 2047 3071 4095 –1 1023 2047 3071 4095 OUTPUT CODE OUTPUT CODE Figure 40. AD9230-250 INL; 250 MSPS Figure 43. AD9230-250 DNL; 250 MSPS 0 120 IMD3 (dBFS) –20 100 SFDR (dBFS) –40 80 –60 60 –80 SFDR (dBc) 40 –100 20 –120 –140 0 08 10 20 30 40 50 60 700 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 41. AD9230-250 64k Point, Two-Tone FFT; 250 MSPS, Figure 44. AD9230-250 Two-Tone SFDR vs. Input Amplitude; 250 MSPS, 170.1 MHz, 171.1 MHz 170.1 MHz, 171.1 MHz 210 480 0 460 190 IAVDD –20 440 170 –40 420 150 TOTAL POWER 400 –60 130 380 110 360 –80 90 340 –100 70 320 IDRVDD 50 300 –120 50 100 150 200 250 300 0 30.72 61.44 92.16 122.88 SAMPLE RATE (MSPS) FREQUENCY (MHz) Figure 42. AD9230 Power Supply Current vs. Sample Rate Figure 45. AD9230-250 64k Point FFT; Four W-CDMA Carriers, IF = 184 MHz, 245.6 MSPS Rev. 0 | Page 19 of 32 CURRENT (mA) INL (LSBs) AMPLITUDE (dB) 06002-121 06002-135 POWER (mW) 06002-127 AMPLITUDE (dBFS) SFDR (dB) DNL (LSBs) 06002-120 06002-043 06002-101 AD9230 85 90 SFDR (dBFS) w/ DCS ON SFDR (dBFS) w/ DCS OFF 80 80 SFDR (dBc) 70 75 70 60 SNR (dBFS) w/ DCS ON 50 65 SNR (dB) SNR (dBFS) w/ DCS OFF 60 40 30 55 50 20 1.01.11.21.31.41.51.6 1.7 1.8 0 102030 405060708090 100 V (V) INPUT CLOCK DUTY CYCLE (% CLK+ HIGH) CM Figure 49. SNR/SFDR vs. Sample Clock Duty Cycle; Figure 46. SNR/SFDR vs. Common-Mode Voltage; 250 MSPS, 170.3 MHz @ −1 dBFS 250 MSPS, 70.3 MHz @ −1 dBFS 2.5 80 SFDR (dBc) 75 2.0 AD9230-250 70 1.5 65 AD9230-210 SNR (dB) 1.0 60 AD9230-170 55 0.5 50 0 45 –0.5 40 –60 –40 –20 0 20 40 60 80 100 120 50 100 150 200 250 300 TEMPERATURE (°C) SAMPLE RATE (MSPS) Figure 50. Gain vs. Temperature Figure 47. SNR/SFDR vs. Sample Rate; 250 MSPS, 170.3 MHz @ −1 dBFS 6.0 85 5.5 SFDR (dBFS) AD9230-250 80 5.0 4.5 75 AD9230-210 4.0 AD9230-170 70 3.5 3.0 65 2.5 SNR (dBFS) 2.0 60 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 TEMPERATURE (°C) ANALOG INPUT RANGE (MHz) Figure 51. Offset vs. Temperature Figure 48. SNR/SFDR vs. Analog Input Range; 250 MSPS, 170.3 MHz @ −1 dBFS Rev. 0 | Page 20 of 32 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 06002-122 06002-131 06002-130 GAIN (%FS) SNR/SFDR (dB) OFFSET (mV) 06002-103 06002-102 06002-100 AD9230 THEORY OF OPERATION The AD9230 architecture consists of a front-end sample and 1V p-p 49.9Ω hold amplifier (SHA) followed by a pipelined switched capacitor 499Ω AVDD ADC. The quantized outputs from each stage are combined into 33Ω 499Ω VIN+ a final 12-bit result in the digital correction logic. The pipelined 20pF AD8138 AD9230 architecture permits the first stage to operate on a new input 523Ω 0.1µF sample, while the remaining stages operate on preceding VIN– 33Ω CML samples. Sampling occurs on the rising edge of the clock. 499Ω Each stage of the pipeline, excluding the last, consists of a low Figure 52. Differential Input Configuration Using the AD8138 resolution flash ADC connected to a switched capacitor DAC At input frequencies in the second Nyquist zone and above, the and interstage residue amplifier (MDAC). The residue amplifier performance of most amplifiers may not be adequate to achieve magnifies the difference between the reconstructed DAC output the true performance of the AD9230. This is especially true in and the flash input for the next stage in the pipeline. One bit of IF undersampling applications where frequencies in the 70 MHz redundancy is used in each stage to facilitate digital correction to 100 MHz range are being sampled. For these applications, of flash errors. The last stage simply consists of a flash ADC. differential transformer coupling is the recommended input The input stage contains a differential SHA that can be ac- or configuration. The signal characteristics must be considered dc-coupled in differential or single-ended mode. The output- when selecting a transformer. Most RF transformers saturate at staging block aligns the data, carries out the error correction, frequencies below a few MHz, and excessive signal power can and passes the data to the output buffers. The output buffers are also cause core saturation, which leads to distortion. powered from a separate supply, allowing adjustment of the In any configuration, the value of the shunt capacitor, C, is output voltage swing. During power-down, the output buffers dependent on the input frequency and may need to be reduced go into a high impedance state. or removed. ANALOG INPUT AND VOLTAGE REFERENCE 15Ω The analog input to the AD9230 is a differential buffer. For best VIN+ dynamic performance, the source impedances driving VIN+ 1.25V p-p 50Ω 2pF AD9230 and VIN− should be matched such that common-mode settling VIN– errors are symmetrical. The analog input is optimized to 15Ω provide superior wideband performance and requires that the 0.1µF analog inputs be driven differentially. SNR and SINAD Figure 53. Differential Transformer—Coupled Configuration performance degrades significantly if the analog input is driven with a single-ended signal. As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential A wideband transformer, such as Mini-Circuits® ADT1-1WT, driver can be used (see Figure 54). can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog V CC inputs are self-biased by an on-chip resistor divider to a nominal 1.3 V. 0.1µF 0.1µF 0Ω 16 8, 13 An internal differential voltage reference creates positive and 1 0.1µF ANALOG INPUT 11 R negative reference voltages that define the 1.25 V p-p fixed span 2 VIN+ 200Ω of the ADC core. This internal voltage reference can be adjusted C R R AD8352 C D D G AD9230 200Ω by means of SPI control. See the AD9230 Configuration Using 3 0.1µF 10 R CML VIN– 4 the SPI section for more details. ANALOG INPUT 5 14 0Ω 0.1µF 0.1µF Differential Input Configurations 0.1µF Optimum performance is achieved while driving the AD9230 Figure 54. Differential Input Configuration Using the AD8352 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Rev. 0 | Page 21 of 32 06002-056 06002-055 06002-059 AD9230 In some applications, it is acceptable to drive the sample clock CLOCK INPUT CONSIDERATIONS inputs with a single-ended CMOS signal. In such applications, For optimum performance, the AD9230 sample clock inputs CLK+ should be directly driven from a CMOS gate, and the (CLK+ and CLK−) should be clocked with a differential signal. CLK− pin should be bypassed to ground with a 0.1 μF capacitor This signal is typically ac-coupled into the CLK+ pin and CLK− in parallel with a 39 kΩ resistor (see Figure 58). Although the pin via a transformer or capacitors. These pins are biased CLK+ input circuit supply is AVDD (1.8 V), this input is internally and require no additional bias. designed to withstand input voltages up to 3.3 V, making the Figure 55 shows one preferred method for clocking the AD9230. selection of the drive logic voltage very flexible. The low jitter clock source is converted from single-ended to AD9510/AD9511/ differential using an RF transformer. The back-to-back Schottky AD9512/AD9513/ AD9514/AD9515 0.1µF diodes across the secondary transformer limit clock excursions CLOCK CLK INPUT OPTIONAL into the AD9230 to approximately 0.8 V p-p differential. This 0.1µF 1 100Ω 50Ω CLK+ helps prevent the large voltage swings of the clock from feeding CMOS DRIVER ADC through to other portions of the AD9230 and preserves the fast CLK AD9230 rise and fall times of the signal, which are critical to low jitter 0.1µF CLK– performance. 0.1µF 39kΩ MINI-CIRCUITS 1 50Ω RESISTOR IS OPTIONAL. ADT1–1WT, 1:1Z 0.1µF 0.1µF Figure 58. Single-Ended 1.8 V CMOS Sample Clock XFMR CLOCK CLK+ INPUT 100Ω ADC 50Ω 0.1µF AD9230 AD9510/AD9511/ CLK– AD9512/AD9513/ 0.1µF SCHOTTKY AD9514/AD9515 0.1µF DIODES: CLOCK HSM2812 CLK INPUT OPTIONAL 0.1µF 1 50Ω 100Ω Figure 55. Transformer-Coupled Differential Clock CLK+ CMOS DRIVER ADC If a low jitter clock is available, another option is to ac couple a CLK AD9230 0.1µF 0.1µF differential PECL signal to the sample clock input pins, as CLK– shown in Figure 56. The AD9510/AD9511/AD9512/AD9513/ AD9514/AD9515 family of clock drivers offers excellent jitter 1 50Ω RESISTOR IS OPTIONAL. performance. Figure 59. Single-Ended 3.3 V CMOS Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 Clock Duty Cycle Considerations 0.1µF 0.1µF CLOCK Typical high speed ADCs use both clock edges to generate a CLK CLK+ INPUT variety of internal timing signals. As a result, these ADCs may ADC 100Ω PECL DRIVER AD9230 0.1µF be sensitive to clock duty cycle. Commonly, a 5% tolerance is 0.1µF CLOCK CLK– CLK INPUT required on the clock duty cycle to maintain dynamic performance 1 1 240Ω 240Ω 50Ω 50Ω characteristics. The AD9230 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock 1 50Ω RESISTORS ARE OPTIONAL. signal with a nominal 50% duty cycle. This allows a wide range Figure 56. Differential PECL Sample Clock of clock input duty cycles without affecting the performance of the AD9230. When the DCS is on, noise and distortion perfor- AD9510/AD9511/ mance are nearly flat for a wide range of duty cycles. However, AD9512/AD9513/ AD9514/AD9515 some applications may require the DCS function to be off. If so, 0.1µF 0.1µF CLOCK keep in mind that the dynamic range performance can be affected CLK CLK+ INPUT ADC when operated in this mode. See the AD9230 Configuration 100Ω LVDS DRIVER AD9230 0.1µF 0.1µF Using the SPI section for more details on using this feature. CLOCK CLK– CLK INPUT The duty cycle stabilizer uses a delay-locked loop (DLL) to 1 1 50Ω 50Ω create the nonsampling edge. As a result, any changes to the 1 50Ω RESISTORS ARE OPTIONAL. sampling frequency require approximately eight clock cycles Figure 57. Differential LVDS Sample Clock to allow the DLL to acquire and lock to the new rate. Rev. 0 | Page 22 of 32 06002-060 06002-070 06002-061 06002-071 06002-072 AD9230 Clock Jitter Considerations DIGITAL OUTPUTS High speed, high resolution ADCs are sensitive to the quality of the Digital Outputs and Timing clock input. The degradation in SNR at a given input frequency The AD9230 differential outputs conform to the ANSI-644 (fA) due only to aperture jitter (tJ) can be calculated by LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 SNR Degradation = 20 × log10[1/2 × π × fA × tJ] standard using the SPI. This LVDS standard can further reduce In this equation, the rms aperture jitter represents the root mean the overall power dissipation of the device, which reduces the square of all jitter sources, including the clock input, analog input power by ~39 mW. See the Memory Map section for more signal, and ADC aperture jitter specifications. IF undersampling information. The LVDS driver current is derived on-chip and applications are particularly sensitive to jitter (see Figure 60). sets the output current at each output equal to a nominal The clock input should be treated as an analog signal in cases 3.5 mA. A 100 Ω differential termination resistor placed at the where aperture jitter may affect the dynamic range of the AD9230. LVDS receiver inputs results in a nominal 350 mV swing at the Power supplies for clock drivers should be separated from the receiver. ADC output driver supplies to avoid modulating the clock signal The AD9230 LVDS outputs facilitate interfacing with LVDS with digital noise. Low jitter, crystal-controlled oscillators make receivers in custom ASICs and FPGAs that have LVDS capability the best clock sources. If the clock is generated from another for superior switching performance in noisy environments. type of source (by gating, dividing, or other methods), it should Single point-to-point net topologies are recommended with a be retimed by the original clock at the last step. 100 Ω termination resistor placed as close to the receiver as Refer to the AN-501 Application Note and the AN-756 possible. No far-end receiver termination and poor differential Application Note for more in-depth information about jitter trace routing may result in timing errors. It is recommended performance as it relates to ADCs (visit www.analog.com). that the trace length is no longer than 24 inches and that the 130 differential output traces are kept close together and at equal RMS CLOCK JITTER REQUIREMENT 120 lengths. 110 An example of the LVDS output using the ANSI standard (default) 16 BITS 100 data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is 90 14 BITS shown in Figure 61. Figure 62 shows an example of when the 80 12 BITS trace lengths exceed 24 inches on regular FR-4 material. Notice 70 that the TIE jitter histogram reflects the decrease of the data eye 10 BITS 60 opening as the edge deviates from the ideal position. It is up to 0.125ps 8 BITS 50 0.25ps the user to determine if the waveforms meet the timing budget 0.5ps of the design when the trace lengths exceed 24 inches. 1.0ps 40 2.0ps 14 30 1 10 100 1000 500 ANALOG INPUT FREQUENCY (MHz) 12 400 Figure 60. Ideal SNR vs. Input Frequency and Jitter 300 10 200 POWER DISSIPATION AND POWER-DOWN MODE 100 8 As shown in Figure 42, the power dissipated by the AD9230 is 0 proportional to its sample rate. The digital power dissipation 6 –100 does not vary much because it is determined primarily by the –200 DRVDD supply and bias current of the LVDS output drivers. 4 –300 By asserting PDWN (Pin 29) high, the AD9230 is placed in –400 2 standby mode or full power-down mode, as determined by the –500 contents of Serial Port Register 08. Reasserting the PDWN pin 0 –3 –2 –1 0 1 2 3 –40 –20 0 20 40 low returns the AD9230 into its normal operational mode. TIME (ns) TIME (ps) An additional standby mode is supported by means of varying Figure 61. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4, AD9230-250 the clock input. When the clock rate falls below 20 MHz, the AD9230 assumes a standby state. In this case, the biasing network and internal reference remain on, but digital circuitry is powered down. Upon reactivating the clock, the AD9230 resumes normal operation after allowing for the pipeline latency. Rev. 0 | Page 23 of 32 SNR (dB) 06002-065 EYE DIAGRAM: VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) AD9230 +FS – 1 LSB 600 12 OR DATA OUTPUTS 1 1111 1111 1111 OR 0 1111 1111 1111 400 10 0 1111 1111 1110 –FS + 1/2 LSB 200 8 0 0000 0000 0001 0 0000 0000 0000 1 0000 0000 0000 0 6 –FS +FS –FS – 1/2 LSB +FS – 1/2 LSB –200 4 Figure 63. OR Relation to Input Voltage and Output Data –400 2 TIMING The AD9230 provides latched data outputs with a pipeline delay –600 0 of seven clock cycles. Data outputs are available one –3 –2 –1 0 1 2 3 –100 0 100 propagation delay (t ) after the rising edge of the clock signal. TIME (ns) TIME (ps) PD Figure 62. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths The length of the output data lines and loads placed on them Greater than 24 Inches on Standard FR-4, AD9230-250 should be minimized to reduce transients within the AD9230. The format of the output data is offset binary by default. An These transients can degrade the converter’s dynamic performance. example of the output coding format can be found in Table 12. The AD9230 also provides data clock output (DCO) intended for If it is desired to change the output data format to twos comple- capturing the data in an external register. The data outputs are valid ment, see the AD9230 Configuration Using the SPI section. on the rising edge of DCO. An output clock signal is provided to assist in capturing data The lowest typical conversion rate of the AD9230 is 40 MSPS. from the AD9230. The DCO is used to clock the output data At clock rates below 1 MSPS, the AD9230 assumes the standby and is equal to the sampling clock (CLK) rate. In single data rate mode. mode (SDR), data is clocked out of the AD9230 and must be RBIAS captured on the rising edge of the DCO. In double data rate The AD9230 requires the user to place a 10 kΩ resistor between mode (DDR), data is clocked out of the AD9230 and must be the RBIAS pin and ground. This resister should have a 1% captured on the rising and falling edges of the DCO See the tolerance and is used to set the master current reference of the timing diagrams shown in Figure 2 and Figure 3 for more ADC core. information. AD9230 CONFIGURATION USING THE SPI Output Data Rate and Pinout Configuration The AD9230 SPI allows the user to configure the converter for The output data of the AD9230 can be configured to drive 12 specific functions or operations through a structured register pairs of LVDS outputs at the same rate as the input clock signal space inside the ADC. This gives the user added flexibility to (single data rate, or SDR, mode), or six pairs of LVDS outputs at customize device operation depending on the application. 2× the rate of the input clock signal (double data rate, or DDR, Addresses are accessed (programmed or readback) serially in mode). SDR is the default mode; the device may be reconfigured one-byte words. Each byte may be further divided down into for DDR by setting Bit 3 in Register 14 (see Table 13). fields, which are documented in the Memory Map section. Out-of-Range (OR) There are three pins that define the serial port interface or SPI An out-of-range condition exists when the analog input voltage to this particular ADC. They are the SPI SCLK/DFS, SPI is beyond the input range of the ADC. OR is a digital output SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used that is updated along with the data output corresponding to the to synchronize the read and write data presented the ADC. The particular sampled input voltage. Thus, OR has the same SDIO/DCS (serial data input/output) is a dual-purpose pin that pipeline latency as the digital data. OR is low when the analog allows data to be sent and read from the internal ADC memory input voltage is within the analog input range and high when map registers. The CSB is an active low control that enables or the analog input voltage exceeds the input range, as shown in disables the read and write cycles (see Table 9). Figure 63. OR remains high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OR with the MSB and its complement, over- range high or underrange low conditions can be detected. Rev. 0 | Page 24 of 32 EYE DIAGRAM: VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) 06002-062 AD9230 HARDWARE INTERFACE Table 9. Serial Port Pins Mnemonic Function The pins described in Table 9 comprise the physical interface SCLK SCLK (Serial Clock) is the serial shift clock in. between the user’s programming device and the serial port of SCLK is used to synchronize serial interface the AD9230. All serial pins are inputs, which is an open-drain reads and writes. output and should be tied to an external pull-up or pull-down SDIO SDIO (Serial Data Input/Output) is a dual-purpose resistor (suggested value of 10 kΩ). pin. The typical role for this pin is an input and output depending on the instruction being sent This interface is flexible enough to be controlled by either and the relative position in the timing frame. PROMS or PIC mirocontrollers as well. This provides the user CSB CSB (Chip Select Bar) is active low controls that with an alternate method to program the ADC other than a SPI gates the read and write cycles. controller. RESET Master Device Reset. When asserted, device assumes default settings. Active low. If the user chooses not to use the SPI interface, some pins serve a dual function and are associated with a specific function when The falling edge of the CSB, in conjunction with the rising edge strapped externally to AVDD or ground during device power of the SCLK, determines the start of the framing. An example of on. The Configuration Without the SPI section describes the the serial timing and its definitions can be found in Figure 64 strappable functions supported on the AD9230. and Table 11. CONFIGURATION WITHOUT THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data then follows the instruction phase and is determined by In applications that do not interface to the SPI control registers, the W0 and W1 bits, which is 1 or more bytes of data. All data is the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately composed of 8-bit words. The first bit of each individual byte of serve as standalone CMOS-compatible control pins. When the serial data indicates whether this is a read or write command. device is powered up, it is assumed that the user intends to use This allows the serial data input/output (SDIO) pin to change the pins as static control lines for the duty cycle stabilizer. In direction from an input to an output. this mode, the SPI CSB chip select should be connected to ground, which disables the serial port interface. Data may be sent in MSB or in LSB first mode. MSB first is default on power-up and can be changed by changing the Table 10. Mode Selection configuration register. For more information about this feature External and others, see Interfacing to High Speed ADCs via SPI at Mnemonic Voltage Configuration www.analog.com. SPI SDIO/DCS AVDD Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SPI SCLK/DFS AVDD Twos complement enabled AGND Offset binary enabled t t t t DS HI CLK H t t S DH t LO CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SDIO DON’T CARE DON’T CARE Figure 64. Serial Port Interface Timing Diagram Rev. 0 | Page 25 of 32 06002-063 AD9230 Table 11. Serial Timing Definitions Parameter Timing (minimum, ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK t 40 Period of the clock CLK t 5 Setup time between CSB and SCLK S t 2 Hold time between CSB and SCLK H tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 1 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 64) t 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK DIS_SDIO rising edge (not shown in Figure 64) Table 12. Output Data Format Gray Code Mode Offset Binary Twos Complement Mode (SPI Accessible) Output Mode Input (V) Condition (V) D11 to D0 D11 to D0 D11 to D0 OR VIN+ − VIN− < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 VIN+ − VIN− = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0 VIN+ − VIN− > 0.62 + 0.5 LSB 1111 1111 1111 1111 1111 1111 0000 0000 0000 1 Rev. 0 | Page 26 of 32 AD9230 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map table has eight address locations. Undefined memory locations should not be written to other The memory map is roughly divided into three sections: chip than their default values suggested in this data sheet. Addresses configuration register map (Address 0x00 to Address 0x02), that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. transfer register map (Address 0xFF), and program register map (Address 0x08 to Address 0x2A). DEFAULT VALUES The Addr. (Hex) column of the memory map indicates the Coming out of reset, critical registers are preloaded with default register address in hexadecimal, and the Default Value (Hex) values. These values are indicated in Table 13. Other registers column shows the default hexadecimal value that is already do not have default values and retain the previous value when written into the register The Bit 7 (MSB) column is the start of exiting reset. the default hexadecimal value given. For example, Hexadecimal LOGIC LEVELS Address 0x09, clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, An explanation of various registers follows: “Bit is set” is Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The synonymous with “bit is set to Logic 1” or “writing Logic 1 for default value enables the duty cycle stabilizer. Overwriting this the bit.” Similarly, “clear a bit” is synonymous with “bit is set to default so that Bit 0 = 0 disables the duty cycle stabilizer. For more Logic 0” or “writing Logic 0 for the bit.” information on this and other functions, consult the Interfacing to High-Speed ADCs via SPI® user manual at www.analog.com. Table 13. Memory Map Register Default Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 00 chip_port_config 0 LSB Soft 1 1 Soft LSB first 0 0x18 The nibbles first reset reset should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. 01 chip_id 8-bit chip ID, Bits[7:0] Read- Default is unique AD9230 = 0x0C only chip ID, different for each device. This is a read- only register. 02 chip_grade 0 0 0 Speed grade: X X X Read- Child ID used to only differentiate 00 = 250 MSPS graded devices. 01 = 210 MSPS 10 = 170 MSPS Transfer Register FF device_update 0 0 0 0 0 0 0 SW 0x00 Synchronously transfer transfers data from the master shift register to the slave. Rev. 0 | Page 27 of 32 AD9230 Def. Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments ADC Functions 08 modes 0 0 PDWN: 0 0 Internal power-down mode: 0x00 Determines various generic 0 = full 000 = normal (power-up, modes of chip (default) default) operation. 1 = 001 = full power-down standby 010 = standby 011 = normal (power-up) Note: External PDWN pin overrides this setting. 09 clock 0 0 0 0 0 0 0 Duty 0x01 cycle stabilizer: 0 = disabled 1 = enabled (default) OD test_io Reset Reset Output test mode: 0x00 When set, the PN23 PN9 gen: test data is 0000 = off (default) gen: 1 = on 0001 = midscale short placed on the 1 = on 0 = off output pins in 0010 = +FS short 0 = off (default) place of normal 0011 = −FS short (default) data. 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) OF ain_config 0 0 0 0 0 Analog CML 0 0x00 input enable: disable: 1 = on 1 = on 0 = off 0 = off (default) (default) 14 output_mode 0 0 Output DDR: Output Data format select: 0x00 0 enable: 1 = invert: 00 = offset binary enabled 1 = on (default) 0 = 0 = 0 = off 01 = twos enable disabled (default) complement (default) (default) 10 = Gray code 1 = disable 15 output_adjust 0 0 LVDS LVDS fine adjust: 0x00 0 course 001 = 3.50 mA adjust: 010 = 3.25 mA 0 = 011 = 3.00 mA 3.5 mA 100 = 2.75 mA (default) 101 = 2.50 mA 1 = 110 = 2.25 mA 2.0 mA 111 = 2.00 mA 16 output_phase Output 0 0 0 0x03 clock polarity 1 = inverted 0 = normal (default) Rev. 0 | Page 28 of 32 AD9230 Def. Addr. Bit 7 Bit 0 Value Default Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 17 flex_output_delay Output Output clock delay: 0 delay 00000 = 0.1 ns enable: 00001 = 0.2 ns 0 = 00010 = 0.3 ns enable … 1 = 11101 = 3.0 ns disable 11110 = 3.1 ns 11111 = 3.2 ns 18 flex_vref Input voltage range setting: 0 10000 = 0.98 V 10001 =1.00 V 10010 = 1.02 V 10011 =1.04 V … 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V … 01110 = 1.48 V 01111 = 1.50 V 2A ovr_config OR OR 00000001 position enable: (DDR 1 = on mode (default) only): 0 = off 0 = Pin 9, Pin 10 1 = Pin 21, Pin 22 Rev. 0 | Page 29 of 32 AD9230 OUTLINE DIMENSIONS 0.30 8.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 56 43 INDICATOR 1 42 PIN 1 INDICATOR TOP 4.45 7.75 EXPOSED VIEW BSC SQ PAD 4.30 SQ (BOTTOM VIEW) 4.15 0.50 14 0.40 29 28 15 0.30 0.30 MIN 6.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY SEATING 0.50 BSC 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 65. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9230BCPZ-170 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2 1 AD9230BCPZ-210 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2 1 AD9230BCPZ-250 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2 1 AD9230-170EBZ LVDS Evaluation Board with AD9230BCPZ-170 1 AD9230-210EBZ LVDS Evaluation Board with AD9230BCPZ-210 1 AD9230-250EBZ LVDS Evaluation Board with AD9230BCPZ-250 1 Z = Pb-free part. Rev. 0 | Page 30 of 32 112805-0 AD9230 NOTES Rev. 0 | Page 31 of 32 AD9230 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06002-0-2/07(0) Rev. 0 | Page 32 of 32