ANALOG DEVICES AD9229

Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter AD9229 FEATURES FUNCTIONAL BLOCK DIAGRAM PDWN DTP DRVDD DRGND Four ADCs in 1 package Serial LVDS digital output data rates AD9229 to 780 Mbps (ANSI-644) VIN+A 12 D+A SERIAL Data and frame clock outputs PIPELINE SHA LVDS VIN–A ADC D–A SNR = 69.5 dB (to Nyquist) Excellent linearity VIN+B 12 D+B SERIAL PIPELINE SHA LVDS VIN–B ADC D–B DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) VIN+C 12 D+C SERIAL PIPELINE SHA LVDS 400 MHz full power analog bandwidth VIN–C ADC D–C Power dissipation VIN+D 12 D+D SERIAL PIPELINE SHA 1,350 mW at 65 MSPS LVDS VIN–D ADC D–D 985 mW at 50 MSPS VREF 1 V p-p to 2 V p-p input voltage range SENSE 3.0 V supply operation FCO+ 0.5V Power-down mode FCO– DATA RATE REFT REF MULTIPLIER Digital test pattern enable for timing alignments SELECT DCO+ REFB DCO– APPLICATIONS AGND LVDSBIAS CLK Digital beam-forming systems for ultrasound Wireless and wired broadband communications Figure 1. Communication test equipment GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital 1. Four ADCs are contained in a small, space-saving package. converter (ADC) with an on-chip sample-and-hold circuit that 2. A data clock out (DCO) is provided, which operates up to is designed for low cost, low power, small size, and ease of use. 390 MHz and supports double-data rate operation (DDR). The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance in applications 3. The outputs of each ADC are serialized LVDS with data where a small package size is critical. rates up to 780 Mbps (12 bits × 65 MSPS). The ADC requires a single 3 V power supply and TTL-/CMOS- 4. The AD9229 operates from a single 3.0 V power supply. compatible sample rate clock for full performance operation. No external reference or driver components are required for 5. Packaged in a Pb-free, 48-lead LFCSP package. many applications. 6. The internal clock duty cycle stabilizer maintains The ADC automatically multiplies the sample rate clock for the performance over a wide range of input clock duty cycles. appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled. Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 04418-001 AD9229 TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 11 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 16 General Description ......................................................................... 1 Theory of Operation ...................................................................... 18 Revision History ............................................................................... 2 Analog Input Considerations ................................................... 18 Specif ica t ions ..................................................................................... 3 Clock Input Considerations ...................................................... 19 AC Specifications .......................................................................... 4 Evaluation Board ............................................................................ 24 Digital Specifications ................................................................... 5 Power Supplies ............................................................................ 24 Switching Specifications .............................................................. 6 Input Signals................................................................................ 24 Timing Diagram ............................................................................... 7 Output Signals ............................................................................ 24 Absolute Maximum Ratings ............................................................ 8 Default Operation and Jumper Selection Settings ................. 25 Explanation of Test Levels ........................................................... 8 Alternate Analog Input Drive Configuration ......................... 25 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 39 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 39 REVISION HISTORY 5/10—Rev. A to Rev. B Change to Item 47 in Table 11 ...................................................... 38 Updated Outline Dimensions ....................................................... 39 Change to Ordering Guide ............................................................ 39 9/05—Rev. 0 to Rev. A Change to Specifications .................................................................. 3 Changes to Differential Input Configurations Section .............. 19 Changes to Exposed Paddle Thermal Heat Slug Recommendations Section ........................................................ 23 Changes to Evaluation Board Section .......................................... 24 Changes to Table 11 ........................................................................ 36 3/05—Revision 0: Initial Version Rev. B | Page 2 of 40 AD9229 SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 1. AD9229-50 AD9229-65 Test Parameter Temperature Level Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Offset Error Full VI ±5 ±25 ±5 ±25 mV Offset Matching Full VI ±5 ±25 ±5 ±25 mV 1 Gain Error Full VI ±0.3 ±2.5 ±0.3 ±2.5 % FS 1 Gain Matching Full VI ±0.2 ±1.5 ±0.2 ±1.5 % FS Differential Nonlinearity (DNL) 25°C V ±0.3 ±0.3 LSB Full VI ±0.3 ±0.6 ±0.3 ±0.7 LSB Integral Nonlinearity (INL) 25°C V ±0.6 ±0.4 LSB Full VI ±0.6 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full V ±2 ±3 ppm/°C 1 Gain Error Full V ±12 ±12 ppm/°C Reference Voltage, VREF = 1 V Full V ±16 ±16 ppm/°C REFERENCE Output Voltage Error, VREF = 1 V Full VI ±10 ±30 ±10 ±30 mV Load Regulation @ 1.0 mA, VREF = 1 V Full V 3 3 mV Output Voltage Error, VREF = 0.5 V Full VI ±8 ±17 ±8 ±17 mV Load Regulation @ 0.5 mA, Full V 0.2 0.2 mV VREF = 0.5 V Input Resistance Full V 7 7 kΩ ANALOG INPUTS Differential Input Voltage Range Full VI 2 2 V p-p VREF = 1 V Full VI 1 1 V p-p Differential Input Voltage Range VREF = 0.5 V Common Mode Voltage Full V 1.5 1.5 V 2 Input Capacitance Full V 7 7 pF Analog Bandwidth, Full Power Full V 400 400 MHz POWER SUPPLY AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V IAVDD Full VI 300 330 420 455 mA DRVDD Full VI 28 31 29 33 mA 3 Power Dissipation Full VI 985 1083 1350 1465 mW Power-Down Dissipation Full V 3 3 mW 4 CROSSTALK Full V –95 –95 dB 1 Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. 4 Typical specification over the first Nyquist zone. Rev. B | Page 3 of 40 AD9229 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. AD9229-50 AD9229-65 Test Parameter Temperature Level Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz Full IV 69.5 70.4 69.0 70.2 dB IN f = 10.3 MHz 25°C V 70.4 70.2 dB IN fIN = 25 MHz Full VI 68.7 69.6 dB fIN = 30 MHz Full VI 68.0 69.5 dB fIN = 70 MHz 25°C V 67.2 67.1 dB SIGNAL-TO-NOISE RATIO (SINAD) fIN = 2.4 MHz Full V 70.0 69.8 dB fIN = 10.3 MHz 25°C V 70.0 69.8 dB fIN = 25 MHz Full VI 68.4 69.4 dB f = 30 MHz Full VI 67.3 69.0 dB IN f = 70 MHz 25°C V 66.8 66.7 dB IN EFFECTIVE NUMBER OF BITS f = 2.4 MHz Full V 11.3 11.3 Bits IN (ENOB) f = 10.3 MHz 25°C V 11.3 11.3 Bits IN fIN = 25 MHz Full VI 11.1 11.2 Bits fIN = 30 MHz Full VI 10.9 11.2 Bits fIN = 70 MHz 25°C V 10.8 10.8 Bits SPURIOUS-FREE DYNAMIC RANGE fIN = 2.4 MHz Full V 85 85 dBc (SFDR) fIN = 10.3 MHz 25°C V 85 85 dBc f = 25 MHz Full VI 76 85 dBc IN f = 30 MHz Full VI 73 85 dBc IN f = 70 MHz 25°C V 78 77 dBc IN WORST HARMONIC f = 2.4 MHz Full V –85 –85 dBc IN (Second or Third) f = 10.3 MHz 25°C V –85 –85 dBc IN fIN = 25 MHz Full VI –85 –76 dBc fIN = 30 MHz Full VI –85 –73 dBc fIN = 70 MHz 25°C V –78 –77 dBc WORST OTHER f = 2.4 MHz Full V –90 –90 dBc IN (Excluding Second or Third) f = 10.3 MHz 25°C V –90 –90 dBc IN f = 25 MHz Full VI –88 –81.7 dBc IN fIN = 30 MHz Full VI –88 –79.7 dBc fIN = 70 MHz 25°C V –85 –83 dBc f = 15 MHz 25°C V –73 –73 dBc TWO-TONE INTERMODULATION IN1 DISTORTION (IMD) AIN1 and AIN2 = –7.0 dBFS fIN2 = 16 MHz f = 69 MHz 25°C V –68.5 –68.5 dBc IN1 f = 70 MHz IN2 Rev. B | Page 4 of 40 AD9229 DIGITAL SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 3. AD9229-50 AD9229-65 Test Parameter Temperature Level Min Typ Max Min Typ Max Unit CLOCK INPUT Logic Compliance TTL/CMOS TTL/CMOS High Level Input Voltage Full IV 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 V High Level Input Current Full VI 0.5 ±10 0.5 ±10 μA Low Level Input Current Full VI 0.5 ±10 0.5 ±10 μA Input Capacitance 25°C V 2 2 pF LOGIC INPUTS (PDWN) Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V High Level Input Current Full IV 0.5 ±10 0.5 ±10 μA Low Level Input Current Full IV 0.5 ±10 0.5 ±10 μA Input Capacitance 25°C V 2 2 pF DIGITAL OUTPUTS (D+, D–) Logic Compliance LVDS LVDS Differential Output Voltage Full VI 260 440 260 440 mV Output Offset Voltage Full VI 1.15 1.25 1.35 1.15 1.25 1.35 V Output Coding Full VI Offset Offset binary binary Rev. B | Page 5 of 40 AD9229 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. AD9229-50 AD9229-65 Test Parameter Temp Level Min Typ Max Min Typ Max Unit CLOCK Maximum Clock Rate Full VI 50 65 MSPS Minimum Clock Rate Full IV 10 10 MSPS Clock Pulse Width High Full VI 8 10 6.2 7.7 ns (t ) EH Clock Pulse Width Low Full VI 8 10 6.2 7.7 ns (t ) EL OUTPUT PARAMETERS Propagation Delay (tPD) Full VI 3.3 6.5 7.9 3.3 6.5 7.9 ns Rise Time (tR) Full V 250 250 ps (20% to 80%) Fall Time (t ) Full V 250 250 ps F (20% to 80%) FCO Propagation Delay Full V 6.5 6.5 ns (t ) FCO DCO Propagation Delay Full V t + t + ns FCO FCO (t ) (t /24) (t /24) CPD SAMPLE SAMPLE DCO-to-Data Delay (t ) Full IV (t /24) – (t /24) (t /24) + (t /24) – (t /24) (t /24) + ps DATA SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE 250 250 250 250 DCO-to-FCO Delay (t ) Full IV (t /24) – (t /24) (t /24) + (t /24) – (t /24) (t /24) + ps FRAME SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE 250 250 250 250 Data-to-Data Skew Full IV ±100 ±250 ±100 ±250 ps (tDATA-MAX – tDATA-MIN) Wake-Up Time 25°C V 4 4 ms Pipeline Latency Full IV 10 10 CLK cycles APERTURE Aperture Delay (t) 25°C V 1.8 1.8 ns A Aperture Uncertainty 25°C V <1 <1 ps (Jitter) rms OUT-OF-RANGE RECOVERY 25°C V 2 2 CLK TIME cycles Rev. B | Page 6 of 40 AD9229 TIMING DIAGRAM N–1 AIN N t A t t EH EL CLK t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t t PD DATA D– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9) D+ Figure 2. Timing Diagram Rev. B | Page 7 of 40 04418-002 AD9229 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any ELECTRICAL other conditions above those indicated in the operational AVDD AGND –0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute DRVDD DRGND –0.3 V to +3.9 V maximum rating conditions for extended periods may affect AGND DRGND –0.3 V to +0.3 V device reliability. AVDD DRVDD –3.9 V to +3.9 V Digital Outputs (D+, D–, DRGND –0.3 V to DRVDD EXPLANATION OF TEST LEVELS DCO+, DCO–, FCO+, FCO–) I. 100% production tested. LVDSBIAS DRGND –0.3 V to DRVDD CLK AGND –0.3 V to AVDD II. 100% production tested at 25°C and guaranteed by design VIN+, VIN– AGND –0.3 V to AVDD and characterization at specified temperatures. PDWN, DTP AGND –0.3 V to AVDD REFT, REFB AGND –0.3 V to AVDD III. Sample tested only. VREF, SENSE AGND –0.3 V to AVDD IV. Parameter is guaranteed by design and characterization ENVIRONMENTAL testing. –40°C to +85°C Operating Temperature Range (Ambient) V. Parameter is a typical value only. Maximum Junction 150°C Temperature VI. 100% production tested at 25°C and guaranteed by design Lead Temperature 300°C and characterization for industrial temperature range. (Soldering, 10 sec) –65°C to +150°C Storage Temperature Range (Ambient) 1 Thermal Impedance 25°C/W 1 θJA for a 4-layer PCB with a solid ground plane in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 8 of 40 AD9229 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR DRGND 1 36 DRGND DRVDD 2 35 DRVDD 34 LVDSBIAS NC 3 EXPOSED PADDLE, PIN 0 (Bottom of Package) DTP 4 33 AGND AVDD 5 32 AVDD AGND 6 31 AGND AD9229 PDWN 7 TOP VIEW 30 CLK (Not to Scale) AVDD 8 29 AVDD AGND 9 28 AGND VIN+A 10 27 VIN+D VIN–A 11 26 VIN–D AGND 12 25 AGND NC = NO CONNECT Figure 3. LFCSP Top View Table 6. Pin Function Descriptions Pin No. Mnemonic Description Pin No. Mnemonic Description AVDD Analog Supply 26 VIN–D 5, 8, 16, 21, ADC D Analog Input— 29, 32 Complement 6, 9, 12, 15, 22, AGND Analog Ground 27 VIN+D ADC D Analog Input—True 25, 28, 31, 33 30 CLK Input Clock 2, 35 DRVDD Digital Output Supply 34 LVDSBIAS LVDS Output Current Set 1, 36 DRGND Digital Ground Resistor Pin 0 AGND Exposed Paddle/Thermal Heat 37 D–D ADC D Complement Digital Slug (Located on Bottom of Output Package) 38 D+D ADC D True Digital Output 3 NC No Connect 39 D–C ADC C Complement Digital 4 DTP Digital Test Pattern Enable Output 7 PDWN 40 D+C ADC C True Digital Output Power-Down Selection (AVDD = Power Down) 41 D–B ADC B Complement Digital 10 VIN+A ADC A Analog Input—True Output 11 VIN–A ADC A Analog Input— 42 D+B ADC B True Digital Output Complement 43 D–A ADC A Complement Digital 13 VIN–B ADC B Analog Input— Output Complement 44 D+A ADC A True Digital Output 14 VIN+B ADC B Analog Input—True 45 FCO– Frame Clock Indicator— 17 SENSE Reference Mode Selection Complement Output 18 VREF Voltage Reference Input/Output 46 FCO+ Frame Clock Indicator—True Output 19 REFB Differential Reference (Bottom) 47 DCO– Data Clock Output— 20 REFT Differential Reference (Top) Complement 23 VIN+C ADC C Analog Input—True 48 DCO+ Data Clock Output—True 24 VIN–C ADC C Analog Input— Complement Rev. B | Page 9 of 40 VIN–B 13 48 DCO+ VIN+B 14 47 DCO– 46 FCO+ AGND 15 AVDD 16 45 FCO– SENSE 17 44 D+A VREF 18 43 D–A REFB 19 42 D+B REFT 20 41 D–B 40 D+C AVDD 21 AGND 22 39 D–C VIN+C 23 38 D+D 37 D–D VIN–C 24 04418-003 AD9229 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– V V D– D+ V V AGND DRGND Figure 4. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit AVDD AVDD DTP 375Ω CLK 100kΩ 170Ω AGND AGND Figure 5. Equivalent Clock Input Circuit Figure 8. Equivalent DTP Input Circuit AVDD PDWN 375Ω AGND Figure 6. Equivalent Digital Input Circuit Rev. B | Page 10 of 40 04418-006 04418-005 04418-004 04418-007 04418-051 AD9229 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 70.4dB SNR = 68.1dB ENOB = 11.4 BITS ENOB = 11.0 BITS –20 –20 SFDR = 85.8dBC SFDR = 77.0dBC –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 65 MSPS Figure 12. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS 0 90 1V p-p, SFDR (dBc) AIN = –0.5dBFS SNR = 69.6dB ENOB = 11.3 BITS –20 85 SFDR = 82.4dBC 2V p-p, SFDR (dBc) –40 80 –60 75 2V p-p, SNR (dB) –80 70 –100 65 1V p-p, SNR (dB) AIN = –0.5dBFS –120 60 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) ENCODE (MSPS) Figure 10. Single-Tone 32k FFT with f = 30 MHz, f = 65 MSPS Figure 13. SNR/SFDR vs. f , f = 10.3 MHz, f = 50 MSPS IN SAMPLE SAMPLE IN SAMPLE 0 90 1V p-p, SFDR (dBc) AIN = –0.5dBFS SNR = 68.5dB ENOB = 11.1 BITS –20 85 SFDR = 81.3dBC –40 80 2V p-p, SFDR (dBc) –60 75 2V p-p, SNR (dB) –80 70 –100 65 1V p-p, SNR (dB) AIN = –0.5dBFS –120 60 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) ENCODE (MSPS) Figure 11. Single-Tone 32k FFT with f = 70 MHz, f = 65 MSPS Figure 14. SNR/SFDR vs. f , f = 25 MHz, f = 50 MSPS IN SAMPLE SAMPLE IN SAMPLE Rev. B | Page 11 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 04418-011 04418-010 04418-009 SNR/SFDR (dB) SNR/SFDR (dB) AMPLITUDE (dBFS) 04418-014 04418-013 04418-012 AD9229 95 90 1V p-p, SFDR (dBc) 2V p-p, SFDR (dBc) 80 90 1V p-p, SFDR (dBc) 70 85 60 2V p-p, SFDR (dBc) 80 50 40 80 dB REFERENCE 75 2V p-p, SNR (dB) 30 70 20 2V p-p, SNR (dB) 65 1V p-p, SNR (dB) 1V p-p, SNR (dB) 10 AIN = –0.5dBFS 60 0 10 15 20 25 30 35 40 45 50 55 60 65 –60 –50 –40 –30 –20 –10 0 ENCODE (MSPS) ANALOG INPUT LEVEL (dBFS) Figure 15. SNR/SFDR vs. f , f = 10.3 MHz, f = 65 MSPS Figure 18. SNR/SFDR vs. Analog Input Level, SAMPLE IN SAMPLE f =25 MHz, f = 50 MSPS IN SAMPLE 85 90 2V p-p, SFDR (dBc) 80 2V p-p, SFDR (dBc) 80 1V p-p, SFDR (dBc) 70 1V p-p, SFDR (dBc) 60 75 50 40 80 dB REFERENCE 2V p-p, SNR (dB) 70 30 20 65 2V p-p, SNR (dB) 1V p-p, SNR (dB) 1V p-p, SNR (dB) 10 AIN = –0.5dBFS 60 0 10 15 20 25 30 35 40 45 50 55 60 65 –60 –50 –40 –30 –20 –10 0 ENCODE (MSPS) ANALOG INPUT LEVEL (dBFS) Figure 16. SNR/SFDR vs. f , f = 30 MHz, f = 65 MSPS Figure 19. SNR/SFDR vs. Analog Input Level, SAMPLE IN SAMPLE f = 10.3 MHz, f = 65 MSPS IN SAMPLE 90 90 2V p-p, SFDR (dBc) 2V p-p, SFDR (dBc) 80 80 70 70 1V p-p, SFDR (dBc) 1V p-p, SFDR (dBc) 60 60 50 50 40 40 80 dB REFERENCE 80 dB REFERENCE 30 30 20 20 2V p-p, SNR (dB) 2V p-p, SNR (dB) 1V p-p, SNR (dB) 1V p-p, SNR (dB) 10 10 0 0 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT LEVEL (dBFS) ANALOG INPUT LEVEL (dBFS) Figure 17. SNR/SFDR vs. Analog Input Level, Figure 20. SNR/SFDR vs. Analog Input Level, f = 10.3 MHz, f = 50 MSPS fIN = 30 MHz, fSAMPLE = 65 MSPS IN SAMPLE Rev. B | Page 12 of 40 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 04418-017 04418-016 04418-015 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 04418-020 04418-019 04418-018 AD9229 90 80 85 70 SFDR (dBc) 2V p-p, SFDR (dBc) 80 60 75 50 80 dB REFERENCE 70 40 SNR (dB) 65 30 1V p-p, SFDR (dBc) 60 20 55 10 50 45 0 1 10 100 1000 –60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 –7 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 21. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz Figure 24. Two-Tone SFDR vs. Analog Input Level, fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS 0 80 AIN1 AND AIN2= –7.0dBFS SFDR = 73.0dBc 70 IMD2 = 80.5dBc –20 2V p-p, SFDR (dBc) IMD3 = 73.0dBc 60 –40 50 80 dB REFERENCE –60 40 1V p-p, SFDR (dBc) 30 –80 20 –100 10 –120 0 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 –60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 –7 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 22. Two-Tone 32k FFT with f = 15 MHz and f = 16 MHz, IN1 IN2 Figure 25. Two-Tone SFDR vs. Analog Input Level, fIN1 = 69 MHz and f = 65 MSPS SAMPLE fIN2 = 70 MHz, fSAMPLE = 65 MSPS 0 90 AIN1 AND AIN2= –7.0dBFS 1V p-p, SFDR (dBc) SFDR = 68.5dBc IMD2 = 77.0dBc –20 85 IMD3 = 68.5dBc 2V p-p, SFDR (dBc) –40 80 –60 75 2V p-p, SINAD (dB) –80 70 –100 65 1V p-p, SINAD (dB) –120 60 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 –40 –20 0 20 40 60 80 FREQUENCY (MHz) TEMPERATURE (°C) Figure 23. Two-Tone 32k FFT with f = 69 MHz and f = 70 MHz, Figure 26. SINAD/SFDR vs. Temperature, f 10.3 MHz, f = 65 MSPS IN1 IN2 IN SAMPLE f = 65 MSPS SAMPLE Rev. B | Page 13 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dB) 04418-023 04418-022 04418-021 SNR/SFDR (dB) SFDR (dB) SFDR (dB) 04418-026 04418-025 04418-024 AD9229 –40 15 10 –50 5 0 –60 –5 –10 –70 –15 –20 –80 –40 –20 0 20 40 60 80 02 5 10 15 20530 TEMPERATURE (°C) FREQUENCY (MHz) Figure 27. Gain Error vs. Temperature Figure 30. CMRR vs. Frequency, fSAMPLE = 65 MSPS 0.5 10 0.36LSB rms 9 0.4 8 0.3 7 0.2 6 0.1 5 0 –0.1 4 3 –0.2 –0.3 2 1 –0.4 –0.5 0 0 512 1024 1536 2048 2560 3072 3584 4095 N – 3 N– 2 N – 1 N N + 1 N + 2 N + 3 CODE CODE Figure 28. Typical INL, f = 2.4 MHz, f = 65 MSPS IN SAMPLE Figure 31. Input Referred Noise Histogram, fSAMPLE = 65 MSPS 0.5 0 NPR = 60.8dB 0.4 NOTCH = 18MHz NOTCH WIDTH = 3MHz –20 0.3 0.2 –40 0.1 0 –60 –0.1 –80 –0.2 –0.3 –100 –0.4 –0.5 –120 0 512 1024 1536 2048 2560 3072 3584 4095 0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5 CODE FREQUENCY (MHz) Figure 29. Typical DNL, f = 2.4 MHz, f = 65 MSPS Figure 32. Noise Power Ratio (NPR), f = 65 MSPS IN SAMPLE SAMPLE Rev. B | Page 14 of 40 DNL (LSB) INL (LSB) GAIN ERROR (ppm/°C) 04418-030 04418-028 04418-027 AMPLITUDE (dBFS) NUMBER OF HITS (1M) CMRR (dB) 04418-035 04418-039 04418-031 AD9229 0 –1 –2 –3 –4 –5 –6 –7 –8 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 33. Full Power Bandwidth vs. Frequency, f = 65 MSPS SAMPLE Rev. B | Page 15 of 40 FUNDAMENTAL LEVEL (dB) 04418-038 AD9229 TERMINOLOGY Analog Bandwidth Full Power Bandwidth Analog bandwidth is the analog input frequency at which the Full power bandwidth is the measured –3 dB point at the analog spectral power of the fundamental frequency (as determined by front-end input relative to the frequency measured. the FFT analysis) is reduced by 3 dB from full scale. Gain Error Aperture Delay The largest gain error is specified and is considered the Aperture delay is a measure of the sample-and-hold amplifier difference between the measured and ideal full-scale input (SHA) performance and is measured from the 50% point rising voltage range. edge of the clock input to the time at which the input signal is Gain Matching held for conversion. Expressed as a percentage of FSR and computed using the Aperture Uncertainty (Jitter) following equation: Aperture jitter is the variation in aperture delay for successive FSR max− FSR min samples and can be manifested as frequency-dependent noise Gain Matching= × 100% FSR max+ FSR min ⎛ ⎞ on the ADC input. ⎜ ⎟ ⎝ 2 ⎠ Clock Pulse Width and Duty Cycle where FSRMAX is the most positive gain error of the ADCs, and Pulse width high is the minimum amount of time that the clock FSRMIN is the most negative gain error of the ADCs. pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock Input-Referred Noise pulse should be left in the low state. At a given clock rate, these Input-referred noise is a measure of the wideband noise specifications define an acceptable clock duty cycle. generated by the ADC core. Histograms of the output codes are created while a dc signal is applied to the ADC input. Input- Common Mode Rejection Ratio (CMRR) referred noise is calculated using the standard deviation of the CMRR is defined as the amount of rejection on the differential histograms and presented in terms of LSB rms. analog inputs when a common signal is applied. Typically expressed as 20 log (differential gain/common-mode gain). Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line Crosstalk drawn from negative full scale through positive full scale. The Crosstalk is defined as the measure of any feedthrough coupling point used as negative full scale occurs 0.5 LSB before the first onto the quiet channel when all other channels are driven by a code transition. Positive full scale is defined as a level 1.5 LSB full-scale signal. beyond the last code transition. The deviation is measured from Differential Analog Input Voltage Range the middle of each code to the true straight line. The peak-to-peak differential voltage that must be applied to Noise Power Ratio (NPR) the converter to generate a full-scale response. Peak differential NPR is the full-scale rms noise power injected into the ADC vs. voltage is computed by observing the voltage on a pin and the rejected band of interest (notch depth measured). subtracting the voltage from a second pin that is 180° out of phase. Offset Error The largest offset error is specified and is considered the Differential Nonlinearity (DNL, No Missing Codes) difference between the measured and ideal voltage at the analog An ideal ADC exhibits code transitions that are exactly 1 LSB input that produces the midscale code at the outputs. apart. DNL is the deviation from this ideal value. Guaranteed n no missing codes to an n-bit resolution indicates that all 2 Offset Matching codes, respectively, must be present over all operating ranges. Expressed in millivolts and computed using the following equation: Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the Offset Matching = OFF − OFF MAX MIN number of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective where OFF is the most positive offset error, and OFF is MAX MIN number of bits: the most negative offset error. N = (SINAD – 1.76)/6.02 Rev. B | Page 16 of 40 AD9229 Out-of-Range Recovery Time Signal-to-Noise Ratio (SNR) Out-of-range recovery time is the time it takes for the ADC to SNR is the ratio of the rms value of the measured input signal to reacquire the analog input after a transient from 10% above the rms sum of all other spectral components below the Nyquist positive full scale to 10% above negative full scale, or from 10% frequency, excluding the first six harmonics and dc. The value below negative full scale to 10% below positive full scale. for SNR is expressed in decibels. Output Propagation Delay Spurious-Free Dynamic Range (SFDR) The delay between the clock logic threshold and the time when SFDR is the difference in decibels between the rms amplitude of all bits are within valid logic levels. the input signal and the peak spurious signal. Second and Third Harmonic Distortion Temperature Drift The ratio of the rms signal amplitude to the rms value of the The temperature drift for offset error and gain error specifies second or third harmonic component, reported in decibels the maximum change from the initial (25°C) value to the value relative to the carrier. at TMIN or TMAX. Signal-to Noise and Distortion (SINAD) Ratio Two-Tone SFDR SINAD is the ratio of the rms value of the measured input The ratio of the rms value of either input tone to the rms value signal to the rms sum of all other spectral components below of the peak spurious component. The peak spurious component the Nyquist frequency, including harmonics but excluding dc. may or may not be an IMD product. It may be reported in The value for SINAD is expressed in decibels. decibels relative to the carrier (that is, degrades as signal levels are lowered) or in decibels relative to full scale (always related back to converter full scale). Rev. B | Page 17 of 40 AD9229 THEORY OF OPERATION of a clock cycle. A small resistor in series with each input can The AD9229 architecture consists of a front-end switched capa- help reduce the peak transient current required from the output citor sample-and-hold amplifier (SHA) followed by a pipelined stage of the driving source. Also, a small shunt capacitor can ADC. The pipelined ADC is divided into three sections: a 4-bit be placed across the inputs to provide dynamic charging first stage followed by eight 1.5-bit stages and a final 3-bit flash. currents. This passive network creates a low-pass filter at the Each stage provides sufficient overlap to correct for flash errors ADC’s input; therefore, the precise values are dependent on in the preceding stages. The quantized outputs from each stage the application. are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to The analog inputs of the AD9229 are not internally dc-biased. operate on a new input sample while the remaining stages In ac-coupled applications, the user must provide this bias operate on preceding samples. Sampling occurs on the rising externally. For optimum performance, set the device so that edge of the clock. VCM = AVDD/2; however, the device can function over a wider range with reasonable performance (see Figure 35 and Figure 36). Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC 90 and interstage residue amplifier (MDAC). The residue amplifier 2V p-p, SFDR (dBc) magnifies the difference between the reconstructed DAC output 85 and the flash input for the next stage in the pipeline. One bit of 1V p-p, SFDR (dBc) 80 redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. 75 The input stage contains a differential SHA that can be config- 2V p-p, SNR (dB) ured as ac- or dc-coupled in differential or single-ended modes. 70 The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is 65 1V p-p, SNR (dB) then serialized and aligned to the frame and output clock. 60 0 0.5 1.0 1.5 2.0 2.5 3.0 ANALOG INPUT CONSIDERATIONS ANALOG INPUT COMMON-MODE VOLTAGE (V) The analog input to the AD9229 is a differential switched- Figure 35. SNR/SFDR vs. Common-Mode Voltage, f = 2.4 MHz, IN capacitor SHA that has been designed for optimum perfor- f = 65 MSPS SAMPLE mance while processing a differential input signal. The SHA 90 input can support a wide common-mode range and maintain 2V p-p, SFDR (dBc) 85 excellent performance. An input common-mode voltage of 80 midsupply minimizes signal-dependent errors and provides 1V p-p, SFDR (dBc) optimum performance. 75 2V p-p, SNR (dB) H 70 65 1V p-p, SNR (dB) S S 60 VIN+ 55 C PAR 50 45 S 40 0 0.5 1.0 1.5 2.0 2.5 3.0 VIN– ANALOG INPUT COMMON-MODE VOLTAGE (V) C PAR Figure 36. SNR/SFDR vs. Common-Mode Voltage, f = 30 MHz, S IN f = 65 MSPS SAMPLE H For best dynamic performance, the source impedances driving Figure 34. Switched-Capacitor SHA Input VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the The clock signal alternately switches the SHA between sample common-mode rejection of the ADC. mode and hold mode (see Figure 34). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half Rev. B | Page 18 of 40 04418-029 SNR/SFDR (dB) SNR/SFDR (dB) 04418-054 04418-053 AD9229 An internal reference buffer creates the positive and negative AVDD R reference voltages, REFT and REFB, respectively, that defines VIN+ the span of the ADC core. The output common-mode of the 2Vp-p 49.9Ω AD9229 C reference buffer is set to midsupply, and the REFT and REFB R AVDD VIN– voltages and span are defined as AGND 1kΩ REFT = 1/2 (AVDD + VREF) 1kΩ REFB = 1/2 (AVDD − VREF) 0.1μF Span = 2 × (REFT − REFB) = 2 × VREF Figure 38. Differential Transformer—Coupled Configuration It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage Single-Ended Input Configuration and, by definition, the input span is twice the value of the A single-ended input can provide adequate performance in VREF voltage. cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input The internal voltage reference can be pin-strapped to fixed common-mode swing. However, if the source impedances values of 0.5 V or 1.0 V or adjusted within the same range, as on each input are matched, there should be little effect on discussed in the Internal Reference Connection section. SNR performance. Figure 39 details a typical single-ended Maximum SNR performance is achieved by setting the AD9229 input configuration. to the largest input span of 2 V p-p. 10μF The SHA should be driven from a source that keeps the signal peaks within the allowable range for the selected reference AVDD 1kΩ R voltage. The minimum and maximum common-mode input VIN+ 0.1μF 1kΩ levels are defined in Figure 35 and Figure 36. 2V p-p 49.9Ω AD9229 C AVDD Differential Input Configurations 1kΩ R Optimum performance is achieved by driving the AD9229 in a VIN– differential input configuration. For ultrasound applications, 10μF 0.1μF AGND 1kΩ the AD8332 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 37). Figure 39. Single-Ended Input Configuration 0.1μF AVDD LOP VIP CLOCK INPUT CONSIDERATIONS 0.1μF AVDD 187Ω R 0.1μF 120nH VOH INH VIN+ Typical high speed ADCs use both clock edges to generate a 1V p-p 1.0kΩ 22p AD8332 LNA VGA 374Ω C AD9229 variety of internal timing signals and, as a result, may be sensi- 1.0kΩ R LMD 0.1μF VIN– tive to clock duty cycle. Typically, a 10% tolerance is required on VOL 187nH 0.1μF VREF AGND 0.1μF10μF LON VIN the clock duty cycle to maintain dynamic performance charac- 274Ω 18nF 0.1μF teristics. The AD9229 has a self-contained clock duty cycle stabilizer that retimes the nonsampling edge, providing an Figure 37. Differential Input Configuration Using the AD8332 internal clock signal with a nominal 50% duty cycle. This allows However, the noise performance of most amplifiers is not a wide range of clock input duty cycles without affecting the adequate to achieve the true performance of the AD9229. For performance of the AD9229. applications where SNR is a key parameter, differential transfor- An on-board phase-locked loop (PLL) multiplies the input mer coupling is the recommended input configuration. An clock rate for the purpose of shifting the serial data out. The example of this is shown in Figure 38. stability criteria for the PLL limits the minimum sample clock In any configuration, the value of the shunt capacitor, C, is rate of the ADC to 10 MSPS. Assuming steady state operation of dependent on the input frequency and may need to be reduced the input clock, any sudden change in the sampling rate could or removed. create an out-of-lock condition leading to invalid outputs at the DCO, FCO, and data out pins. Rev. B | Page 19 of 40 04418-032 04418-033 04418-034 AD9229 1400 500 High speed, high resolution ADCs are sensitive to the quality of 450 the clock input. The degradation in SNR at a given full-scale 1300 I AVDD 400 input frequency (f ) due only to aperture jitter (t ) can be A A calculated with the following equation: 350 1200 SNR degradation = 20 × log 10 [1/2 × π × fA × tA] 300 TOTAL POWER In the equation, the rms aperture jitter, tA, represents the root 1100 250 sum square of all jitter sources, which include the clock input, 200 analog input signal, and ADC aperture jitter specification. 1000 150 Applications that require undersampling are particularly 100 sensitive to jitter. 900 I DRVDD 50 The clock input should be treated as an analog signal in cases 800 0 10 20 30 40 50 60 where aperture jitter may affect the dynamic range of the ENCODE (MSPS) AD9229. Power supplies for clock drivers should be separated Figure 41. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled By asserting the PDWN pin high, the AD9229 is placed in oscillators make the best clock sources. If the clock is generated power-down mode. In this state, the ADC typically dissipates from another type of source (by gating, dividing, or other 3 mW. During power-down, the LVDS output drivers are placed methods), it should be retimed by the original clock at the in a high impedance state. Reasserting the PDWN pin low last step. returns the AD9229 to normal operating mode. Power Dissipation and Power-Down Mode In power-down mode, low power dissipation is achieved by As shown in Figure 40 and Figure 41, the power dissipated by shutting down the reference, reference buffer, PLL, and biasing the AD9229 is proportional to its sample rate. The digital power networks. The decoupling capacitors on REFT and REFB are dissipation does not vary much because it is determined discharged when entering standby mode and then must be primarily by the DRVDD supply and bias current of the LVDS recharged when returning to normal operation. As a result, the output drivers. wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up 1200 350 times. With the recommended 0.1 μF and 10 μF decoupling 300 capacitors on REFT and REFB, it takes approximately 1 sec to 1100 I AVDD fully discharge the reference buffer decoupling capacitors and 250 4 ms to restore full operation. 1000 200 Digital Outputs TOTAL POWER 900 The AD9229’s differential outputs conform to the ANSI-644 150 LVDS standard. To set the LVDS bias current, place a resistor 800 100 (RSET is nominally equal to 4.0 kΩ) to ground at the LVDSBIAS pin. The RSET resistor current is derived on-chip 700 50 I DRVDD and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the 600 0 10 15 20 25 30 35 40 45 50 LVDS receiver inputs results in a nominal 350 mV swing at the ENCODE (MSPS) receiver. To adjust the differential signal swing, simply change Figure 40. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS the resistor to a different value, as shown in Table 7. Table 7. LVDSBIAS Pin Configuration RSET Differential Output Swing 3.7 kΩ 375 mV p-p 4.0 kΩ (default) 350 mV p-p 4.3 kΩ 325 mV p-p Rev. B | Page 20 of 40 POWER (mW) 04418-056 CURRENT (mA) POWER (mW) 04418-055 CURRENT (mA) AD9229 Table 9. Digital Test Pattern Pin Settings The AD9229’s LVDS outputs facilitate interfacing with LVDS Resulting Resulting receivers in custom ASICs and FPGAs that have LVDS capa- Selected DTP DTP Voltage D+ and D– FCO and DCO bility for superior switching performance in noisy environ- Normal AGND Normal Normal ments. Single point-to-point net topologies are recommended operation operation operation with a 100 Ω termination resistor placed as close to the receiver DTP1 AVDD/3 1000 0000 0000 Normal operation as possible. It is recommended to keep the trace length no DTP2 2 × AVDD/3 1010 1010 1010 Normal longer than 12 inches and to keep differential output traces operation close together and at equal lengths. Restricted AVDD N/A N/A The format of the output data is offset binary. An example of Voltage Reference the output coding format can be found in Table 8. A stable and accurate 0.5 V voltage reference is built into the Table 8. Digital Output Coding AD9229. The input range can be adjusted by varying the refer- ence voltage applied to the AD9229, using either the internal (VIN+) − (VIN−), (VIN+) − (VIN−), Digital Output Input Span = Input Span = Offset Binary reference or an externally applied reference voltage. The input Code 2 V p-p (V) 1 V p-p (V) (D11 ... D0) span of the ADC tracks reference voltage changes linearly. 4095 1.000 0.500 1111 1111 1111 2048 0 0 1000 0000 0000 When applying the decoupling capacitors to the VREF, REFT, 2047 −0.000488 −0.000244 0111 1111 1111 and REFB pins, use ceramic, low ESR capacitors. These 0 −1.00 −0.5000 0000 0000 0000 capacitors should be close to the ADC pins and on the same Timing layer of the PCB as the AD9229. The recommended capacitor values and configurations for the AD9229 reference pin can be Data from each ADC is serialized and provided on a separate found in Figure 42 and Figure 43. channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 bps (12 bits Table 10. Reference Settings × 65 MSPS = 780 bps). The lowest typical conversion rate is Resulting SENSE Resulting Differential 10 MSPS. Selected Mode Voltage VREF (V) Span (V p-p) External Reference AVDD N/A 2 × external Two output clocks are provided to assist in capturing data from reference the AD9229. The DCO is used to clock the output data and is Internal, 1 V p-p FSR VREF 0.5 1.0 equal to six times the sampling clock (CLK) rate. Data is Programmable 0.2 V to 0.5 × (1 + 2 × VREF clocked out of the AD9229 and can be captured on the rising VREF R2/R1) and falling edges of the DCO that supports double-data rate Internal, 2 V p-p FSR AGND to 1.0 2.0 0.2 V (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock Internal Reference Connection rate. See the timing diagram shown in Figure 2 for more A comparator within the AD9229 detects the potential at the information. SENSE pin and configures the reference into four possible states (summarized in Table 10). If SENSE is grounded, the reference DTP Pin amplifier switch is connected to the internal resistor divider (see The digital test pattern (DTP) pin can be enabled for two types Figure 42), setting VREF to 1 V. Connecting the SENSE pin to of test patterns, as summarized in Table 9. When the DTP is the VREF pin switches the amplifier output to the SENSE pin, tied to AVDD/3, all the ADC channel outputs shift out the configuring the internal op amp circuit as a voltage follower and following pattern: 1000 0000 0000. When the DTP is tied to 2 × providing a 0.5 V reference output. If an external resistor AVDD/3, all the ADC channel outputs shift out the following divider is connected as shown in Figure 43, the switch is again pattern: 1010 1010 1010. The FCO and DCO outputs still work set to the SENSE pin. This puts the reference amplifier in a as usual while all channels shift out the test pattern. This noninverting mode and defines the VREF output as pattern allows the user to perform timing alignment adjustments between the FCO, DCO, and the output data. For R2 ⎛ ⎞ VREF= 0.5× 1+ ⎜ ⎟ normal operation, this pin should be tied to AGND. R1 ⎝ ⎠ In all reference configurations, REFT and REFB establish their input span of the ADC core. The analog input full-scale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. Rev. B | Page 21 of 40 AD9229 External Reference Operation VIN+ The use of an external reference may be necessary to enhance VIN– REFT the gain accuracy of the ADC or improve thermal drift charac- 0.1μF teristics. Figure 45 shows the typical drift characteristics of the + ADC 0.1μF 10μF CORE internal reference. REFB 0.10 0.1μF VREF 0.08 10μF 0.1μF 0.5V 0.06 SELECT LOGIC 0.04 SENSE VREF = 0.5V 0.02 0 –0.02 –0.04 VREF = 1.0V Figure 42. Internal Reference Configuration –0.06 –0.08 VIN+ –0.10 VIN– –40 –25 –10 5 20 35 50 65 80 REFT TEMPERATURE (°C) 0.1μF Figure 45. Typical VREF Drift + ADC 0.1μF 10μF CORE REFB When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external 0.1μF VREF reference is loaded with an equivalent 7 kΩ load. An internal + 10μF 0.1μF 0.5V reference buffer generates the positive and negative full-scale SELECT R2 LOGIC references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V. SENSE R1 Power and Ground Recommendations When connecting power to the AD9229, it is recommended that two separate 3.0 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is Figure 43. Programmable Reference Configuration available, it should be routed to the AVDD first and tapped off If the internal reference of the AD9229 is used to drive multiple and isolated with a ferrite bead or filter choke with decoupling converters to improve gain matching, the loading of the refer- capacitors proceeding. The user can employ several different ence by the other converters must be considered. Figure 44 decoupling capacitors to cover both high and low frequencies. depicts how the internal reference voltage is affected by loading. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. 0.05 A single PC board ground plane should be sufficient when 0 using the AD9229. With proper decoupling and smart parti- tioning of the PC board’s analog, digital, and clock sections, –0.05 VREF = 0.5V optimum performance is easily achieved. –0.10 –0.15 –0.20 VREF = 1.0V –0.25 –0.30 –0.35 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 I (mA) LOAD Figure 44. VREF Accuracy vs. Load Rev. B | Page 22 of 40 VREF ERROR (%) 04418-037 04418-036 04418-058 VREF ERROR (%) 04418-057 AD9229 SILKSCREEN PARTITION Exposed Paddle Thermal Heat Slug Recommendations PIN 1 INDICATOR It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9229. A continuous exposed copper plane on the PCB should mate to the AD9229 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Figure 46. Typical PCB Layout These vias should be solder or epoxy filled (plugged). To maximize the solder coverage and adhesion between the ADC and PCB, overlay a silkscreen to partition the continuous copper plane on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no silkscreen partitions only guarantees one tie point between the ADC and PCB. See Figure 46 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, visit www.analog.com. Rev. B | Page 23 of 40 04418-052 AD9229 EVALUATION BOARD power supply. This enables the user to individually bias each The AD9229 evaluation board provides all of the support cir- section of the board. Use P501 to connect a different supply for cuitry required to operate the ADC in its various modes and each section. At least one 3.0 V supply is needed with a 1 A configurations. The converter can be driven differentially current capability for AVDD_DUT and DRVDD_DUT; through a transformer (default) or through the AD8332 driver. however, it is recommended that separate supplies be used for The ADC can also be driven in a single-ended fashion. Separate both analog and digital. To operate the evaluation board using power pins are provided to isolate the DUT from the AD8332 the VGA option, a separate 5.0 V analog supply is needed in drive circuitry. Each input configuration can be selected by addition to the other 3.0 V supplies. The 5.0 V supply, or proper connection of various jumpers (see Figure 48 to Figure 52). AVDD_VGA, should have a 1 A current capability as well. Figure 47 shows the typical bench characterization setup used to evaluate the ac performance of the AD9229. It is critical that INPUT SIGNALS the signal sources used for the analog input and clock have very When connecting the clock and analog source, use clean signal low phase noise (<1 ps rms jitter) to realize the ultimate generators with low phase noise, such as Rohde & Schwarz SMHU performance of the converter. Proper filtering of the analog or HP8644 signal generators or the equivalent. Use 1 m long, input signal to remove harmonics and lower the integrated or shielded, RG-58, 50 Ω coaxial cable for making connections to broadband noise at the input is also necessary to achieve the the evaluation board. Dial in the desired frequency and amplitude specified noise performance. within the ADC’s specifications tables. Typically, most ADI evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave See Figure 47 to Figure 57 for complete schematics and layout input for the clock. When connecting the analog input source, it plots that demonstrate the routing and grounding techniques is recommended to use a multipole, narrow-band band-pass that should be applied at the system level. filter with 50 Ω terminations. ADI uses TTE, Allen Avionics, POWER SUPPLIES and K&L types of band-pass filters. The filter should be This evaluation board comes with a wall mountable switching connected directly to the evaluation board if possible. power supply that provides a 6 V, 2 A maximum output. Simply OUTPUT SIGNALS connect the supply to the rated 100 V to 240 V ac wall outlet at The default setup uses the HSC-ADC-FPGA high speed 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the deserialization board, which deserializes the digital output data 6 V supply is fused and conditioned before connecting to three and converts it to parallel CMOS. These two channels interface low dropout linear regulators that supply the proper bias to each directly with ADI’s standard dual-channel FIFO data capture of the various sections on the board. board (HSC-ADC-EVALA-DC). Two of the four channels can then be evaluated at the same time. For more information on When operating the evaluation board in a nondefault condition, channel settings on these boards and their optional settings, L504 to L506 can be removed to disconnect the switching visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2Amax 5.0V 3.0V 3.0V –+ –+ –+ SWITCHING POWER SUPPLY HSC-ADC-FPGA HSC-ADC-EVALA-DC PC HIGH SPEED FIFO DATA RUNNING DESERIALIZATION CAPTURE ADC ROHDE & SCHWARZ, BOARD BOARD ANALYZER SMHU, BAND-PASS XFMR 2V p-p SIGNAL CHA–CHD FILTER INPUT 2 CH AD9229 SYNTHESIZER 12-BIT USB 12-BIT EVALUATION BOARD SERIAL CONNECTION PARALLEL ROHDE & SCHWARZ, LVDS CMOS CLK SMHU, 2V p-p SIGNAL SYNTHESIZER Figure 47. Evaluation Board Connections Rev. B | Page 24 of 40 GND AVDD_VGA GND AVDD_DUT GND DRVDD_DUT 04418-040 AD9229 DEFAULT OPERATION AND JUMPER SELECTION • DTP: To enable one of the two digital test patterns on SETTINGS digital outputs of the ADC, use JP202. If Pins 2 and 3 on JP202 are tied together (1.0 V source), this enables test The following is a list of the default and optional settings or pattern 1000 0000 0000. If Pins 1 and 2 on JP202 are tied modes allowed on the AD9229 Rev C evaluation board. together (2.0 V source), this enables test pattern 1010 1010 • POWER: Connect the switching power supply that is 1010. See the DTP Pin section for more details. supplied in the evaluation kit between a rated 100 V to • LVDSBIAS: To change the level of the LVDS output level 240 V ac wall outlet at 47 Hz to 63 Hz and P503. swing, simply change the value of R204. Other recom- • AIN: The evaluation board is set up for a transformer mended values can be found in the Digital Outputs coupled analog input with optimum 50 Ω impedance section. matching out to 400 MHz. For more bandwidth response, • D+, D–: If an alternate data capture method to the setup the 2.2 pF differential capacitor across the analog inputs described in Figure 47 is used, optional receiver could be changed or removed. The common mode of the terminations, R205 to R210, can be installed next to the analog inputs is developed from the center tap of the high speed backplane connector. transformer or AVDD_DUT/2. ALTERNATE ANALOG INPUT DRIVE • VREF: VREF is set to 1.0 V by tying the SENSE pin to CONFIGURATION ground, R224. This causes the ADC to operate in 2.0 V p-p full-scale range. A number of other VREF options are The following is a brief description of the alternate analog input available on the evaluation board, including 1.0 V p-p full- drive configuration using the AD8332 dual VGA. This parti- scale range, a variable range that the user can set by cular drive option may need to be populated, in which case all choosing R219 and R220 as well as a separate external the necessary components are listed in Table 11. This table lists reference option using the ADR510 or ADR520. Simply the necessary settings to properly configure the evaluation populate R218 and R222 and remove C208. To use these board for this option. For more details on the AD8332 dual optional VREF modes, switch the jumper setting on R221 VGA, how it works, and its optional pin settings, consult the to R224. Proper use of the VREF options is noted in the AD8332 data sheet. Voltage Reference section. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to • CLOCK: The clock input circuitry is derived from a simple be removed and/or changed. logic circuit using a high speed inverter that adds a very low amount of jitter to the clock path. The clock input is 1. Remove R102, R115, R128, R141, T101, T102, T103, and 50 Ω terminated and ac-coupled to handle sine wave T1044 in the default analog input path. type inputs. If using an oscillator, two oscillator footprint options are also available (OSC200-201) to check the 2. Populate R101, R114, R127, and R140 with 0 Ω resistors in ADC’s performance. J203 and J204 give the user flexibility the analog input path. in using the enable pin, which is common on most 3. Populate R106, R107, R119, R120, R132, R133, R144, and oscillators. R145 with 10 kΩ resistors to provide an input common- • PWDN: To enable the power-down feature, simply short mode level to the analog input. JP201 to AVDD on the PWDN pin. 4. Populate R105, R113, R118, R124, R131, R137, R151, and R43 with 0 Ω resistors in the analog input path. 5. Currently L305 to L312 and L405 to L412 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. Rev. B | Page 25 of 40 AD9229 R105 0Ω AVDD_DUT DNP CH_A VGA INPUT R106 CONNECTION 1kΩ R152 FB102 P102 DNP INH1 C101 R108 DNP R104 T101 10 DNP 0.1μF 33Ω 0Ω 6 1 VIN_A A CHANNEL A IN R101 R160 C103 C104 R109 2 5 C102 FB101 CM1 CM1 P101 0Ω 499Ω DNP 2.2pF 1kΩ 0.1μF 10 DNP 34 A FB103 IN R110 10 33Ω R103 R102 CH_A VIN_A 0Ω 65Ω R113 C105 R107 R156 0Ω DNP 1kΩ DNP CM1 DNP DNP R111 1kΩ C106 AVDD_DUT DNP AVDD_DUT R112 C107 1kΩ 0.1μF VGA INPUT R118 CONNECTION 0Ω AVDD_DUT DNP INH2 CH_B R119 1kΩ R153 CHANNEL B R114 FB105 DNP FB104 C108 R121 DNP P103 0Ω T102 10 10 0.1μF 33Ω 6 DNP 1 A VIN_B IN R161 C110 C111 R123 2 5 P104 C109 R115 CM2 CM2 R116 499Ω DNP 2.2pF 1kΩ DNP 0.1μF 65Ω 0Ω 34 FB106 R122 A IN 10 33Ω R117 CH_B VIN_B 0Ω R124 C112 R120 R157 0Ω DNP 1kΩ DNP CM2 DNP DNP R125 1kΩ C113 AVDD_DUT DNP AVDD_DUT R126 C114 1kΩ 0.1μF ANALOG INPUTS R131 0Ω AVDD_DUT DNP CH_C VGA INPUT R132 CONNECTION 1kΩ R154 FB108 P106 DNP INH3 C115 R134 DNP R130 T103 DNP 10 0.1μF 33Ω 0Ω 6 1 VIN_C A CHANNEL C IN R162 C117 C118 R135 R127 2 5 FB107 C116 CM3 CM3 P105 0Ω 499Ω DNP 2.2pF 1kΩ 10 0.1μF DNP 34 A FB109 IN R136 10 33Ω R129 R128 CH_C VIN_C 0Ω 65Ω R137 R133 C119 R158 0Ω 1kΩ DNP DNP CM3 DNP DNP R138 1kΩ C120 AVDD_DUT DNP AVDD_DUT R139 C121 1kΩ 0.1μF VGA INPUT R151 CONNECTION 0Ω AVDD_DUT DNP INH4 CH_D R144 1kΩ CHANNEL D R155 R140 FB111 DNP FB110 C122 R146 DNP P107 0Ω T104 10 10 0.1μF 33Ω 6 DNP 1 A VIN_D IN R163 C124 C125 R148 2 5 P108 R141 C123 R143 CM4 CM4 499Ω DNP 2.2pF 1kΩ DNP 65Ω 0.1μF 0Ω 34 FB112 R147 A IN 10 33Ω R142 CH_D VIN_D 0Ω R43 C126 R145 R159 0Ω 1kΩ DNP DNP CM4 DNP DNP R149 1kΩ C127 AVDD_DUT DNP AVDD_DUT R150 C128 1kΩ 0.1μF DNP : DO NOT POPULATE Figure 48. Evaluation Board Schematic, DUT Analog Inputs Rev. B | Page 26 of 40 04418-041 AD9229 U201 1 36 DRGND DRGND GND GND 2 35 DRVDD_DUT DRVDD DRVDD DRVDD_DUT DIGITAL TEST AVDD_DUT 3 34 PATTERN DNC LVDSBIAS ENABLE 4 33 DTP AGND GND R204 R201 4.0kΩ 10kΩ 5 32 PIN 1 TO PIN 2 = 1010 1010 1010 AVDD_DUT AVDD AVDD AVDD_DUT 2 PIN 2 TO PIN 3 = 1000 0000 0000 6 31 1 3 AGND AGND GND GND JP202 GND R202 AD9229 7 30 10kΩ PWDN ENABLE PDWN CLK DUTCLK JP201 29 8 AVDD_DUT AVDD AVDD AVDD_DUT AVDD_DUT R228 R203 28 9 10kΩ AGND AGND 10kΩ GND GND 27 10 VIN_A VIN +A VIN +D VIN_D OPTIONAL CLOCK OSCILLATOR 26 11 VIN_A VIN –A VIN –D VIN_D 25 12 AGND AGND GND GND DIGITAL OUTPUTS P202 GNDCD10 AVDD_DUT 60 R205 JP204 JP203 C10 D10 DCO DCO DNP 40 50 AVDD_VGA GNDCD9 OSC200 59 R206 C203 FCO C9 D9 FCO 1 2 0.1μF DNP EOH GND 39 49 GNDCD8 4 3 58 VCC OUTPUT C202 R207 REFERENCE C8 D8 10μF CHA CHA DECOUPLING C209 38 DNP 48 CBELV3I66MT 0.1μF GNDCD7 C204 C201 57 R208 0.1μF 0.1μF C7 D7 OSC201 CHB CHB DNP 37 47 1 7 GNDCD6 NC/ENB GND 56 R209 14 8 CHC C6 D6 CHC VCC OUTPUT DNP 36 46 C210 R225 GNDCD5 CX3600C-65 0.1μF 0Ω 55 DNP R210 DNP CHD C5 D5 CHD DNP 35 45 CLOCK CIRCUIT AVDD_DUT GNDCD4 54 C4 D4 34 44 R212 GNDCD3 R229 R214 U202 U202 P201 1kΩ 0Ω 22Ω 53 12 34 ENCODE DUTCLK C3 D3 INPUT 33 43 R230 GNDCD2 R211 R231 C205 R213 AVDD_DUT:14 AVDD_DUT:14 1kΩ 0Ω 0Ω 0.1μF 52 49.9Ω GND:7 GND:7 DNP DNP C2 D2 32 42 GNDCD1 51 C1 D1 31 41 GNDAB10 30 A10 B10 10 20 GNDAB9 29 EXTERNAL REFERENCE CIRCUIT A9 B9 9 19 GNDAB8 28 AVDD_DUT A8 B8 REFERENCE CIRCUIT 8 18 GNDAB7 VREF SELECT VREF = 1V = DEFAULT U203 27 R218 VREF_DUT R215 R221 A7 B7 0Ω 7 17 ADR510/ADR520 2kΩ 0Ω GNDAB6 DNP VREF = 0.5V TRIM/NC 1NV VOUT 26 A6 B6 R222 C206 6 16 GNDAB5 0.1μF 0Ω AVDD_DUT VREF = EXTERNAL R219 25 DNP A5 B5 R216 C207 C208 R223 5 15 GNDAB4 10kΩ 0.1μF 10μF 0Ω VREF = 0.5V (1 + R219/R220) 24 R217 CW A4 B4 470kΩ 4 14 R220 R224 GNDAB3 DNP 0Ω VREF = 1V 23 A3 B3 VSENSE_DUT 3 13 GNDAB2 22 A2 B2 2 12 REMOVE C208 WHEN GNDAB1 USING EXTERNAL VREF 21 A1 B1 1 11 1469169-1 R205-R210 DNP : DO NOT POPULATE OPTIONAL OUTPUT TERMINATIONS Figure 49. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface Rev. B | Page 27 of 40 GND 13 48 VIN _B VIN –B DCO+ DCO 14 47 VIN_B VIN +B DCO– DCO 15 46 GND AGND FCO+ FCO 16 45 AVDD_DUT AVDD FCO– FCO 17 44 VSENSE_DUT SENSE D+A CHA 18 43 VREF_DUT VREF A–D CHA 19 42 REFB D+B CHB 20 41 REFT D–B CHB 21 40 AVDD_DUT AVDD D+C CHC 22 39 GND AGND D–C CHC 23 38 VIN _C VIN +C D+D CHD 24 37 VIN_C VIN –C D–D CHD 04418-042 AD9229 CH_D CH_D CH_C CH_C EXT VG JP301 12 R320 R321 POPULATE L305 TO L312 DNP DNP WITH 0Ω RESISTORS OR GND DESIGN YOUR OWN FILTER VG C303 C304 DNP DNP L306 L308 L305 DNP L307 DNP DNP C305 DNP C306 DNP DNP L310 L312 L309 DNP L311 DNP DNP R318 DNP R319 DNP DNP R302 VG 10kΩ C310 CW C307 C309 0.1μF 0.1μF 0.1μF R303 R305 R308 39kΩ C308 374Ω 374Ω 0.1μF R304 R306 R307 R309 AVDD_VGA 187Ω 187Ω 187Ω 187Ω C311 C312 R310 1nF 0.1μF 100kΩ AVDD_VGA DNP AVDD_VGA R312 U301 AVDD_VGA 10Ω 25 16 ENBV RCLMP R311 R311 26 15 10kΩ 10kΩ VG ENBL GAIN DNP DNP 27 14 HILO MODE 28 13 VCM1 VCM2 AD8332 29 12 VIN1 VIN2 30 11 VIP1 VIP2 31 10 C313 C314 COM1 COM2 0.1μF 0.1μF 32 9 LOP1 LOP2 C315 C316 0.1μF 0.1μF R314 C317 C318 R315 R316 C319 C320 R317 10kΩ 10μF 0.1μF 274Ω 274Ω 0.1μF 10μF 10kΩ DNP C321 C322 18nF 18nF C325 C326 0.1μF 0.1μF C323 C324 22pF 22pF L313 L314 120nH 120nH C327 C328 0.1μF 0.1μF DNP : DO NOT POPULATE INH4 INH3 Figure 50. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. B | Page 28 of 40 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS C AND D HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V POWER-DOWN ENABLE (0V TO 1V = DISABLE POWER) 1 24 LON1 COMM 2 23 AVDD_VGA VPS1 VOH1 3 22 INH1 VOL1 4 21 LMD1 VPSV 5 20 LMD2 NC 6 19 INH2 VOL2 7 18 AVDD_VGA VPS2 VOH2 8 17 LON2 COMM EXTERNAL VARIABLE GAIN DRIVE VARIABLE GAIN CIRCUIT (0V TO 1.0V DC) MODE PIN RCLAMP PIN POSITIVE GAIN SLOPE = 0V TO 1.0V HILO PIN = LO =± 50mV NEGATIVE GAIN SLOPE = 2.25V TO 5.0V HILO PIN = HI =± 75mV 044181-003 AD9229 CH_B CH_B CH_A CH_A R417 R418 POPULATE L405 TO L412 DNP DNP WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER C403 C404 DNP DNP L406 L408 L405 DNP L407 DNP DNP C405 DNP C406 DNP DNP L410 L412 L409 DNP L411 DNP DNP R415 DNP R416 DNP DNP C410 C407 C409 0.1μF 0.1μF 0.1μF R404 R407 C408 374Ω 374Ω 0.1μF R403 R405 R406 R408 187Ω 187Ω 187Ω 187Ω C411 C412 R409 1nF 0.1μF 100kΩ AVDD_VGA DNP AVDD_VGA R402 U401 AVDD_VGA 10kΩ 25 16 ENBV RCLMP R401 R409 26 15 10kΩ 10kΩ VG ENBL GAIN DNP DNP 27 14 HILO MODE 28 13 VCM1 VCM2 AD8332 29 12 VIN1 VIN2 30 11 VIP1 VIP2 31 10 C413 C414 COM1 COM2 0.1μF 0.1μF 32 9 LOP1 LOP2 C415 C416 0.1μF 0.1μF R411 C417 C418 R412 R413 C419 C420 R414 10kΩ 10μF 0.1μF 274Ω 274Ω 0.1μF 10μF 10kΩ DNP C423 C424 18nF 18nF C421 C422 0.1μF 0.1μF C425 C426 22pF 22pF L413 L414 120pH 120nH C427 C428 0.1μF 0.1μF DNP : DO NOT POPULATE INH2 INH1 Figure 51. Evaluation Board Schematic, Optional DUT Analog Input Drive Continued Rev. B | Page 29 of 40 OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS A AND B HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V POWER-DOWN ENABLE (0V TO 1V = DISABLE POWER) 1 24 LON1 COMM 2 23 VPS1 VOH1 3 22 INH1 VOL1 4 21 LMD1 VPSV 5 20 LMD2 NC 6 19 INH2 VOL2 7 18 AVDD_VGA VPS2 VOH2 8 17 LON2 COMM MODE PIN RCLAMP PIN POSITIVE GAIN SLOPE = 0V TO 1.0V HILO PIN = LO =± 50mV NEGATIVE GAIN SLOPE = 2.25V TO 5.0V HILO PIN = HI =± 75mV 044181-044 AD9229 D502 POWER SUPPLY INPUT SHOT_RECT 6V 3A FER501 2A MAX F501 CHOKE_COIL DO-214AB PWR_IN 4 3 P503 SMDC110F 1 2 1 R500 374Ω D501 C501 S2A_RECT 10μF 2A CR500 2 3 DO-214AA U501 L504 ADP33339AKC-3 10μH 32 PWR_IN INPUT OUTPUT1 DUT_AVDD 4 C502 C503 OUTPUT4 1μF 1μF GND 1 U502 L506 ADP33339AKC-5 10μH 32 PWR_IN INPUT OUTPUT1 VGA_AVDD 4 C514 C515 OUTPUT4 1μF 1μF GND 1 U503 L505 ADP33339AKC-3 10μH 32 PWR_IN INPUT OUTPUT1 DUT_DRVDD 4 C506 C507 OUTPUT4 1μF 1μF GND 1 OPTIONAL POWER INPUT P501 L503 DNP 10μH 1 VGA_AVDD P1 AVDD_VGA 5.0V 2 C516 C517 P2 10μF 0.1μF 3 DUT_AVDD P3 4 P4 L502 5 DUT_DRVDD 10μH P5 AVDD_DUT 3.0V 6 P6 C508 C509 10μF 0.1μF L501 10μH DRVDD_DUT 3.0V C504 C505 10μF 0.1μF DNP : DO NOT POPULATE Figure 52. Evaluation Board Schematic, Power Supply Inputs Rev. B | Page 30 of 40 04418-045 AD9229 DECOUPLING CAPACITORS DRVDD_DUT C613 C614 0.1μF 0.1μF AVDD_VGA C617 C618 C619 C620 C625 C628 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF AVDD_DUT C627 C630 C631 C621 C632 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF H1 H2 UNUSED GATES H3 H4 U202 56 GND MOUNTING HOLES AVDD_DUT : 14 CONNECTED TO GROUND GND : 7 U202 98 AVDD_DUT : 14 GND : 7 U202 11 10 AVDD_DUT : 14 GND : 7 U202 13 12 AVDD_DUT : 14 DNP : DO NOT POPULATE GND : 7 Figure 53. Evaluation Board Schematic, Decoupling and Miscellaneous Rev. B | Page 31 of 40 04418-046 AD9229 Figure 54. Evaluation Board Layout, Primary Side Rev. B | Page 32 of 40 04418-047 AD9229 Figure 55. Evaluation Board Layout, Ground Plane Rev. B | Page 33 of 40 04418-048 AD9229 Figure 56. Evaluation Board Layout, Power Plane Rev. B | Page 34 of 40 04418-049 AD9229 Figure 57. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. B | Page 35 of 40 04418-050 AD9229 Table 11. Evaluation Board Bill of Materials (BOM) Qnty. per Item Board REFDES Device Pkg. Value Mfg. Mfg. Part Number 1 1 AD9229LFCSP_REVC PCB PCB PCB 2 59 C327, C328, C630, C628, Capacitor 402 0.1 μF, ceramic, Panasonic ECJ-0EB1A104K C629, C631, C632, C101, X5R, 10 V, 10% tol C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C207, C313, C314, C315, C312, C318, C319, C412, C316, C325,C326, C413, C414, C415, C418, C419, C416, C421, C422, C427, C428, C505, C509, C517, C613, C614, C617, C618, C619, C620, C621, C625, C209, C210, C627 3 4 C104, C111, C118, C125 Capacitor 402 2.2 pF, ceramic, Murata GRM1555C1H2R2GZ01B COG, 0.25 pF tol, 50 V 4 9 C202, C208, C317, C320, Capacitor 805 10 μF, 6.3 V ±10% AVX 08056D106KAT2A C417, C420, C504, C508, ceramic X5R C516 5 8 C307, C308, C309, C310, Capacitor 603 0.1 μF, ceramic, Kemet C0603C104K4RACTU C407, C408, C409, C410 X7R, 16 V, 10% tol 6 2 C311, C411 Capacitor 402 1000 pF, ceramic, Kemet C0402C102K3RACTU X7R, 25 V, 10% tol 7 4 C321, C322, C423, C424 Capacitor 402 0.018 μF, ceramic, AVX 0402YC183KAT2A X7R, 16 V, 10% tol 8 4 C323, C324, C425, C426 Capacitor 402 22 pF, ceramic, Kemet C0402C220J5GACTU NPO, 5% tol, 50 V 9 1 C501 Capacitor 1206 10 μF, tantalum, Kemet T491B106K016AS 16 V, 10% tol 10 6 C502, C503, C506, C507, Capacitor 603 1 μF, ceramic, X5R, Panasonic ECJ-1VB0J105K C514, C515 6.3 V, 10% tol 11 1 CR500 LED 603 Panasonic LNJ314G8TRA Green, 4 V, 5 m candela 12 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro SK33MSCT Commercial Co. 13 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro S2A Commercial Co. 14 1 F501 Fuse 1210 6.0 V, 2.2 A trip Tyco/Raychem NANOSMDC110F-2 current resettable fuse 15 1 FER501 Ferrite 2020 10 μH, 5 A, 50 V, Murata DLW5BSN191SQ2L bead 190 Ω @ 100 MHz 16 12 FB101, FB102, FB103, Ferrite 603 10 Ω, test freq Murata BLM18BA100SN1 FB104, FB105, FB106, bead 100 MHz, 25% tol, FB107, FB108, FB109, 500 mA FB110, FB111, FB112 17 2 JP201, JP301 Connector 2-pin 100 mil header Samtec TSW-102-07-G-S jumper, 2-pin 18 3 JP204, JP203, JP202 Connector 3-pin 100 mil header Samtec TSW-103-07-G-S jumper, 3-pin Rev. B | Page 36 of 40 AD9229 Qnty. per Item Board REFDES Device Pkg. Value Mfg. Mfg. Part Number 19 6 L501, L502, L503, L504, Ferrite 1210 10 μH, bead core Panasonic - EXC-CL3225U1 L505, L506 bead 3.2 × 2.5 × 1.6 SMD, ECG 2 A 20 4 L313, L314, L413, L414 Inductor 402 120 nH, test freq Murata LQG15HNR12J02B 100 MHz, 5% tol, 150 mA 21 12 L305, L306, L307, L308, Resistor 805 0 Ω, 1/8 W, 5% tol Panasonic ERJ-6GEY0R00V L309, L310, L405, L406, L407, L408, L409, L410, L311, L312, L411, L412 22 1 OSC200 Oscillator SMT Clock oscillator, CTS REEVES CB3LV-3C-66M6666-T 66.66 MHz, 3.3 V 23 5 P201, P101, P103, P105, Connector SMA Sidemount SMA Johnson 142-0711-821 P107 for 0.063" board Components thickness 24 1 P202 Connector HEADER 1469169-1, right Tyco 1469169-1 angle 2-pair, 25 mm, header assembly 25 1 P503 Connector 0.1", PCMT RAPC722, power Switchcraft SC1153 supply connector 26 10 R201, R202, R228, R203, Resistor 402 10 kΩ, 1/16 W, 5% Yageo 9C04021A1002JLHF3 R312, R314, R317, R402, tol America R411, R414 27 7 R225, R129, R142, R224 Resistor 402 0 Ω, 1/16 W, 5% tol Yageo 9C04021A0R00JLHF3 America 28 4 R102, R115, R128, R141 Resistor 402 64.9 Ω, 1/16 W, Panasonic ERJ-2RKF64R9X 1% tol 29 4 R104, R116, R130, R143 Resistor 603 0 Ω, 1/10 W, 5% tol Panasonic ERJ-3GEY0R00V 30 14 R111, R112, R125, R126, Resistor 402 1 kΩ, 1/16 W, 1% tol Panasonic ERJ-2RKF1001X R138, R139, R149, R150, R211, R212, R109, R123, R135, R148 31 8 R108, R110, R121, R122, Resistor 402 33 Ω, 1/16 W, 5% Yageo 9C04021A33R0JLHF3 R134, R136, R146, R147 tol America 32 4 R160, R161, R162, R163 Resistor 402 499 Ω, 1/16 W, Panasonic ERJ-2RKF4990X 1% tol 33 1 R215 Resistor 402 2 kΩ, 1/16 W, 5% tol Yageo 9C04021A2001JLHF3 America 34 1 R204 Resistor 402 4.02 kΩ, 1/16 W, Panasonic ERJ-2RKF4021X 1% tol 35 1 R213 Resistor 402 49.9 Ω, 1/16 W, Susumu RR0510R-49R9-D 0.5% tol 36 1 R214 Resistor 402 22 Ω, 1/16 W, Yageo 9C04021A22R0JLHF3 5% tol America 37 2 R216,R302 Potentiom 3-lead 10 kΩ, Cermet BC CT-94W-103 eter trimmer Components potentiometer, 18 turn top adjust, 10%, ½ W 38 1 R217 Resistor 402 470 kΩ, 1/16 W, Yageo 9C04021A4703JLHF3 5% tol America 39 1 R303 Resistor 402 39 kΩ, 1/16 W, Susumu RR0510P-393-D 5% tol 40 8 R304, R306, R307, R309, Resistor 402 187 Ω, 1/16 W, Panasonic ERJ-2RKF1870X R403, R405, R406, R408, 1% tol Rev. B | Page 37 of 40 AD9229 Qnty. per Item Board REFDES Device Pkg. Value Mfg. Mfg. Part Number 41 4 R305, R308, R404, R407, Resistor 402 374 Ω, 1/16 W, Panasonic ERJ-2RKF3740X R500 1% tol 42 4 R315, R316, R412, R413 Resistor 402 274 Ω, 1/16 W, Panasonic ERJ-2RKF2740X 1% tol 43 4 T101, T102, T103, T104 Transforme CD542 ADT1-1WT, 1:1 Mini-Circuits ADT1-1WT r impedance ratio transformer 44 2 U501, U503 IC SOT-223 ADI ADP33339AKC-3 ADP33339AKC-3, 1.5 A, 3.0 V LDO regulator 45 2 U301, U401 IC LFCSP, CP- AD8332ACP, ADI AD8332ACP 32 ultralow noise precision dual VGA 46 1 U502 IC SOT-223 ADP33339AKC-5 ADI ADP33339AKC-5 47 1 U201 IC LFCSP, CP- AD9229-65, quad ADI AD9229ABCPZ-65 48-1 12-bit, 65 MSPS serial LVDS 3 V ADC 48 1 U203 IC SOT-23 ADR510AR, 1.0 V, ADI ADR510AR precision low noise shunt voltage reference 49 1 U202 IC TSSOP 74VHC04MTC, hex Fairchild 74VHC04MTC inverter 50 4 MP101-104 Part of CBSB-14-01A-RT, Richco CBSB-14-01A-RT assembly 7/8" height, standoffs for circuit board support 51 4 MP105-108 Part of SNT-100-BK-G-H, Samtec SNT-100-BK-G-H assembly 100 mil jumpers 52 4 MP109-112 Part of 5-330808-3, pin AMP 5-330808-3 assembly sockets, closed end for OSC200 Rev. B | Page 38 of 40 AD9229 OUTLINE DIMENSIONS 7.10 0.30 0.60 MAX 7.00 SQ 0.23 6.90 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 1 36 PIN 1 INDICATOR 0.50 6.85 REF * 5.55 6.75 SQ EXPOSED 5.50 SQ 6.65 PAD (BOTTOM VIEW) 5.45 25 12 24 13 0.50 0.22 MIN TOP VIEW 0.40 5.50 REF 0.30 0.80 MAX 12° MAX 1.00 0.65 TYP FORPROPERCONNECTIONOF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 58. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9229ABCPZ-65 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8 AD9229ABCPZRL7-65 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8 AD9229ABCPZ-50 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8 AD9229ABCPZRL7-50 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8 1 Z = RoHS Compliant Part. Rev. B | Page 39 of 40 02-23-2010-C AD9229 NOTES © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04418–0–5/10(B) Rev. B | Page 40 of 40